JPH0620196B2 - Burst conversion circuit - Google Patents

Description

The present invention relates to a burst conversion circuit, and more particularly to a circuit for performing phase absorption of a data signal sequence, frame matching and burst conversion using a FIFO memory.

[Conventional technology]

FIG. 4 is a block diagram of a conventional burst conversion circuit.
In FIG. 4, a FIFO (First-In First-Out) memory 101 inputs an input digital signal sequence 1 and an input timing pulse 2 by a write pulse 11. FIFO memory
Reference numeral 101 also performs phase absorption, frame matching, and burst conversion for the reference clock pulse 5 and the reference timing pulse 5 that should output the burst signal train 6, and the read pulse 13
The burst signal train 6 and the timing pulse 7 are output according to, and the "overflow" information 8 and the "empty" information 9 are output according to the data storage amount. Here, the frame aligner means the FIFO memory 10 based on the reference timing pulse 5.
It is to perform the cueing of the burst signal train output from the first example. The margin counter 102 counts N (N is a natural number) bits of the input clock 3 in an initial state such as when the power is turned on, and during normal operation, a margin of N bits is provided for the FIFO memory 101 with respect to the intra-bit phase fluctuation of the input clock 3. Margin counter information 10 is output. Input control circuit
103 is "overflow" information 8 output from the FIFO memory 101
A write pulse 11 is output according to the input clock 3, the margin counter information 10 output from the margin counter 102, and the reference timing pulse 5. The read control counter 104 sets the reference timing pulse 5 to M by the margin counter information 10 in an initial state such as when the power is turned on.
(M is a natural number) are counted and a read control pulse 12 is output. The output control circuit 105 outputs a timing pulse 7 output from the FIFO memory 101, "empty" information 9, a reference clock 4, a reference timing pulse 5, and a read control pulse.
A read pulse 13 is output according to 12 and.

This circuit will be described with reference to the timing charts of FIGS. 5 and 3. In this circuit, reading is stopped in the initial state such as when the power is turned on, and the input timing pulse 2 (FIG. 5b).
Of the input digital signal train 1 (FIG. 5A) having a length of 1 bit (l is a natural number) and the input timing pulse 2 for N bits first by the input control circuit 103 to the FIFO memory 101.
Write in. Then, after the input clock 3 is counted N bits in the margin counter 102, the writing is temporarily stopped by the margin counter information 10, and then the reference timing pulse 5 (FIG. 5c) is first input again. Start writing the input digital signal sequence 1 and input timing pulse, and store M cycles of data in the FIFO
It is stored in the memory 101. The read control counter 104 is (M
When the +1) th reference timing pulse 5 is input, the read control pulse 12 is output, and the output control circuit 105 outputs the read pulse 13 (FIG. 5d). On the other hand, the output control circuit 105 keeps the FIFO until the timing pulse 7 is output.
Data is read from the memory 101. Timing pulse 7
When (FIG. 5f) is output from the FIFO memory 101, the output control circuit 105 stops outputting the read pulse 13 and FIF.
The output of data from the O memory 101 is stopped, and the burst signal train 6 stops in the state of FIG. 5e.

In FIG. 3, when a new reference timing pulse 5 is input in the next cycle, the output control circuit 105 outputs a read pulse 13 again, and the burst signal train 6 (frame-matched and burst-converted from the FIFO memory 101) Figure e ')
And timing pulse 7 (f 'in FIG. 7) is output. In this way, phase absorption, frame matching, and burst conversion were performed using the FIFO memory.

[Problems to be solved by the invention]

However, in such a circuit, since the burst read pulse 13 is used for frame matching and burst conversion,
As shown in FIG. 5, while reading the burst signal train 6 from the FIFO memory 101, it was necessary to stop the momentary reading when the timing pulse 7 was output and perform frame matching. As a result, the burst conversion is temporarily suspended, and since the read pulse is commonly used for frame matching and burst conversion, an element that operates at high speed is required. Moreover, the burst conversion stops midway, which is inefficient and takes too much time. was there.

The present invention eliminates the above-mentioned drawbacks and achieves reliable and time-efficient operation by performing frame matching by using an empty time slot from the time when the data signal sequence is read out in burst form until the signal is read out again in burst form. The purpose is to provide a good burst conversion circuit.

[Means for solving problems]

The present invention, in a burst conversion circuit for converting an input signal into a high-speed signal and outputting it in a burst form, writes an input digital signal sequence and an input timing pulse by an input clock, and outputs a reference clock and a burst signal sequence on the output side of the conversion circuit. A FIFO memory that performs phase absorption, frame matching and burst conversion for a power reference timing pulse, a margin counter that counts the input clock by N bits in order to have a margin for the bit unit phase fluctuation of the input clock, and the FIFO memory "Overflow" information to be output, input clock, counter output for the margin and an input control circuit for controlling writing of the input digital signal sequence and the input timing pulse to the FIFO memory using the reference timing pulse as an input signal, and the margin The reference output depends on the counter output. The timing pulse M pieces count, and the read control counter for accumulating data of M cycles in the FIFO memory is stopped reading during M cycles,
Frame matching of the input digital signal and the input timing pulse with respect to the reference timing pulse is performed by using an empty time slot from the time when the burst data signal is read from the FIFO memory to the time when the signal is read again in the burst shape. Frame matching circuit that outputs the "empty" output by the FIFO memory
And an output control circuit for generating a read pulse for reading the input digital signal sequence and the input timing pulse from the FIFO memory according to the information, the reference clock, the reference timing pulse, the output of the read control counter and the output of the frame matching circuit. To do.

〔Example〕

 Examples of the present invention will be described below.

FIG. 1 is a block diagram of an embodiment of the present invention. The same parts and the same signals as in FIG. In this embodiment, the timing pulse 7 is frame-matched with respect to the reference timing pulse 5, and the frame-matching result 14 is provided in the output frame matching circuit 106. The output control circuit 105 outputs the "empty" information 9 output from the FIFO memory 101, the reference clock 4 and the reference timing pulse 5.
A read pulse 13 is output according to the read control pulse 12 and the frame matching result 14 which are outputs of the read control counter 104.

The input timing pulse 2 is for indicating the phase of the frame of the input digital signal sequence 1, and the reference timing pulse 5 is for the frame phase of the burst signal sequence 6 output from the FIFO memory 101 for frame matching. It is for management. The timing pulse 7 is a pulse for indicating the phase of the frame of the burst signal train 6 and for comparing the phase with the reference timing pulse 5.

Hereinafter, a detailed description will be given with reference to FIGS. 1, 2, and 3. In this circuit, reading is stopped in the initial state such as when the power is turned on, and the input digital signal train 1 (Fig. 2a) of 1-bit length is first input at the cycle of the input timing pulse 2 (Fig. 2b). The N bits of 2 are written by the input control circuit 103. Then, after N bits are counted in the margin counter 102, the writing is temporarily stopped by the margin counter information 10 which is the output, and then the reference timing pulse 5 is set first.
The writing of the input digital signal sequence 1 and the input timing pulse 2 is started again when (Fig. 2c) is input, and M
The data for a period is stored in the FIFO memory 101. The read control counter 104 outputs the read control pulse 12 when the M + 1th reference timing pulse is input, and the output control circuit 105 outputs the burst read pulse 13 (FIG. 2d).
Is output. Since the read pulse 13 is not output immediately after the last bit that outputs data in burst form (FIG. 2e) and (FIG. 2f) in the FIFO memory 101, the last bit until the next reference timing pulse 5 arrives. Bit information is retained. Utilizing this fact, the frame matching circuit 10
6 monitors the last bit of the data read out in burst form and determines whether the timing pulse 7 is output. If the timing pulse 7 is not output, the frame matching result 14 is output, and the output control circuit 105 outputs the timing pulse 7 from the FIFO memory 101.
And the read pulse 13 is output from the output control circuit 105. When the timing pulse 7 is output from the FIFO memory 101, the reading is stopped.

In such a burst conversion circuit, since the amount of data information written to and read from the FIFO memory 101 during one cycle of the reference timing pulse 5 is the same, if the frame matching circuit 106 performs a normal operation, the output data is
In (Fig. 3e ') and (Fig. 3f'), the timing pulse 7 is continuously output to the last bit in the burst form.

Therefore, in the present invention, the FIFO memory is used to absorb the phase of the input digital signal sequence 1 and the input timing pulse 2 with respect to the reference clock 4 on the output side of the conversion circuit and the reference timing pulse 5 which should output the burst signal sequence 6, and frame matching and When performing burst conversion, by performing frame matching using an empty time slot from the time when the reading of the burst signal train 6 is completed to the time when the burst signal train 6 is read again, the burst conversion and the frame matching can be controlled reliably and efficiently. .

〔The invention's effect〕

As described above, the present invention has an effect of reliably and efficiently performing burst conversion and frame matching by utilizing a time slot after converting an input digital signal sequence into a burst signal sequence.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the burst conversion circuit of the present invention. FIGS. 2 and 3 are timing charts showing the operation of the burst conversion circuit, respectively.
FIG. 3 shows after control. FIG. 4 is a block diagram of a conventional burst conversion circuit. FIG. 5 is a timing chart for explaining the operation of the conventional burst conversion circuit. In the figure, 101 is a FIFO memory, 102 is a margin counter, 10
3 is an input control circuit, 104 is a read control counter, 105 is an output control circuit, and 106 is a frame matching circuit.

Claims (1)

[Claims] 1. A burst conversion circuit for converting an input signal into a high-speed signal and outputting it in a burst form, wherein an input digital signal sequence and an input timing pulse are written by an input clock, and a reference clock and a burst signal sequence on the output side of the conversion circuit are output. Phase absorption for the reference timing pulse to be
A FIFO (First-In, First-Out) memory for performing frame matching and burst conversion for finding the beginning of a burst signal sequence, and an N-bit (N-bit) input clock in order to have a margin for bit-wise phase fluctuations of the input clock. : Natural number) Margin counter for counting, "overflow" information output from the FIFO memory, input clock, output of the margin counter and reference timing pulse as input signals, and the FIFO memory of input digital signal sequence and input timing pulse M (M: natural number) of reference timing pulses are counted by an input control circuit for controlling writing to the
The reading is stopped during a cycle and the data for M cycles is stored in the FI.
A read control counter for accumulating in the FO memory, and an input digital signal for a reference timing pulse using an empty time slot from the time when the data signal is read in burst form from the FIFO memory until the signal is read in burst form again. A frame matching circuit that performs frame matching of input timing pulses and outputs a frame matching result, "empty" information output from the FIFO memory, a reference clock, a reference timing pulse, the read control counter output, and frame matching A burst conversion circuit comprising an input digital signal sequence and an output control circuit for generating a read pulse for reading an input timing pulse from the FIFO memory by a circuit output.