EP3060930A1

EP3060930A1 - Clock spurs reduction technique

Info

Publication number: EP3060930A1
Application number: EP14815427.1A
Authority: EP
Inventors: Luca Romano
Original assignee: Marvell World Trade Ltd
Current assignee: Marvell World Trade Ltd
Priority date: 2013-10-23
Filing date: 2014-10-21
Publication date: 2016-08-31
Also published as: CN105793717A; WO2015059564A1; CN105793717B

Abstract

Aspects of the disclosure provide a circuit having a jittered clock generator. The jittered clock generator is configured to add jitter of a controlled characteristic to a first clock signal of a clock frequency to generate a second clock signal to be used by a transceiver for operating at a radio frequency. The jitter of the controlled characteristic adjusts a clock harmonic at the radio frequency of the transceiver.

Description

CLOCK SPURS REDUCTION TECHNIQUE

CROSS REFERENCE TO RELATED APPLICATIONS

[0001] This present disclosure claims the benefit of U.S. Provisional Application No. 61/894,702, "Clock Spurs Reduction Technique" filed on October 23, 2013, and is a

continuation-in-part of U.S. Patent Application No. 13/839,696 , "Fractional Spur Reduction Using Controlled Clock Jitter" filed on March 15, 2013, which is a continuation of U.S. Patent Application No. 13/191,329, "Fractional Spur Reduction using Controlled Clock Jitter" filed on July 26, 201 1 and issued as U.S. Patent No. 8,400,197 on March 19, 2013, which in turn claims the benefit of U.S. Provisional Application No. 61/368,459, entitled "A PLL Fractional Spurs Reduction" filed on July 28, 2010. The entire disclosures of the prior applications are hereby incorporated by reference herein in their entirety.

BACKGROUND

[0002] Generally, radio frequency (RF) circuits operate based on a reference clock signal. In an example, a clock generator generates a reference clock signal of a relatively low frequency, such as in the order of 20 MHz, and provides the reference clock signal to a transceiver that transmits/receives radio frequency signal. The transceiver includes a phase locked loop that generates an RF carrier signal of much higher frequency, such as in the order of 1 GHz and the like, based on the reference clock signal.

SUMMARY

[0003] Aspects of the disclosure provide a circuit having a jittered clock generator. The jittered clock generator is configured to add jitter of a controlled characteristic to a first clock signal of a clock frequency to generate a second clock signal to be used by a transceiver for operating at a radio frequency. The jitter of the controlled characteristic adjusts a clock harmonic at the radio frequency of the transceiver.

[0004] In an embodiment, the jittered clock generator includes a jitter controller and a jitter generator. The jitter controller is configured to generate a control signal as a function of the clock harmonic. The jitter generator is configured to add the jitter according to the control signal to the first clock signal to generate the second clock signal. In an example, the jitter generator is configured to add a variable delay to the first clock signal to generate the second clock signal. For example, the jitter generator includes a delay chain of a plurality of delay elements to add an additional amount of delay to the first clock signal. Further, the jitter generator includes an edge selector configured to vary a selection of one of the delay elements to output the second clock in order to change the variable delay of the second clock signal to the first clock signal. The jitter controller is configured to generate a sequence of selection codes to control the edge selector to vary the selection of the delay elements. In an example, the jitter controller is configured to generate the sequence of the selection codes to vary the selection of the delay elements in a random manner. In an embodiment, the jitter generator is configured to form a loop that includes the delay chain to calibrate the additional amount of delay added by each delay element to suppress the clock harmonic.

[0005] According to an aspect of the disclosure, the jittered clock generator is configured to add the jitter of the controlled characteristic to convert a power at the clock harmonic to spurs out of the radio frequency band of interest. According to another aspect of the disclosure, the jittered clock generator is configured to add the jitter of the controlled characteristic to convert a power at the clock harmonic to a large number of frequency components having low power. In an example, the power of the clock harmonic is converted to a noise floor.

[0006] Aspects of the disclosure provide a method. The method includes receiving a first clock signal of a clock frequency and adding jitter of a controlled characteristic to the first clock signal to generate a second clock signal to be used by a transceiver for operating at a radio frequency. The jitter of the controlled characteristic adjusts a clock harmonic at the radio frequency of the transceiver.

BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Various embodiments of this disclosure that are proposed as examples will be described in detail with reference to the following figures, wherein like numerals reference like elements, and wherein:

[0008] Fig. 1 shows a block diagram of an electronic device example 100 according to an embodiment of the disclosure;

[0009] Fig. 2 shows a block diagram of a jittered clock generator example 230 according to an embodiment of the disclosure;

[0010] Fig. 3 shows a plot 300 of waveforms according to an embodiment of the disclosure; [0011] Fig. 4 shows a plot 400 illustrating harmonic suppression according to an embodiment of the disclosure;

[0012] Fig. 5 shows a block diagram of another jittered clock generator example 530 according to an embodiment of the disclosure;

[0013] Fig. 6 shows a block diagram of a jittered clock generator example 630 for calibration according to an embodiment of the disclosure; and

[0014] Fig. 7 shows a flow chart outlining a process example 700 according to an embodiment of the disclosure.

DETAILED DESCRIPTION OF EMBODIMENTS

[0015] Fig. 1 shows a block diagram of an electronic device example 100 according to an embodiment of the disclosure. The electronic device 100 includes a jittered clock generator 130 configured to add jitter of a controlled characteristic to a first clock signal of a clock frequency to generate a second clock signal to be used by a transceiver. The jitter of the controlled characteristic reduces a specific harmonic of the clock frequency at the transceiver.

[0016] The electronic device 100 can be any suitable device, such as a desktop computer, a laptop computer, a tablet computer, a smart phone, an access point, and the like that includes a transmitting circuit and/or a receiving circuit that operate based on a reference clock signal.

[0017] According to an aspect of the disclosure, the jittered clock generator 130 is configured to generate a reference clock signal CLOCKSYS having a controlled jitter

characteristic and provide the reference clock signal CLOCKSYS to circuits that require a reference clock signal, such as a transceiver 180 on a same IC chip 120 as the jittered clock generator 130, a transceiver 1 12 on another IC chip 1 10, and the like.

[0018] Specifically, in the Fig. 1 example, the jittered clock generator 130 includes a jitter generator 150 and a jitter controller 160 coupled together as shown in Fig. 1. The jitter controller 160 provides control signals indicative a jitter characteristic. According to the control signals, the jitter generator 150 adds jitter to a first clock signal (CLOCKCLE_AN) to generate a second clock signal (CLOCKJUTER) having the jitter characteristic. The second clock signal CLOCKJITTER is buffered and output as the reference clock signal CLOCKSYS-

[0019] According to an aspect of the disclosure, the first clock signal CLOCKCLEAN has a precise frequency F_c and little jitter and can be considered as a clean clock. In an example, the first clock signal CLOCKCLEAN is generated by a clock generator 140 on the same IC chip 120. In another example, the first clock signal CLOCKCLEAN is generated by a crystal oscillator external to the IC chip 120, and is input to the IC chip 120 and received by the jitter generator 150.

[0020] The jitter generator 150 is configured to add jitter to the first clock signal

CLOCKCLE_AN, in an embodiment, the jitter generator 150 is configured to delay transition edges, such as rising edges and/or falling edges, of the first clock signal according to the control signals from the jitter controller 160.

[0021] In an embodiment, the jitter generator 150 includes a delay chain of multiple delay stages. In an example, the delay stages can be calibrated to have specific delays. The delay chain is configured to delay transition edges, and output delayed transitions from the multiple delay stages. The outputs from the multiple delay stages are selected to output transitions in the second clock signal CLOCKJUTER- In an example, to output a transition in the second clock signal CLOCKJITTER, one of the outputs from the multiple delay stages is selected.

[0022] The jitter controller 160 is configured to determine the control signals to control the jitter generator 150 to generate and add jitter in the first clock signal CLOCKCLEAN- The jitter controller 160 can use any suitable algorithm to generate the control signals. In an example, the jitter controller 160 includes a controller 165 configured to generate the control signals for adding jitter to suppress clock harmonic that can deteriorate transceiver performance.

[0023] It is noted that the jitter controller 160 can include other suitable controller to generate the control signals to add jitter for other purpose. For example, the jitter controller 160 can include a controller 169 for fractional spur reduction. The jitter controller 160 can be implemented using various techniques, such as circuits, instructions executed by a processor, and the like.

[0024] According to an aspect of the disclosure, clock signals can impair radio frequency (RF) transceiver performance through various interference mechanisms. In an embodiment, clock signals cause current pulses. In an example, clock signals are generally buffered, such as by a clock buffer 170 and the like, and are provided to digital circuits to synchronize operations of the digital circuits. The clock signals can cause current pulses flowing through buffers, supplies, grounds and the digital circuits at the time of clock transitions. The current pulses can cause electromagnetic emission of high order harmonics. Further, the current pulses can cause supply noise (e.g., high frequency voltage ripple), in power supply, such as in a voltage supply (VDD), in a ground supply (VSS), and the like. The electromagnetic emission and the supply noise can deteriorate performance of a transceiver 180 on the IC chip 120.

[0025] In an example, when the high order harmonics and/or the supply noise is in the RF band of a receiving circuit in the transceiver 180, the high order harmonics and/or the supply noise interferes the performance of the receiving circuit. In another example, the high order harmonics and/or the supply noise can be directly coupled to a transmitting circuit in the transceiver 180. The harmonics and/or the supply noise can cause violation of the spectral emission mask.

[0026] In another example, the clock signals on the IC chip 120 can also deteriorate performance of the transceiver 1 12 on the other IC chip 110. For example, the reference clock signal CLOCKSYS on the IC chip 120 is a system clock and is provided to other IC chips, such as the IC chip 1 10, to be used by other IC chips. In the Fig. 1 example, the IC chip 120 provides the reference clock signal CLOCKSYS to the IC chip 1 10 via various conductive components, such as bond pads 121 and 111, bond wire 116, printed copper lines (not shown), vias (not shown) and the like. Further, in an example, the power supply VDD and the ground supply VSS of the IC chip 120 and the IC chip 1 10 can be coupled together via conductive components. The driving current Io and the supply current IVDD are pulse current, and can cause electromagnetic emission of clock harmonics to impair performance of the transceiver 1 12 on the IC chip 1 10. Further, supply noise in the power supply VDD and the ground supply VSS on the IC chip 120 can be coupled to the IC chip 1 10 to impair the performance of the transceiver 1 12.

[0027] According to an aspect of the disclosure, jitter characteristic of the reference clock signal CLOCKSYS is suitably controlled to cause one or more specific high-order harmonics of the clock frequency Fc to be attenuated or eliminated. In an example, when a high-order harmonic of the clock frequency is in an RF band of a receiving circuit, jitter characteristic of the reference clock signal CLOCKSYS is controlled to attenuate or eliminate the high-order harmonic. In an example, the jitter of reference clock signal CLOCKSYS causes spurs at other frequencies that are outside of the RF band of the receiving circuit, and can be suitably filtered out.

[0028] According to another aspect of the disclosure, jitter characteristic of the reference clock signal CLOCKSYS is suitably controlled to cause the specific high-order harmonics to be converted to a noise floor to reduce the spectral emission per unit bandwidth in order to satisfy the spectral emission mask requirement.

[0029] Fig. 2 shows a block diagram of a jittered clock generator example 230 according to an embodiment of the disclosure. In an example, the jittered clock generator 230 can be used in the electronic device 100 as the jittered clock generator 130. The jittered clock generator 230 receives a first clock signal CLOCKCLEAN, adds jitter of a controlled characteristic and outputs a second clock signal CLOCKJITTER having the jitter of the controlled characteristic.

[0030] The jittered clock generator 230 includes a jitter generator 250 and a jitter controller 260 coupled together as shown in Fig. 2. The jitter generator 250 includes a delay module 251 configured to delay the first clock signal CLOCKCLEAN by a delay time τ to generate a delayed first clock signal CLOCKDEL_AY, and a multiplexer 252 configured to select one of the first clock signal CLOCKCLEAN and the delayed first clock signal CLOCKDELAY based on a control signal SELECT from the jitter controller 260.

[0031] The jitter controller 260 can use any suitable technique to generate the control signal SELECT. In an embodiment, the jitter controller 260 includes a frequency divider 261 to frequency-divide the delayed first clock signal CLOCKDELAY to generate the control signal SELECT. In an example, the frequency divider 261 is implemented using a flip-flop that frequency-divides the delayed first clock signal CLOCKDELAY by two to generate the control signal SELECT. Then, the control signal SELECT controls the jitter generator 250 to add delays to clock transitions every other clock cycle to introduce jitter in the second clock signal

CLOCKJITTER · The second clock signal CLOCKJITTER is buffered by a clock buffer 170. The clock buffer 170 drives the second clock signal CLOCKJITTER to other circuits, such as digital circuits, off-chip circuits, and the like. The jitter in the second clock signal CLOCKJITTER attenuates or eliminates specific harmonic of the clock frequency.

[0032] Generally, circuits that operate based on a clock signal introduce noise in circuit current, such as a supply current IVDD from a power supply VDD, a ground current Ivss injected into a ground supply VSS, an output current Io from a buffer, and the like. In general, the noise current can be described as a train of pulses, aligned with the clock transitions, such as rising edges and falling edges of the clock signal.

[0033] Fig. 3 shows a plot 300 of waveforms according to the jittered clock generator 230 in Fig. 2. The plot 300 includes a first waveform 310 for the first clock signal CLOCKCLEAN, a second waveform 320 for the second clock signal CLOCKJITTER, and a third waveform 330 for the supply current IVDD-

[0034] In the Fig. 3 example, the first clock signal CLOCKCLEAN is a clean clock signal with a relatively precise clock frequency Fc as shown by the first waveform 310. The second clock signal CLOCKJITTER has jitter with a controlled characteristic. Specifically, a delay time τ is added to clock transitions every other clock cycle to introduce jitter in the second clock signal CLOCKjiTTER, as shown by 323 and 324. The second clock signal CLOCKJHTER is provided to circuits, such as the clock buffer 170, and the like. The supply current IVDD has current pulse in response to the clock transitions of the second clock signal CLOCKJHTER, as shown by 331 -336.

[0035] It is noted that the current pulse may have different shapes in response to rising edges and falling edges. The current pulses cause a high order harmonic in a RF band of a transceiver, and may deteriorate the transceiver performance.

[0036] In an embodiment, to suppress an N-th order harmonic of the clock frequency F_c (N is a positive integer), the delay time τ is determined according to Eq. 1 :

ZNFc Eq. 1

where k denotes a whole number. In this embodiment, due to the added jitter, the N-th order

Fc harmonic of the clock frequency Fc is suppressed, however two spurs appear at ⁴ z in the frequency spectrum. In an example, the two spurs are outside a channel band of the transceiver and do not affect the transceiver performance. For example, the clock frequency Fc is 26 MHz, and the transceiver operates at an RF frequency of 1.846 GHz, which is the 71th order harmonic of the clock frequency. When jitter is added according to Fig. 2 and Eq. 1 to suppress the 71th order harmonic, two spurs appear at 13 MHz from the RF frequency. In an example, the RF channel bandwidth is smaller than 13 MHz, thus the two spurs are outside of the channel band and do not affect the performance of the transceiver.

[0037] Further, according to an aspect of the disclosure, the level of harmonic suppression and the amplitude of the two spurs are related to the delay time τ, and the value of k can be chosen arbitrarily, e.g., to have a delay time τ suitable for circuit implementation.

[0038] Fig. 4 shows a plot 400 illustrating the relationships of harmonic suppression and the amplitude of the spurs to the delay time according to an embodiment of the disclosure. In the plot 400, the X-axis denotes normalized delay * and the Y-axis denotes the level of harmonic suppression and the amplitude of the spurs. The plot 400 includes a first curve 410 and a second curve 420. The first curve 410 shows a relationship of harmonic suppression to the normalized delay. The second curve 420 shows a relationship of spur amplitude to the normalized delay. It is noted that when the normalized delay is about 0.5, the jittered clock achieves a maximum harmonic suppression.

[0039] Fig. 5 shows a block diagram of another jittered clock generator example 530 according to an embodiment of the disclosure. In an example, the jittered clock generator 530 is used in the electronic device 100 as the jittered clock generator 130. The jittered clock generator 530 includes a jitter generator 550 and a jitter controller 560. The jittered clock generator 530 receives a first clock signal CLOCKCLEAN, adds jitter of a controlled characteristic and outputs a second clock signal CLOCKJUTER having the jitter of the controlled characteristic.

[0040] In the Fig. 5 example, the jitter generator 550 includes a delay chain 551, an edge selector 552. The jitter controller 560 is implemented using a digital sequence generator 562. These elements are coupled together as shown in Fig. 5.

[0041] According to an aspect of the disclosure, the first clock signal CLOCKCLEAN has a precise frequency Fc and little jitter and can be considered as a clean clock. In an example, the first clock signal CLOCKCLEAN is generated by a crystal oscillator.

[0042] The jitter generator 550 receives the first clock signal CLOCKCLEAN, and input the first clock signal CLOCKCLEAN to the delay chain 551. The delay chain 551 includes a plurality of delay stages 553(1)-553(N). In an example, each delay stage is configured to delay a received signal by a delay time τ. The delay chain 551 generates a set of delayed replicas of the first clock signal CLOCKCLEAN-

[0043] The edge selector 552 receives the first clock signal CLOCKCLEAN and the delayed replicas of the first clock signal CLOCKCLEAN, selects one of the received signals according to control signals from the jitter controller 560, and outputs the selected signal as the second clock signal CLOCKJITTER- In an embodiment, the edge selection code is updated once every clock period 1/Fc. Timing may be provided to guarantee a glitch-free output of the second clock signal CLOCKJUTER.

[0044] The digital sequence generator 562 generates a sequence of edge selection codes to control the jitter generator 550 to introduce the desired amount of jitter onto the first clock signal CLOCKCLEAN with the desired spectral characteristics. In an example, the digital sequence generator 562 is clocked at the clock frequency Fc to update the edge selection code once every clock period to select a different delayed replica. The selection of different delayed replicas of the first clock CLOCKCLEAN introduces jitter on the second clock signal CLOCKJUTER output by the edge selector 552.

[0045] The digital sequence generator 562 can be implemented using various techniques. In an example, the digital sequence generator 562 is implemented as a programmable sequence generator using shift register/look-up table, and is used to introduce jitter of a characteristic, such as a sinusoidal modulation characteristic, a square wave modulation characteristic, a triangular wave modulation characteristic, and the like. In another example, the digital sequence generator 562 is implemented using a sigma-delta digital modulator. In another example, the digital sequence generator 562 is implemented as a pseudo-random sequence generator using shift registers.

[0046] In an example, the digital sequence generator 562 is configured to generate a pseudo-random pattern as the edge selection codes to introduce time jitter in a random manner to convert a clock harmonic to noise floor. For example, the clock frequency Fc is 26 MHz, and a transceiver operates at an RF frequency of 1.846 GHz, which is the 71th order harmonic of the clock frequency. Further, the unit delay τ is configured to be 1/(71 ^xFc), about 271 ps to cancel harmonic suppression. In an example, the pseudo-random pattern repeats a sequence of 100 samples. Each sample is randomly selected from (0 and 1) to control the jitter generator 550 to add no delay or add a unit delay to transitions in a clock cycle. In this example, the clock harmonic at 1.846 GHz is converted to 100 equally spaced spurious tones between 1.846 GHz- 13 MHz and 1.846 GHz+13 MHz. The power sum of the tones is about the same as the power of the original clock harmonic, and the average power of the tones is about 20dB less than the original clock harmonic. Thus, when the number of samples is large, such as larger than one hundred and the like, the average power per tone is relatively low, and spurious tones can be considered as a white noise floor in an example.

[0047] Fig. 6 shows a block diagram of a jittered clock generator example 630 for calibration according to an embodiment of the disclosure. The jittered clock generator 630 has a calibration mode and a jitter generation mode. In the jitter generation mode, the jittered clock generator 630 operates similarly to the jittered clock generator 530 described above. The jittered clock generator 630 also utilizes certain components that are identical or equivalent to those used in the jittered clock generator 530; the description of these components has been provided above and will be omitted here for clarity purposes. However, in this embodiment, the delay elements in the jittered clock generator 630 are programmable and can be calibrated to have a specific delay for clock harmonic suppression.

[0048] In an embodiment, the jitter generator 650 includes an odd number of programmable delay elements 653(1)-653(N) where N is an odd number. Further, the jitter generator 650 includes a multiplexer 655, the edge selector 652 and a frequency counter 654. The programmable delay elements 653(1)-653(N) form a delay chain. In an example, each programmable delay element is an inverter with a unit delay being adjustable. For example, the delay of the inverter is a function of the supply voltage of the inverter, the load capacitance, and the like. Thus, the supply voltage of the inverter or the load capacitance can be adjusted to adjust the delay of the inverter. The multiplexer 655 receives the first clock signal CLOCKCLEAN and a feedback output of the delay chain and selects one of them as the input to the delay chain based on a calibration control signal CALIBRATION.

[0049] The jitter generator 650 enters the calibration mode or the jitter generation mode based on the calibration control signal CALIBRATION to the multiplexer 655. For example, when the calibration control signal CALIBRATION is indicative of the calibration mode, the multiplexer 655 selects the output of the delay chain to input to the delay chain. Due to the odd number of inverters, the delay chain forms a ring oscillator. The frequency counter 654 counts the frequency of the ring oscillator. The frequency of the ring oscillator is indicative of a unit delay of each of the inverters. The delay information is provided to a calibration algorithm to adjust the unit delay value. For example, the jitter controller 660 includes a processor executing the calibration algorithm to adjust the unit delay of the inverters.

[0050] When the calibration signal is indicative of the jitter generation mode, the multiplexer 655 selects the first clock signal CLOCKCLEAN to input to the delay chain. Then, the jittered clock generator 630 operates similarly to the jittered clock generator 530.

[0051] Fig. 7 shows a flow chart outlining a process example 700 according to an embodiment of the disclosure. In an example, the process 700 is executed in a jittered clock generator, such as the jittered clock generator 130, the jittered clock generator 230, the jittered clock generator 530, the jittered clock generator 630, and the like. The process starts at S701, and proceeds to S710. [0052] At S710, frequency information of a transceiver is received. For example, the transceiver is in an electronic device that operates based on a system clock having a clock frequency Fc, such as 26 MHz. Based on the system clock, the transceiver operates at an RF frequency, such as 1.846 GHz, which is the 71th order harmonic of the clock frequency Fc.

[0053] At S720, a unit delay of a delay chain is calibration. In the Fig. 6 example, the jitter generator 630 enters a calibration mode. In the calibration mode, the programmable delay elements 653 are adjusted to achieve a specific unit delay. For example, the unit delay τ of each of the delay elements 653 is suitably adjusted to be 1/(71 xFc), about 271 ps.

[0054] At S730, a method to suppress clock harmonic at the transceiver is selected. In an example, a clock harmonic is about the same as a RF carrier frequency used by a receiving circuit, and may impair the receiving circuit performance. Thus, in the example, a jitter controller, such as the jitter controller 160, and the like selects a method that adds jitter to convert the power at the clock harmonic to spurs out of the RF frequency band of interest of the receiving circuit. In another example, the clock harmonic causes violation of spectral emission mask and may impair a transmitting circuit performance. The jitter controller selects a method that adds jitter to convert the power at the clock harmonic to a large number of spurs, such as larger than 100 spurs, and the like. Thus, the power at the clock harmonic is converted to noise floor.

[0055] At S740, a control signal is generated and provided to a jitter generator to introduce jitter. In an example, according to the selected method, the jitter controller 560 generates control signals, such as a sequence of edge selection codes, and the like. The edge selection codes are sequentially provided to the jitter generator 550. The jitter generator 550 receives the first clock signal CLOCKCLEAN, generates a set of delayed replicas of the first clock signal CLOCKCLEAN, selects one of the received signals based on the edge selection codes, and outputs the second clock signal CLOCKJITTER having jitter of the controlled characteristic. Then, the process proceeds to S799 and terminates.

[0056] While aspects of the present disclosure have been described in conjunction with the specific embodiments thereof that are proposed as examples, alternatives, modifications, and variations to the examples may be made. Accordingly, embodiments as set forth herein are intended to be illustrative and not limiting. There are changes that may be made without departing from the scope of the claims set forth below.

Claims

WHAT IS CLAIMED IS:

1. A circuit comprising:

a jittered clock generator configured to add jitter of a controlled characteristic to a first clock signal of a clock frequency to generate a second clock signal to be used by a transceiver for operating at a radio frequency, the jitter of the controlled characteristic adjusting a clock harmonic at the radio frequency of the transceiver.

2. The circuit of claim 1, wherein the jittered clock generator further comprises: a jitter controller configured to generate a control signal as a function of the specific clock harmonic; and

a jitter generator configured to add the jitter according to the control signal to the first clock signal to generate the second clock signal.

3. The circuit of claim 2, wherein the jitter generator is configured to add a variable delay to the first clock signal to generate the second clock signal.

4. The circuit of claim 2, wherein the jitter generator comprises a delay chain of a plurality of delay elements to add an additional amount of delay to the first clock signal.

5. The circuit of claim 4, wherein the jitter generator comprises an edge selector configured to vary a selection of one of the delay elements to output the second clock in order to change the variable delay of the second clock signal to the first clock signal.

6. The circuit of claim 5, wherein the jitter controller is configured to generate a sequence of selection codes to control the edge selector to vary the selection of the delay elements.

7. The circuit of claim 6, wherein the jitter controller is configured to generate the sequence of the selection codes to vary the selection of the delay elements in a random manner.

8. The circuit of claim 4, wherein the jitter generator is configured to form a loop that includes the delay chain to calibrate the additional amount of delay added by each delay element to suppress the clock harmonic.

9. The circuit of claim 1 , wherein the jittered clock generator is configured to add the jitter of the controlled characteristic to convert a power at the clock harmonic to spurs out of a radio frequency of interest.

10. The circuit of claim 1 , wherein the jittered clock generator is configured to add the jitter of the controlled characteristic to convert a power at the clock harmonic to a noise floor.

1 1. A method comprising:

receiving a first clock signal of a clock frequency; and

adding jitter of a controlled characteristic to the first clock signal to generate a second clock signal to be used by a transceiver for operating at a radio frequency, the jitter of the controlled characteristic adjusting a clock harmonic at the radio frequency of the transceiver.

12. The method of claim 1 1, wherein adding the jitter of the controlled characteristic to the first clock signal further comprises:

generating a control signal as a function of the clock harmonic; and adding the jitter according to the control signal to the first clock signal to generate the second clock signal.

13. The method of claim 1 1, wherein adding the jitter of the controlled characteristic to the first clock signal further comprises:

adding a variable delay to the first clock signal to generate the second clock signal.

14. The method of claim 13, wherein adding the variable delay to the first clock signal further comprises:

delaying the first clock signal via a delay chain of multiple delay elements.

15. The method of claim 14, further comprising:

varying a selection of one of the delay elements to output the second clock.

16. The method of claim 15, further comprising:

generating a sequence of selection codes to control the edge selector to vary the selection of the delay elements.

17. The method of claim 16, further comprising:

generating the sequence of the selection codes to vary the selection of the delay elements in a random manner.

18. The method of claim 14, further comprising:

calibrating the additional amount of delay added by each delay element to suppress the clock harmonic.

19. The method of claim 1 1, wherein adding the jitter of a controlled characteristic to the first clock signal to generate the second clock signal further comprises:

adding the jitter of the controlled characteristic to convert a power at the clock harmonic to spurs out of a radio frequency band of interest.

20. The method of claim 1 1, adding the jitter of a controlled characteristic to the first clock signal to generate the second clock signal further comprises:

adding the jitter of the controlled characteristic to convert a power at the clock harmonic to a noise floor.