KR100844960B1 - A spread spectrum clock generator - Google Patents

Abstract

A spread spectrum clock generator is provided to simplify a configuration of the spread spectrum clock generator by generating a spread spectrum clock by applying a triangular modulation waveform on a delay terminal as a control voltage. A spread spectrum clock generator(400) comprises as follows. A multiple-DLL(Delay Locked Loop)(410) receives a reference clock and outputs 2n+1 multiple clocks of different phases, when locked. One end of a first switch(420) is connected to the multiple-DLL and the first switch is turned off when the multiple-DLL is locked. One end of a second switch(430) is connected to the other end of the first switch, and the second switch is turned on when the multiple-DLL is locked. A loop filter(440) is connected to the other end of the first switch. A delay terminal(450) is connected to the other end of the first switch and the loop filter, receives the reference clock, and outputs 2n+1 multiple clocks of different phases. A charge pump(460) is connected to the other end of the second switch. A charge pump controller(470) is connected to the charge pump and receives an (N-K)-th clock and an (N+K)-th clock from the multiple-DLL and an N-th clock from the delay terminal, when the multiple-DLL is locked. The charge pump controller compares the (N-K)-th clock with the (N+K)-th clock and outputs a triangular up/down signal to the charge pump. The charge pump controller adjusts the N and K values.

Description

Spread Spectrum Clock Generator {A SPREAD SPECTRUM CLOCK GENERATOR}

The present invention relates to a Spread Spectrum Clock Generator (SSCG), and more particularly to a multi-phase of a Voltage Controlled Delay Line (VCDL) of a delay locked loop (DLL). By using a triangular modulation waveform by applying a control voltage of another locked voltage control delay stage (VCDL) to generate a spread spectrum clock, thereby simplifying the structure, And a spread spectrum clock generator (SSCG) with improved power consumption and easy design changes.

As the frequency of operation and increase in the number of data input bits between various information devices has been increased, a high frequency clock signal generated from a VCO, which is an internal block of a phase locked loop (PLL), is required for timing data at an interface between data transmission and reception. Electromagnetic interference (EMI) is prominently generated, which causes malfunctions in peripheral circuits, thereby causing side effects in transmission and reception of interface devices and data. Among various methods for reducing such EMI, a spread spectrum clock generator is known to effectively reduce EMI by reducing the power density of the output frequency of the output signal by using spectrum spread of the output signal frequency. SSCG is not only applied to high-speed interface circuits in computer boards such as Serial Advanced Technology Attachment (II-II), but also widely used in computer peripherals and LCD panels.

Most commonly used SSCGs use Σ-Δ modulators and functional N-dividers to spread the spectrum of the output frequency by periodically changing the division ratio. Modulation method is used. 1 is a block diagram illustrating an example of an SSCG of a divider modulation scheme. The SSCG 100 of the divider modulation scheme having the structure shown in FIG. 1 can be easily spread by using the Σ-Δ modulator 150 and the functional N-divider 140 to adjust the division ratio. δ) and the modulating waveform, while the Σ-Δ modulator 150 and the functional N-divider 140 used for modulation are complex digital circuits, so that the chip is actually manufactured. The disadvantage is that the total area of the SSCG 100 is greatly increased. FIG. 2 is a diagram illustrating an area occupied by a Σ-Δ modulator in an SSCG of a divider modulation scheme. 2, the phase locked loop (PLL) 210 and the address generator 220 determine how large the Σ-Δ modulator 230 occupies in the total area 200 when the divider modulation scheme is adopted. It can confirm by comparing with the area to occupy. Table 1 shows the general chip area of the SSCG of the divider modulation method. When designing the SSCG of the divider modulation method using a 0.18 um CMOS process from Table 1, the chip area is more than 1.00 mm × 1.00 mm. You can check it.

author fair Modulation method Chip Area (with Loop Filter) Wei-Ta Chen 0.18 um Σ-Δ modulation 1.00mm × 1.00mm Hyun Rok, Lee 0.18 um Σ-Δ modulation 0.94mm × 1.75mm Masaru kokubo 0.15 um Σ-Δ modulation 0.88mm × 0.48mm

In addition to the SSCG of the frequency division modulation method described above, SSCGs of various modulation methods have been studied. Among them, the SSCG of the charge pump modulating method adds only a charge pump to the structure of a general phase locked loop (PLL). It is expected to solve the area problem. 3 is a block diagram of the SSCG 300 of the conventionally proposed charge pump modulation scheme. As shown in FIG. 3, the SSCG 300 of the charge pump modulation scheme further includes a programmable charge pump II 350 in addition to the existing charge pump I 320. As mentioned above, although the charge pump modulation SSCG is expected to solve the area problem of the existing SSCG, the charge pump modulation SSCG proposed so far has some problems. First, it has a very complex structure because it is designed for too many application targets, and thus has a larger area than the existing SSCG. Second, because the diffusion rate is adjusted by adjusting the fine current, the regulation of the current is very sensitive to the operation of the circuit. Finally, it has a simple triangle modulation profile (Triangle Modulation Profile) has a problem that the power density by frequency at the maximum spreading frequency is larger than the average power density value.

Therefore, there is a need to develop a spread spectrum clock generator that is simpler than a conventional spread spectrum clock generator (SSCG), improves chip area and power consumption, and is easy to change design.

The present invention has been proposed to solve the above problems of the conventionally proposed methods, and is further locked by using the multi-phase of the voltage controlled delay stage (VCDL) of the delay locked loop (DLL). By generating a spread spectrum clock by applying a triangulation modulated waveform to the control voltage of the voltage controlled delay stage (VCDL), the spread spectrum clock generator is simple in structure, improved chip area and power consumption, and easy to change design. Its purpose is to provide (SSCG).

In addition, it is easy to control the spreading ratio by adjusting the modulation frequency and swing width, and thus spread spectrum that can easily generate a spread clock based on a constant clock on various chips operating at high speeds over a giga band. Its purpose is to provide a clock generator.

Spread Spectrum Clock Generator (SSCG) according to a feature of the present invention for achieving the above object,

(1) a multi-phase delay locked loop (DLL) for receiving a reference clock and outputting multiple clocks having different phases of 2n + 1 (n: natural numbers) when locked;

(2) a first switch having one end connected to the multi-phase delay locked loop and switched off when the multi-phase delay locked loop is locked;

(3) a second switch having one end connected to the other end of the first switch and switched on when the multi-phase delay locked loop is fixed;

(4) a loop filter connected to the other end of the first switch;

(5) a delay stage connected to the other end of the first switch and the loop filter and receiving a reference clock and outputting multiple clocks having different phases of 2n + 1 (n: natural numbers);

(6) a charge pump connected to the other end of the second switch; And

(7) NKth clock and N + of the 2n + 1 (n: natural numbers) clocks output from the multi-phase delay locked loop when connected to the charge pump and the multi-phase delay locked loop is fixed; Receives a K-th clock as an input, receives an N-th clock among the 2n + 1 (n: natural numbers) clocks outputted from the delay stage, and receives the N-th clock as the NK-th clock and the N + K. The configuration is characterized by including a charge pump control unit for outputting an up / down signal in the form of a triangular wave to the charge pump by comparing with the first clock.

Preferably, a multi-phase phase locked loop (PLL) may be included in place of the multi-phase delay locked loop.

Preferably, the loop filter is composed of a capacitor, and it is possible to adjust the capacitance value of the capacitor.

Preferably, N and K are adjustable in the charge pump control unit.

Advantageously, said multi-phase delay locked loop or said multi-phase phase delay loop comprises a second charge pump and a second loop filter, wherein said one end of said first switch is said second charge pump and said second filter. Connected between loop filters.

The present invention uses a multi-phase of the voltage-controlled delay stage (VCDL) of the multi-phase delay locked loop (DLL) to form a triangular modulation waveform with the control voltage of another voltage-controlled delay stage (VCDL) that is locked. By generating a spread spectrum clock by applying a C, it is possible to provide a spread spectrum clock generator (SSCG) whose structure is simple, chip area and power consumption are improved, and design change is easy.

In addition, the spread spectrum clock generator according to the present invention is easy to adjust the spreading ratio by adjusting the modulation frequency and the swing width, and accordingly a clock spread based on a constant clock on various chips operating at high speeds over a giga band. Easy to create.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

4 is a diagram illustrating a configuration of a spread spectrum clock generator 400 according to an embodiment of the present invention. As shown in FIG. 4, the spread spectrum clock generator 400 according to an embodiment of the present invention receives a reference clock Ref and, when fixed, has 2n + 1 (n: natural numbers) phases different from each other. A multi-phase delay locked loop 410 that outputs multiple clocks (clk0 to clk14), one end of which is connected to the multi-phase delay locked loop 410, and the switch when the multi-phase delay locked loop 410 is fixed A first switch 420 which is turned off, one end of which is connected to the other end of the first switch 430, and a second switch 430 that is switched on when the multi-phase delay locked loop 410 is fixed; It is connected to the loop filter 440 connected to the other end of the first switch 420, the other end of the first switch 420, and the loop filter 440. The reference clock Ref is input to 2n + 1 (n: natural number). Delay stage 450 for outputting multiple clocks S_clk0 to S_clk14 having different phases, charge pump 460 connected to the other end of second switch 430, and NKth clock of 2n + 1 (n: natural number) clocks connected to the lower pump 460 and outputted from the multi-phase delay locked loop 410 when the multi-phase delay locked loop 410 is fixed. Receives the N + K-th clock as input, receives the N-th clock of the 2n + 1 (n: natural number) clocks output from the delay stage 450 as a feedback, the N-th clock is the NK-th clock and N + K And a charge pump controller 470 for outputting an up / down signal in the form of a triangular wave to the charge pump 460.

The multi-phase delay locked loop 410 uses an existing DLL as it is, and receives a reference clock (Ref), and when it is fixed, multiple clocks having different phases of 2n + 1 (n: natural numbers) (clk0 to clk14) ) Outputs 5 is a diagram illustrating one embodiment of a multi-phase delay locked loop 410 constituting a spread spectrum clock generator 400 in accordance with the present invention. As shown in FIG. 5, the multi-phase delay locked loop 410 according to an embodiment of the present invention may include a phase detector 411, a charge pump 413, a loop filter 415, and a delay stage. 417, and a false lock detector 419. According to an embodiment, a multi-phase delay locked loop (PLL) may be included in place of the multi-phase delay locked loop 410, and the first switch 420 may include a multi-phase delay locked loop. Or between the loop pump 415 and the charge pump 413 of the multi-phase phase delay loop.

The first switch 420 and the second switch 430 serve to make a different circuit configuration based on before and after the multi-phase delay locked loop 410. That is, the first switch 420 is turned on before the multi-phase delay locked loop 410 is fixed, so that the loop filter 440 and the delay stage 450 are connected to the multi-phase delay locked loop 410. The same clock signal is output from the multi-phase delay locked loop 410 and the delay stage 450. After the multi-phase delay lock loop 410 is locked, the upper multi-phase delay lock loop 410 is turned off by the first switch 420 off, so that the lower loop filter 440 and the delay stage 450 are closed. And the second switch 430 is turned on, so that the lower charge pump 460 and the charge pump controller 470 form a circuit together with the loop filter 440 and the delay stage 450 so that the upper portion A part of the output clock signal of the multi-phase delay locked loop 410 is received as an input to generate a clock of the spread spectrum in the delay stage 450.

The loop filter 440 is connected to the other end of the first switch 420 and, as shown in FIG. 4, is composed of a capacitor and may adjust the capacitance value of the capacitor.

The delay stage 450 adopts a conventional general delay stage configuration, is connected to the other end of the first switch 420 and the loop filter 440, and receives a reference clock Ref to receive 2n + 1 (n Outputs multiple clocks (S_clk0 to S_clk14) with different phases.

The charge pump 460 is connected to the other end of the second switch 430, and adjusts the control voltage of the delay stage 450 in accordance with the control signal (triangular wave form up / down signal) of the electric wave pump control unit 470. Play a role.

The charge pump control unit 470 is connected to the charge pump 460 and outputs 2n + 1 (n: natural number) from the multi-phase delay lock loop 410 when the multi-phase delay lock loop 410 is fixed. The NK-th clock and N + K-th clocks of the four clocks are input, and the N-th clock of the 2n + 1 (n: natural number) clocks output from the delay stage 450 is input as feedback, and the N-th clock is received. Is compared with the NKth clock and the N + Kth clocks, thereby outputting a triangular wave form up / down control signal to the charge pump 460.

The spread spectrum clock generator proposed in the present invention utilizes an existing DLL structure to apply a modulated waveform in the form of a triangular wave to a control voltage of a voltage controlled delay stage (VCDL), thereby generating a clock of a spread spectrum. In particular, the spread ratio can be easily adjusted according to the order of the clocks being compared.

As shown in FIG. 6, the clock generated in the voltage control delay stage VCDL in a typical DLL generates multi-phase by the order according to the order of the voltage control delay stage. The present invention is designed based on such a multi-phase DLL, and uses a multiple phase of the voltage control delay stage of the DLL to change the control voltage of another fixed voltage control delay stage.

In the present invention, the diffusion ratio is determined by the N-K clock and the N + K clock input to the lower charge pump controller. In addition, the modulation frequency generated in the present invention is determined by the capacitance values of the charge pump and the loop filter of the compared clock, and the modulation frequency is adjusted by changing the capacitance of the loop filter and fixing the charge pump. Can be.

As described above, the spread spectrum clock generator according to the present invention includes a general DLL block in the upper portion and a lower block in which a triangular wave is input to the control voltage of the voltage control delay stage by operating after the upper DLL block is fixed. . In order to generate a triangular wave to be input to the voltage control delay stage, two fixed clocks taken from the upper DLL are compared with one clock fed back from the lower voltage control delay stage. The spreading ratio is determined by the N-K clock and the N + K clock selected from the output of the upper DLL block. That is, the range for generating the clock of the spread spectrum from the spread spectrum clock generator is defined as NK <N <N + K (K <N / 2), so that the spreading range increases as the K value increases. do.

7 is a diagram illustrating an embodiment of a charge pump control unit 470 constituting the spread spectrum clock generator 400 according to the present invention. As shown in FIG. 7, the charge pump control unit 470 controls the voltage of the second voltage control delay stage VCDL between the NK clock and the N + K clock based on the clock of the first voltage control delay stage VCDL. The signal is changed to determine the diffusion ratio and generate the up / down signals required for the charge pump input.

8 to 10, a method of generating an up / down signal in the charge pump controller 470 will be described. 8 shows a case where the clock S_clk8 from the lower delay stage 450 exists between the two clocks clk7 and clk9 from the upper multi-phase delay locked loop 410, and the up signal is also down. The figure shows a case where no signal is generated. As can be seen from clk7, clk9 and S_clk8, the examples of FIGS. 8 to 10 are cases where N = 8 and K = 1. 9 shows the case where the clock S_clk8 from the lower delay stage 450 is slower than the two clocks clk7 and clk9 from the upper multi-phase delay locked loop 410, in which case the down signal is generated. Done. Finally, FIG. 10 shows a case where the clock S_clk8 from the lower delay stage 450 is faster than the two clocks clk7 and clk9 from the upper multi-phase delay locked loop 410. Will generate a signal.

In the present invention, the frequency of the modulation profile of the control voltage to be applied to the delay stage 450 is determined by the capacitance values of the charge pump 460 and the loop filter 440 as shown in Equation 1 below. .

In the embodiment of the present invention, since the loop filter 440 constitutes a primary loop, if the charge pump is fixed, the modulation frequency may be determined by the ratio of capacitances. In particular, when doubling the value of capacitance, the modulation frequency is increased by four times. Due to the characteristics of the charge pump control unit 470, since charges are pumped to the up / down signals, respectively, the increase of the capacitance value is four times the effect of maximizing the capacitance effect, and thus the main area of the chip area. The effect of reducing the size of the capacitance that occupies can be expected.

FIG. 11 is a diagram illustrating a simulation result of a spread spectrum clock generator according to an exemplary embodiment of the present invention, and illustrates a simulation result of a control voltage of a lower delay stage after an upper multi-phase delay locked loop is fixed. FIG. 12 is an enlarged view of a triangular modulation waveform portion of FIG. 11.

FIG. 13 shows the frequency domain of the output signal of the upper multi-phase delay locked loop, and thus the analysis of dbm, showing the energy distribution of the clock rather than the spread spectrum. 14 is a diagram illustrating frequency analysis and dbm, that is, energy distribution of an output signal of a lower delay stage. Comparing FIG. 13 and FIG. 14, it can be seen that the energy distribution of the spread spectrum clock is about 10 dbm lower than that of the clock having no spread spectrum form.

15 is a diagram illustrating a layout of a spread spectrum clock generator according to an embodiment of the present invention, designed using the TSMC 018 process. According to the layout design results, the capacitance used can be reduced to 400pF, and as a result, the chip area can be significantly reduced to 0.45 X 0.55. Table 2 summarizes the performance of a spread spectrum clock generator according to an embodiment of the present invention.

SSCG frequency 50 MHz Technology TSMC 0.18 um CMOS Modulation method Modulation on VCO Modulating waveform 30 to 33 kHz Frequency deviation 1.5 to 3% down Jitter (Non-SSC) 7 ps Supply voltage 1.8 V

The present invention described above may be variously modified or applied by those skilled in the art, and the scope of the technical idea according to the present invention should be defined by the following claims.

1 is a block diagram illustrating an example of an SSCG 100 of a divider modulation scheme.

Fig. 2 is a diagram showing the area occupied by the Σ-Δ modulator 230 in the SSCG of the divider modulation scheme.

3 is a block diagram of an SSCG 300 of a conventionally proposed charge pump modulation scheme.

4 illustrates a configuration of a spread spectrum clock generator 400 according to an embodiment of the present invention.

5 illustrates one embodiment of a multi-phase delay locked loop 410 constituting a spread spectrum clock generator 400 in accordance with the present invention.

6 illustrates a multi-phase clock generated at a voltage controlled delay stage (VCDL) in a typical DLL.

7 illustrates an embodiment of a charge pump control unit 470 constituting a spread spectrum clock generator 400 in accordance with the present invention.

8 to 10 are diagrams for explaining the principle of generating an up / down signal in the charge pump control unit 470 constituting the spread spectrum clock generator 400 according to the present invention.

FIG. 11 is a diagram illustrating a simulation result of a spread spectrum clock generator according to an embodiment of the present invention, and illustrates a simulation result of a control voltage of a lower delay stage after an upper multi-phase delay locked loop is fixed.

12 is an enlarged view of a triangular modulation waveform portion of FIG. 11;

FIG. 13 shows the frequency domain of the output signal of the upper, multi-phase delay locked loop, and thus the analysis of dbm, showing the energy distribution of the clock rather than the spread spectrum;

14 is a diagram showing frequency analysis of the output signal of the lower delay stage and dbm, that is, energy distribution.

15 illustrates a layout of a spread spectrum clock generator in accordance with an embodiment of the present invention, designed using the TSMC 018 process.

<Explanation of symbols for main parts of the drawings>

100 : (conventional) divider modulation SSCG

110: Phase Frequency Detector (PFD)

120: charge pump (CP)

130: oscillator

140: Functional N-Divider

150: Σ-Δ modulator

160: reference clock

170: output clock (with spread)

200 : whole chip

210: Phase Locked Loop (PLL)

220: address generator

230: Σ-Δ modulator

300 : SSCG of charge pump modulation

310: phase frequency detector (PFD)

320: charge pump I (CP I)

330: Voltage Control Oscillator (VCO)

340: Programmable Divider

350: Programmable CP II

400 : SSCG (according to one embodiment of the present invention)

410: multi-phase delay locked loop

420: first switch

430: second switch

440 loop filter

450: (voltage control) delay stage

460: charge pump

470: charge pump control unit

Claims (5)

(1) a multi-phase delay locked loop (DLL) for receiving a reference clock and outputting multiple clocks having different phases of 2n + 1 (n: natural numbers) when locked; (2) a first switch having one end connected to the multi-phase delay locked loop and switched off when the multi-phase delay locked loop is locked; (3) a second switch having one end connected to the other end of the first switch and switched on when the multi-phase delay locked loop is fixed; (4) a loop filter connected to the other end of the first switch; (5) a delay stage connected to the other end of the first switch and the loop filter and receiving a reference clock and outputting multiple clocks having different phases of 2n + 1 (n: natural numbers); (6) a charge pump connected to the other end of the second switch; And (7) NKth clock and N + of the 2n + 1 (n: natural numbers) clocks output from the multi-phase delay locked loop when connected to the charge pump and the multi-phase delay locked loop is fixed; Receives a K-th clock as an input, receives an N-th clock among the 2n + 1 (n: natural numbers) clocks outputted from the delay stage, and receives the N-th clock as the NK-th clock and the N + K. A charge pump control unit for outputting a triangular wave form up / down signal to the charge pump by comparing with the first clock; Including; Spread Spectrum Clock Generator (SSCG), characterized in that the charge pump control unit can adjust the values of N and K. The method of claim 1, And a multi-phase phase locked loop (PLL) in place of the multi-phase delay locked loop. The method of claim 1, The loop filter is composed of a capacitor, the spread spectrum clock generator capable of adjusting the capacitance value of the capacitor. delete The method according to claim 1 or 2, The multi-phase delay lock loop or the multi-phase phase delay loop includes a second charge pump and a second loop filter, wherein one end of the first switch is between the second charge pump and the second loop filter. Spread-Spectrum Clock Generator Connected.

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