JP2001202153A - Spread spectrum circuit for clock, integrated circuit and spread spectrum method for clock - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily adjust the spread width, the shape and the radiation level of a spectrum of an unnecessary signal. SOLUTION: In this spread spectrum signal for clock, an internal clock 124 is generated by switching an output 122 of a delay element 102 as a delayed clock and a system clock 121 inputted from the outside by defining an outputted signal of a pseudo random signal generator 104 as a control signal by a selector 103.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock spread spectrum circuit, and more particularly, to an embedded CPU system capable of reducing the transmission level of unnecessary electromagnetic waves.
It relates to things related to SI and electronic equipment.

[0002]

2. Description of the Related Art In recent years, with the development of integrated circuit parts and the like, electronic equipment has become easier to realize smaller and higher frequency than ever before. With the development of such electronic devices, electronic devices, especially from the power supply of the LSI, tend to generate and radiate various harmonic signals and the like more than ever, apart from the signals originally output, Various influences on peripheral electronic devices are no longer ignored.

On the other hand, as described above, LS having a high operating frequency is used.
Electronic devices in which I components and the like are arranged at high density tend to be more sensitive to so-called electromagnetic interference radiated from peripheral electronic devices than ever. For this reason, in recent years, in electronic devices, so-called EMC (Electro) has been proposed in which the radiation level of electromagnetic interference is suppressed as much as possible and the influence of external electromagnetic interference is reduced.
It is more important than ever to take Magnetic Compatibility measures.

Conventionally, USP 5,488,627 U
SP 5,631,920 USP 5,867,5
As described in US Pat. No. 5,872,807, E uses a clock generator for spreading the spectrum.
MC measures were taken.

FIG. 3 shows a block diagram of a conventional clock generator. This clock generator is a so-called PLL
(Phase Locked Loop) This is based on a frequency synthesizer, and compares the phase and frequency of a reference clock generator 301 serving as a reference frequency source with the output signal of this reference clock and a programmable divider (PG DIV) 305. , A phase comparator 302 for outputting a voltage signal according to the comparison result, and a low-pass filter (LPF) 303 as a so-called loop filter
A voltage controlled oscillator (VCO) 304 whose oscillation frequency changes according to the voltage of the comparison result of the phase comparator input through the low-pass filter 303;
4 and a programmable divider 305 capable of varying the frequency division ratio under external control and outputting the desired frequency, so that the output frequency of the voltage controlled oscillator 304 spreads the desired spectrum. And a spreading frequency control unit 306 for controlling the frequency division ratio of the programmable divider 305. Note that VCO 304
Is used as an operation clock of an integrated circuit (not shown).

The operation of the conventional clock generator having such a configuration is as follows. That is, the frequency of the reference clock from the reference clock generator 301 is set to F
Assuming that s, the dividing ratio set in the programmable divider 305 is M, and the frequency of the output clock from the voltage controlled oscillator 304 is Fc, Fc = M × Fs.

Further, by controlling the frequency division ratio M of the programmable divider 305 by a predetermined method, the frequency Fc of the output clock changes, and the spectrum is spread.

[0008]

However, in the above-described conventional example, the output frequency is inadequate due to individual variations and external noise because the configuration is complicated and the voltage controlled oscillator and the phase comparator are analog circuits. May be stable.

The present invention has been made to solve this problem and stably suppresses unnecessary signal radiation to a sufficient level without complicating the circuit configuration. A clock spread spectrum circuit and a clock spread spectrum method are provided. Furthermore, since the configuration is simple, the L
Provided are a clock spread spectrum circuit and a clock spread spectrum method that can easily adjust the spread width and shape of the spectrum of an unnecessary signal and its radiation level for each LSI in accordance with SI, electronic equipment, and its environment. The purpose is to do.

[0010]

In order to achieve the above object, a first aspect of the present invention (corresponding to claim 1) is to delay a clock input from a clock generator and output this as a delayed clock. A delay element, a selector that receives an input of the clock or the delay clock, selects and outputs one of the clocks, and a pseudo-random signal generator that generates a pseudo-random signal for controlling output of the selector. This is a clock spread spectrum circuit.

According to this, the clock output from the selector is pseudo-randomly phase-modulated and spread spectrum. By supplying the clock to the LSI, the line spectrum originally radiated from the LSI has a spread width, and the level of the spectrum is reduced by a simpler configuration than in the related art due to the spread of the spectrum.

Further, the second invention (corresponding to claim 2)
A variable delay element for delaying a clock input from a clock generator and outputting the delayed clock as a variable delay clock, and a pseudo random signal for generating a pseudo random signal for controlling the delay time of the variable delay element. A clock spread spectrum circuit comprising a signal generator.

Thus, the clock output from the variable delay element is pseudo-randomly phase-modulated and spread spectrum. By supplying the clock to the LSI, the line spectrum originally radiated from the LSI has a spread width, and the level of the spectrum is reduced by a simpler configuration than in the related art due to the spread of the spectrum.

A third aspect of the present invention (corresponding to claim 3)
The invention is characterized in that the delay element can set a delay time arbitrarily in advance.

Thus, the clock output from the selector is phase-modulated and spread spectrum.
Since the delay time can be set, the maximum phase amount to be phase-modulated can be optimally selected, and optimization can be achieved for LSIs and electronic devices to be used.

A fourth aspect of the present invention (corresponding to claim 4)
The present invention is characterized in that the random signal generator selects any one of a plurality of pseudo random signals and outputs the selected signal as the pseudo random signal.

Thus, the pseudo-random signal is not a completely random signal but a repetition of a code string having a fixed period, and the spread width and shape of the spectrum change according to the selected pseudo-random signal. It is possible to select a pseudo-random signal that is most suitable for an LSI or electronic device to be used.

The fifth invention (corresponding to claim 5)
Means that the random signal generator has a pseudo noise (Pseudo
o Noise) The present invention is characterized by using a code generation circuit.

Thus, pseudo noise (Pseudo N)
Oise) By using a code generation circuit, a pseudo-random signal generator can be realized more easily.

The sixth invention (corresponding to claim 6)
According to the present invention, the operation of at least the delay element or the variable delay element and the pseudo-random signal generator can be set from a CPU external to the main body.

Thus, in an electronic device using a CPU, setting of a delay time,
A pseudo-random signal can be selected and can be optimized depending on the electronic device used.

A seventh aspect of the present invention (corresponding to claim 7)
Is built in the integrated circuit, and the output from the selector is
The present invention is the internal clock of the integrated circuit.

Thus, by incorporating the electronic circuit of the present invention into each integrated circuit, it is possible to spread the internal clock spectrum optimally for each integrated circuit.

The eighth invention (corresponding to claim 8)
Is an integrated circuit incorporating a clock spread spectrum circuit according to the present invention.

A ninth aspect of the present invention (corresponding to claim 9)
Delays a clock input from a clock generator, outputs the delayed clock as a delayed clock, receives the clock or the input of the delayed clock, selects one of the two, and outputs the selected clock; and And a pseudo-random signal generator step of generating a pseudo-random signal for performing output control.

According to this, the clock output from the selector is pseudo-randomly phase-modulated and spread spectrum. By supplying the clock to the LSI, the line spectrum originally radiated from the LSI has a spread width, and the level of the spectrum is reduced by a simpler configuration than in the related art due to the spread of the spectrum.

According to a tenth aspect of the present invention, there is provided a variable delay step for delaying a system clock input from a clock generator and outputting the delayed system clock as a delay clock having a variable delay time. A pseudo-random signal generation step of generating a pseudo-random signal for controlling a delay time of an element.

Thus, the clock output from the selector step is pseudo-randomly phase-modulated and spread spectrum. By supplying the clock to the LSI, the line spectrum originally radiated from the LSI has a spread width, and the level of the spread is reduced by a simpler method as compared with the related art.

According to an eleventh aspect of the present invention (corresponding to claim 11), there is provided a program and a program for causing a computer to execute all or a part of the functions of all or part of the clock spread spectrum circuit of the present invention. And / or a computer-readable program recording medium on which data is recorded.

A twelfth invention (corresponding to claim 12) provides a program and a program for causing a computer to execute all or some of all or some of the steps of the clock spread spectrum method of the present invention. And / or a computer-readable program recording medium on which data is recorded.

According to the present invention described above, a clock spread spectrum circuit which can surely suppress unnecessary signal emission to a sufficient level without complicating the original circuit configuration, and a clock spread circuit. A spread spectrum method and a principal circuit using the same can be provided.

[0032]

Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1) FIG. 1 is a diagram showing a configuration of a clock spread spectrum circuit according to Embodiment 1 of the present invention. In FIG. 1, reference numeral 101 denotes a clock generator that supplies a system clock 121 to an LSI, 102 denotes a delay element that delays the system clock 121 input to the LSI, outputs a delayed clock 122, and sets the delay time, and 103 denotes a delay element. A selector for selecting and outputting a clock 122 or an externally input system clock 121; 104, a pseudo-random signal generator capable of generating a plurality of pseudo-random patterns as control signals for the selector 103; A CPU interface for setting a delay time to 102 and setting a pseudo-random signal generator 104 to generate a specific pseudo-random pattern from among a plurality of pseudo-random patterns. An internal clock 106 is an output of the selector 103. The original LSI that operates on 124 Ability circuit, 107 incorporating a spread spectrum circuit of the clock of this embodiment LSI, 108 are CPU (Central Pr
processor Unit).

FIG. 5A shows an embodiment of the pseudo random signal generator 104, in which pseudo noise (Pseudo No.
FIG. 3 is a diagram showing a configuration of a pattern generating circuit having a period of 511 bits called PN9, which is a type of code.
In the figure, reference numerals 501 to 509 denote D-type flip-flops which operate in the falling edge of a clock, and constitute a nine-stage shift register by cascade connection. 521
Is a clock for the shift register, and the selector 1
Considering the switching timing of the clock 03, it is better to use the output of the delay element 102 and the delay clock 122. 512 is an XOR (exclusive OR), and the shift register has a register 509 at the last stage and an XOR (exclusive OR).
The register values of the preceding registers 503, 504, 506 are set to X
OR and give feedback. By making the XOR position and the number of shift register stages variable, a plurality of pseudo-random patterns can be generated. Therefore, the size of the spectrum and the width and shape of the diffusion can be selected according to the selected pseudo-random pattern.

FIG. 4 is a circuit diagram of one embodiment of the delay element 102. In the figure, reference numerals 401 to 407 denote buffers that do not invert the clock, 421 to 426 denote resistors,
Reference numerals 11 to 416 indicate capacitors, reference numerals 441 to 446 indicate grounds, and reference numerals 431 to 437 indicate delayed clock outputs.
431 to 437 cascading n stages of circuits for dulling a clock waveform by a resistor and a capacitor, shaping the waveform by a buffer, and generating a delay by n stages.
To generate a delayed clock. Therefore, the delay time can be selected by setting which delay clock is output. In the case of a high-speed clock, the delay time of the buffer itself is sufficient even without a resistor and a capacitor, and can be realized by cascade connection of only the buffer.

The operation of the clock spread spectrum circuit according to the first embodiment of the present invention having the above-described configuration will be described with reference to signal waveforms shown in FIG. 5 (b). The spread spectrum method will be described. However, in FIG. 1 and FIG. 5B, the signal waveform 521 is an output from the clock generator 101, and the system clock 121 and the signal waveform 522
Is the output of the delay element 102, the delayed clock 122 and the signal waveform 523 are the outputs of the pseudo random signal generator 104, and the pseudo random signal 1 using the PN9 pattern generator.
23 and the signal waveform 524 are the outputs of the selector 103,
This indicates the internal clock 124.

First, when the pseudo random signal 123 is at the high level, the selector 103 sets the system clock 12
1 is selected and output. When the pseudo random signal 123 is at a low level, the delay clock 122 is selected and output.

Through the above steps, the internal clock 124 has the signal waveform 524. This signal waveform 524 causes spread spectrum when phase modulated. As a result, an effect similar to that of the frequency modulation described in the conventional example appears, and LS
The spectrum radiated from I is, for example, as shown in FIG.
As shown in FIG. 3, the fundamental wave is Fo, the second harmonic is 2Fo, and the third harmonic is 3F in a so-called line spectrum.
o,..., n-th harmonic nFo
As shown in (b), the individual frequencies Fo, 2Fo,
It has a diffusion width centered on 3Fo,..., NFo, and the level is reduced by the spread of the spectrum. Moreover, the configuration of the entire diffusion circuit can be realized with a simple configuration as compared with the conventional configuration.

By the way, the spectrum of an unnecessary signal differs depending on an electronic device such as an LSI to which a spread spectrum circuit of a clock is used or an environment thereof, or depending on a method of spread spectrum, an LSI may be used.
In some cases, the original performance of the electronic device may be adversely affected. On the other hand, in the present embodiment, the CPU 108
By setting an optimum delay time for the delay element 102 via the U interface 105 and setting the pseudo-random signal generator 104 to generate an optimum pseudo-random pattern among a plurality of pseudo-random patterns, There is an effect that the system can be optimized as well as the diffusion width, shape and level.

(Embodiment 2) FIG. 2 is a diagram showing a configuration of a clock spread spectrum circuit according to Embodiment 2 of the present invention. In FIG. 2, reference numeral 201 denotes a clock generator that supplies a system clock 221 to the LSI, 202 denotes a delay of the system clock 221 input to the LSI,
An internal clock 224 is output and its delay time is changed. 203 is a pseudo-random signal generator capable of generating a plurality of pseudo-random signals as a control signal of the delay time of the variable delay element 202; Among them, a CPU interface for setting a specific pseudo-random pattern to be generated by the pseudo-random signal generator 203, and a functional circuit 206 that operates on the internal clock 224 output from the variable delay element 202 and has an original LSI function , 207 are LSIs incorporating the present invention, 2
05 is a CPU (Central Processor)
Unit).

The operation of the clock spread spectrum circuit according to the second embodiment of the present invention having the above configuration and the clock spread spectrum method of the present invention based on the circuit are as follows. That is, as shown in FIG. 4, since the variable delay element 202 can generate n kinds of delay times, the pseudo random signal generator 203 having a pseudo random signal having an n value causes the internal clock 224 to be n
It has various types of delay time, and its generation is random. This causes the internal clock 224 to spread spectrum when phase modulated.

As a result, in the same manner as described in the first embodiment, the second harmonic 2Fo, the third harmonic 3Fo, and the nth harmonic nFo where the fundamental wave originally radiated from the LSI is Fo. Has a spread width centered on each of the frequencies Fo, 2Fo, 3Fo,..., NFo, and the level is reduced by the spread of this spectrum. Moreover, the configuration of the entire diffusion circuit can be realized with a simple configuration as compared with the conventional configuration.

Further, the pseudo random signal generator 203
When a PN9 pattern generator having a simple circuit configuration as shown in FIG. 5A is used, since a pseudo random signal is binary, it is realized by individually assigning a specific delay time via a CPU interface. You.

In this embodiment, the operation of the pseudo-random signal generators 103 and 203 has been described as being realized by hardware. However, this operation is performed by a program using a computer and a software. May be realized.

It is needless to say that the clock spread spectrum circuit of the present invention may be an integrated circuit that operates on the output clock.

A program recording medium for recording a program and / or data for causing a computer to execute all or a part of the functions of a part of the clock spread spectrum circuit according to the present invention, wherein the program is read by the computer. The program and / or data read out may be realized as a program recording medium characterized in that the program and / or data execute the function in cooperation with the computer.

A program and / or a program for causing a computer to execute all or a part of the operations of all or a part of the clock spread spectrum method of the present invention.
Or a program recording medium on which data is recorded,
It may be realized as a program recording medium readable by a computer, wherein the read program and / or data execute the function in cooperation with the computer.

[0048]

As described above, according to the present invention, in particular, L
The unnecessary spectrum radiated from the SI can be spread, and the radiant energy of the unnecessary signal is dispersed, so that a so-called EMC countermeasure can be easily performed. In particular, in the present invention, the spread width, shape, level, etc. of the spectrum can be easily changed according to the requirements of the external hardware, and the versatility is high, and the radiation of unnecessary signals is reliably and sufficiently reduced. Can be suppressed.

[Brief description of the drawings]

FIG. 1 is a block diagram of an electronic circuit according to Embodiment 1 of the present invention.

FIG. 2 is a block diagram of an electronic circuit according to a second embodiment of the present invention.

FIG. 3 is a block diagram of a storage device according to a conventional embodiment.

FIG. 4 is a circuit diagram of a variable delay element according to an embodiment of the present invention.

5A is a circuit diagram of a pseudo-random signal generator according to an embodiment of the present invention. FIG. 5B is a signal waveform diagram according to an embodiment of the present invention.

6A is a line spectrum of an unnecessary signal in an original LSI, and FIG. 6B is a spread spectrum of an unnecessary signal in a circuit-mounted LSI of the present invention.

[Explanation of symbols]

 101, 201 clock generator 102 delay element 103 selector 104, 204 pseudo-random signal generator 105, 204 CPU interface 106, 206 functional circuit 107, 207 LSI 108, 205 CPU 121, 221 system clock 122 delay clock 123, 223 pseudo-random Signal 124, 224 Internal clock 202 Variable delay element 301 Reference clock generator 302 Phase comparator 303 Low-pass filter 304 Voltage controlled oscillator 305 Programmable frequency divider 306 Spread frequency control unit 401-407 Buffer 411-417 Capacitor 421-426 Resistor 431 To 437 Delayed clock output 441 to 446 Ground 501 to 509 D-type flip-flop 512 Excitable OR (XOR) 521 Voltage waveform of system clock 522 Voltage waveform of delayed clock 523 Voltage waveform of pseudo-random signal 524 Voltage waveform of internal clock

Claims (12)

[Claims] A delay element that delays a clock input from a clock generator and outputs the delayed clock as a delayed clock; a selector that receives the clock or the input of the delayed clock and selects and outputs one of the clock and the delayed clock; And a pseudo-random signal generator for generating a pseudo-random signal for controlling output of a selector. 2. A variable delay element for delaying a clock input from a clock generator and outputting the same as a delay clock having a variable delay time, and a pseudo random signal for controlling the delay time of the variable delay element. And a pseudo-random signal generator. 3. The clock spread spectrum circuit according to claim 1, wherein the delay element can arbitrarily set a delay time in advance. 4. The clock according to claim 1, wherein the random signal generator selects one of a plurality of pseudo random signals and outputs the selected signal as the pseudo random signal. Spread spectrum circuit. 5. The clock spread spectrum circuit according to claim 1, wherein the random signal generator uses a pseudo noise (Pseudo Noise) code generation circuit. 6. The operation setting of at least the delay element or the variable delay element and the pseudo-random signal generator from a CPU outside the main body. Clock spread spectrum circuit as described. 7. The clock spread spectrum circuit according to claim 1, wherein the output from the selector is a built-in clock of the integrated circuit. 8. An integrated circuit comprising the clock spread spectrum circuit according to claim 1. 9. A delay step of delaying a clock input from a clock generator and outputting the delayed clock as a delayed clock; a selecting step of receiving the clock or the input of the delayed clock and selecting and outputting one of the clock and the delayed clock; A pseudo-random signal generator for generating a pseudo-random signal for controlling the output of the selector. 10. A variable delay step of delaying a system clock input from a clock generator and outputting the delayed system clock as a delay clock having a variable delay time, and a pseudo random signal for controlling the delay time of the variable delay element. And generating a pseudo-random signal. 11. A program and / or data for causing a computer to execute all or a part of the functions of all or a part of the clock spread spectrum circuit according to claim 1. A program recording medium readable by a computer. 12. A computer recording a program and / or data for causing a computer to execute all or a part of all or part of the steps of the clock spread spectrum method according to claim 9 or 10. A program recording medium characterized by being readable.