EP0645785B1 - Electronic circuitry - Google Patents
Electronic circuitry Download PDFInfo
- Publication number
- EP0645785B1 EP0645785B1 EP94112865A EP94112865A EP0645785B1 EP 0645785 B1 EP0645785 B1 EP 0645785B1 EP 94112865 A EP94112865 A EP 94112865A EP 94112865 A EP94112865 A EP 94112865A EP 0645785 B1 EP0645785 B1 EP 0645785B1
- Authority
- EP
- European Patent Office
- Prior art keywords
- resistor
- electronic circuit
- resistors
- additional
- circuit according
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01C—RESISTORS
- H01C17/00—Apparatus or processes specially adapted for manufacturing resistors
- H01C17/22—Apparatus or processes specially adapted for manufacturing resistors adapted for trimming
Definitions
- the invention is based on an electronic circuit according to the Genus of the main claim. It is already known to be integrated Circuit to provide an electronic circuit that has multiple has resistors connected in parallel, each with a Fusible link, also called burning section, connected in series are, so that by deliberately burning individual burning sections an adjustable resistor is realized. This circuit is particularly applicable where only when the complete integrated circuit a determination of a certain resistance value is possible. To find resistance values in a wide range To be able to set are electronic for this Circuit very large resistance values necessary, which reduces the resistances a correspondingly large space on the substrate with the integrated Take circuit. Also known is the electronic Circuit as a series connection of resistors with smaller ones Execute resistance values, each bridging with a burning distance are, but with an increased circuit complexity for the Burning sections and their connection arises.
- the electronic circuit according to the invention with the characteristic Features of the main claim has the advantage that a low circuit outlay for fuses and their wiring arises and at the same time small resistance values are sufficient, to an adjustable resistor with great variability realize.
- the control of the thyristors via outputs of a shift register has the advantage that only a single input for the serial input of the programming data bit pattern is provided for a parallel control of a large number of thyristors, so that in particular in the case of already assembled integrated circuits, only one pin for the Control of all thyristors is sufficient.
- the design of the electronic circuit as an integrated circuit offers the advantage of being able to be integrated together with other circuits on a semiconductor substrate, as a result of which the production outlay is minimized.
- temperature-related effects for example, can have an equal effect on the electronic circuit and the further circuits, whereby compensation can be achieved.
- the electronic circuit can be used in particular for ohmic resistors, since in particular the electronic circuit reduces the space problem in these and the behavior of the resistors is improved in comparison with one another. This behavior includes, in particular, dependencies on temperature effects and piezoelectric effects as well as a voltage modulation caused by the pretensioning of the substrate. It also proves to be an advantage if the resistances have different values, since different combinations of conductive and non-conductive fuses lead to different overall resistance values, which increases the variability of the electronic circuit.
- the formation of the resistors in the form of diffused resistors of different lengths and the same width and depth leads to the advantage that approximately the same exposure parameters can be selected for the resistors with regard to the photolithography used for the production, which results in advantages in terms of mask variety, lateral diffusion and layout.
- the dimensioning rule in the form that the overall conductance of the electronic circuit, in which all fuses are in the conductive state, differs from the overall conductance of the electronic circuit, in which exactly one fuse is in the non-conductive state, by a power of two of a unit resistance value and that the exponent
- the selection of the number of additional resistors to the extent that mx R A is approximately equal to the value of the resistor which has no additional resistor parallel to the fuse connected in series with the resistor and has the highest number serves to advantageously dimension the circuit in such a way that An optimal ratio of additional resistors to the resistors is achieved in such a way that the resistance values of the individual resistors and additional resistors are close to each other, whereby the same structure and similar geometrical dimensions can be selected for the resistors and additional resistors, resulting in the advantage that the resistors and additional resistors, if they are designed as integrated resistors, have similar behavior with regard to voltage modulation, temperature dependence, piezoelectric effects.
- FIG. 1 shows a first exemplary embodiment of the electronic circuit with four resistors
- FIG. 2 shows a second exemplary embodiment of the circuit with a resistor and two switches
- Figure 3 shows a third embodiment of the circuit with thyristors and a shift register.
- a series circuit comprising a first fuse Q 0 and a first resistor R 0 is connected between two terminals A, B.
- a further series circuit comprising a further resistor R 1 and a further fuse Q 1 is connected in parallel with this series circuit.
- Also connected in parallel is a third series circuit with a third fuse Q 2 and a third resistor R 2 and a fourth series circuit with a fourth resistor R 3 and a fourth fuse Q 3 .
- the third fuse Q 2 is bridged by a first additional resistor R 2 '.
- the fourth fuse Q 3 is also bridged by means of a second additional resistor R 3 '.
- This circuit is provided in particular as an integrated circuit, wherein individual by controlled melting through fuses Q 0, Q 1, Q 2, Q 3, different values are set for the total measurable between the terminals A, B total conductance Y. Circuits of this type are used in particular when it is not yet possible to precisely set a conductance or resistance at the time the circuit is being designed or constructed. In the case of integrated circuits which are surrounded by a housing, a resistance can be set by selective melting of individual fuses Q 0 , Q 1 , Q 2 , Q 3 even after they have been installed in a housing. Thus, circuits influenced by the housing can be adjusted so that the influence of the housing is compensated or minimized.
- Figure 2 shows the representation of an electronic circuit with two switches.
- the series circuit comprising the first fuse Q 0 and the first resistor R 0 is connected between the terminals A, B.
- terminal A is connected via a first switch N to a connection to a positive programming voltage V prog, while the common connection of fuse Q 0 and resistor R 0 is connected to the negative operating potential V SS via a further switch M.
- the electronic circuit shown in Figure 3 also has the terminals A, B between which the first series circuit with the first fuse Q 0 and the first resistor R 0 is connected.
- further series connections follow, each with a further fuse Q 1 ... Q n + m and with a further resistor R 1 ... R n + m , with a number of m fuses Q n + 1 ... Q n + m an additional resistor R n + 1 '... R n + m ' is connected in parallel.
- a connection to a thyristor T 0 ... T n + m branches off between the fuses Q 0 ... Q n + m and the resistors R 0 ...
- a programming switch S prog is arranged between a positive programming potential V prog and the terminal A.
- a shift register S has a data input E, a clock input T and reset inputs X 0 ... X n + m .
- the shift register S has n + m + 1 stages, the outputs A 0 ... A n + m are each led to control inputs of the thyristors T 0 ... T n + m .
- a reset line is connected to each reset input X 0 ... X n + m .
- a bit pattern is pushed into the shift register controlled by the clock T via the data input E in the shift register while the programming switch S prog is still open.
- a reset pulse is sent via the reset input R to all reset inputs R 0 ... R n + m of the shift register S.
- the content of the entire shift register is set to logic 0, as a result of which all thyristors T 0 ... T n + m + 1 are in the blocked state.
- the programming switch S prog is closed and the programming potential V prog is present at terminal A. Ignition by means of the programming voltage V prog and the bit pattern causes each of the thyristors T 0 ... T n + m , to which a 1 is present via one of the outputs A 0 ... A n + m , to become conductive. As a result, a conductive path is connected between the positive programming potential V prog and the negative operating potential V SS via the fuses Q 0 ... Q n + m , for which the associated thyristor T 0 ... T n + m through the bit pattern of the data signal was ignited.
- the flowing melt current causes the selected fuses Q 0 ... Q n + m to melt. It is intended to ramp up the programming voltage to its maximum value so slowly that unintentional overhead ignition is avoided.
- the resistors R 0 ... R n + m have the following values: Each of the resistors R 0 ... R n + m which are connected in series to one of the Fuses Q 0 ... Q n + m that are not bridged by means of an additional resistor R n + 1 '... R n + m ' have the value 2 i x R D. The remaining resistors R n + 1 ...
- R n + m are assigned the value 1 / (1 / (2 i x R D ) + 1 / (mx R A )).
- i denotes the index, ie the number of the resistor R 0 ... R n + m , if the resistors R 0 ... R n + m starting from 0 up to the number of resistors R 0 ... R reduced by 1 n + m were numbered.
- the additional resistors R n + 1 '... R n + m ' are given the value 1 / (1 / (mx R A - 2 i x R D ) + 1 / (mx R A )).
- m is the number of additional resistors R n + 1 '...
- R n + m ' This dimensioning ensures that the minimum achievable limit value Y min for the total conductance Y total , which can be measured between the terminals A, B, is equal to the reciprocal value of R A.
- the maximum achievable limit value Y max for the total conductance Y total with an infinite number of series connections is 1 / R A + 2 / R D.
- the values for R A , R D and n + are thus used m.
- the total conductance Y total changes by the value 1 / (2 1 x R D ) when the fuse Q i melts.
- An optimization of the ratio of n to m is preferably obtained with the ratio at which the value of the resistor R 0 ... R n + m , the parallel to the fuse connected in series with the resistor R 0 ... R n + m Q 0 ... Q n + m has no additional resistance R n + 1 '... R n + m ' and which has the highest number, is equal to the value mx R A.
- a layout can be achieved by the optimization in which the resistors R 0 ... R n + m and additional resistors R n + 1 '... R n + m ' have approximately the same orders of magnitude, which means that the Resistors R 0 ...
- R n + m and additional resistors R n + 1 '... R n + m ' can be selected with regard to width and depth and the different values can only be achieved by changing the length.
- the behavior of the resistors R 0 ... R n + m and additional resistors R n + 1 '... R n + m ' is approximately identical, which is advantageous for the circuit design.
- the same circuit principle can also be used for complex resistors, for example capacitors or inductors.
- An example of an area of application for the electronic circuit is an integrated pressure sensor.
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
- Credit Cards Or The Like (AREA)
- Details Of Resistors (AREA)
Description
Die Erfindung geht aus von einer elektronischen Schaltung nach der Gattung des Hauptanspruchs. Es ist bereits bekannt, bei einer integrierten Schaltung eine elektronische Schaltung vorzusehen, die mehrere parallel geschaltete Widerstände aufweist, die je mit einer Schmelzsicherung, auch Brennstrecke genannt, in Serie geschaltet sind, so daß durch gezieltes Durchbrennen einzelner Brennstrecken ein einstellbarer Widerstand realisiert ist. Diese Schaltung ist insbesondere dort einsetzbar, wo erst bei Fertigstellung der kompletten integrierten Schaltung eine Festlegung eines bestimmten Widerstandswerts möglich ist. Um in einem großen Spielraum Widerstandswerte einstellen zu können, sind für diese elektronische Schaltung sehr große Widerstandswerte nötig, wodurch die Widerstände einen entsprechend großen Platz auf dem Substrat mit der integrierten Schaltung einnehmen. Weiter bekannt ist, die elektronische Schaltung als eine Serienschaltung von Widerständen mit kleineren Widerstandswerten auszuführen, die je mit einer Brennstrecke überbrückt sind, wobei aber ein erhöhter Schaltungsaufwand für die Brennstrecken und deren Beschaltung entsteht. The invention is based on an electronic circuit according to the Genus of the main claim. It is already known to be integrated Circuit to provide an electronic circuit that has multiple has resistors connected in parallel, each with a Fusible link, also called burning section, connected in series are, so that by deliberately burning individual burning sections an adjustable resistor is realized. This circuit is particularly applicable where only when the complete integrated circuit a determination of a certain resistance value is possible. To find resistance values in a wide range To be able to set are electronic for this Circuit very large resistance values necessary, which reduces the resistances a correspondingly large space on the substrate with the integrated Take circuit. Also known is the electronic Circuit as a series connection of resistors with smaller ones Execute resistance values, each bridging with a burning distance are, but with an increased circuit complexity for the Burning sections and their connection arises.
Die erfindungsgemäße elektronische Schaltung mit den kennzeichnenden Merkmalen des Hauptanspruchs hat demgegenüber den Vorteil, daß ein geringer Schaltungsaufwand für Schmelzsicherungen und deren Beschaltung entsteht und gleichzeitig bereits kleine Widerstandswerte genügen, um einen einstellbaren Widerstand mit großer Variabilität zu realisieren.The electronic circuit according to the invention with the characteristic Features of the main claim has the advantage that a low circuit outlay for fuses and their wiring arises and at the same time small resistance values are sufficient, to an adjustable resistor with great variability realize.
Durch die in den Unteransprüchen aufgeführten Maßnahmen sind vorteilhafte
Weiterbildungen und Verbesserungen der im Hauptanspruch
angegebenen elektronischen Schaltung möglich. Besonders vorteilhaft
ist es, die Schmelzsicherungen mittels Schaltern an eine Strom- oder
Spannungsquelle anzuschließen, da durch die Schalterstellungen eine
einfache Programmierung der Schmelzsicherungen zwischen leitendem
und nicht leitendem Zustand realisiert ist und nur eine einzige
Strom- oder Spannungsquelle benötigt wird. Weiter vorteilhaft ist
es, die Schalter als Thyristoren auszubilden, da diese zum einen
ebenfalls integrierbar sind, zum anderen keinen Abnutzungs- oder Alterungseffekten
ausgesetzt sind. Die Ansteuerung der Thyristoren
über Ausgänge eines Schieberegisters bringt den Vorteil mit sich,
daß für eine parallele Ansteuerung einer großen Anzahl von Thyristoren
nur ein einziger Eingang für die serielle Eingabe des Programmierdatenbitmusters
vorgesehen ist, wodurch insbesondere bei bereits
fertig montierten integrierten Schaltungen nur ein Pin für die
Ansteuerung aller Thyristoren genügt. Die Ausführung der elektronischen
Schaltung als integrierte Schaltung bietet den Vorteil, mit
weiteren Schaltungen auf einem
Halbleitersubstrat gemeinsam integrierbar zu sein, wodurch der Herstellungsaufwand
minimiert ist. Außerdem können sich z.B. temperaturbedingte
Effekte gleichermaßen auf die elektronische Schaltung
und die weiteren Schaltungen auswirken, wodurch eine Kompensation
erreichbar ist. Die elektronische Schaltung ist insbesondere für
ohmsche Widerstände einsetzbar, da insbesondere bei diesen durch die
elektronische Schaltung das Raumproblem verringert und das Verhalten
der Widerstände im Vergleich zueinander verbessert wird. Zu diesem
Verhalten sind insbesondere Abhängigkeiten von Temperatureffekten
und piezoelektrischen Effekten als auch eine durch die Vorspannung
des Substrats bewirkte Spannungsmodulation zu zählen. Es erweist
sich außerdem als Vorteil, wenn die Widerstände voneinander abweichende
Werte aufweisen, da so verschiedene Kombinationen von leitenden
und nicht leitenden Schmelzsicherungen zu unterschiedlichen Gesamtwiderstandswerten
führen, was die Variabilität der elektronischen
Schaltung erhöht. Die Ausbildung der Widerstände in Form von
diffundierten Widerständen verschiedener Länge und gleicher Breite
und Tiefe führt zu dem Vorteil, daß für die Widerstände bezüglich
der zur Herstellung verwendeten Photolithographie annähernd gleiche
Belichtungsparameter wählbar sind, wodurch sich Vorteile bezüglich
Maskenvielfalt, lateraler Diffusion und Layout ergeben. Außerdem ist
der Vorteil vorhanden, daß annähernd gleiche Kontaktwiderstände zu
anschließenden Kontakten vorliegen. Die Dimensionierungsvorschrift,
in der Form, daß sich der Gesamtleitwert der elektronischen Schaltung,
bei der alle Schmelzsicherungen im leitenden Zustand sind, vom
Gesamtleitwert der elektronischen Schaltung, bei der genau eine
Schmelzsicherung in nicht leitendem Zustand ist um eine Zweierpotenz
eines Einheitswiderstandswerts unterscheidet und daß der Exponent,
bei einer Durchnumerierung der Widerstände von 0 bis zur um 1 verminderten
Anzahl der Widerstände gleich der negierten Nummer des mit
der genau einen nicht leitenden Schmelzsicherung in Serie geschalteten
Widerstands ist, birgt den Vorteil in sich, daß eine Umsetzung
des Binärsystems auf die elektronische Schaltung erfolgt ist, wodurch
zwischen niedrigstem und höchstem Gesamtleitwert ohne Lücke
jede Stufe des Gesamtleitwerts mit einem Stufenabstand des Einheitsleitwerts
auswählbar ist. Die Dimensionierung des Widerstands, der
in Serie mit der Schmelzsicherung geschaltet ist, die dem Zusatzwiderstand
parallel geschaltet ist mit dem Wert
1/(1/(2i x RD) + 1 / (m x RA)) sowie des Zusatzwiderstands
mit dem Wert m x RA - 1 / (1 / (2k x RD) + 1 / (m x RA)) und
des Widerstands der parallel zu der zum Widerstand in Serie geschalteten
Schmelzsicherung keinen Zusatzwiderstand aufweist mit dem Wert
2i x RD bringt den Vorteil mit sich, daß durch diese Formeln eine
einfache Realisierung der binären Stufen erfolgt ist. Die Auswahl
der Anzahl der Zusatzwiderstände in dem Umfang, daß m x RA ungefähr
gleich dem Wert des Widerstands ist der parallel zu der zum Widerstand
in Serie geschalteten Schmelzsicherung keinen Zusatzwiderstand
aufweist und die höchste Nummer aufweist, dient der vorteilhaften
Dimensionierung der Schaltung, dergestalt, daß ein optimales
Verhältnis von Zusatzwiderständen zu den Widerständen erzielt ist,
dergestalt, daß die Widerstandswerte der einzelnen Widerstände und
Zusatzwiderstände dabei nahe beieinander liegen, wodurch derselbe
Aufbau und ähnliche geometrische Maße für die Widerstände und Zusatzwiderstände
wählbar sind, wodurch sich der Vorteil ergibt, daß
die Widerstände und Zusatzwiderstände, wenn sie als integrierte Widerstände
ausgeführt sind, ähnliches Verhalten bezüglich Spannungsmodulation,
Temperaturabhängigkeit, piezoelektrischen Effekten aufweisen.Advantageous further developments and improvements of the electronic circuit specified in the main claim are possible through the measures listed in the subclaims. It is particularly advantageous to connect the fuses to a current or voltage source by means of switches, since the switch positions make it easy to program the fuses between the conductive and non-conductive states and only a single current or voltage source is required. It is further advantageous to design the switches as thyristors, since on the one hand they can also be integrated and on the other they are not exposed to any wear or aging effects. The control of the thyristors via outputs of a shift register has the advantage that only a single input for the serial input of the programming data bit pattern is provided for a parallel control of a large number of thyristors, so that in particular in the case of already assembled integrated circuits, only one pin for the Control of all thyristors is sufficient. The design of the electronic circuit as an integrated circuit offers the advantage of being able to be integrated together with other circuits on a semiconductor substrate, as a result of which the production outlay is minimized. In addition, temperature-related effects, for example, can have an equal effect on the electronic circuit and the further circuits, whereby compensation can be achieved. The electronic circuit can be used in particular for ohmic resistors, since in particular the electronic circuit reduces the space problem in these and the behavior of the resistors is improved in comparison with one another. This behavior includes, in particular, dependencies on temperature effects and piezoelectric effects as well as a voltage modulation caused by the pretensioning of the substrate. It also proves to be an advantage if the resistances have different values, since different combinations of conductive and non-conductive fuses lead to different overall resistance values, which increases the variability of the electronic circuit. The formation of the resistors in the form of diffused resistors of different lengths and the same width and depth leads to the advantage that approximately the same exposure parameters can be selected for the resistors with regard to the photolithography used for the production, which results in advantages in terms of mask variety, lateral diffusion and layout. In addition, there is the advantage that there are approximately the same contact resistances to subsequent contacts. The dimensioning rule, in the form that the overall conductance of the electronic circuit, in which all fuses are in the conductive state, differs from the overall conductance of the electronic circuit, in which exactly one fuse is in the non-conductive state, by a power of two of a unit resistance value and that the exponent With a numbering of the resistors from 0 to the number of resistors reduced by 1 is equal to the negated number of the resistor connected in series with exactly one non-conductive fuse, there is the advantage that the binary system is converted to the electronic circuit , whereby between the lowest and highest overall conductance without a gap, each step of the total conductance can be selected with a step spacing of the unit conductance. The dimensioning of the resistor, which is connected in series with the fuse, which is connected in parallel with the additional resistor with the
Ausführungsbeispiele der Erfindung sind in der Zeichnung dargestellt
und in der nachfolgenden Beschreibung näher erläutert.
Es zeigen Figur 1 ein erstes Ausführungsbeispiel der elektronischen
Schaltung mit vier Widerständen,
Figur 2 ein zweites Ausführungsbeispiel der Schaltung mit einem Widerstand
und zwei Schaltern,
Figur 3 ein drittes Ausführungsbeispiel der Schaltung mit Thyristoren
und einem Schieberegister.Embodiments of the invention are shown in the drawing and explained in more detail in the following description.
1 shows a first exemplary embodiment of the electronic circuit with four resistors,
FIG. 2 shows a second exemplary embodiment of the circuit with a resistor and two switches,
Figure 3 shows a third embodiment of the circuit with thyristors and a shift register.
In Figur 1 ist ein erstes Ausführungsbeispiel der elektronischen Schaltung dargestellt. Zwischen zwei Klemmen A, B ist eine Serienschaltung aus einer ersten Schmelzsicherung Q0 und einem ersten Widerstand R0 angeschlossen. Zu dieser Serienschaltung ist parallel eine weitere Serienschaltung aus einem weiteren Widerstand R1 und einer weiteren Schmelzsicherung Q1 parallel geschaltet. Weiter parallel geschaltet ist eine dritte Serienschaltung mit einer dritten Schmelzsicherung Q2 und einem dritten Widerstand R2 sowie eine vierte Serienschaltung mit einem vierten Widerstand R3 und einer vierten Schmelzsicherung Q3. Die dritte Schmelzsicherung Q2 ist mittels eines ersten Zusatzwiderstandes R2' überbrückt. Ebenso ist die vierte Schmelzsicherung Q3 mittels eines zweiten Zusatzwiderstandes R3' überbrückt.1 shows a first exemplary embodiment of the electronic circuit. A series circuit comprising a first fuse Q 0 and a first resistor R 0 is connected between two terminals A, B. A further series circuit comprising a further resistor R 1 and a further fuse Q 1 is connected in parallel with this series circuit. Also connected in parallel is a third series circuit with a third fuse Q 2 and a third resistor R 2 and a fourth series circuit with a fourth resistor R 3 and a fourth fuse Q 3 . The third fuse Q 2 is bridged by a first additional resistor R 2 '. The fourth fuse Q 3 is also bridged by means of a second additional resistor R 3 '.
Diese Schaltung ist insbesondere als integrierte Schaltung vorgesehen, wobei durch gezieltes Durchschmelzen einzelner Schmelzsicherungen Q0, Q1, Q2, Q3 unterschiedliche Werte für den zwischen den Klemmen A, B meßbaren Gesamtleitwert Ygesamt einstellbar sind. Schaltungen dieser Art werden insbesondere dann eingesetzt, wenn ein genaues Einstellen eines Leitwerts bzw. Widerstands zum Zeitpunkt des Schaltungsentwurfs oder Schaltungsaufbaus noch nicht möglich ist. Vorzugsweise bei integrierten Schaltungen, die von einem Gehäuse umgeben sind, kann durch gezieltes Durchschmelzen ein zelner Schmelzsicherungen Q0, Q1, Q2, Q3 noch nach bereits erfolgter Montage in ein Gehäuse ein Einstellen eines Widerstands erfolgen. Somit können z.B. durch das Gehäuse beinflußte Schaltkreise so abgeglichen werden, daß der Einfluß des Gehäuses kompensiert oder minimiert ist.This circuit is provided in particular as an integrated circuit, wherein individual by controlled melting through fuses Q 0, Q 1, Q 2, Q 3, different values are set for the total measurable between the terminals A, B total conductance Y. Circuits of this type are used in particular when it is not yet possible to precisely set a conductance or resistance at the time the circuit is being designed or constructed. In the case of integrated circuits which are surrounded by a housing, a resistance can be set by selective melting of individual fuses Q 0 , Q 1 , Q 2 , Q 3 even after they have been installed in a housing. Thus, circuits influenced by the housing can be adjusted so that the influence of the housing is compensated or minimized.
Figur 2 zeigt die Darstellung einer elektronischen Schaltung mit zwei Schaltern. Zwischen den Klemmen A, B ist die Serienschaltung aus der ersten Schmelzsicherung Q0 und dem ersten Widerstand R0 angeschlossen. Zusätzlich ist die Klemme A über einen ersten Schalter N einen Anschluß an eine positive Programmierspannung V prog angeschlossen, während der gemeinsame Anschluß von Schmelzsicherung Q0 und Widerstand R0 über einen weiteren Schalter M an das negative Betriebspotential VSS gelegt ist.Figure 2 shows the representation of an electronic circuit with two switches. The series circuit comprising the first fuse Q 0 and the first resistor R 0 is connected between the terminals A, B. In addition, terminal A is connected via a first switch N to a connection to a positive programming voltage V prog, while the common connection of fuse Q 0 and resistor R 0 is connected to the negative operating potential V SS via a further switch M.
Durch Schließen des weiteren Schalters M und des ersten Schalters N wird ein Strompfad vom positiven Programmierpotential V prog zum negativen Betriebspotential VSS über die erste Schmelzsicherung Q0 hergestellt. Der dabei fließende große Strom I bewirkt ein Durchschmelzen der ersten Schmelzsicherung Q0, wodurch der Strompfad zwischen den Klemmen A, B unterbrochen wird. Durch das Schließen der Schalter M, N wurde somit eine Widerstandsänderung zwischen den Klemmen A, B bewirkt. Für die integrierte Form dieser Schaltung ist es vorgesehen, den ersten Schalter N nach dem weiteren Schalter M zu betätigen, um Schalterbetätigungen des weiteren Schalters M vor dem gewünschten Programmiervorgang unwirksam zu machen. Erst durch Schließen des ersten Schalters N ist die dann vorhandene Schalterstellung des weiteren Schalters M für die Programmierung relevant.By closing the further switch M and the first switch N, a current path from the positive programming potential V prog to the negative operating potential V SS is established via the first fuse Q 0 . The large current I flowing in the process causes the first fuse Q 0 to melt, as a result of which the current path between the terminals A, B is interrupted. Closing switches M, N thus caused a change in resistance between terminals A, B. For the integrated form of this circuit, provision is made to actuate the first switch N after the further switch M in order to render switch operations of the further switch M ineffective before the desired programming operation. Only when the first switch N is closed is the then existing switch position of the further switch M relevant for programming.
Die in Figur 3 dargestellte elektronische Schaltung weist ebenfalls die Klemmen A, B auf zwischen denen die erste Serienschaltung mit der ersten Schmelzsicherung Q0 und dem ersten Widerstand R0 angeschlossen ist. Parallel zu dieser Serienschaltung folgen weitere Serienschaltungen mit je einer weiteren Schmelzsicherung Q1...Qn+m und mit je einem weiteren Widerstand R1...Rn+m, wobei einer Anzahl von m Schmelzsicherungen Qn+1...Qn+m je ein Zusatzwiderstand Rn+1'...Rn+m' parallel geschaltet ist. Zwischen den Schmelzsicherungen Q0...Qn+m und den Widerständen R0...Rn+m zweigt in jeder Serienschaltung ein Anschluß zu einem Thyristor T0...Tn+m ab. Die Kathodenanschlüsse der Thyristoren T0...Tn+m sind an das negative Betriebspotential VSS angeschlossen. Zwischen einem positiven Programmierpotential V prog und der Klemme A ist ein Programmierschalter S prog angeordnet. Ein Schieberegister S weist einen Dateneingang E, einen Takteingang T sowie Reseteingänge X0...Xn+m auf. Das Schieberegister S besitzt n+m+1 Stufen, deren Ausgänge A0...An+m jeweils an Steuereingänge der Thyristoren T0...Tn+m geführt sind. Eine Resetleitung ist mit jedem Reseteingang X0...Xn+m verbunden.The electronic circuit shown in Figure 3 also has the terminals A, B between which the first series circuit with the first fuse Q 0 and the first resistor R 0 is connected. In parallel to this series connection, further series connections follow, each with a further fuse Q 1 ... Q n + m and with a further resistor R 1 ... R n + m , with a number of m fuses Q n + 1 ... Q n + m an additional resistor R n + 1 '... R n + m ' is connected in parallel. In each series connection, a connection to a thyristor T 0 ... T n + m branches off between the fuses Q 0 ... Q n + m and the resistors R 0 ... R n + m . The cathode connections of the thyristors T 0 ... T n + m are connected to the negative operating potential V SS . A programming switch S prog is arranged between a positive programming potential V prog and the terminal A. A shift register S has a data input E, a clock input T and reset inputs X 0 ... X n + m . The shift register S has n + m + 1 stages, the outputs A 0 ... A n + m are each led to control inputs of the thyristors T 0 ... T n + m . A reset line is connected to each reset input X 0 ... X n + m .
Zur Einstellung einer Programmierung in Form einer bestimmten Folge
von sich in leitendem oder nicht leitendem Zustand befindlichen
Schmelzsicherungen Q0...Qn+m wird bei noch geöffnetem Programmierschalter
S prog ein Bitmuster über den Dateneingang E in
das Schieberegister vom Takt T gesteuert geschoben. Zu Beginn dieses
Schiebevorgangs wird ein Resetimpuls über den Reseteingang R an alle
Reseteingänge R0...Rn+m des Schieberegisters S geleitet. Dadurch
wird der Inhalt des gesamten Schieberegisters auf logisch 0 gesetzt,
wodurch alle Thyristoren T0...Tn+m+1 im gesperrten Zustand sind.
Nach dem Einschieben des Bitmusters in das Schieberegister S wird
der Programmierschalter S prog geschlossen und das Programmierpotential
V prog liegt an der Klemme A an. Durch Zündung mittels der
Programmierspannung V prog und des Bitmusters gerät jeder der Thyristoren
T0...Tn+m, an dem über einen der Ausgänge A0...An+m
eine 1 anliegt, in den leitenden Zustand. Dadurch ist ein leitender
Pfad zwischen dem positiven Programmierpotential
V prog und dem negativen Betriebspotential VSS über die Schmelzsicherungen
Q0...Qn+m geschaltet, für die der zugehörige Thyristor
T0...Tn+m durch das Bitmuster des Datensignals gezündet
wurde. Der dabei fließende Schmelzstrom bewirkt ein Durchschmelzen
der ausgewählten Schmelzsicherungen Q0...Qn+m. Es ist vorgesehen,
die Programmierspannung so langsam auf ihren Maximalwert hochzufahren,
daß ein unbeabsichtigtes Überkopfzünden vermieden wird. Um
eine exakte Einstellung des Gesamtleitwerts Ygesamt zwischen den
Klemmen A, B zu ermöglichen weisen die Widerstände R0...Rn+m
folgende Werte auf: Jeder der Widerstände R0...Rn+m die in Serie
zu einer der Schmelzsicherungen Q0...Qn+m geschaltet sind, die
nicht mittels eines Zusatzwiderstands Rn+1'...Rn+m' überbrückt
ist weist den Wert 2i x RD auf. Die restlichen Widerstände
Rn+1...Rn+m sind mit dem Wert
1 / (1 / (2i x RD) + 1 / (m x RA)) belegt. Dabei bezeichnet i
den Index, d.h. die Nummer des Widerstands R0...Rn+m, wenn die
Widerstände R0...Rn+m von 0 ausgehend bis zur um 1 verminderten
Anzahl der Widerstände R0...Rn+m numeriert wurden. Die Zusatzwiderstände
Rn+1'...Rn+m' sind mit dem Wert
1 / (1 /(m x RA - 2i x RD) + 1 / (m x RA)) versehen. m ist
dabei die Anzahl der Zusatzwiderstände Rn+1'...Rn+m'. Durch diese
Dimensionierung ist gewährleistet, daß der minimal erreichbare
Grenzwert Ymin für den Gesamtleitwert Ygesamt, der zwischen den
Klemmen A, B gemessen werden kann, gleich dem reziproken Wert von
RA ist. Der maximal erreichbare Grenzwert Ymax für den Gesamtleitwert
Ygesamt bei einer unendlichen Anzahl von Serienschaltungen
beträgt 1 / RA + 2 / RD. Durch die Vorgabe der gewünschten
Werte für den maximal erreichbaren
Grenzwert Ymax und den minimal erreichbaren Grenzwert Ymin sowie
des gewünschten Maximalaufwandes in Form der Anzahl der Serienschaltungen
n+m+1 dient somit der Festlegung der Werte für RA, RD und
n+m. Außerdem ändert sich der Gesamtleitwert Ygesamt beim Durchschmelzen
der Schmelzsicherung Qi um den Wert 1 /(21x RD). Eine
Optimierung des Verhältnisses von n zu m erhält man vorzugsweise
bei dem Verhältnis, bei dem der Wert des Widerstands R0...Rn+m,
der parallel zu der zum Widerstand R0...Rn+m in Serie geschalteten
Schmelzsicherung Q0...Qn+m keinen Zusatzwiderstand
Rn+1'...Rn+m' aufweist und der die höchste Nummer aufweist,
gleich dem Wert m x RA ist.
Bei ohmschen diffundierten Widerständen ist durch die Optimierung
ein Layout erreichbar, bei dem die Widerstände R0...Rn+m und Zusatzwiderstände
Rn+1'...Rn+m' annähernd gleiche Größenordnungen
aufweisen, wodurch ein identischer Aufbau der Widerstände
R0...Rn+m und Zusatzwiderstände Rn+1'...Rn+m' bezüglich
Breite und Tiefe wählbar ist und die unterschiedlichen Werte lediglich
durch Verändern der Länge erreicht werden. Dadurch ist das Verhalten
der Widerstände R0...Rn+m und Zusatzwiderstände
Rn+1'...Rn+m' annähernd identisch, was für den Schaltungsentwurf
von Vorteil ist. Dasselbe Schaltungsprinzip ist ebenfalls für komplexe
Widerstände einsetzbar, also z.B. Kondensatoren oder auch Induktivitäten.
Ein Beispiel für ein Einsatzgebiet der elektronischen
Schaltung ist ein integrierter Drucksensor.To set a programming in the form of a certain sequence of fuses Q 0 ... Q n + m which are in a conductive or non-conductive state, a bit pattern is pushed into the shift register controlled by the clock T via the data input E in the shift register while the programming switch S prog is still open. At the beginning of this shifting process, a reset pulse is sent via the reset input R to all reset inputs R 0 ... R n + m of the shift register S. As a result, the content of the entire shift register is set to logic 0, as a result of which all thyristors T 0 ... T n + m + 1 are in the blocked state. After the bit pattern has been inserted into the shift register S, the programming switch S prog is closed and the programming potential V prog is present at terminal A. Ignition by means of the programming voltage V prog and the bit pattern causes each of the thyristors T 0 ... T n + m , to which a 1 is present via one of the outputs A 0 ... A n + m , to become conductive. As a result, a conductive path is connected between the positive programming potential V prog and the negative operating potential V SS via the fuses Q 0 ... Q n + m , for which the associated thyristor T 0 ... T n + m through the bit pattern of the data signal was ignited. The flowing melt current causes the selected fuses Q 0 ... Q n + m to melt. It is intended to ramp up the programming voltage to its maximum value so slowly that unintentional overhead ignition is avoided. In order to enable an exact setting of the total conductance Y total between the terminals A, B, the resistors R 0 ... R n + m have the following values: Each of the resistors R 0 ... R n + m which are connected in series to one of the Fuses Q 0 ... Q n + m that are not bridged by means of an additional resistor R n + 1 '... R n + m ' have the value 2 i x R D. The remaining resistors R n + 1 ... R n + m are assigned the
In the case of ohmic diffused resistors, a layout can be achieved by the optimization in which the resistors R 0 ... R n + m and additional resistors R n + 1 '... R n + m ' have approximately the same orders of magnitude, which means that the Resistors R 0 ... R n + m and additional resistors R n + 1 '... R n + m ' can be selected with regard to width and depth and the different values can only be achieved by changing the length. As a result, the behavior of the resistors R 0 ... R n + m and additional resistors R n + 1 '... R n + m ' is approximately identical, which is advantageous for the circuit design. The same circuit principle can also be used for complex resistors, for example capacitors or inductors. An example of an area of application for the electronic circuit is an integrated pressure sensor.
Claims (11)
- Electronic circuit having a plurality of parallel-connected series circuits having at least a respective resistor and a respective fuse link, which can be brought to a non-conducting state by means of a fusing current applied thereto, characterized in that at least one additional resistor (Rn+1',...Rn+m') is connected in parallel with at least one fuse link (Q0...Qn+m).
- Electronic circuit according to Claim 1, characterized in that the fuse links (Q0...Qn+m) are connected to at least one current or voltage source (VDD, VSS) via connecting lines and at least one switch (M) is provided in at least one of the connecting lines of each fuse link (Q0...Qn+m), by means of which switch the fusing current can be switched on and off.
- Electronic circuit according to Claim 2, characterized in that the switches (M) are thyristors (T0...Tn+m).
- Electronic circuit according to Claim 3, characterized in that the thyristors are driven via outputs (A0...An+m) of a shift register (S).
- Electronic circuit according to one of Claims 1 to 4, characterized in that the electronic circuit is an integrated circuit.
- Electronic circuit according to one of Claims 1 to 5, characterized in that the resistors (R0...Rn+m) and the at least one additional resistor (Rn+1'...Rn+m) are non-reactive resistors.
- Electronic circuit according to one of Claims 1 to 6, characterized in that the resistors (R0...Rn+m) have values that differ from one another.
- Electronic circuit according to Claims 5, 6 and 7, characterized in that the resistors (R0...Rn+m) and the at least one additional resistor (Rn+1'...Rn+m') are diffused resistors and differ only in terms of their length.
- Electronic circuit according to one of Claims 1 to 8, characterized in that the resistors (R0...Rn+m) and the at least one additional resistor (Rn+1'...Rn+m') are dimensioned in such a way that the total admittance of the electronic circuit in which all the fuse links (Q0...Qn+m) are in the conducting state differs from the total admittance of the electronic circuit in which exactly one fuse link (Q0...Qn+m) is in the non-conducting state by a power of two of a unit resistance (RD), and that the exponent, in the case of consecutive numbering of the resistors (R0...Rn+m) from zero to the number of resistors (R0...Rn+m) reduced from one, is equal to the negated number of the resistor (R0...Rn+m) which is connected in series with the exactly one non-conducting fuse link (Q0...Qn+m).
- Electronic circuit according to Claim 9, characterized in thata) the at least one resistor (R0...Rn+m) which is connected in series with the at least one fuse link (Q0...Qn+m) which is connected in parallel with the at least one additional resistor (Rn+1'...Rn+m') has the valueb) the at least one additional resistor (Rn+1'...Rn+m') has the valuec) the at least one resistor (R0...Rn+m) which has no additional resistor (Rn+1'...Rn+m') in parallel with the fuse link (Q0...Qn+m) connected in series with the resistor (R0...Rn+m) has the value 2i x RD.
- Electronic circuit according to Claim 10, characterized in that the number of additional resistors (Rn+1'...Rn+m') is so large that m x RA is approximately equal to the value of the resistor (R0...Rn+m) which has no additional resistor (Rn+1'...Rn+m') in parallel with the fuse link (Q0...Qn+m) connected in series with the resistor (R0...Rn+m) and has the highest number.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE4333065A DE4333065A1 (en) | 1993-09-29 | 1993-09-29 | Electronic switch |
| DE4333065 | 1993-09-29 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| EP0645785A2 EP0645785A2 (en) | 1995-03-29 |
| EP0645785A3 EP0645785A3 (en) | 1997-04-16 |
| EP0645785B1 true EP0645785B1 (en) | 2002-12-04 |
Family
ID=6498891
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| EP94112865A Expired - Lifetime EP0645785B1 (en) | 1993-09-29 | 1994-08-18 | Electronic circuitry |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US5612664A (en) |
| EP (1) | EP0645785B1 (en) |
| JP (1) | JPH07249501A (en) |
| DE (2) | DE4333065A1 (en) |
| ES (1) | ES2188599T3 (en) |
Families Citing this family (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1071918C (en) * | 1996-07-20 | 2001-09-26 | 何兴银 | Method for automatic regulation of electric resistance and its device |
| WO2001095120A1 (en) * | 2000-06-06 | 2001-12-13 | Vitesse Semiconductor Corporation | Crosspoint switch with switch matrix module |
| TW523661B (en) * | 2001-11-16 | 2003-03-11 | Via Tech Inc | Control circuit of suspend to random access memory mode |
| FR2860641B1 (en) * | 2003-10-03 | 2006-10-13 | Commissariat Energie Atomique | ADDRESSABLE RESISTOR MATRIX INDEPENDENTLY, AND METHOD FOR MAKING SAME |
| JP2013153129A (en) | 2011-09-29 | 2013-08-08 | Rohm Co Ltd | Chip resistor and electronic equipment having resistor network |
| JP6609646B2 (en) * | 2011-09-29 | 2019-11-20 | ローム株式会社 | Electronic device having chip resistor and resistor network |
| JP6615240B2 (en) * | 2011-12-28 | 2019-12-04 | ローム株式会社 | Chip resistor |
| JP2013153130A (en) | 2011-12-28 | 2013-08-08 | Rohm Co Ltd | Chip resistor |
| JP6626135B2 (en) * | 2012-01-27 | 2019-12-25 | ローム株式会社 | Chip components |
| JP2013232620A (en) | 2012-01-27 | 2013-11-14 | Rohm Co Ltd | Chip component |
| JP6259184B2 (en) * | 2012-02-03 | 2018-01-10 | ローム株式会社 | Chip component and manufacturing method thereof |
| JP2014072239A (en) * | 2012-09-27 | 2014-04-21 | Rohm Co Ltd | Chip component |
| JP6101465B2 (en) * | 2012-09-27 | 2017-03-22 | ローム株式会社 | Chip parts |
| JP2014072241A (en) * | 2012-09-27 | 2014-04-21 | Rohm Co Ltd | Chip component |
| US9773588B2 (en) | 2014-05-16 | 2017-09-26 | Rohm Co., Ltd. | Chip parts |
| JP6723689B2 (en) * | 2014-05-16 | 2020-07-15 | ローム株式会社 | CHIP COMPONENT, MANUFACTURING METHOD THEREOF, CIRCUIT ASSEMBLY AND ELECTRONIC DEVICE HAVING THE |
| JP2017130671A (en) * | 2017-02-27 | 2017-07-27 | ローム株式会社 | Chip component |
| JP6535073B2 (en) * | 2017-12-14 | 2019-06-26 | ローム株式会社 | Chip parts |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3441804A (en) * | 1966-05-02 | 1969-04-29 | Hughes Aircraft Co | Thin-film resistors |
| FR2228271B1 (en) * | 1973-05-04 | 1976-11-12 | Honeywell Bull Soc Ind | |
| US4016483A (en) * | 1974-06-27 | 1977-04-05 | Rudin Marvin B | Microminiature integrated circuit impedance device including weighted elements and contactless switching means for fixing the impedance at a preselected value |
| JPS56132815A (en) * | 1980-03-21 | 1981-10-17 | Nec Corp | Reference step voltage generating circuit |
| US4788620A (en) * | 1987-11-09 | 1988-11-29 | General Electric Company | Static trip circuit breaker with automatic circuit trimming |
| US5191279A (en) * | 1990-03-15 | 1993-03-02 | Ixys Corporation | Current limiting method and apparatus |
-
1993
- 1993-09-29 DE DE4333065A patent/DE4333065A1/en not_active Withdrawn
-
1994
- 1994-08-18 EP EP94112865A patent/EP0645785B1/en not_active Expired - Lifetime
- 1994-08-18 DE DE59410216T patent/DE59410216D1/en not_active Expired - Lifetime
- 1994-08-18 ES ES94112865T patent/ES2188599T3/en not_active Expired - Lifetime
- 1994-09-19 US US08/308,721 patent/US5612664A/en not_active Expired - Lifetime
- 1994-09-29 JP JP6235657A patent/JPH07249501A/en active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| JPH07249501A (en) | 1995-09-26 |
| DE59410216D1 (en) | 2003-01-16 |
| DE4333065A1 (en) | 1995-03-30 |
| EP0645785A3 (en) | 1997-04-16 |
| ES2188599T3 (en) | 2003-07-01 |
| EP0645785A2 (en) | 1995-03-29 |
| US5612664A (en) | 1997-03-18 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP0645785B1 (en) | Electronic circuitry | |
| DE10134665C1 (en) | Operating method for semiconductor element has differential resistance switched to lesser value above given current limit | |
| DE3110800C2 (en) | Reference voltage generator for A / D or D / A converters | |
| DE2331660B2 (en) | CIRCUIT ARRANGEMENT FOR DISPLAYING DC VOLTAGE USING ELECTRO-OPTICAL DISPLAY ELEMENTS | |
| DE2706931C2 (en) | ||
| DE2509732C3 (en) | Circuit arrangement for correlating two groups of parallel binary signals | |
| DE1537236B2 (en) | FUp flop that is switched on and back in time | |
| DE2758758C3 (en) | Non-linear function circuit | |
| EP0784344A1 (en) | Semiconductor structure for resistive networks | |
| DE10258780B4 (en) | Anti-fuse circuit and anti-fuse system | |
| EP1547113B1 (en) | Self-configuring component by means of arcing | |
| EP0978131B1 (en) | Circuit arrangement for a load transfer switch | |
| DE2942777C2 (en) | ||
| DE4110340A1 (en) | Digital multiplexer-controlled delay generator - uses groups of current-switching elements to vary propagation delay in connection input voltage to load | |
| DE2320075A1 (en) | PROTECTIVE CIRCUIT FOR ELECTRONIC EQUIPMENT AND COMPONENTS | |
| DE19756916B4 (en) | monitoring system | |
| DE2618140C2 (en) | Arrangement for switching and power control of electrical consumers, especially incandescent lamps | |
| DE1210364B (en) | Flashing light signal device | |
| DE10216707C1 (en) | Switching circuit for high voltages uses series switch elements and associated switched current sinks | |
| DE2506582A1 (en) | Low-loss supply circuit for LV DC series loads e.g. LEDs - has transistors shunting each LED to allow independent operation | |
| DE3502421A1 (en) | Overvoltage protection for electronic circuits | |
| DE3813319C2 (en) | ||
| DE1640295C3 (en) | Circuit arrangement for setting a multi-digit decadic voltage | |
| CH682224A5 (en) | ||
| DE2944605C2 (en) | Resistance in thick film technology |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
|
| AK | Designated contracting states |
Kind code of ref document: A2 Designated state(s): DE ES FR GB IT |
|
| PUAL | Search report despatched |
Free format text: ORIGINAL CODE: 0009013 |
|
| RHK1 | Main classification (correction) |
Ipc: H01C 1/16 |
|
| AK | Designated contracting states |
Kind code of ref document: A3 Designated state(s): DE ES FR GB IT |
|
| 17P | Request for examination filed |
Effective date: 19971016 |
|
| GRAG | Despatch of communication of intention to grant |
Free format text: ORIGINAL CODE: EPIDOS AGRA |
|
| 17Q | First examination report despatched |
Effective date: 20011122 |
|
| GRAG | Despatch of communication of intention to grant |
Free format text: ORIGINAL CODE: EPIDOS AGRA |
|
| GRAH | Despatch of communication of intention to grant a patent |
Free format text: ORIGINAL CODE: EPIDOS IGRA |
|
| GRAH | Despatch of communication of intention to grant a patent |
Free format text: ORIGINAL CODE: EPIDOS IGRA |
|
| GRAA | (expected) grant |
Free format text: ORIGINAL CODE: 0009210 |
|
| AK | Designated contracting states |
Kind code of ref document: B1 Designated state(s): DE ES FR GB IT |
|
| REG | Reference to a national code |
Ref country code: GB Ref legal event code: FG4D Free format text: NOT ENGLISH |
|
| REF | Corresponds to: |
Ref document number: 59410216 Country of ref document: DE Date of ref document: 20030116 |
|
| GBT | Gb: translation of ep patent filed (gb section 77(6)(a)/1977) |
Effective date: 20030225 |
|
| REG | Reference to a national code |
Ref country code: ES Ref legal event code: FG2A Ref document number: 2188599 Country of ref document: ES Kind code of ref document: T3 |
|
| ET | Fr: translation filed | ||
| PLBE | No opposition filed within time limit |
Free format text: ORIGINAL CODE: 0009261 |
|
| STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT |
|
| 26N | No opposition filed |
Effective date: 20030905 |
|
| PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: GB Payment date: 20090821 Year of fee payment: 16 |
|
| GBPC | Gb: european patent ceased through non-payment of renewal fee |
Effective date: 20100818 |
|
| PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: GB Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20100818 |
|
| PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: ES Payment date: 20110825 Year of fee payment: 18 |
|
| REG | Reference to a national code |
Ref country code: ES Ref legal event code: FD2A Effective date: 20131018 |
|
| PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: ES Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20120819 |
|
| PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: FR Payment date: 20130820 Year of fee payment: 20 |
|
| PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: IT Payment date: 20130823 Year of fee payment: 20 |
|
| PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: DE Payment date: 20131025 Year of fee payment: 20 |
|
| REG | Reference to a national code |
Ref country code: DE Ref legal event code: R071 Ref document number: 59410216 Country of ref document: DE |
|
| PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: DE Free format text: LAPSE BECAUSE OF EXPIRATION OF PROTECTION Effective date: 20140819 |