JP6609646B2 - Electronic device having chip resistor and resistor network - Google Patents

Description

  The present invention relates to an electronic device having a chip resistor and a resistor network as discrete components.

  2. Description of the Related Art Conventionally, a chip resistor has a configuration including an insulating substrate such as ceramic, a resistance film formed by screen printing a material paste on the surface, and an electrode connected to the resistance film. In order to adjust the resistance value of the chip resistor to the target value, laser trimming is performed in which a trimming groove is formed by irradiating the resistance film with a laser beam. More specifically, a method has been adopted in which trimming grooves are formed until the measured value reaches a target value while measuring the resistance value of the resistance film (see Patent Document 1).

Japanese Patent Laid-Open No. 2001-76912

In a conventional chip resistor, a resistance film is formed on the surface of an insulating substrate such as ceramic by screen printing or the like. In the formation of the resistance film, a resistance film having a target resistance value is designed. However, since the actually printed resistance film has a deviation from the target resistance value, the resistance value is adjusted so as to become the target value by laser trimming. . Therefore, it cannot cope with a wide range of resistance values.
The present invention has been made under such a background, and a main object thereof is to provide a novel chip resistor having a resistor network on a substrate and having a configuration different from that of a conventional chip resistor.

  Another object of the present invention is to provide an electronic apparatus having a resistance network that can easily cope with a plurality of required resistance values with the same design structure.

A chip resistor according to an aspect of the present invention includes a silicon substrate having one surface as a mounting surface and the other surface on the opposite side, the side surface of which is formed linearly, and the one of the substrates. covering the surface and both side surfaces are covered with a protective film in which an opening is formed, the protective film on the one surface of the substrate made of a material different from that of the protective film, and communicating with the opening of the protective film A resin film having an opening; a first connection electrode and a second connection electrode which are formed only on the one surface of the substrate and disposed in the opening of the protective film and the resin film ; and the first connection And a resistor network connected to the second connection electrode, the resistor network including a plurality of resistors having equal resistance values arranged in a matrix on the substrate, and the resistor One or more of A plurality of types of resistance unit bodies configured in succession, circuit network connection means for connecting the plurality of types of resistance unit bodies in a predetermined manner, and provided individually corresponding to the resistance unit bodies, A plurality of fuse films that can be blown to electrically incorporate a resistive unit in the resistive network or to be electrically isolated from the resistive network, the resistive body extending over the substrate Including a film line and a conductor film laminated on the resistance film line at a certain interval in the line direction, and in a plan view, the resistor film line and the conductor film having a certain width are alternately spaced at a certain interval. As arranged, the resistance film lines at the constant interval where the conductor films are not stacked constitute one resistor, and the other surface of the substrate is a polished surface, The connection electrode and the second connection electrode are From the opening of the protective film and the resin film protrudes upward has a larger portion than the opening in a plan view, a portion covering both sides of the substrate of the protective film, the other surface of said substrate The resin film has an end that is flush with the other surface of the substrate, and the resin film has an arcuate tension projecting outward from the protective film on the side surface of the substrate in a cross-sectional view. Has a protruding part.

In addition, an electronic component according to another aspect of the present invention includes a silicon substrate having one surface as a mounting surface and the other surface opposite to the mounting surface, the side surface of which is formed in a straight line, and the substrate covering the one surface and both side surfaces are covered with a protective film in which an opening is formed, the protective film on the one surface of the substrate made of a material different from that of the protective film, and communicating with the opening of the protective film A resin film having an opening formed thereon, a first connection electrode and a second connection electrode which are formed only on the one surface of the substrate and are disposed in the opening of the protective film and the resin film ; and A resistor network having a plurality of resistors formed on the one surface, connected at one end side to the first connection electrode and connected at the other end side to the second connection electrode by a wiring film; A resistor is electrically connected to the resistor network. Or a plurality of fuse films that can be fused to be electrically separated from the resistor network, and the other surface of the substrate is a polished surface, and the first connection electrode and the second connection The electrode protrudes upward from the opening of the protective film and the resin film , and has a portion larger than the opening in plan view, and the portion of the protective film that covers both side surfaces of the substrate is the substrate. The other surface of the substrate has an end portion that is flush with the other surface of the substrate, and the resin film projects outward from the protective film on the side surface of the substrate in a cross-sectional view. It has an arcuate overhang.

FIG. 1A is an illustrative perspective view showing an external configuration of a chip resistor 10 according to an embodiment of the first invention, and FIG. 1B shows the chip resistor 10 mounted on a substrate. It is a side view which shows the state. FIG. 2 is a plan view of the chip resistor 10, showing the arrangement relationship of the first connection electrode 12, the second connection electrode 13, and the resistor network 14 and the configuration of the resistor network 14 in plan view. FIG. 3A is an enlarged plan view illustrating a part of the resistor network 14 shown in FIG. FIG. 3B is a longitudinal sectional view in the length direction for explaining the configuration of the resistor R in the resistor network 14. FIG. 3C is a longitudinal sectional view in the width direction drawn for explaining the configuration of the resistor R in the resistor network 14. FIG. 4 is a diagram showing the electrical characteristics of the resistor film line 20 and the conductor film 21 with circuit symbols and electrical circuit diagrams. 5A is a partially enlarged plan view of a region including the fuse film F drawn by enlarging a part of the plan view of the chip resistor shown in FIG. 2, and FIG. 5B is a plan view of FIG. It is a figure which shows the cross-sectional structure which follows BB of). FIG. 6 shows the arrangement relationship of the connecting conductor film C and the fuse film F connecting the plurality of types of resistance unit bodies in the resistor network 14 shown in FIG. It is a figure which shows the connection relation with several types of resistance unit bodies diagrammatically. FIG. 7 is an electric circuit diagram of the resistor network 14. FIG. 8 is a plan view of the chip resistor 30, showing the arrangement relationship of the first connection electrode 12, the second connection electrode 13, and the resistor network 14 and the configuration of the resistor network 14 in plan view. FIG. 9 shows the arrangement relationship of the connecting conductor film C and the fuse film F connecting the plurality of types of resistance unit bodies in the resistor network 14 shown in FIG. It is a figure which shows the connection relation with several types of resistance unit bodies diagrammatically. FIG. 10 is an electric circuit diagram of the resistor network 14. FIGS. 11A and 11B are electric circuit diagrams showing modifications of the electric circuit shown in FIG. FIG. 12 is an electric circuit diagram of a resistor network 14 according to still another embodiment of the first invention. FIG. 13 is an electric circuit diagram showing a configuration example of a resistance network in a chip resistor displaying a specific resistance value. FIG. 14 is a circuit diagram of the electronic apparatus 1 according to one embodiment of the first invention. FIG. 15 is an illustrative view for explaining that the chip resistor is cut out from the wafer. FIG. 16A is a schematic perspective view for explaining the configuration of an electronic device according to an embodiment of the second invention, and FIG. 16B is a state where the electronic device is mounted on a circuit board. It is a typical side view which shows. FIG. 17 is a plan view of the electronic device, and is a diagram illustrating a positional relationship between the first connection electrode, the second connection electrode, and the element, and a configuration in plan view of the element. FIG. 18A is a plan view illustrating a part of the element shown in FIG. 17 in an enlarged manner. 18B is a longitudinal sectional view in the length direction along BB of FIG. 18A drawn for explaining the configuration of the resistor in the element. FIG. 18C is a longitudinal sectional view in the width direction along CC of FIG. 18A drawn to explain the configuration of the resistor in the element. FIG. 19 is a diagram showing the electrical characteristics of the resistor film line and the wiring film with circuit symbols and electrical circuit diagrams. 20A is a partially enlarged plan view of a region including a fuse film drawn by enlarging a part of the plan view of the electronic device shown in FIG. 17, and FIG. 20B is a plan view of FIG. It is a figure which shows the cross-sectional structure which follows BB. FIG. 21 is an electric circuit diagram of an element according to the embodiment of the second invention. FIG. 22 is an electric circuit diagram of an element according to another embodiment of the second invention. FIG. 23 is an electric circuit diagram of an element according to still another embodiment of the second invention. FIG. 24 is a schematic cross-sectional view of an electronic device. 25A is a schematic cross-sectional view showing a method for manufacturing the electronic device shown in FIG. FIG. 25B is an illustrative sectional view showing a step subsequent to FIG. 25A. FIG. 25C is an illustrative sectional view showing a step subsequent to FIG. 25B. FIG. 25D is an illustrative sectional view showing a step subsequent to FIG. 25C. FIG. 25E is an illustrative sectional view showing a step subsequent to FIG. 25D. FIG. 25F is an illustrative sectional view showing a step subsequent to FIG. 25E. FIG. 26 is a schematic plan view of a part of a resist pattern used for forming a groove in the step of FIG. 25B. FIG. 27A is a schematic plan view of the wafer after the grooves are formed in the process of FIG. 25B, and FIG. 27B is an enlarged view of a part of FIG. FIGS. 28A and 28B are schematic perspective views showing a state in which a polyimide sheet is attached to a wafer in the step of FIG. 25D. FIG. 29A is a plan view of the electronic device, FIG. 29B is a plan view of the electronic device according to the first modification, and FIG. 29C is a second modification. It is a top view of the electronic device which concerns. FIG. 30A is a diagram illustrating a circuit configuration of an element according to another embodiment of the electronic device, and FIG. 30B is a diagram illustrating a circuit configuration of an element according to still another embodiment of the electronic device. It is. FIG. 31A is an illustrative perspective view showing an external configuration of the chip resistor 10 according to one embodiment of the third invention, and FIG. 31B shows the chip resistor 10 mounted on a substrate. It is a side view which shows the state. FIG. 32 is a plan view of the chip resistor 10, and shows a positional relationship between the first connection electrode 12, the second connection electrode 13, and the resistor network 14 and a configuration in plan view of the resistor network 14. FIG. 33A is an enlarged plan view of a part of the resistor network 14 shown in FIG. FIG. 33B is a longitudinal sectional view in the longitudinal direction drawn for explaining the configuration of the resistor R in the resistor network 14. FIG. 33C is a longitudinal sectional view in the width direction drawn for explaining the configuration of the resistor R in the resistor network 14. FIG. 34 is a diagram showing the electrical characteristics of the resistive film line 20 and the conductor film 21 with circuit symbols and electrical circuit diagrams. 35A is a partially enlarged plan view of a region including the fuse film F drawn by enlarging a part of the plan view of the chip resistor shown in FIG. 32, and FIG. 35B is a plan view of FIG. It is a figure which shows the cross-sectional structure which follows BB of). FIG. 36 shows the arrangement relationship of the connecting conductor film C and the fuse film F connecting the plurality of types of resistance unit bodies in the resistor network 14 shown in FIG. It is a figure which shows the connection relation with several types of resistance unit bodies diagrammatically. FIG. 37 is an electric circuit diagram of the resistor network 14. FIG. 38 is a plan view of the chip resistor 30, and shows a positional relationship between the first connection electrode 12, the second connection electrode 13, and the resistor network 14 and a configuration in plan view of the resistor circuit 14. FIG. 39 shows the arrangement relationship of the connecting conductor film C and the fuse film F connecting the plurality of types of resistance unit bodies in the resistor network 14 shown in FIG. It is a figure which shows the connection relation with several types of resistance unit bodies diagrammatically. FIG. 40 is an electric circuit diagram of the resistor network 14. FIG. 41 is a cross-sectional structure diagram showing a configuration example when the wiring film in an arbitrary region in the resistance network 14 has a laminated two-layer structure. 42A and 42B are electric circuit diagrams showing modifications of the electric circuit shown in FIG. FIG. 43 is an electric circuit diagram of a resistor network 14 according to still another embodiment of the third invention. FIG. 44 is an electric circuit diagram showing a configuration example of a resistance network in a chip resistor displaying a specific resistance value. FIG. 45 is a circuit diagram of the electronic apparatus 1 according to one embodiment of the third invention. FIG. 46 is an illustrative view illustrating that the chip resistor is cut out from the wafer. FIG. 47A is a schematic perspective view for explaining the configuration of an electronic apparatus according to an embodiment of the fourth invention, and FIG. 47B is a state in which the electronic apparatus is mounted on a circuit board. It is a typical side view which shows. FIG. 48 is a plan view of the electronic device, and is a diagram illustrating a positional relationship between the first connection electrode, the second connection electrode, and the element, and a configuration in plan view of the element. FIG. 49A is a plan view illustrating a part of the element shown in FIG. 48 in an enlarged manner. FIG. 49B is a longitudinal sectional view in the length direction along BB of FIG. 49A drawn for explaining the configuration of the resistor in the element. 49C is a longitudinal sectional view in the width direction along CC of FIG. 49A drawn to explain the configuration of the resistor in the element. FIG. 50 is a diagram showing the electrical characteristics of the resistor film line and the wiring film with circuit symbols and electrical circuit diagrams. 51A is a partially enlarged plan view of a region including a fuse film drawn by enlarging a part of the plan view of the electronic device shown in FIG. 48, and FIG. 51B is a plan view of FIG. It is a figure which shows the cross-sectional structure which follows BB. FIG. 52 is an electric circuit diagram of an element according to the embodiment of the fourth invention. FIG. 53 is an electric circuit diagram of an element according to another embodiment of the fourth invention. FIG. 54 is an electric circuit diagram of an element according to still another embodiment of the fourth invention. FIG. 55 is a schematic cross-sectional view of an electronic device. 56A is a schematic sectional view showing a method for manufacturing the electronic device shown in FIG. 55. FIG. FIG. 56B is a schematic sectional view showing a step subsequent to FIG. 56A. FIG. 56C is an illustrative sectional view showing a step subsequent to FIG. 56B. FIG. 56D is an illustrative sectional view showing a step subsequent to FIG. 56C. FIG. 56E is a schematic sectional view showing a step subsequent to FIG. 56D. FIG. 56F is an illustrative sectional view showing a step subsequent to FIG. 56E. FIG. 57 is a schematic plan view of a part of a resist pattern used for forming a groove in the step of FIG. 56B. FIG. 58 (a) is a schematic plan view of the wafer after the grooves are formed in the step of FIG. 56B, and FIG. 58 (b) is a partially enlarged view of FIG. 58 (a). FIGS. 59A and 59B are schematic perspective views showing a state in which a polyimide sheet is attached to a wafer in the step of FIG. 56D. 60A is a plan view of an electronic device, FIG. 60B is a plan view of the electronic device according to the first modification, and FIG. 60C is a second modification. It is a top view of the electronic device which concerns. 61A is a diagram illustrating a circuit configuration of an element according to another embodiment of the electronic device, and FIG. 61B is a diagram illustrating a circuit configuration of an element according to still another embodiment of the electronic device. It is. FIG. 62 (A) is an illustrative perspective view showing the external configuration of the chip resistor 10 according to one embodiment of the fifth invention, and FIG. 62 (B) shows the chip resistor 10 mounted on a substrate. It is a side view which shows the state. FIG. 63 is a plan view of the chip resistor 10, and shows a positional relationship between the first connection electrode 12, the second connection electrode 13, and the resistor network 14 and a configuration in plan view of the resistor network 14. 64A is a plan view illustrating a part of the resistor network 14 shown in FIG. 63 in an enlarged manner. FIG. 64B is a longitudinal sectional view in the length direction drawn for explaining the configuration of the resistor R in the resistor network 14. FIG. 64C is a longitudinal sectional view in the width direction drawn for explaining the configuration of the resistor R in the resistor network 14. FIG. 65 is a diagram showing the electrical characteristics of the resistance film line 20 and the wiring film 21 with circuit symbols and electrical circuit diagrams. 66A and 66B are views for explaining a manufacturing process (resistor film forming process) according to an embodiment of the fifth invention, wherein FIG. 66A is an example of sputtering, and FIG. 66B is another example of sputtering. Illustrated schematically. 67A is a partially enlarged plan view of a region including the fuse film F drawn by enlarging a part of the plan view of the chip resistor shown in FIG. 63, and FIG. 67B is a plan view of FIG. It is a figure which shows the cross-sectional structure which follows BB of). FIG. 68 shows the arrangement relationship between the connection wiring film C and the fuse film F connecting the plurality of types of resistance unit bodies in the resistance network 14 shown in FIG. It is a figure which shows the connection relation with several types of resistance unit bodies diagrammatically. FIG. 69 is an electric circuit diagram of the resistor network 14. FIG. 70 is a plan view of the chip resistor 30, showing the arrangement relationship of the first connection electrode 12, the second connection electrode 13, and the resistor network 14 and the configuration of the resistor network 14 in plan view. 71 shows the arrangement relationship between the connection wiring film C and the fuse film F for connecting a plurality of types of resistance unit bodies in the resistance network 14 shown in FIG. 70, and the connection wiring film C and the fuse film F connected thereto. It is a figure which shows the connection relation with several types of resistance unit bodies diagrammatically. FIG. 72 is an electric circuit diagram of the resistor network 14. 73A and 73B are electric circuit diagrams showing modifications of the electric circuit shown in FIG. FIG. 74 is an electric circuit diagram of a resistor network 14 according to still another embodiment of the fifth invention. FIG. 75 is an electric circuit diagram showing a configuration example of a resistance network in a chip resistor displaying a specific resistance value. FIG. 76 is an illustrative view showing a state in which the chip resistor 10 is cut out from the wafer. FIG. 77 (a) is a schematic perspective view for explaining the configuration of an electronic device according to an embodiment of the sixth invention, and FIG. 77 (b) is a state in which the electronic device is mounted on a circuit board. It is a typical side view which shows. FIG. 78 is a plan view of the electronic device, and is a diagram illustrating a positional relationship between the first connection electrode, the second connection electrode, and the element, and a configuration in plan view of the element. 79A is a plan view illustrating a part of the element shown in FIG. 78 in an enlarged manner. FIG. 79B is a longitudinal cross-sectional view in the length direction along BB of FIG. 79A drawn to explain the configuration of the resistor in the element. FIG. 79C is a longitudinal cross-sectional view in the width direction along CC of FIG. 79A drawn to explain the configuration of the resistor in the element. FIG. 80 is a diagram showing the electrical characteristics of the resistor film line and the wiring film with circuit symbols and electrical circuit diagrams. 81 (a) is a partially enlarged plan view of a region including a fuse film drawn by enlarging a part of the plan view of the electronic device shown in FIG. 78, and FIG. 81 (b) is a plan view of FIG. It is a figure which shows the cross-sectional structure which follows BB. FIG. 82 is an electric circuit diagram of an element according to the embodiment of the sixth invention. FIG. 83 is an electric circuit diagram of an element according to another embodiment of the sixth invention. FIG. 84 is an electric circuit diagram of an element according to still another embodiment of the sixth invention. FIG. 85 is a schematic cross-sectional view of an electronic device. 86A is a schematic sectional view showing a method for manufacturing the electronic device shown in FIG. 85. FIG. FIG. 86B is an illustrative sectional view showing a step subsequent to FIG. 86A. FIG. 86C is an illustrative sectional view showing a step subsequent to FIG. 86B. FIG. 86D is an illustrative sectional view showing a step subsequent to FIG. 86C. FIG. 86E is an illustrative sectional view showing a step subsequent to FIG. 86D. FIG. 86F is an illustrative sectional view showing a step subsequent to FIG. 86E. FIG. 87 is a schematic plan view of a part of a resist pattern used for forming a groove in the step of FIG. 86B. FIG. 88 (a) is a schematic plan view of the wafer after the grooves are formed in the step of FIG. 86B, and FIG. 88 (b) is a partially enlarged view of FIG. 88 (a). 89 (a) and 89 (b) are schematic perspective views showing a state in which a polyimide sheet is attached to a wafer in the step of FIG. 86D. 90A is a plan view of the electronic device, FIG. 90B is a plan view of the electronic device according to the first modification, and FIG. 90C is a second modification. It is a top view of the electronic device which concerns. FIG. 91A is a diagram illustrating a circuit configuration of an element according to another embodiment of the electronic device, and FIG. 91B is a diagram illustrating a circuit configuration of an element according to still another embodiment of the electronic device. It is. FIG. 92A is a schematic perspective view for explaining the configuration of an electronic device according to an embodiment of the seventh invention, and FIG. 92B is a state in which the electronic device is mounted on a circuit board. It is a typical side view which shows. FIG. 93 is a plan view of the electronic device, and is a diagram illustrating a positional relationship between the first connection electrode, the second connection electrode, and the element, and a configuration in a plan view of the element. FIG. 94A is an enlarged plan view showing a part of the element shown in FIG. FIG. 94B is a longitudinal cross-sectional view in the length direction along BB of FIG. 94A drawn for explaining the configuration of the resistor in the element. FIG. 94C is a longitudinal cross-sectional view in the width direction along CC of FIG. 94A drawn to explain the configuration of the resistor in the element. FIG. 95 is a diagram showing the electrical characteristics of the resistor film line and the wiring film with circuit symbols and electrical circuit diagrams. FIG. 96 (a) is a partially enlarged plan view of a region including a fuse film drawn by enlarging a part of the plan view of the electronic device shown in FIG. 93, and FIG. 96 (b) is a plan view of FIG. 96 (a). It is a figure which shows the cross-sectional structure which follows BB. FIG. 97 is an electric circuit diagram of an element according to the embodiment of the seventh invention. FIG. 98 is an electric circuit diagram of an element according to another embodiment of the seventh invention. FIG. 99 is an electric circuit diagram of an element according to still another embodiment of the seventh invention. FIG. 100 is a schematic cross-sectional view of an electronic device. 101A is a schematic cross-sectional view showing a method for manufacturing the electronic device shown in FIG. 100. FIG. FIG. 101B is an illustrative sectional view showing a step subsequent to FIG. 101A. FIG. 101C is an illustrative sectional view showing a step subsequent to FIG. 101B. FIG. 101D is an illustrative sectional view showing a step subsequent to FIG. 101C. FIG. 101E is an illustrative sectional view showing a step subsequent to FIG. 101D. FIG. 101F is an illustrative sectional view showing a step subsequent to FIG. 101E. FIG. 102 is a schematic plan view of a part of a resist pattern used for forming a groove in the step of FIG. 101B. FIG. 103 (a) is a schematic plan view of the wafer after the grooves are formed in the step of FIG. 101B, and FIG. 103 (b) is a partially enlarged view of FIG. 103 (a). 104 (a) and 104 (b) are schematic perspective views showing a state in which a polyimide sheet is attached to the wafer in the step of FIG. 101D. 105 (a) is a plan view of the electronic device, FIG. 105 (b) is a plan view of the electronic device according to the first modification, and FIG. 105 (c) is a second modification. It is a top view of the electronic device which concerns. FIG. 106A is a diagram illustrating a circuit configuration of an element according to another embodiment of the electronic device, and FIG. 106B is a diagram illustrating a circuit configuration of an element according to still another embodiment of the electronic device. It is. FIG. 107 (a) is a schematic perspective view for explaining the configuration of the chip resistor according to one embodiment of the eighth invention, and FIG. 107 (b) is a diagram showing that the chip resistor is mounted on a circuit board. It is a typical side view which shows the state. FIG. 108 is a plan view of the chip resistor, showing the arrangement relationship of the first connection electrode, the second connection electrode and the element, and the configuration of the element in plan view. FIG. 109A is an enlarged plan view of a part of the element shown in FIG. FIG. 109B is a longitudinal cross-sectional view in the length direction along BB of FIG. 109A drawn to explain the configuration of the resistor in the element. FIG. 109C is a longitudinal sectional view in the width direction along CC of FIG. 109A drawn to explain the configuration of the resistor in the element. FIG. 110 is a diagram showing the electrical characteristics of the resistor film line and the wiring film with circuit symbols and electrical circuit diagrams. FIG. 111A is a partially enlarged plan view of a region including a fuse film drawn by enlarging a part of the plan view of the chip resistor shown in FIG. 108, and FIG. 111B is a plan view of FIG. 111A. It is a figure which shows the cross-sectional structure in alignment with BB. FIG. 112 is an electric circuit diagram of an element according to the embodiment of the eighth invention. FIG. 113 is an electric circuit diagram of an element according to another embodiment of the eighth invention. FIG. 114 is an electric circuit diagram of an element according to still another embodiment of the eighth invention. FIG. 115 is a schematic cross-sectional view of a chip resistor. 116A is a schematic cross-sectional view showing a method for manufacturing the chip resistor shown in FIG. 115. FIG. 116B is a schematic sectional view showing a step subsequent to FIG. 116A. FIG. 116C is an illustrative sectional view showing a step subsequent to FIG. 116B. FIG. 116D is an illustrative sectional view showing a step subsequent to FIG. 116C. FIG. 116E is an illustrative sectional view showing a step subsequent to FIG. 116D. FIG. 116F is a schematic sectional view showing a step subsequent to FIG. 116E. FIG. 116G is an illustrative sectional view showing a step subsequent to FIG. 116F. 117 is a schematic plan view of a part of a resist pattern used for forming a groove in the step of FIG. 116B. 118 (a) is a schematic plan view of the substrate after the grooves are formed in the step of FIG. 116B, and FIG. 118 (b) is a partially enlarged view of FIG. 118 (a). FIG. 119A is a schematic cross-sectional view during the manufacture of the chip resistor according to one embodiment of the eighth invention. FIG. 119B is a schematic cross-sectional view during the manufacture of the chip resistor according to the comparative example. 120 (a) and 120 (b) are schematic perspective views showing a state in which a polyimide sheet is attached to the substrate in the process of FIG. 116D. FIG. 121 is an illustrative perspective view showing a semi-finished chip resistor immediately after the step of FIG. 116G. FIG. 122 is a first schematic diagram showing a process subsequent to that in FIG. 116G. FIG. 123 is a second schematic diagram showing a process subsequent to that in FIG. 116G.

Hereinafter, embodiments of the first invention will be described in detail with reference to the accompanying drawings.
FIG. 1A is an illustrative perspective view showing an external configuration of a chip resistor 10 according to an embodiment of the first invention, and FIG. 1B shows the chip resistor 10 mounted on a substrate. It is a side view which shows the state.
Referring to FIG. 1A, a chip resistor 10 according to an embodiment of the first invention includes a first connection electrode 12, a second connection electrode 13, and a resistor formed on a substrate 11 as a substrate. And a network 14. The substrate 11 has a substantially rectangular parallelepiped shape in plan view. For example, the length L in the long side direction is 0.3 mm, the width W in the short side direction is 0.15 mm, and the thickness T of the substrate 11 is about 0.1 mm. It is a very small chip.

As shown in FIG. 15, the chip resistor 10 is obtained by forming a large number of chip resistors 10 on a wafer in a lattice shape, and cutting the wafer into individual chip resistors 10. .
On the substrate 11, the first connection electrode 12 is a rectangular electrode that is provided along one short side 111 of the substrate 11 and is long in the direction of the short side 111. The second connection electrode 13 is a rectangular electrode extending in the direction of the short side 112 provided along the other short side 112 on the substrate 11. The resistance network 14 is provided in a central region sandwiched between the first connection electrode 12 and the second connection electrode 13 on the substrate 11. One end side of the resistor network 14 is electrically connected to the first connection electrode 12, and the other end side of the resistor network 14 is electrically connected to the second connection electrode 13. As will be described later, the first connection electrode 12, the second connection electrode 13, and the resistance network 14 are provided on the substrate 11 by using, for example, a semiconductor manufacturing process. Therefore, a semiconductor substrate (semiconductor wafer) such as a silicon substrate (silicon wafer) can be used as the substrate 11. The substrate 11 may be another type of substrate such as an insulating substrate.

  The first connection electrode 12 and the second connection electrode 13 each function as an external connection electrode. In a state where the chip resistor 10 is mounted on the circuit board 15, as shown in FIG. 1B, the first connection electrode 12 and the second connection electrode 13 are respectively connected to a circuit (not shown) of the circuit board 15. ) And solder and are electrically and mechanically connected. The first connection electrode 12 and the second connection electrode 13 that function as external connection electrodes are made of gold (Au) or plated with gold in order to improve solder wettability and reliability. It is desirable.

FIG. 2 is a plan view of the chip resistor 10, showing the arrangement relationship of the first connection electrode 12, the second connection electrode 13, and the resistor network 14 and the configuration of the resistor network 14 in plan view.
Referring to FIG. 2, the chip resistor 10 includes a first connection electrode 12 that is disposed along one short side 111 on the upper surface of the substrate and has a substantially rectangular shape in plan view in the width direction, and the other short side 112 on the upper surface of the substrate. A second connection electrode 13 having a substantially rectangular shape in plan view that is long in the width direction, and a resistor network 14 provided in a rectangular region in plan view between the first connection electrode 12 and the second connection electrode 13; Is included.

  The resistor network 14 includes a plurality of resistors R having the same resistance value arranged in a matrix on the substrate 11 (in the example of FIG. 2, eight resistors along the row direction (longitudinal direction of the substrate)). Resistors R are arranged, and 44 resistors are arranged along the column direction (substrate width direction), and a total of 352 resistor R configurations) are provided. One to 64 of these many resistors R are electrically connected to form a plurality of types of resistance unit bodies. The plurality of types of resistance unit bodies formed are connected in a predetermined manner by a conductor film (a wiring film formed of a conductor) as a circuit network connecting means. Further, a plurality of fuse films F that can be blown in order to electrically incorporate the resistance unit into the resistance network 14 or to be electrically separated from the resistance network 14 are provided. The plurality of fuse films F are arranged along the inner side of the second connection electrode 13 so that the arrangement region is linear. More specifically, a plurality of fuse films F and connecting conductor films C are arranged in a straight line.

3A is an enlarged plan view of a part of the resistor network 14 shown in FIG. 2, and FIGS. 3B and 3C are drawn to explain the structure of the resistor R in the resistor network 14, respectively. It is the longitudinal cross-sectional view of the length direction, and the longitudinal cross-sectional view of the width direction.
The configuration of the resistor R will be described with reference to FIGS. 3A, 3B, and 3C.
An insulating layer (SiO ₂ ) 19 is formed on the upper surface of the substrate 11 as a substrate, and a resistor film 20 constituting the resistor R is disposed on the insulating layer 19. The resistor film 20 is made of TiN or TiON. The resistor film 20 includes a plurality of resistor films (hereinafter referred to as “resistor film lines”) extending in a line between the first connection electrode 12 and the second connection electrode 13. The line 20 may be cut at a predetermined position in the line direction. On the resistor film line 20, an aluminum film as the conductor film 21 is laminated. The conductor film 21 is laminated on the resistor film line 20 with a constant interval R in the line direction.

  The electrical characteristics of the resistor film line 20 and the conductor film 21 having this configuration are shown by circuit symbols as shown in FIG. That is, as shown in FIG. 4A, the resistor film lines 20 in the region of the predetermined interval R each form a resistor R having a constant resistance value r. In the region where the conductor film 21 is laminated, the resistor film line 20 is short-circuited by the conductor film 21. Therefore, a resistance circuit is formed which is formed by connecting in series the resistor R of the resistor r shown in FIG.

Further, since the adjacent resistor film lines 20 are connected to each other by the resistor film 20 and the conductor film 21, the resistor network shown in FIG. 3A constitutes the resistor circuit shown in FIG. 4C.
Here, the manufacturing process of the resistor network 14 will be briefly described.
(1) The surface of the substrate 11 is thermally oxidized to form a silicon dioxide (SiO 2) layer as the insulating layer 19.
(2) A resistor film 20 of TiN, TiON, or TiSiON is formed on the entire surface of the insulating layer 19 by sputtering.
(3) Furthermore, an aluminum (Al) conductor film 21 is laminated on the resistor film 20 by sputtering.
(4) Thereafter, using a photolithography process, the conductor film 21 and the resistor film 20 are selectively removed by dry etching, for example, and as shown in FIG. A configuration is obtained in which the conductor films 21 are arranged in the column direction at regular intervals. At this time, a region in which the resistor film line 20 and the conductor film 21 are partially cut is also formed.
(5) Subsequently, the conductor film 21 laminated on the resistor film line 20 is selectively removed. As a result, a configuration in which the conductor film 21 is laminated on the resistor film line 20 with a constant interval R is obtained.
(6) Thereafter, a SiN film 22 as a protective film is deposited, and a polyimide layer 23 as a protective layer is further laminated thereon.

  In this embodiment, the resistor R included in the resistor network 14 formed on the substrate 11 is laminated on the resistor film line 20 and the resistor film line 20 with a certain interval in the line direction. A resistor film line 20 at a constant interval R that includes the conductor film 21 and on which the conductor film 21 is not laminated constitutes one resistor R. The resistor film lines 20 constituting the resistor R are all equal in shape and size. Therefore, based on the characteristic that the same-shaped and large-sized resistor films formed on the substrate have substantially the same value, the multiple resistors R arranged in a matrix on the substrate 11 have the same resistance value. doing.

The conductor film 21 laminated on the resistor film line 20 forms a resistor R and also serves as a connecting conductor film for connecting a plurality of resistors R to form a resistance unit body. .
5A is a partially enlarged plan view of a region including the fuse film F drawn by enlarging a part of the plan view of the chip resistor 10 shown in FIG. 2, and FIG. It is a figure which shows the cross-section which follows BB of A).

  As shown in FIGS. 5A and 5B, the fuse film F is also formed of a conductor film 21 laminated on the resistor film 20 forming the resistor R. That is, it is formed of aluminum (Al), which is the same metal material as the conductor film 21, in the same layer as the conductor film 21 stacked on the resistor film line 20 that forms the resistor R. As described above, the conductor film 21 is also used as the connection conductor film 21 for electrically connecting a plurality of resistors R in order to form a resistance unit body.

  That is, in the same layer laminated on the resistor film 20, the conductor film for forming the resistor R, the connecting conductor film for forming the resistance unit body, and the connecting conductor film for configuring the resistor network 14 , The fuse film, and the conductor film for connecting the resistor network 14 to the first connection electrode 12 and the second connection electrode 13 are made of the same manufacturing process (sputtering and photolithography) using the same metal material (for example, aluminum). Process). Thereby, the manufacturing process of this chip resistor 10 is simplified, and various conductive films can be simultaneously formed using a common mask. Furthermore, the alignment with the resistor film 20 is also improved.

FIG. 6 shows the arrangement relationship of the connecting conductor film C and the fuse film F connecting the plurality of types of resistance unit bodies in the resistor network 14 shown in FIG. It is a figure which shows the connection relation with several types of resistance unit bodies diagrammatically.
Referring to FIG. 6, one end of a reference resistance unit R <b> 8 included in the resistance network 14 is connected to the first connection electrode 12. The reference resistance unit R8 is composed of eight resistors R connected in series, and the other end is connected to the fuse film F1. One end and the other end of a resistance unit body R64 formed of a series connection of 64 resistors R are connected to the fuse film F1 and the connecting conductor film C2. One end and the other end of a resistance unit body R32 formed of a series connection of 32 resistors R are connected to the connecting conductor film C2 and the fuse film F4. One end and the other end of a resistance unit body R32 composed of a series connection of 32 resistors R are connected to the fuse film F4 and the connecting conductor film C5. One end and the other end of a resistance unit body R16 formed by connecting 16 resistor bodies R in series are connected to the connecting conductor film C5 and the fuse film F6. One end and the other end of a resistance unit body R8 composed of eight resistors R connected in series are connected to the fuse film F7 and the connecting conductor film C9. One end and the other end of a resistance unit body R4 composed of four resistors R connected in series are connected to the connecting conductor film C9 and the fuse film F10. One end and the other end of a resistance unit body R2 made of a series connection of two resistors R are connected to the fuse film F11 and the connecting conductor film C12. One end and the other end of a resistance unit body R1 including one resistor R are connected to the connecting conductor film C12 and the fuse film F13. One end and the other end of a resistance unit body R / 2 composed of two resistors R connected in parallel are connected to the fuse film F13 and the connecting conductor film C15. One end and the other end of a resistance unit body R / 4 formed of four resistors R connected in parallel are connected to the connecting conductor film C15 and the fuse film F16. One end and the other end of a resistance unit body R / 8 composed of eight resistors R connected in parallel are connected to the fuse film F16 and the connecting conductor film C18. One end and the other end of a resistance unit body R / 16 formed by parallel connection of 16 resistors R are connected to the connecting conductor film C18 and the fuse film F19. The fuse film F19 and the connecting conductor film C22 are connected to a resistance unit R / 32 composed of 32 resistors R connected in parallel.

  The plurality of fuse films F and the connecting conductor film C are respectively a fuse film F1, a connecting conductor film C2, a fuse film F3, a fuse film F4, a connecting conductor film C5, a fuse film F6, a fuse film F7, and a connecting conductor. Film C8, connecting conductor film C9, fuse film F10, fuse film F11, connecting conductor film C12, fuse film F13, fuse film F14, connecting conductor film C15, fuse film F16, fuse film F17, connecting conductor film C18 The fuse film F19, the fuse film F20, the connecting conductor film C21, and the connecting conductor film C22 are arranged in a straight line and connected in series. When each fuse film F is melted, the electrical connection with the connection conductor film C adjacently connected to the fuse film F is cut off.

  This configuration is shown in an electric circuit diagram as shown in FIG. In other words, in a state where all the fuse films F are not blown, the resistance network 14 has a reference resistance composed of eight resistors R provided in series between the first connection electrode 12 and the second connection electrode 13. A resistance circuit of the unit body R8 (resistance value 8r) is configured. For example, if the resistance value r of one resistor R is r = 80Ω, the chip resistor 10 to which the first connection electrode 12 and the second connection electrode 13 are connected is configured by a resistance circuit of 8r = 640Ω. ing.

  A plurality of types of resistance unit bodies other than the reference resistance unit body R8 are connected in parallel to the fuse film F, and the plurality of types of resistance unit bodies are short-circuited by each fuse film F. Yes. That is, 12 types of 13 resistance unit bodies R64 to R / 32 are connected in series to the reference resistance unit body R8, but each resistance unit body is short-circuited by the fuse film F connected in parallel. Therefore, when viewed electrically, each resistance unit is not incorporated in the resistance network 14.

  The chip resistor 10 according to this embodiment selectively melts the fuse film F with, for example, laser light according to a required resistance value. As a result, the resistance unit body in which the fuse films F connected in parallel are melted is incorporated in the resistance network 14. Therefore, the entire resistance value of the resistor network 14 can be a resistor network having a resistance value in which resistance unit bodies corresponding to the blown fuse film F are connected in series.

  In other words, the chip resistor 10 according to the present embodiment selectively blows a fuse film provided corresponding to a plurality of types of resistance unit bodies, so that a plurality of types of resistance unit bodies (for example, F1,. When F4 and F13 are fused, the resistance unit bodies R64, R32, and R1 can be incorporated into the resistor network. Since the resistance value of each of the plurality of types of resistance units is determined, the resistance value of the resistance network 14 is digitally adjusted to make the chip resistor 10 having the required resistance value. be able to.

  In addition, the plurality of types of resistance unit bodies include one, two, four, eight, sixteen, thirty-two, and sixty-four resistors R having equal resistance values in series. A plurality of types of series resistance units connected by increasing the number of resistors R, and two, four, eight, sixteen, and thirty-two resistors R having the same resistance value in parallel, a geometric sequence A plurality of types of parallel resistance units connected to each other by increasing the number of resistors R are provided, and these units are connected in series in a state of being short-circuited by the fuse film F, so the fuse film F is selected. By fusing, the resistance value of the entire resistor network 14 can be set to an arbitrary resistance value within a wide range from a small resistance value to a large resistance value.

  FIG. 8 is a plan view of a chip resistor 30 according to another embodiment of the first invention. The arrangement relationship of the first connection electrode 12, the second connection electrode 13, and the resistor network 4 and the plane of the resistor network 14 are shown. The visual configuration is shown. The difference between the chip resistor 30 and the chip resistor 10 described above is the connection mode of the resistor R in the resistor network 14. That is, the resistor network 14 of the chip resistor 30 includes a large number of resistors R having equal resistance values arranged in a matrix on the substrate (in the configuration of FIG. 8, in the row direction (longitudinal direction of the substrate)). 8 resistors R are arrayed along with 44 resistors along the column direction (substrate width direction), and a total of 352 resistor R configurations). One to 128 of these many resistors R are electrically connected to form a plurality of types of resistance unit bodies. The formed plural types of resistance unit bodies are connected in a parallel manner by a conductor film and a fuse film F as circuit network connecting means. The plurality of fuse films F are arranged along the inner side of the second connection electrode 13 so that the arrangement region is linear, and when the fuse film F is blown, the resistance unit body connected to the fuse film Is electrically separated from the resistor network 14.

The structure of the multiple resistors R constituting the resistor network 14, the structure of the connecting conductor film, and the fuse film F are the same as the structure of the corresponding portion in the chip resistor 10 described above. The description here will be omitted.
FIG. 9 shows a connection mode of a plurality of types of resistance unit bodies in the resistance network shown in FIG. 8, an arrangement relationship of fuse films F connecting them, and a connection relationship of a plurality of types of resistance unit bodies connected to the fuse film F. FIG.

  Referring to FIG. 9, one end of a reference resistance unit R / 16 included in the resistance network 14 is connected to the first connection electrode 12. The reference resistance unit R / 16 is composed of 16 resistors R connected in parallel, and the other end is connected to a connecting conductor film C to which the remaining resistor units are connected. One end and the other end of a resistance unit body R128 comprising 128 resistors R connected in series are connected to the fuse film F1 and the connecting conductor film C. One end and the other end of a resistance unit body R64 composed of 64 resistors R connected in series are connected to the fuse film F5 and the connecting conductor film C. One end and the other end of a resistance unit body R32 formed of a series connection of 32 resistors R are connected to the fuse film F6 and the connecting conductor film C. One end and the other end of a resistance unit body R <b> 16 including 16 resistors R connected in series are connected to the fuse film F <b> 7 and the connecting conductor film C. One end and the other end of a resistance unit body R8 composed of eight resistors R connected in series are connected to the fuse film F8 and the connecting conductor film C. One end and the other end of a resistance unit body R4 composed of four resistors R connected in series are connected to the fuse film F9 and the connecting conductor film C. One end and the other end of a resistance unit body R2 formed by connecting two resistors R in series are connected to the fuse film F10 and the connecting conductor film C. One end and the other end of a resistance unit body R <b> 1 composed of a series connection of one resistor R are connected to the fuse film F <b> 11 and the connecting conductor film C. One end and the other end of a resistance unit body R / 2 composed of two resistors R connected in parallel are connected to the fuse film F12 and the connecting conductor film C. The fuse film F13 and the connecting conductor film C are connected to one end and the other end of a resistance unit R / 4 formed by connecting four resistors R in parallel. The fuse films F14, F15, and F16 are electrically connected, and the fuse films F14, F15, and F16 and the connecting conductor film C are connected to the resistance unit R / R that includes eight resistors R connected in parallel. One end and the other end of 8 are connected. The fuse films F17, F18, F19, F20, and F21 are electrically connected, and the fuse films F17 to F21 and the connecting conductor film C have a resistance unit body composed of 16 resistors R connected in parallel. One end and the other end of R / 16 are connected.

The fuse film F includes 21 fuse films F <b> 1 to F <b> 21, all of which are connected to the second connection electrode 13.
With this configuration, when one of the fuse films F to which one end of the resistance unit body is connected is blown, the resistance unit body having one end connected to the fuse film F is electrically connected from the resistance network 14. Disconnected.

  The configuration of FIG. 9, that is, the configuration of the resistor network 14 provided in the chip resistor 30 is shown in an electric circuit diagram as shown in FIG. 10. In a state in which all the fuse films F are not blown, the resistance network 14 includes a reference resistance unit body R8, 12 types of resistance unit bodies R / 16, between the first connection electrode 12 and the second connection electrode 13. A series connection circuit is formed with a parallel connection circuit of R / 8, R / 4, R / 2, R1, R2, R4, R8, R16, R32, R64, and R128.

  A fuse film F is connected in series to each of 12 types of resistance unit bodies other than the reference resistance unit body R / 16. Therefore, in the chip resistor 30 having the resistance network 14, if the fuse film F is selectively blown by, for example, laser light according to a required resistance value, a resistance corresponding to the blown fuse film F is obtained. The unit body (resistance unit body in which the fuse film F is connected in series) is electrically separated from the resistance network 14, and the resistance value of the chip resistor 10 can be adjusted.

  In other words, the chip resistor 30 according to this embodiment also selectively blows the fuse film provided corresponding to the plurality of types of resistance unit bodies, thereby removing the plurality of types of resistance unit bodies from the resistor network. It can be electrically separated. Since the resistance value of each of the plurality of types of resistance units is determined, the resistance value of the resistance network 14 is digitally adjusted so that the chip resistor 30 having the required resistance value is obtained. be able to.

  In addition, the plurality of types of resistance unit bodies include one, two, four, eight, sixteen, thirty-two, sixty-four, and 128 resistors R having the same resistance value in series. A plurality of types of series resistance units connected by increasing the number of resistors R and two, four, eight, and sixteen resistors R having the same resistance value in parallel are in a geometric sequence. Since a plurality of types of parallel resistance unit bodies connected by increasing the number of the resistors R are provided, by selectively fusing the fuse film F, the resistance value of the entire resistor network 14 is reduced finely and Digitally, any resistance value can be set.

In the electric circuit shown in FIG. 10, among the reference resistance unit R / 16 and the resistance unit bodies connected in parallel, the resistance unit body having a small resistance value tends to flow an overcurrent, and the resistance setting is performed. Sometimes, it is necessary to design a large rated current that can flow through the resistor.
Therefore, in order to disperse the current, the connection structure of the resistor network may be changed so that the electric circuit shown in FIG. 10 has the electric circuit configuration shown in FIG. That is, the resistance unit bodies connected in parallel without the reference resistance unit R / 16 include a configuration 140 in which a minimum resistance value is r and a plurality of resistance unit bodies R1 having a resistance value r are connected in parallel. It turns into a circuit. FIG. 11B is an electric circuit diagram showing a specific resistance value, which is a circuit including a configuration 140 in which a plurality of series connections of 80Ω resistance unit bodies and fuse films F are connected in parallel. . Thereby, distribution of the flowing current can be achieved.

  FIG. 12 is an electric circuit diagram showing a circuit configuration of a resistor network 14 provided in a chip resistor according to still another embodiment of the first invention. The characteristic of the resistance network 14 shown in FIG. 12 is that the circuit configuration is such that a series connection of a plurality of types of resistance unit bodies and a parallel connection of a plurality of types of resistance unit bodies are connected in series. As in the previous embodiment, the plurality of types of resistance unit bodies connected in series are connected to the fuse film F in parallel for each resistance unit body, and the plurality of types of resistance unit bodies connected in series are: All are short-circuited by the fuse film F. Therefore, when the fuse film F is melted, the resistance unit body short-circuited by the fuse film F is electrically incorporated into the resistance network 14.

On the other hand, a fuse film F is connected in series to each of a plurality of types of resistance unit bodies connected in parallel. Therefore, by fusing the fuse film F, the resistance unit bodies to which the fuse film F is connected in series can be electrically disconnected from the parallel connection of the resistance unit bodies.
With this configuration, for example, a small resistance of 1 kΩ or less can be made on the parallel connection side, and a resistance circuit of 1 kΩ or more can be made on the series connection side. Therefore, a wide range of resistance circuits from a small resistance of several Ω to a large resistance of several MΩ can be made using the resistance network 14 configured with the same basic design.

When setting the resistance value with higher accuracy, if the fuse film of the resistance circuit on the series connection side that is close to the required resistance value is cut in advance, fine adjustment of the resistance value can be performed on the fuse film of the resistance circuit on the parallel connection side. This can be performed by fusing, and the accuracy of adjustment to a desired resistance value is increased.
FIG. 13 is an electric circuit diagram showing a specific configuration example of the resistor network 14 in the chip resistor having a resistance value of 10Ω to 1MΩ.

13 also includes a series connection of a plurality of types of resistance unit bodies short-circuited by the fuse film F and a series connection of a plurality of types of resistance unit bodies to which the fuse film F is connected in series. The circuit configuration is as described above.
According to the resistance circuit of FIG. 13, an arbitrary resistance value of 10 to 1 kΩ can be set within an accuracy of 1% on the parallel connection side. In addition, an arbitrary resistance value of 1 k to 1 MΩ can be set within an accuracy of 1% in the circuit on the serial connection side. When using a circuit on the serial connection side, it is possible to set the resistance value with higher accuracy by fusing the fuse film F of the resistance unit body close to the desired resistance value in advance and adjusting it to the desired resistance value. There are advantages.

The fuse film F has been described only in the case of using the same layer as the connection conductor film C. However, the connection conductor film C portion is formed by stacking another conductor film on the conductor film C. The resistance value may be lowered. Even in this case, if the conductor film is not laminated on the fuse film F, the fusing property of the fuse film F does not deteriorate.
FIG. 14 is a diagram illustrating a circuit configuration of the electronic apparatus 1 in which another circuit is incorporated in the above-described chip resistor.

The electronic device 1 is, for example, a diode 55 and a resistor network 14 connected in series. This electronic device 1 is a chip-type electronic device including a diode 55. The first invention can be applied not only to the chip type as in this example but also to an electronic device having the above-described resistance network 14.
In addition, the following features can be extracted from the above-described embodiment.

  The invention according to Item 1 is a substrate having one surface as a mounting surface and the other surface on the opposite side, a first connection electrode and a second connection electrode formed on the one surface of the substrate, and the substrate A resistive circuit network formed on one side and connected to the first connection electrode at one end side and connected to the second connection electrode at the other end side, and the resistance network is formed in a matrix on the substrate A plurality of resistors having the same resistance value, a plurality of types of resistor units configured by electrically connecting one or more of the resistors, and the plurality of types of resistor units. Circuit network connection means for connecting the resistor unit bodies in a predetermined manner, and individually corresponding to the resistor unit bodies, and the resistor unit bodies are electrically incorporated in the resistor circuit network, or electrically connected to the resistor unit network. Multiples that can be melted apart A fuse film, and the resistor includes a resistance film line extending on the substrate, and a conductor film laminated on the resistance film line at a predetermined interval in the line direction, in plan view, The resistor film lines of the constant interval where the conductor films are not stacked constitute one resistor so that the resistor film lines and the conductor films having a constant width are alternately arranged with a constant interval. It is a chip resistor characterized by having.

In the invention according to Item 2, the conductor film of the resistor, the connection conductor film included in the resistance unit body, the connection conductor film included in the network connection means, and the fuse film are formed in the same layer. Item 2. The chip resistor according to Item 1, comprising a metal film of the same material.
The invention according to Item 3 is the chip resistor according to Item 1 or 2, wherein the resistor unit includes a plurality of the resistors connected in series.

The invention according to Item 4 is the chip resistor according to Item 1 or 2, wherein the resistance unit includes a plurality of the resistors connected in parallel.
Item 5 is the invention according to Items 1 to 4, wherein the plurality of types of resistance unit bodies are set with the number of connected resistors, and the resistance values form a geometric progression with respect to each other. The chip resistor according to any one of the above.

Item 6 is the chip resistor according to any one of Items 1 to 5, wherein the network connection means includes a conductive film for connecting the plurality of types of resistance unit bodies in series. It is a vessel.
Item 7. The chip resistor according to any one of Items 1 to 6, wherein the network connection means includes a conductive film for connection that connects the plurality of types of resistance unit bodies in parallel. It is a vessel.

The invention according to Item 8 is characterized in that the plurality of fuse films are arranged linearly along one end of a matrix arrangement of the plurality of resistors. It is a chip resistor of description.
The invention according to Item 9 is characterized in that the resistance unit body is configured by connecting a predetermined number of resistors and includes a reference resistance unit body that is incorporated into the resistor network and cannot be separated. The chip resistor according to any one of 8.

The invention according to Item 10 is the chip resistor according to any one of Items 1 to 9, wherein the resistance film line of the resistor is formed of TiN, TiON, or TiSiON.
The invention according to Item 11 is the chip resistor according to any one of Items 1 to 10, wherein the resistance film line and the conductor film are formed by patterning all together.

The invention according to item 12 is the chip resistor according to any one of items 1 to 11, further including a protective layer made of polyimide covering the one surface of the substrate.
The invention according to Item 13 is a substrate having one surface as a mounting surface and the other surface on the opposite side, a first connection electrode and a second connection electrode formed on the one surface of the substrate, A resistor network having a plurality of resistors formed on the one surface, connected at one end side to the first connection electrode and connected at the other end side to the second connection electrode by a wiring film; An electronic apparatus comprising: a plurality of fuse films that can be blown in order to electrically incorporate a resistor into the resistor network or to electrically separate the resistor from the resistor network.

Item 14 is the electronic device according to Item 13, wherein the resistor is made of TiON or TiSiON.
Item 15 is the electronic device according to Item 13 or 14, wherein the resistor and the wiring film are patterned at once.
According to the invention described in item 1, a resistor network can be formed on a substrate, and a large number of high-quality chip resistors can be manufactured by one manufacturing.

In addition, since the resistor network is formed, the resistance network can be miniaturized and the chip resistor can be made smaller than before.
Furthermore, the resistor network includes a large number of resistors having equal resistance values arranged in a matrix, and the required resistance value can be easily changed by changing the connection mode of the large number of resistors. It can correspond to.

Furthermore, it is possible to easily cope with a change in the required resistance value by changing the connection mode of a plurality of types of resistance unit bodies.
Furthermore, the resistance value of the resistance circuit network can be reduced by fusing any fuse film of the plurality of fuse films and electrically incorporating the resistance unit body into the resistance network or electrically separating it from the resistance network. In addition to being able to adjust, the resistance value of the chip resistor can be matched to a plurality of types of required resistance values without changing the basic design. Thereby, it is possible to provide a chip resistor having the same basic design and having the resistance value as a required resistance value.

  In the invention according to item 1, each of a plurality of resistors having the same resistance value arranged in a matrix is laminated on the resistance film line and the resistance film line at a predetermined interval in the line direction. A conductive film. For this reason, the resistive film area | region where the conductor film is not laminated | stacked functions as one resistor. The resistance film regions can be formed in the same size by setting the intervals between the laminated conductor films to be constant. And, using the characteristic that the resistance value of the same size and shape of the resistor (resistive film) made on the substrate is almost the same value, a large number of resistors can be easily configured with a common layout pattern. Can be formed.

According to the invention described in Item 2, the conductor film of the resistor, the connection conductor film included in the resistance unit body, the connection conductor film included in the network connection means, and the fuse film are formed on the same layer. Then, by removing unnecessary portions of the metal film by etching or the like, a plurality of types of metal films (conductor films) can be easily formed at a time by a relatively small number of processes.
According to the invention described in Item 3, since the resistance unit body is formed by connecting a plurality of resistors in series, a resistance unit body having a large resistance value can be configured.

According to the invention described in Item 4, since the resistance unit body is formed by connecting a plurality of resistors in parallel, a resistance unit body having a small resistance value and a small error between the resistance values can be configured. it can.
According to the invention described in item 5, since the resistance values of the resistance units form a geometric progression, the resistance values of the resistance units are set in various types from a relatively small resistance value to a relatively large resistance value. it can. Thereby, even if the required resistance value required for the chip resistor varies depending on the connection mode of the resistance unit bodies, it is possible to cope with the same design contents.

According to invention of claim | item 6, a resistance unit body can be connected in series and a chip resistor with a large resistance value can be comprised.
According to the invention described in Item 7, it is possible to provide a chip resistor capable of coping with various required resistance values by finely adjusting the resistance value of the chip resistor by connecting the resistance unit bodies in parallel.
According to the invention described in item 8, since the fuse film is arranged linearly along one end of the matrix arrangement of the resistors, a chip that is easily blown when the fuse film is selectively blown. It can be a resistor.

According to the invention described in item 9, since the reference resistance unit is included, it is possible to provide a resistor in which the resistance value of the chip resistor can be easily set.
As described in Item 10, it is preferable in manufacturing that the resistor is made of TiN, TiON, or TiSiON.
If the resistor film and the conductor film are patterned together as described in Item 11, the manufacturing process can be simplified and the circuit accuracy is improved.

According to the inventions of Items 13 to 15, by fusing an arbitrary fuse film of the plurality of fuse films, the resistor is electrically incorporated into the resistor network, or electrically separated from the resistor network, The resistance value of the resistor network can be adjusted, and it can be matched to a plurality of types of required resistance values without changing the basic design. As a result, it is possible to provide an electronic apparatus having a resistance circuit network of the same basic design and having the resistance value required.
<Second invention>
(1) Features of the second invention For example, the features of the second invention are the following A1 to A11.
(A1) A substantially rectangular parallelepiped substrate having an element formation surface and a plurality of side surfaces perpendicular to the element formation surface, an element formed on the element formation surface of the substrate, a wiring film connected to the element, and the substrate A chip component including an external connection electrode formed on an element formation surface, wherein a corner portion where the plurality of side surfaces intersect is shaped into a round shape.

According to this configuration, since the corner portion of the chip component is round, chipping can be prevented and productivity can be improved.
(A2) The chip component according to A1, further including a protective film formed on the substrate so as to cover the element and the wiring film, and a corner portion of the protective film having a round shape.
According to this configuration, the element and the wiring film can be protected by the protective film, and the occurrence of chipping at the corner portion of the protective film can be prevented.
(A3) The chip component according to A2, wherein the element includes a resistor formed of a thin film resistor formed on the substrate, and the wiring film forms a wiring connected to the resistor.

Thereby, the chip component can be configured as a chip resistor.
(A4) The chip component according to A3, wherein a part of the thin film resistor and the wiring film is used as a fuse element.
By fusing the fuse element, the chip resistor can generate a desired value of resistance.
(A5) The chip component according to any one of A2 to A4, wherein the protective film also covers a side surface of the substrate.

In this case, since the side surface is covered with the protective film, it is possible to prevent the occurrence of a short circuit path on the side surface.
(A6) The chip component according to any one of A2 to A5, further including a resin film that covers an upper surface of the protective film.
(A7) The chip component according to A6, wherein the external connection electrode is connected to the wiring film through a through hole that penetrates the resin film and the protective film.
(A8) The chip component according to A6 or 7, wherein the resin film is made of a sheet and protrudes beyond the protective film on the side surface.

According to this configuration, when the chip component comes into contact with the surrounding material, the overhanging portion that protrudes beyond the protective film in the resin film first comes into contact with the surrounding material, so that the shock caused by the contact is reduced. It can be prevented that it reaches the elements.
(A9) The chip part according to any one of A1 to A8, wherein a concave portion or a convex portion is formed on at least one of the side surfaces.

In this case, since the outer shape of the chip component can be made asymmetric by the concave portion or the convex portion, the chip direction of the chip component (the direction of the chip component when mounted on the wiring board) can be recognized by this outer shape. The chip direction can be grasped by the appearance of the chip component.
(A10) Forming elements on the element formation surface of the substrate, and using plasma etching, forming a plurality of side surfaces orthogonal to the element formation surface in the substrate, and forming corner portions where the plurality of side surfaces intersect A method of manufacturing a chip part, including a step of shaping into a round shape.

According to this method, it is possible to manufacture a chip component in which the corner portion is shaped into a round shape.
(A11) A step of forming an element on the element formation surface of the substrate, and a step of forming a plurality of side surfaces orthogonal to the element formation surface on the substrate and shaping a corner portion where the plurality of side surfaces intersect into a round shape A method for manufacturing a chip part, comprising:

Also by this method, it is possible to manufacture a chip component in which the corner portion is shaped into a round shape.
(2) Embodiment of Second Invention Hereinafter, an embodiment of the second invention will be described in detail with reference to the accompanying drawings. Note that the reference numerals shown in FIGS. 16 to 30 are effective only in these drawings, and even if they are used in other embodiments, they do not indicate the same elements as those in the other embodiments.

FIG. 16A is a schematic perspective view for explaining the configuration of an electronic device according to an embodiment of the second invention, and FIG. 16B is a state in which the electronic device is mounted on a circuit board. It is a typical side view which shows.
The electronic device 1 is a minute chip component and has a rectangular parallelepiped shape as shown in FIG. Regarding the dimensions of the electronic device 1, the length L in the long side direction is about 0.3 mm, the width W in the short side direction is about 0.15 mm, and the thickness T is about 0.1 mm.

The electronic device 1 is obtained by forming a large number of electronic devices 1 in a lattice shape on a wafer and then cutting the wafer into individual electronic devices 1.
The electronic device 1 mainly includes a substrate 2, a first connection electrode 3 and a second connection electrode 4 that are external connection electrodes, and an element 5. The first connection electrode 3, the second connection electrode 4, and the element 5 are formed on the substrate 2 by using, for example, a semiconductor manufacturing process. Accordingly, a semiconductor substrate (semiconductor wafer) such as a silicon substrate (silicon wafer) can be used as the substrate 2. The substrate 2 may be another type of substrate such as an insulating substrate.

  The substrate 2 has a substantially rectangular parallelepiped chip shape. In the substrate 2, the upper surface in FIG. 16A is the element formation surface 2A. The element formation surface 2A is the surface of the substrate 2 and has a substantially rectangular shape. The surface opposite to the element formation surface 2A in the thickness direction of the substrate 2 is a back surface 2B. The element formation surface 2A and the back surface 2B have substantially the same shape. In addition to the element formation surface 2A and the back surface 2B, the substrate 2 has a side surface 2C, a side surface 2D, a side surface 2E, and a side surface 2F that extend perpendicular to these surfaces.

  The side surface 2C is laid between one end edge in the longitudinal direction of the element formation surface 2A and the back surface 2B (the left front edge in FIG. 16A), and the side surface 2D is the length of the element formation surface 2A and the back surface 2B. It is constructed between the other ends in the direction (the edge on the right back side in FIG. 16A). The side surface 2C and the side surface 2D are both end surfaces of the substrate 2 in the longitudinal direction. The side surface 2E is provided between one end edge in the short direction of the element forming surface 2A and the back surface 2B (the left edge on the left side in FIG. 16A), and the side surface 2F is composed of the element forming surface 2A and the back surface 2B. Between the other edges in the short direction (the edge on the right front side in FIG. 16A). The side surface 2E and the side surface 2F are both end surfaces of the substrate 2 in the lateral direction.

  In the substrate 2, the element formation surface 2 </ b> A, the side surface 2 </ b> C, the side surface 2 </ b> D, the side surface 2 </ b> E, and the side surface 2 </ b> F are covered with the protective film 23. Therefore, strictly speaking, in FIG. 16A, the element formation surface 2A, the side surface 2C, the side surface 2D, the side surface 2E, and the side surface 2F are located on the inner side (back side) of the protective film 23 and are exposed to the outside. Absent. Further, the protective film 23 on the element formation surface 2 </ b> A is covered with a resin film 24. The resin film 24 protrudes from the element formation surface 2A to the end portion on the element formation surface 2A side (the upper end portion in FIG. 16A) of each of the side surface 2C, the side surface 2D, the side surface 2E, and the side surface 2F. The protective film 23 and the resin film 24 will be described in detail later.

  In the substrate 2, the substrate 2 is placed on a portion corresponding to one side A (the side surface 2C, 2D, 2E, or 2F of the substantially rectangular element forming surface 2A, here, the side surface 2C as described later). A recess 10 is formed that is notched in the thickness direction. The side A is also one side of the electronic device 1 in plan view. The concave portion 10 in FIG. 16A is formed on the side surface 2C, and is recessed toward the side surface 2D while extending in the thickness direction of the substrate 2. The recess 10 penetrates the substrate 2 in the thickness direction, and the end of the recess 10 in the thickness direction is exposed from each of the element formation surface 2A and the back surface 2B. The recess 10 is smaller than the side surface 2C in the direction in which the side surface 2C extends (the short direction described above). The shape of the recess 10 in a plan view when the substrate 2 is viewed from the thickness direction (also the thickness direction of the electronic device 1) is a rectangular shape (rectangular shape) that is long in the short direction. The shape of the recess 10 in plan view may be a trapezoidal shape that becomes narrower in the direction in which the recess 10 is recessed (side 2D side), or a triangular shape that becomes narrower in the direction of recess. Alternatively, it may be U-shaped (a shape recessed in a U-shape). In any case, the concave portion 10 having such a simple shape can be easily formed. Moreover, although the recessed part 10 is formed in the side surface 2C here, you may form in at least one of the side surfaces 2C-2F instead of the side surface 2C.

  The concave portion 10 represents the direction (chip direction) of the electronic device 1 when the electronic device 1 is mounted on the circuit board 9 (see FIG. 16B). Since the outline of the electronic device 1 (strictly speaking, the substrate 2) in plan view is a rectangle having a recess 10 on one side A thereof, it has an asymmetric outer shape in the longitudinal direction. That is, the asymmetric outer shape has the concave portion 10 indicating the chip direction on any one of the side surfaces 2C, 2D, 2E, and 2F (one side A). It represents that the concave side in the longitudinal direction is the chip direction. Thus, the chip direction of the electronic device 1 can be recognized only by making the outer shape of the substrate 2 in the electronic device 1 asymmetric in a plan view. That is, the chip direction can be recognized from the outer shape of the electronic device 1 without a marking process. In particular, since the asymmetric outer shape of the electronic device 1 is a rectangle having a concave portion 10 representing the chip direction on one side A, the electronic device 1 has a concave portion 10 side in the longitudinal direction connecting the one side A and the opposite side B. It can be in the chip direction. Therefore, for example, in the plan view, the longitudinal direction of the electronic device 1 is aligned with the left-right direction so that the electronic device 1 can be correctly mounted on the circuit board 9 when the side A is located at the left end. When mounting, it can be grasped from the appearance of the electronic device 1 by the recess 10 that the electronic device 1 must be oriented so that the side A is located at the left end in plan view.

  In the rectangular parallelepiped substrate 2, the corner portion 11 (the portion where the adjacent ones intersect) adjacent to each other on the side surface 2C, the side surface 2D, the side surface 2E, and the side surface 2F has a chamfered round shape. It is shaped (rounded). In the substrate 2, a corner portion 12 (a corner portion of the concave portion 10 in the side surface 2 </ b> C) 12 that forms a boundary between the concave portion 10 and the side surface 2 </ b> C around the concave portion 10 is also shaped into a chamfered round shape. Here, the corner portion 12 exists not only at the boundary between the concave portion 10 and the surrounding side surface 2C (portion other than the concave portion 10) but also at the deepest portion side of the concave portion 10, and is present at four locations in plan view.

Thus, in the outline of the board | substrate 2 in planar view, all the bent parts (corner parts 11 and 12) are round shape. Therefore, the occurrence of chipping can be prevented at the corner portions 11 and 12 in the round shape. Thereby, in the manufacture of the electronic apparatus 1, it is possible to improve the yield (improvement of productivity).
The first connection electrode 3 and the second connection electrode 4 are formed on the element formation surface 2 </ b> A of the substrate 2 and are partially exposed from the resin film 24. Each of the first connection electrode 3 and the second connection electrode 4 is configured, for example, by stacking Ni (nickel), Pd (palladium), and Au (gold) on the element formation surface 2A in this order. The first connection electrode 3 and the second connection electrode 4 are arranged at intervals in the longitudinal direction of the element formation surface 2A, and are long in the short direction of the element formation surface 2A. In FIG. 16A, on the element formation surface 2A, the first connection electrode 3 is provided near the side surface 2C, and the second connection electrode 4 is provided near the side surface 2D. The concave portion 10 of the side surface 2 </ b> C described above is recessed at a depth that does not interfere with the first connection electrode 3. However, in some cases, the first connection electrode 3 may be provided with a recess (becomes a part of the recess 10) according to the recess 10.

  The element 5 is a circuit element, and is formed in a region between the first connection electrode 3 and the second connection electrode 4 on the element formation surface 2A of the substrate 2, and from above by the protective film 23 and the resin film 24. It is covered. The element 5 of this embodiment is a circuit network in which a plurality of thin film resistors (thin film resistors) R made of TiN (titanium nitride) or TiON (titanium oxynitride) are arranged in a matrix on the element formation surface 2A. A configured resistor 56. The element 5 is connected to a wiring film 22 which will be described later, and is connected to the first connection electrode 3 and the second connection electrode 4 via the wiring film 22. Thereby, in the electronic device 1, a resistance circuit including the element 5 is formed between the first connection electrode 3 and the second connection electrode 4. Therefore, the electronic device 1 in this embodiment is a chip resistor.

  As shown in FIG. 16B, the first connection electrode 3 and the second connection electrode 4 are opposed to the circuit board 9, and electrical and mechanical to the circuit (not shown) of the circuit board 9 by the solder 13. Thus, the electronic device 1 can be flip-chip connected to the circuit board 9. The first connection electrode 3 and the second connection electrode 4 that function as external connection electrodes are formed of gold (Au) or are plated with gold in order to improve solder wettability and reliability. It is desirable.

FIG. 17 is a plan view of the electronic device, and is a diagram illustrating a positional relationship between the first connection electrode, the second connection electrode, and the element, and a configuration in plan view of the element.
Referring to FIG. 17, as an example, element 5 that is a resistance network includes eight resistors R arranged in the row direction (longitudinal direction of substrate 2) and the column direction (of substrate 2). It has a total of 352 resistors R composed of 44 resistors R arranged along the width direction. Each resistor R has an equal resistance value.

  A plurality of types of resistance unit bodies (unit resistances) are formed by grouping and electrically connecting a large number of these resistor bodies R every predetermined number of 1 to 64 pieces. The formed plural types of resistance unit bodies are connected in a predetermined manner via the connecting conductor film C. In addition, a plurality of fuse films F that can be blown on the element forming surface 2A of the substrate 2 in order to electrically incorporate the resistance unit into the element 5 or to electrically separate it from the element 5 are provided. Is provided. The plurality of fuse films F and connection conductor films C are arranged along the inner side of the second connection electrode 4 so that the arrangement region is linear. More specifically, a plurality of fuse films F and connecting conductor films C are arranged in a straight line.

FIG. 18A is a plan view illustrating a part of the element shown in FIG. 17 in an enlarged manner. FIG. 18B is a longitudinal sectional view in the length direction along BB of FIG. 18A drawn for explaining the configuration of the resistor in the element. FIG. 18C is a longitudinal sectional view in the width direction along CC of FIG. 18A drawn to explain the configuration of the resistor in the element.
The configuration of the resistor R will be described with reference to FIGS. 18A, 18B, and 18C.

The electronic device 1 further includes an insulating film 20 and a resistor film 21 in addition to the wiring film 22, the protective film 23, and the resin film 24 described above (see FIGS. 18B and 18C). The insulating film 20, the resistor film 21, the wiring film 22, the protective film 23, and the resin film 24 are formed on the substrate 2 (element formation surface 2A).
The insulating film 20 is made of SiO ₂ (silicon oxide). The insulating film 20 covers the entire area of the element formation surface 2A of the substrate 2. The insulating film 20 has a thickness of about 10,000 mm.

  The resistor film 21 constitutes the resistor R. The resistor film 21 is made of TiN or TiON, and is laminated on the surface of the insulating film 20. The thickness of the resistor film 21 is about 2000 mm. The resistor film 21 forms a plurality of lines (hereinafter referred to as “resistor film line 21 </ b> A”) extending in a line between the first connection electrode 3 and the second connection electrode 4. 21A may be cut at a predetermined position in the line direction (see FIG. 18A).

A wiring film 22 is laminated on the resistor film line 21A. The wiring film 22 is made of Al (aluminum) or an alloy of aluminum and Cu (copper) (AlCu alloy). The thickness of the wiring film 22 is about 8000 mm. The wiring film 22 is laminated on the resistor film line 21A with a constant interval R in the line direction.
The electrical characteristics of the resistor film line 21A and the wiring film 22 of this configuration are shown by circuit symbols as shown in FIG. That is, as shown in FIG. 19A, each of the resistor film lines 21A in the region of the predetermined interval R forms one resistor R having a constant resistance value r.

In the region where the wiring film 22 is laminated, the resistor film lines 21 </ b> A are short-circuited by the wiring film 22 by electrically connecting the resistors R adjacent to each other. Therefore, a resistance circuit is formed which is formed by connecting in series the resistor R of the resistor r shown in FIG.
Further, since the adjacent resistor film lines 21A are connected to each other by the resistor film 21 and the wiring film 22, the resistor network of the element 5 shown in FIG. 18A is shown in FIG. A resistor circuit (consisting of R unit resistors) is formed.

Here, based on the characteristic that the same-shaped and large-sized resistor films 21 formed on the substrate 2 have substantially the same value, a large number of resistors R arranged in a matrix on the substrate 2 have the same resistance. Has a value.
Further, the wiring film 22 laminated on the resistor film line 21A forms a resistor R and also serves as a connecting wiring film for connecting a plurality of resistors R to form a resistance unit body. Plays.

20A is a partially enlarged plan view of a region including a fuse film drawn by enlarging a part of the plan view of the electronic device shown in FIG. 17, and FIG. 20B is a plan view of FIG. It is a figure which shows the cross-sectional structure which follows BB.
As shown in FIGS. 20A and 20B, the above-described fuse film F and connecting conductor film C are also formed by the wiring film 22 laminated on the resistor film 21 forming the resistor R. . That is, on the same layer as the wiring film 22 laminated on the resistor film line 21A forming the resistor R, the fuse film F and the connecting conductor film C are formed of Al or AlCu alloy which is the same metal material as the wiring film 22. Is formed.

  That is, in the same layer laminated on the resistor film 21, the wiring film for forming the resistor R, the fuse film F, the connecting conductor film C, and the element 5 are connected to the first connection electrode 3. A wiring film for connecting to the second connection electrode 4 is formed as the wiring film 22 by using the same metal material (Al or AlCu alloy) by the same manufacturing process (a sputtering and a photolithography process described later). Yes.

The fuse film F is not only a part of the wiring film 22 but also a group (fuse element) of a part of the resistor R (resistor film 21) and a part of the wiring film 22 on the resistor film 21. You may point.
The fuse film F has been described only in the case where the same layer as the connecting conductor film C is used. However, the connecting conductor film C is formed by stacking another conductor film on the conductor film C. The resistance value may be lowered. Even in this case, if the conductor film is not laminated on the fuse film F, the fusing property of the fuse film F does not deteriorate.

FIG. 21 is an electric circuit diagram of an element according to the embodiment of the second invention.
Referring to FIG. 21, element 5 includes reference resistance unit R8, resistance unit R64, two resistance units R32, resistance unit R16, resistance unit R8, resistance unit R4, resistance unit R2, The resistance unit body R1, the resistance unit body R / 2, the resistance unit body R / 4, the resistance unit body R / 8, the resistance unit body R / 16, and the resistance unit body R / 32 are arranged in this order from the first connection electrode 3. It is configured by connecting in series. Each of the reference resistance unit R8 and the resistance unit bodies R64 to R2 is configured by connecting in series the same number of resistors R as the last number (“64” in the case of R64). The resistance unit R1 is composed of one resistor R. Each of the resistance unit bodies R / 2 to R / 32 is configured by connecting in parallel the same number of resistor bodies R as the last number of itself (“32” in the case of R / 32). The meaning of the number at the end of the resistance unit body is the same in FIGS. 22 and 23 described later.

One fuse film F is connected in parallel to each of the resistance unit bodies R64 to R / 32 other than the reference resistance unit body R8. The fuse films F are connected in series either directly or via a connecting conductor film C (see FIG. 20A).
As shown in FIG. 21, in the state where all the fuse films F are not blown, the element 5 is composed of eight resistors R provided in series between the first connection electrode 3 and the second connection electrode 4. A resistance circuit of the reference resistance unit R8 (resistance value 8r) is configured. For example, if the resistance value r of one resistor R is r = 80Ω, a chip resistor (electronic device 1) in which the first connection electrode 3 and the second connection electrode 4 are connected by a resistance circuit of 8r = 64Ω. Is configured.

  Further, in a state where all the fuse films F are not blown, a plurality of types of resistance unit bodies other than the reference resistance unit body R8 are short-circuited. That is, 12 types of 13 resistance unit bodies R64 to R / 32 are connected in series to the reference resistance unit body R8, but each resistance unit body is short-circuited by the fuse film F connected in parallel. Therefore, when viewed electrically, each resistance unit is not incorporated in the element 5.

  In the electronic apparatus 1 according to this embodiment, the fuse film F is selectively blown by, for example, laser light according to a required resistance value. Thereby, the resistance unit body in which the fuse films F connected in parallel are melted is incorporated into the element 5. Therefore, the entire resistance value of the element 5 can be a resistance value in which resistance unit bodies corresponding to the blown fuse film F are connected in series and incorporated.

  In particular, in the plurality of types of resistance unit bodies, the resistor R having the same resistance value is one, two, four, eight, sixteen, thirty-two, etc. in series. The number of the series resistor unit bodies connected by increasing the number of resistors and the resistors R having the same resistance value are two, four, eight, sixteen, etc. in parallel. A plurality of types of parallel resistance units connected in increasing numbers are provided. Therefore, by selectively fusing the fuse film F (including the above-described fuse element), the resistance value of the entire element 5 (resistor 56) is adjusted finely and digitally to an arbitrary resistance value. Thus, a desired value of resistance can be generated in the electronic device 1.

FIG. 22 is an electric circuit diagram of an element according to another embodiment of the second invention.
Instead of configuring the element 5 by connecting the reference resistance unit R8 and the resistance unit R64 to the resistance unit R / 32 in series as described above, the element 5 may be configured as shown in FIG. Specifically, between the first connection electrode 3 and the second connection electrode 4, the reference resistance unit body R / 16 and the 12 types of resistance unit bodies R / 16, R / 8, R / 4, R / 2, R1 , R2, R4, R8, R16, R32, R64, R128 may be used to form the element 5 in a series connection circuit.

  In this case, the fuse film F is connected in series to each of the 12 types of resistance unit bodies other than the reference resistance unit body R / 16. In a state where all the fuse films F are not blown, each resistance unit body is electrically incorporated into the element 5. If the fuse film F is selectively blown by, for example, laser light according to a required resistance value, a resistance unit body corresponding to the blown fuse film F (a resistance unit body in which the fuse film F is connected in series) ) Is electrically separated from the element 5, the resistance value of the entire electronic device 1 can be adjusted.

FIG. 23 is an electric circuit diagram of an element according to still another embodiment of the second invention.
The feature of the element 5 shown in FIG. 23 is that it has a circuit configuration in which a plurality of types of resistance unit bodies are connected in series and a plurality of types of resistance unit bodies are connected in series. As in the previous embodiment, the fuse film F is connected in parallel to each of the plurality of types of resistance unit bodies connected in series, and the plurality of types of resistance unit bodies connected in series are all The fuse film F is short-circuited. Therefore, when the fuse film F is blown, the resistance unit body short-circuited by the blown fuse film F is electrically incorporated into the element 5.

On the other hand, a fuse film F is connected in series to each of a plurality of types of resistance unit bodies connected in parallel. Therefore, by fusing the fuse film F, the resistance unit body to which the blown fuse film F is connected in series can be electrically disconnected from the parallel connection of the resistance unit bodies.
With this configuration, for example, a small resistance of 1 kΩ or less is made on the parallel connection side, and if a resistance circuit of 1 kΩ or more is made on the series connection side, a wide range from a small resistance of several Ω to a large resistance of several MΩ is obtained. Resistor circuits can be made using a network of resistors constructed with an equal basic design.

FIG. 24 is a schematic cross-sectional view of an electronic device.
Next, the electronic device 1 will be described in more detail with reference to FIG. For convenience of explanation, in FIG. 24, the element 5 described above is shown in a simplified manner, and each element other than the substrate 2 is hatched.
Here, the protective film 23 and the resin film 24 described above will be described.

  The protective film 23 is made of, for example, SiN (silicon nitride) and has a thickness of about 3000 mm. The protective film 23 is provided over the entire element forming surface 2A and covers the resistor film 21 and each wiring film 22 (that is, the element 5) on the resistor film 21 from the surface (upper side in FIG. 24) ( That is, an element covering portion 23A that covers the upper surface of each resistor R in the element 5 and a side surface covering portion 23B that covers the entire area of each of the four side surfaces 2C to 2F (see FIG. 16A) of the substrate 2. It has one. The element covering portion 23A and the side surface covering portion 23B are actually substantially the same thickness and are continuous with each other. Therefore, the entire protective film 23 continuously covers the upper surface of the resistor R and the side surfaces 2C to 2F of the substrate 2 with substantially the same thickness.

The element covering portion 23A prevents a short circuit other than the wiring film 22 between the resistors R (short circuit between adjacent resistor film lines 21A).
The side surface covering portion 23B covers not only the entire area of each of the side surfaces 2C to 2F but also the portion of the insulating film 20 exposed at the side surfaces 2C to 2F. The side surface covering portion 23B covers the entire area including the portion where the concave portion 10 is formed on the side surface 2C (see FIG. 16A). The side surface covering portion 23B prevents a short circuit in each of the side surfaces 2C to 2F (a short circuit path is generated on the side surface).

  Referring to FIG. 16A, the protective film 23 continuously covers the element forming surface 2A of the substrate 2 and the four side surfaces 2C to 2F, so that the corner portions 11 and 12 of the substrate 2 are covered. A rounded corner portion 26 is provided. In this case, the element 5 and the wiring film 22 can be protected by the protective film 23 and the occurrence of chipping at the corner portion 26 of the protective film 23 can be prevented.

  Returning to FIG. 24, the resin film 24 protects the electronic device 1 together with the protective film 23, and is made of a resin such as polyimide. The thickness of the resin film 24 is about 5 μm. The resin film 24 covers the entire surface of the element covering portion 23A (the upper surface of the protective film 23) over the entire area, and the element forming surface 2A side in the side surface covering portions 23B on the four side surfaces 2C to 2F of the substrate 2. Are covered (upper end in FIG. 24). That is, the resin film 24 exposes at least the portion on the side opposite to the element formation surface 2A (the lower side in FIG. 24) in the side surface covering portion 23B on the four side surfaces 2C to 2F.

  In such a resin film 24, portions that coincide with the four side surfaces 2 </ b> C to 2 </ b> F in a plan view are arc-shaped projecting portions 24 </ b> A that project to the side (outside) of the side surface covering portions 23 </ b> B on these side surfaces. It has become. That is, the resin film 24 (the overhang portion 24A) protrudes beyond the side surface covering portion 23B (the protective film 23) at the side surfaces 2C to 2F. Such a resin film 24 has a round-shaped side surface 24B convex toward the side in the arc-shaped overhanging portion 24A. The overhanging portion 24A covers a corner portion 27 that forms a boundary between the element formation surface 2A and each of the side surfaces 2C to 2F. For this reason, when the electronic device 1 comes into contact with the surrounding object, the overhanging portion 24A first contacts the surrounding object to alleviate the impact caused by the contact. Chipping at the portion 27 can be prevented. In particular, since the overhanging portion 24A has the round-shaped side surface 24B, the impact caused by the contact can be smoothly reduced.

There may be a configuration in which the resin film 24 does not cover the side surface covering portion 23B at all (a configuration in which the entire side surface covering portion 23B is exposed).
In the resin film 24, one opening 25 is formed at two positions separated in a plan view. Each opening 25 is a through-hole that continuously penetrates the resin film 24 and the protective film 23 (element covering portion 23A) in each thickness direction. Therefore, the opening 25 is formed not only in the resin film 24 but also in the protective film 23. A part of the wiring film 22 is exposed from each opening 25. A portion of the wiring film 22 exposed from each opening 25 is a pad region 22A for external connection.

  Of the two openings 25, one opening 25 is filled with the first connection electrode 3, and the other opening 25 is filled with the second connection electrode 4. A part of each of the first connection electrode 3 and the second connection electrode 4 protrudes from the opening 25 on the surface of the resin film 24. The first connection electrode 3 is electrically connected to the wiring film 22 in the pad region 22 </ b> A in the opening 25 through the one opening 25. The second connection electrode 4 is electrically connected to the wiring film 22 in the pad region 22 </ b> A in the opening 25 through the other opening 25. Thereby, each of the first connection electrode 3 and the second connection electrode 4 is electrically connected to the element 5. Here, the wiring film 22 forms wiring connected to each of the group of resistors R (resistor 56), the first connection electrode 3, and the second connection electrode 4.

  Thus, the resin film 24 and the protective film 23 in which the opening 25 is formed are formed so as to expose the first connection electrode 3 and the second connection electrode 4 from the opening 25. Therefore, the electrical connection between the electronic device 1 and the circuit board 9 can be achieved via the first connection electrode 3 and the second connection electrode 4 protruding from the opening 25 on the surface of the resin film 24 (FIG. 16 (b)).

25A to 25F are schematic sectional views showing a method for manufacturing the electronic device shown in FIG.
First, as shown in FIG. 25A, a wafer 30 is prepared. The wafer 30 is a source of the substrate 2. Therefore, the front surface 30A of the wafer 30 is the element forming surface 2A of the substrate 2, and the back surface 30B of the wafer 30 is the back surface 2B of the substrate 2.

Then, the insulating film 20 made of SiO ₂ or the like is formed on the surface 30A of the wafer 30, and the element 5 (resistor R and wiring film 22) is formed on the insulating film 20. Specifically, first, a TiN or TiON resistor film 21 is formed on the entire surface of the insulating film 20 by sputtering, and an aluminum (Al) wiring film 22 is stacked on the resistor film 21. . Thereafter, by using a photolithography process, the resistor film 21 and the wiring film 22 are selectively removed by dry etching, for example, and as shown in FIG. A configuration is obtained in which the body membrane lines 21A are arranged in the column direction at regular intervals. At this time, a region in which the resistor film line 21A and the wiring film 22 are partially cut is also formed. Subsequently, the wiring film 22 stacked on the resistor film line 21A is selectively removed. As a result, the element 5 having a configuration in which the wiring film 22 is laminated on the resistor film line 21A with a predetermined interval R is obtained.

Referring to FIG. 25A, the elements 5 are formed at a number of locations on the surface 30 </ b> A of the wafer 30 according to the number of electronic devices 1 formed on one wafer 30.
Next, as shown in FIG. 25B, a resist pattern 41 is formed over the entire surface 30 </ b> A of the wafer 30 so as to cover all the elements 5 on the insulating film 20. An opening 42 is formed in the resist pattern 41.

  FIG. 26 is a schematic plan view of a part of a resist pattern used for forming a groove in the step of FIG. 25B. The opening 42 of the resist pattern 41 is a region between the outlines of adjacent electronic devices 1 in plan view (a hatched portion in FIG. 26) when a large number of electronic devices 1 are arranged in a matrix (also in a lattice shape). ). Therefore, the entire shape of the opening 42 is a lattice shape having a plurality of linear portions 42A and 42B orthogonal to each other. Further, any one of the straight portions 42A and 42B (here, the straight portion 42A) has a protruding portion that protrudes orthogonally from the straight portion 42A in accordance with the concave portion 10 (see FIG. 16A) of the electronic device 1. 42C is continuously provided.

  Here, in the electronic device 1, the corner parts 11 and 12 are round shape (refer Fig.16 (a)). Accordingly, the straight portions 42A and 42B that are orthogonal to each other in the opening 42 are connected while being curved. Further, the linear portion 42A and the protruding portion 42C which are orthogonal to each other are connected while being curved. For this reason, the intersecting portion 43A of the straight portions 42A and 42B and the intersecting portion 43B of the straight portions 42A and the protruding portion 42C have a round shape with rounded corners. Further, the corners of the protruding portion 42C other than the intersecting portion 43B are also rounded.

  Referring to FIG. 25B, each of insulating film 20 and wafer 30 is selectively removed by plasma etching using resist pattern 41 as a mask. Thereby, a groove 44 that penetrates the insulating film 20 and reaches the middle of the thickness of the wafer 30 is formed at a position that coincides with the opening 42 of the resist pattern 41 in plan view. The groove 44 has a side surface 44A that faces each other and a bottom surface 44B that connects a lower end of the facing side surface 44A (an end on the back surface 30B side of the wafer 30). The depth of the groove 44 with respect to the surface 30A of the wafer 30 is about 100 μm, and the width of the groove 44 (the interval between the opposing side surfaces 44A) is about 20 μm.

FIG. 27A is a schematic plan view of the wafer after the grooves are formed in the process of FIG. 25B, and FIG. 27B is an enlarged view of a part of FIG.
Referring to FIG. 27B, the overall shape of the groove 44 is a lattice shape that matches the opening 42 (see FIG. 26) of the resist pattern 41 in plan view. On the surface 30A of the wafer 30, a rectangular frame portion in the groove 44 surrounds the area where each element 5 is formed. A portion where the element 5 is formed on the wafer 30 is a semi-finished product 50 of the electronic apparatus 1. On the surface 30A of the wafer 30, one semi-finished product 50 is located in a region surrounded by the grooves 44, and these semi-finished products 50 are arranged in a matrix.

  Further, the groove 44 is formed so as to bite into the middle part of one side A of the semi-finished product 50 at a portion corresponding to the protruding portion 42C (see FIG. 26) in the opening 42 of the resist pattern 41. 50 is formed with the above-described recess 10 (see FIG. 16A). Then, according to the intersecting portions 43A and 43B (see FIG. 26) having a round shape in the opening 42 of the resist pattern 41, the corner portions 60 of the semi-finished product 50 (the corner portions 11 and 12 of the electronic device 1) are seen in plan view. ) Is shaped into a round shape. Although this round shape is formed by using plasma etching, silicon etching (normal etching using a chemical solution) may be used instead of plasma etching.

  By etching the wafer 30 in this way, the outer shape of the semi-finished product 50 (in other words, the final electronic device 1) can be arbitrarily set. As in this embodiment, the corner portion 60 (corner portions 11 and 12). ) Has a round shape and can be an asymmetric rectangle having a recess 10 on one side A (see also FIG. 16A). In this case, the electronic device 1 capable of recognizing the chip direction can be manufactured without a marking process (a process of marking a mark or the like indicating the chip direction with a laser or the like).

  After the trench 44 is formed, the resist pattern 41 is removed, and as shown in FIG. 25C, a protective film (SiN) made of SiN is formed on the surface of the element 5 by a CVD (Chemical Vapor Deposition) method. Film) 45 is formed. The SiN film 45 has a thickness of about 3000 mm. The SiN film 45 is formed so as to cover not only the entire surface of the element 5 but also the inner surface (side surface 44A and bottom surface 44B) of the groove 44. Since the SiN film 45 is a thin film formed on the side surface 44A and the bottom surface 44B with a substantially constant thickness, the groove 44 is not filled up. Further, since the SiN film 45 may be formed in the entire area of the side surface 44A in the groove 44, it may not be formed on the bottom surface 44B.

Next, as shown in FIG. 25D, a photosensitive resin sheet 46 made of polyimide is attached to the wafer 30 from above the SiN film 45 other than the grooves 44. FIGS. 28A and 28B are schematic perspective views showing a state in which a polyimide sheet is attached to a wafer in the step of FIG. 25D.
Specifically, as shown in FIG. 28A, after the polyimide sheet 46 is covered from the surface 30A side on the wafer 30 (strictly, the SiN film 45 on the wafer 30), FIG. The sheet 46 is pressed against the wafer 30 by the rotating roller 47 as shown in FIG.

  As shown in FIG. 25D, when the sheet 46 is affixed to the entire surface of the SiN film 45 other than the groove 44, a part of the sheet 46 slightly enters the groove 44 side, but on the side surface 44A of the groove 44. The sheet 46 does not reach the bottom surface 44 </ b> B of the groove 44 only by covering a part of the SiN film 45 on the element 5 side (surface 30 </ b> A side). Therefore, in the groove 44 between the sheet 46 and the bottom surface 44 </ b> B of the groove 44, a space S having almost the same size as the groove 44 is formed. At this time, the thickness of the sheet 46 is 10 μm to 30 μm.

Next, the sheet 46 is subjected to heat treatment. Thereby, the thickness of the sheet 46 is thermally contracted to about 5 μm.
Next, as shown in FIG. 25E, the sheet 46 is patterned, and portions of the sheet 46 that coincide with the pad 44A of the groove 44 and the wiring film 22 in plan view are selectively removed. Specifically, the sheet 46 is exposed and developed in the pattern using the mask 62 in which the opening 61 having a pattern that matches (matches) with the groove 44 and each pad region 22A in plan view. As a result, the sheet 46 is separated above the groove 44 and each pad region 22A, and the edge portion separated in the sheet 46 slightly overlaps the groove 44 side and overlaps the SiN film 45 on the side surface 44A of the groove 44. Therefore, the above-described overhanging portion 24A (having the round-shaped side surface 24B) is naturally formed on the edge portion.

Next, by etching using the sheet 46 thus separated as a mask, portions of the SiN film 45 that correspond to the pad regions 22A in plan view are removed. Thereby, the opening 25 is formed. Here, the SiN film 45 is formed so as to expose each pad region 22A.
Next, a Ni / Pd / Au laminated film constituted by laminating Ni, Pd and Au is formed on the pad region 22A in each opening 25 by electroless plating. At this time, the Ni / Pd / Au laminated film protrudes from the opening 25 to the surface of the sheet 46. Thereby, the Ni / Pd / Au laminated film in each opening 25 becomes the first connection electrode 3 and the second connection electrode 4 shown in FIG. 25F.

  Next, after conducting an energization inspection between the first connection electrode 3 and the second connection electrode 4, the wafer 30 is ground from the back surface 30B. Here, since the entire portion of the portion forming the side surface 44A of the groove 44 in the wafer 30 is covered with the SiN film 45, it is possible to prevent the occurrence of microcracks or the like in the portion during grinding of the wafer 30, and temporarily Even if a microcrack occurs, the microcrack can be prevented from expanding by filling the microcrack with the SiN film 45.

  Then, when the wafer 30 is thinned by grinding until reaching the bottom surface 44B (strictly speaking, the SiN film 45 on the bottom surface 44B) of the groove 44, there is no connection between the adjacent semi-finished products 50. , The wafer 30 is divided, and the semi-finished product 50 becomes the electronic device 1 and is separated individually. Thereby, the electronic device 1 (see FIG. 24) is completed. In each electronic device 1, the portion that formed the side surface 44 </ b> A of the groove 44 becomes one of the side surfaces 2 </ b> C to 2 </ b> F of the substrate 2. Then, the SiN film 45 becomes the protective film 23. Further, the separated sheet 46 becomes the resin film 24.

  Even if the chip size of the electronic device 1 is small, the electronic device 1 can be divided into pieces by grinding the wafer 30 from the back surface 30B after the grooves 44 are formed in this way. Therefore, as compared with the case where the electronic device 1 is divided into pieces by dicing the wafer 30 with a dicing saw as in the prior art, cost reduction and time reduction can be achieved and yield improvement can be achieved by omitting the dicing process.

According to the above, when manufacturing the electronic device 1, the groove 44 for dividing the electronic device 1 one by one is formed on the surface 30 </ b> A (element forming surface 2 </ b> A). If it forms in the boundary of the element 5 in 30A, the side surface 44A of the groove | channel 44 will become the side surfaces 2C-2F of each electronic device 1 after a division | segmentation.
Prior to the division into the electronic device 1, the SiN film 45 (protective film 23) is formed on the side surface 44 </ b> A of the groove 44 and the surface 30 </ b> A of the wafer 30. Here, as shown in FIG. 25C, a CVD protective film (CVD protective film) 23 having substantially the same thickness is continuously formed on the upper surface of the resistor R and the inner surface (side surface 44A and bottom surface 44B) of the resistor R by the CVD method. Formed. In this case, since the formation of the CVD protective film 23 (SiN film 45) is performed in a reduced pressure environment in the course of CVD, the CVD protective film 23 serves as the side surface covering portion 23B and the side surfaces 2C to 2F (grooves 44) of the substrate 2. Can be attached to the entire side surface 44A). Therefore, the protective film 23 can be uniformly formed on the side surface 44 </ b> A of the groove 44 when the electronic device 1 is manufactured.

  Then, after the formation of the protective film 23, as shown in FIG. 25D, the resin film 24 is formed by a sheet 46 that covers the SiN film 45 (the portion of the protective film 23 that becomes the element covering portion 23A) of the element forming surface 2A. Since the resin film 24 exposes at least the side opposite to the element formation surface 2A (the bottom surface 44B side of the groove 44) in the SiN film 45 on the side surface 44A of the groove 44 (the portion that becomes the side surface covering portion 23B of the protective film 23). It is possible to prevent the grooves 44 from being filled with the resin film 24 from the bottom surface 44B side when the resin film 24 is formed (when the electronic apparatus 1 is manufactured).

Specifically, the resin film 24 is formed by sticking a sheet 46 on the protective film 23. In this case, the groove 46 is not filled from the bottom surface 44B side by the sheet 46. Therefore, as shown in FIG. 25F, if the substrate 2 is thinned until it reaches the bottom surface 44B of the groove 44, the substrate 2 can be divided into the individual electronic devices 1 in the groove 44.
As mentioned above, although embodiment of 2nd invention was described, 2nd invention can also be implemented with another form.

  For example, when the wafer 30 is divided into individual electronic devices 1, the wafer 30 is ground from the back surface 30B side to the bottom surface 44B of the groove 44 (see FIG. 25F). Instead, the portion of the SiN film 45 that covers the bottom surface 44B and the portion of the wafer 30 that coincides with the groove 44 in plan view are selectively etched away from the back surface 30B, thereby individually removing the wafer 30. The electronic device 1 may be divided.

FIG. 29A is a plan view of the electronic device, FIG. 29B is a plan view of the electronic device according to the first modification, and FIG. 29C is a second modification. It is a top view of the electronic device which concerns. In each of FIGS. 29A to 14C, the element 5, the protective film 23, and the resin film 24 are not shown for convenience of explanation.
Moreover, the recessed part 10 mentioned above is provided in the position shifted | deviated from the midpoint P of the one side A in the one side A of the electronic device 1, as shown to Fig.29 (a). When the recess 10 is displaced from the midpoint P, the center 10A of the recess 10 and the midpoint P do not coincide with each other in the direction in which the side A extends. According to this configuration, not only the recess 10 side in the direction (longitudinal direction) connecting the one side A and one side B opposite to the one side A, but also the recess in the extending direction (short direction) of the one side A. The 10 side can also be in the chip direction described above. For example, in a plan view viewed from the element forming surface 2A side, the short side direction of the electronic device 1 and the front-back direction (vertical direction in FIG. 29) are matched, and the long direction of the electronic device 1 is matched with the left-right direction. When the concave portion 10 is positioned on the left front side (upper left side in FIG. 29), the electronic device 1 can be correctly mounted on the circuit board 9. Then, when mounting, the orientation of the electronic device 1 must be aligned so that the concave portion 10 is located on the left front side in plan view (when the electronic device 1 is viewed from the back surface 2B of the substrate 2, the right front side). This can be grasped from the appearance of the electronic device 1. That is, it can be understood from the appearance of the electronic device 1 that the orientation of the electronic device 1 in both the longitudinal direction and the short direction must be matched.

  Of course, as shown in FIG. 29 (b), the concave portion 10 may be provided at a position where one side A coincides with the midpoint P (a position where the center 10A of the concave portion 10 and the midpoint P coincide in the short direction). . Moreover, you may provide the convex part 51 which protrudes outward instead of the recessed part 10, as shown in FIG.29 (c). The convex portion 51 may have a rectangular shape in plan view, or may have a U shape (a shape that bulges into a U shape) or a triangular shape. Of course, in the side surface 2 </ b> C, the corner portion (four corner portions in a plan view including the tip side and the root side of the convex portion 51) 52 of the convex portion 51 is also chamfered, like the other corner portions 11. It has become. Here, the side surface covering portion 23 </ b> B (see FIG. 16A) covers the entire area including the portion where the convex portion 51 is formed on the side surface 2 </ b> C, as in the case of the concave portion 10. Moreover, it is preferable that the depth of the recessed part 10 and the height (projection amount) of the convex part 51 are 20 micrometers or less (about 1/5 or less of the width of the 1st connection electrode 3 or the 2nd connection electrode 4). And as for the chamfering amount in each of the corner part 11, the corner part 12, and the corner part 52, it is preferable that the distance of one side is about 20 micrometers or less.

FIG. 30A is a diagram illustrating a circuit configuration of an element according to another embodiment of the electronic device, and FIG. 30B is a diagram illustrating a circuit configuration of an element according to still another embodiment of the electronic device. It is.
In the embodiment described above, since the electronic device 1 is a chip resistor, the element 5 between the first connection electrode 3 and the second connection electrode 4 is the resistor 56, but the diode 55 shown in FIG. Alternatively, a diode 55 and a resistor 56 may be connected in series as shown in FIG. The electronic device 1 becomes a chip diode by having the diode 55, and the first connection electrode 3 and the second connection electrode 4 have polarity, but the above-described chip direction is a direction corresponding to the polarity. Thereby, since the polarity of the 1st connection electrode 3 and the 2nd connection electrode 4 can be shown with a chip | tip direction, the said polarity can be grasped | ascertained by the external appearance of the electronic device 1. FIG. That is, it can be seen which side in the chip direction (that is, which of the first connection electrode 3 and the second connection electrode 4) is the positive or negative pole side. Therefore, the electronic device 1 can be correctly mounted on the circuit board 9 (see FIG. 16B) so that the side on which the concave portion 10 and the convex portion 51 (see FIG. 29) described above are provided on the corresponding pole side. Can be.

Of course, the second invention can be applied to an element device in which various elements such as a chip capacitor in which a capacitor is used instead of the diode 55 in the element 5 and a chip inductor are formed on the chip-sized substrate 2. .
<Third invention>
(1) Features of the third invention For example, the features of the invention according to the third invention are the following B1 to A13.
(B1) A substrate, a first connection electrode and a second connection electrode formed on the substrate, formed on the substrate, one end side is connected to the first connection electrode, and the other end side is the second connection electrode. A plurality of resistor films having equal resistance values arranged in a matrix on the substrate, and electrically connecting the resistor films. A plurality of types of resistance unit bodies including one or a plurality of connection body films electrically connected by a connection wiring film, and the plurality of types of resistance unit bodies are defined in a predetermined manner. A wiring film for connecting a network connected in a form and provided individually corresponding to the resistance unit body, and the resistance unit body is electrically incorporated in the resistance circuit network, or electrically from the resistance circuit network Multiple fuses that can be fused to separate And at least a part of the wiring film has a multilayer wiring structure including a first wiring layer stacked on the resistor film and a second wiring layer stacked on the first wiring layer. A chip resistor, characterized in that

According to this configuration, a resistor network can be formed on the substrate, and many high-quality chip resistors can be manufactured by one manufacturing.
In addition, since the resistor network is formed, the resistance network can be miniaturized and the chip resistor can be made smaller than before.
Further, the resistor network includes a plurality of resistor films having equal resistance values arranged in a matrix, and the required resistance value can be changed by changing the connection mode of the plurality of resistor films. Can be easily accommodated.

Furthermore, it is possible to easily cope with a change in the required resistance value by changing the connection mode of a plurality of types of resistance unit bodies.
Furthermore, the resistance value of the resistance circuit network can be reduced by fusing any fuse film of the plurality of fuse films and electrically incorporating the resistance unit body into the resistance network or electrically separating it from the resistance network. In addition to being able to adjust, the resistance value of the chip resistor can be matched to a plurality of types of required resistance values without changing the basic design. Thereby, it is possible to provide a chip resistor having the same basic design and having the resistance value as a required resistance value.

In addition, the wiring film included in the resistance network includes a second wiring layer laminated on the first wiring layer and the first wiring layer in at least a part thereof, for example, in a region where a plurality of resistor films are connected in parallel in a comb shape. It has a laminated wiring structure including a wiring layer. Therefore, the wiring film in such a region has a smaller resistance value due to the laminated structure, and the resistance value of the wiring film does not affect the resistance value of the resistor. As a result, the overall resistance value and the resistance ratios of a plurality of types of resistance unit bodies do not change, and a highly accurate resistance network can be configured.
(B2) The resistor film includes a resistor film line extending on the substrate and a wiring film laminated on the resistor film line at a predetermined interval in the line direction, and the wiring film is laminated. The chip resistor as set forth in B1, wherein the resistor film lines of the constant interval not formed constitute one resistor film.

In this configuration, a plurality of resistor films having the same resistance value arranged in a matrix form are each laminated on the resistor film line and the resistor film line at a certain interval in the line direction. Contains a membrane. For this reason, the resistor film region in which the wiring film is not stacked functions as one resistor film. This resistor film region can be formed in the same size by setting the interval between the laminated wiring films to a constant interval. And the resistance value of the same size and the same shape of the resistor (resistor film) made on the substrate has a common layout pattern, and a large number of resistor films. Can be easily formed.
(B3) A wiring film partitioning the resistor film, a connection wiring film included in the resistance unit body, the circuit network connection wiring film, and the fuse film are formed of the same material metal film formed in the same layer. A chip resistor according to B2, characterized by comprising.

According to this configuration, the wiring film that divides the resistor film, the connecting wiring film included in the resistance unit body, the connecting wiring film included in the network connection means, and the fuse film are formed on the same layer. Then, by removing unnecessary portions of the metal film by etching or the like, a plurality of types of metal films (wiring films) can be easily formed at a time by a relatively small number of processes.
(B4) The chip resistor according to any one of B1 to B3, wherein the resistor unit includes a plurality of the resistor films connected in series.

According to this configuration, since the resistance unit body is formed by connecting a plurality of resistor films in series, a resistance unit body having a large resistance value can be configured.
(B5) The chip resistor according to any one of B1 to B3, wherein the resistor unit includes a plurality of the resistor films connected in parallel.
According to this configuration, since the resistance unit body is formed by connecting a plurality of resistor films in parallel, a resistance unit body having a small resistance value and a small error between the resistance values can be configured.
(B6) The parallel connection of the resistor films includes a comb-shaped portion in which the wiring film has a comb-tooth shape, and the comb-tooth-shaped portion has the laminated wiring structure. The chip resistor according to B5.

According to this configuration, the wiring film for connection related to the parallel connection of a plurality of resistor films is narrow in the comb-shaped portion and the resistance value of the wiring film is likely to increase. Since the film has a laminated wiring structure, the resistance value of the wiring film does not adversely affect the resistance network.
(B7) In any one of B1 to B6, the number of the resistor films to be connected is set in the plurality of types of resistance unit bodies, and the resistance values form a geometric progression with respect to each other. Chip resistor.

According to this configuration, since the resistance values of the resistance unit bodies form a geometric sequence, the resistance values of the resistance unit bodies can be set in various types from a relatively small resistance value to a relatively large resistance value. Thereby, even if the required resistance value required for the chip resistor varies depending on the connection mode of the resistance unit bodies, it is possible to cope with the same design contents.
(B8) The chip resistor according to any one of B1 to B7, wherein the circuit network connection wiring film includes a connection wiring film for connecting the plurality of types of resistance unit bodies in series.

According to this configuration, it is possible to configure a chip resistor having a large resistance value by connecting resistance unit bodies in series.
(B9) The chip resistor according to any one of B1 to B8, wherein the circuit network connection wiring film includes a connection wiring film for connecting the plurality of types of resistance unit bodies in parallel.
According to this configuration, it is possible to provide a chip resistor capable of coping with various required resistance values by finely adjusting the resistance value of the chip resistor by connecting the resistance unit bodies in parallel.
(B10) The network connection wiring film for connecting the plurality of types of resistance unit bodies in parallel includes a comb-shaped portion, and the comb-shaped portion has the laminated wiring structure. The chip resistor according to B9.

According to this configuration, when the resistance unit bodies are connected in parallel, a large number of resistors may be connected in parallel to the connection wiring film in a comb shape, and the resistance value of the entire resistor becomes small. In some cases, the resistance value of the wiring film cannot be ignored. Therefore, in this portion, the wiring film has a laminated wiring structure, the resistance value of the wiring film is further lowered, and the resistance value of the wiring film does not affect the entire resistance network.
(B11) A substrate, a first connection electrode and a second connection electrode formed on the substrate, formed on the substrate, one end side is connected to the first connection electrode, and the other end side is the second connection electrode. A resistor network having a plurality of resistors connected by a wiring film connected to the wire, and fusing to electrically incorporate the resistor into the resistor network or to electrically separate it from the resistor network A plurality of possible fuse films, and at least a part of the wiring film includes a first wiring layer stacked on the resistor film and a second wiring layer stacked on the first wiring layer. The fuse film has a laminated wiring structure composed of only the first wiring film or the second wiring film.
(B12) The electronic device according to B11, wherein the resistor is made of TiON or TiSiON.
(B13) The electronic device according to B11 or B12, wherein the resistor and the wiring film are patterned together.

  According to the configuration of B11 to B13, a resistance circuit is obtained by fusing an arbitrary fuse film of a plurality of fuse films and electrically incorporating the resistor into the resistor network or electrically separating the resistor from the resistor network. The resistance value of the net can be adjusted, and it can be matched to a plurality of types of required resistance values without changing the basic design. As a result, it is possible to provide an electronic apparatus having a resistance circuit network of the same basic design and having the resistance value required.

In addition, the wiring film included in the resistance network includes a second wiring layer laminated on the first wiring layer and the first wiring layer in at least a part thereof, for example, a region in which a plurality of resistors are connected in parallel in a comb shape. It has a laminated wiring structure including layers. Therefore, the wiring film in such a region has a smaller resistance value due to the laminated structure, and the resistance value of the wiring film does not affect the resistance value of the resistor. As a result, a highly accurate resistor network can be configured.
(2) Embodiment of the Third Invention Hereinafter, an embodiment of the third invention will be described in detail with reference to the accompanying drawings. In addition, the code | symbol shown in FIGS. 31-46 is effective only in these drawings, and even if it is used for other embodiment, it does not show the same element as the code | symbol of the said other embodiment.

FIG. 31A is an illustrative perspective view showing an external configuration of the chip resistor 10 according to one embodiment of the third invention, and FIG. 31B shows the chip resistor 10 mounted on a substrate. It is a side view which shows the state.
Referring to FIG. 31A, a chip resistor 10 according to an embodiment of the third invention includes a first connection electrode 12, a second connection electrode 13, and a resistor formed on a substrate 11 as a substrate. And a network 14. The substrate 11 has a substantially rectangular parallelepiped shape in plan view. For example, the length L in the long side direction is 0.3 mm, the width W in the short side direction is 0.15 mm, and the thickness T of the substrate 11 is about 0.1 mm. It is a very small chip.

As shown in FIG. 46, the chip resistor 10 is obtained by forming a large number of chip resistors 10 on a wafer in a lattice pattern, and cutting the wafer into individual chip resistors 10. .
On the substrate 11, the first connection electrode 12 is a rectangular electrode that is provided along one short side 111 of the substrate 11 and is long in the direction of the short side 111. The second connection electrode 13 is a rectangular electrode extending in the direction of the short side 112 provided along the other short side 112 on the substrate 11. The resistance network 14 is provided in a central region sandwiched between the first connection electrode 12 and the second connection electrode 13 on the substrate 11. One end side of the resistor network 14 is electrically connected to the first connection electrode 12, and the other end side of the resistor network 14 is electrically connected to the second connection electrode 13. As will be described later, the first connection electrode 12, the second connection electrode 13, and the resistance network 14 are provided on the substrate 11 by using, for example, a semiconductor manufacturing process. Therefore, a semiconductor substrate (semiconductor wafer) such as a silicon substrate (silicon wafer) can be used as the substrate 11. The substrate 11 may be another type of substrate such as an insulating substrate.

  The first connection electrode 12 and the second connection electrode 13 each function as an external connection electrode. In the state where the chip resistor 10 is mounted on the circuit board 15, as shown in FIG. 31B, the first connection electrode 12 and the second connection electrode 13 are respectively connected to a circuit (not shown) of the circuit board 15. ) And solder and are electrically and mechanically connected. The first connection electrode 12 and the second connection electrode 13 that function as external connection electrodes are made of gold (Au) or plated with gold in order to improve solder wettability and reliability. It is desirable.

FIG. 32 is a plan view of the chip resistor 10, showing the arrangement relationship of the first connection electrode 12, the second connection electrode 13, and the resistor network 14 and the configuration of the resistor network 14 in plan view.
Referring to FIG. 32, the chip resistor 10 includes a first connection electrode 12 that is disposed along one short side 111 on the upper surface of the substrate and has a substantially rectangular shape in plan view in the width direction, and the other short side 112 on the upper surface of the substrate. A second connection electrode 13 having a substantially rectangular shape in plan view that is long in the width direction, and a resistance network 14 provided in a rectangular region in plan view between the first connection electrode 12 and the second connection electrode 13; Is included.

  The resistor network 14 includes a plurality of resistor films R having equal resistance values arranged in a matrix on the substrate 11 (in the example of FIG. 32, eight resistor films along the row direction (longitudinal direction of the substrate)). The resistor films R are arranged, and 44 resistor films R are arranged along the column direction (the width direction of the substrate) to have a total of 352 resistor film R configurations). One to 64 of these many resistor films R are electrically connected to form a plurality of types of resistance unit bodies. The formed plural types of resistance unit bodies are connected in a predetermined manner with a wiring film for connection as a network connection means. Further, a plurality of fuse films F that can be blown in order to electrically incorporate the resistance unit into the resistance network 14 or to be electrically separated from the resistance network 14 are provided. The plurality of fuse films F are arranged along the inner side of the second connection electrode 13 so that the arrangement region is linear. More specifically, a plurality of fuse films F and connection wiring films C are arranged in a straight line.

33A is an enlarged plan view of a part of the resistor network 14 shown in FIG. 32, and FIGS. 33B and 33C are drawn to explain the structure of the resistor R in the resistor network 14, respectively. It is the longitudinal cross-sectional view of the length direction, and the longitudinal cross-sectional view of the width direction.
The configuration of the resistor film R will be described with reference to FIGS. 33A, 33B, and 33C.

An insulating layer (SiO ₂ ) 19 is formed on the upper surface of the substrate 11 as a substrate, and a resistor film 20 constituting the resistor film R is disposed on the insulating layer 19. The resistor film 20 is made of TiN or TiON. The resistor film 20 includes a plurality of resistor films (hereinafter referred to as “resistor film lines”) extending in a line between the first connection electrode 12 and the second connection electrode 13. The line 20 may be cut at a predetermined position in the line direction. An aluminum film as a wiring film 21 is laminated on the resistor film line 20. The wiring film 21 is laminated on the resistor film line 20 with a constant interval R in the line direction.

  The electrical characteristics of the resistor film line 20 and the wiring film 21 having this configuration are shown by circuit symbols as shown in FIG. That is, as shown in FIG. 34A, each of the resistor film lines 20 in the region of the predetermined interval R forms a resistor film R having a constant resistance value r. In the region where the wiring film 21 is laminated, the resistor film line 20 is short-circuited by the wiring film 21. Therefore, a resistor circuit is formed which is formed by connecting in series the resistor film R of the resistor r shown in FIG.

Further, since the resistor film lines 20 adjacent to each other are connected by the resistor film 20 and the wiring film 21, the resistor network shown in FIG. 33A constitutes a resistor circuit shown in FIG.
Here, the manufacturing process of the resistor network 14 will be briefly described.
(1) The surface of the substrate 11 is thermally oxidized to form a silicon dioxide (SiO 2) layer as the insulating layer 19.
(2) A resistor film 20 of TiN, TiON, or TiSiON is formed on the entire surface of the insulating layer 19 by sputtering.
(3) Further, an aluminum (Al) wiring film 21 is laminated on the resistor film 20 by sputtering.
(4) Then, using a photolithography process, the wiring film 21 and the resistor film 20 are selectively removed by dry etching, for example, and as shown in FIG. A configuration is obtained in which the wiring films 21 are arranged in the column direction at regular intervals. At this time, a region in which the resistor film line 20 and the wiring film 21 are partially cut is also formed.
(5) Subsequently, the wiring film 21 stacked on the resistor film line 20 is selectively removed. As a result, a configuration in which the wiring film 21 is laminated on the resistor film line 20 with a predetermined interval R is obtained.
(6) Thereafter, a SiN film 22 as a protective film is deposited, and a polyimide layer 23 as a protective layer is further laminated thereon.

  In this embodiment, the resistor film R included in the resistor network 14 formed on the substrate 11 is laminated on the resistor film line 20 and the resistor film line 20 at a certain interval in the line direction. The resistor film lines 20 at a constant interval R where the wiring film 21 is not laminated constitute a single resistor film R. The resistor film lines 20 constituting the resistor film R are all equal in shape and size. Therefore, based on the characteristic that the same-shaped and large-sized resistor films formed on the substrate have substantially the same value, the multiple resistor films R arranged in a matrix on the substrate 11 have the same resistance value. Have.

The wiring film 21 laminated on the resistor film line 20 defines the resistor film R and also serves as a connection wiring film for connecting a plurality of resistor films R to form a resistance unit body. Plays.
FIG. 35A is a partially enlarged plan view of a region including the fuse film F drawn by enlarging a part of the plan view of the chip resistor 10 shown in FIG. 32, and FIG. It is a figure which shows the cross-section which follows BB of A).

  As shown in FIGS. 35A and 35B, the fuse film F is also formed by the wiring film 21 laminated on the resistor film 20. That is, it is formed of aluminum (Al), which is the same metal material as the wiring film 21, in the same layer as the wiring film 21 laminated on the resistor film line 20. As described above, the wiring film 21 is also used as a connection wiring film 21 for electrically connecting a plurality of resistor films R in order to form a resistance unit body.

  That is, in the same layer laminated on the resistor film 20, a wiring film that partitions the resistor film R, a connection wiring film for forming a resistance unit body, and a connection wiring for forming the resistance network 14 The wiring film for connecting the film, the fuse film, and the resistor network 14 to the first connection electrode 12 and the second connection electrode 13 is formed using the same metal material (for example, aluminum) and the same manufacturing process (sputtering and photo Lithographic process). Thereby, the manufacturing process of the chip resistor 10 is simplified, and various wiring films can be simultaneously formed using a common mask. Furthermore, the alignment with the resistor film 20 is also improved.

FIG. 36 shows the arrangement relationship between the connection wiring film C and the fuse film F connecting the plurality of types of resistance unit bodies in the resistance network 14 shown in FIG. It is a figure which shows the connection relation with multiple types of resistance unit bodies diagrammatically.
Referring to FIG. 36, one end of a reference resistance unit R8 included in the resistance network 14 is connected to the first connection electrode 12. The reference resistance unit R8 is composed of eight resistor films R connected in series, and the other end is connected to the fuse film F1. One end and the other end of a resistance unit body R64 composed of 64 resistor films R connected in series are connected to the fuse film F1 and the connection wiring film C2. One end and the other end of a resistance unit body R32 formed of a series connection of 32 resistor films R are connected to the connection wiring film C2 and the fuse film F4. One end and the other end of a resistance unit body R32 formed of a series connection of 32 resistor films R are connected to the fuse film F4 and the connection wiring film C5. One end and the other end of a resistance unit body R16 formed of a series connection of 16 resistor films R are connected to the connection wiring film C5 and the fuse film F6. One end and the other end of a resistance unit body R8 composed of eight resistor films R connected in series are connected to the fuse film F7 and the connection wiring film C9. One end and the other end of a resistance unit body R4 made of a series connection of four resistor films R are connected to the connection wiring film C9 and the fuse film F10. One end and the other end of a resistance unit body R2 formed of a series connection of two resistor films R are connected to the fuse film F11 and the connection wiring film C12. One end and the other end of a resistance unit R1 made of one resistor film R are connected to the connection wiring film C12 and the fuse film F13. One end and the other end of a resistance unit body R / 2 formed by parallel connection of two resistor films R are connected to the fuse film F13 and the connection wiring film C15. One end and the other end of a resistance unit body R / 4 formed by parallel connection of four resistor films R are connected to the connection wiring film C15 and the fuse film F16. One end and the other end of a resistance unit body R / 8 composed of eight resistor films R connected in parallel are connected to the fuse film F16 and the connection wiring film C18. One end and the other end of a resistance unit body R / 16 formed by parallel connection of 16 resistor films R are connected to the connection wiring film C18 and the fuse film F19. To the fuse film F19 and the connection wiring film C22, a resistance unit body R / 32 composed of a parallel connection of 32 resistor films R is connected.

  The plurality of fuse films F and the connection wiring film C are respectively a fuse film F1, a connection wiring film C2, a fuse film F3, a fuse film F4, a connection wiring film C5, a fuse film F6, a fuse film F7, and a connection wiring. Film C8, connecting wiring film C9, fuse film F10, fuse film F11, connecting wiring film C12, fuse film F13, fuse film F14, connecting wiring film C15, fuse film F16, fuse film F17, connecting wiring film C18 The fuse film F19, the fuse film F20, the connection wiring film C21, and the connection wiring film C22 are arranged in a straight line and connected in series. When each fuse film F is melted, the electrical connection with the connection wiring film C adjacently connected to the fuse film F is cut off.

  This configuration is shown in an electric circuit diagram as shown in FIG. In other words, in a state where all the fuse films F are not blown, the resistance network 14 has a reference resistance composed of eight resistors R provided in series between the first connection electrode 12 and the second connection electrode 13. A resistance circuit of the unit body R8 (resistance value 8r) is configured. For example, if the resistance value r of one resistor R is r = 80Ω, the chip resistor 10 to which the first connection electrode 12 and the second connection electrode 13 are connected is configured by a resistance circuit of 8r = 640Ω. ing.

  A plurality of types of resistance units other than the reference resistance unit R8 are connected in parallel to the fuse films F, and the plurality of types of resistance units are short-circuited by the fuse films F. Yes. That is, 12 types of 13 resistance unit bodies R64 to R / 32 are connected in series to the reference resistance unit body R8, but each resistance unit body is short-circuited by the fuse film F connected in parallel. Therefore, when viewed electrically, each resistance unit is not incorporated in the resistance network 14.

  The chip resistor 10 according to this embodiment selectively fuses the fuse film F with, for example, laser light according to a required resistance value. As a result, the resistance unit body in which the fuse films F connected in parallel are melted is incorporated in the resistance network 14. Therefore, the entire resistance value of the resistor network 14 can be a resistor network having a resistance value in which resistance unit bodies corresponding to the blown fuse film F are connected in series.

  In other words, the chip resistor 10 according to the present embodiment selectively blows a fuse film provided corresponding to a plurality of types of resistance unit bodies, so that a plurality of types of resistance unit bodies (for example, F1,. When F4 and F13 are fused, the resistance unit bodies R64, R32, and R1 can be incorporated into the resistor network. Since the resistance value of each of the plurality of types of resistance units is determined, the resistance value of the resistance network 14 is digitally adjusted to make the chip resistor 10 having the required resistance value. be able to.

  Further, the plurality of types of resistance unit bodies are equal in number sequence, such as one, two, four, eight, sixteen, thirty-two, and sixty-four resistor films R having the same resistance value in series. A plurality of series resistance unit bodies connected to each other by increasing the number of resistor films R, and two, four, eight, sixteen, and thirty-two resistor films R having the same resistance value in parallel; Since a plurality of types of parallel resistance unit bodies connected by increasing the number of resistor films R in a geometric sequence are connected in series while being short-circuited by the fuse film F, the fuse By selectively fusing the film F, the resistance value of the entire resistor network 14 can be set to an arbitrary resistance value in a wide range from a small resistance value to a large resistance value.

  FIG. 38 is a plan view of a chip resistor 30 according to another embodiment of the third invention. The arrangement relationship of the first connection electrode 12, the second connection electrode 13, and the resistor network 4 and the plane of the resistor network 14 are shown. The visual configuration is shown. The difference between the chip resistor 30 and the chip resistor 10 described above is the connection mode of the resistor film R in the resistor network 14. That is, the resistor network 14 of the chip resistor 30 includes a plurality of resistor films R having equal resistance values arranged in a matrix on the substrate (in the configuration of FIG. 38, in the row direction (longitudinal direction of the substrate)). And eight resistor films R are arranged along the column direction (substrate width direction), and a total of 352 resistor film R configurations) are provided. Yes. One to 128 of the many resistor films R are electrically connected to form a plurality of types of resistance unit bodies. The formed plural types of resistance unit bodies are connected in parallel by a wiring film as a network connection means and a fuse film F. The plurality of fuse films F are arranged along the inner side of the second connection electrode 13 so that the arrangement region is linear. When the fuse film F is blown, the resistance unit connected to the fuse film F The body is electrically separated from the resistor network 14.

The structure of the many resistor films R constituting the resistor network 14, the structure of the connection wiring film, and the fuse film F are the same as the structures of the corresponding parts in the chip resistor 10 described above. Therefore, the description here is omitted.
FIG. 39 shows a connection mode of a plurality of types of resistance unit bodies in the resistance circuit network shown in FIG. FIG.

  Referring to FIG. 39, one end of a reference resistance unit R / 16 included in the resistance network 14 is connected to the first connection electrode 12. The reference resistance unit R / 16 is composed of 16 resistor films R connected in parallel, and the other end is connected to the connection wiring film C to which the remaining resistor unit bodies are connected. One end and the other end of a resistance unit body R128 formed by serial connection of 128 resistor films R are connected to the fuse film F1 and the connection wiring film C. One end and the other end of a resistance unit body R64 composed of 64 resistor films R connected in series are connected to the fuse film F5 and the connection wiring film C. One end and the other end of a resistance unit body R32 formed of a series connection of 32 resistor films R are connected to the fuse film F6 and the connection wiring film C. One end and the other end of a resistance unit body R16 formed by connecting 16 resistor films R in series are connected to the fuse film F7 and the connection wiring film C. One end and the other end of a resistance unit body R8 composed of eight resistor films R connected in series are connected to the fuse film F8 and the connection wiring film C. One end and the other end of a resistance unit body R4 formed of a series connection of four resistor films R are connected to the fuse film F9 and the connection wiring film C. One end and the other end of a resistance unit body R2 formed by connecting two resistor films R in series are connected to the fuse film F10 and the connection wiring film C. One end and the other end of a resistance unit body R1 made of a series connection of one resistor film R are connected to the fuse film F11 and the connection wiring film C. One end and the other end of a resistance unit body R / 2 formed by parallel connection of two resistor films R are connected to the fuse film F12 and the connection wiring film C. One end and the other end of a resistance unit body R / 4 composed of four resistor films R connected in parallel are connected to the fuse film F13 and the connection wiring film C. The fuse films F14, F15, and F16 are electrically connected, and the fuse films F14, F15, and F16 and the connection wiring film C have a resistance unit R formed by connecting eight resistor films R in parallel. One end and the other end of / 8 are connected. The fuse films F17, F18, F19, F20, and F21 are electrically connected, and the fuse films F17 to F21 and the connecting wiring film C are resistance units formed by parallel connection of 16 resistor films R. One end and the other end of the body R / 16 are connected.

The fuse film F includes 21 fuse films F <b> 1 to F <b> 21, all of which are connected to the second connection electrode 13.
With this configuration, when one of the fuse films F to which one end of the resistance unit body is connected is blown, the resistance unit body having one end connected to the fuse film F is electrically connected from the resistance network 14. Disconnected.

  The configuration of FIG. 39, that is, the configuration of the resistor network 14 provided in the chip resistor 30 is shown in an electric circuit diagram as shown in FIG. In a state in which all the fuse films F are not blown, the resistance network 14 includes a reference resistance unit body R8, 12 types of resistance unit bodies R / 16, between the first connection electrode 12 and the second connection electrode 13. A series connection circuit is formed with a parallel connection circuit of R / 8, R / 4, R / 2, R1, R2, R4, R8, R16, R32, R64, and R128.

  A fuse film F is connected in series to each of 12 types of resistance unit bodies other than the reference resistance unit body R / 16. Therefore, in the chip resistor 30 having the resistance network 14, if the fuse film F is selectively blown by, for example, laser light according to a required resistance value, a resistance corresponding to the blown fuse film F is obtained. The unit body (resistance unit body in which the fuse film F is connected in series) is electrically separated from the resistance network 14, and the resistance value of the chip resistor 10 can be adjusted.

  In other words, the chip resistor 30 according to this embodiment also selectively blows the fuse film provided corresponding to the plurality of types of resistance unit bodies, thereby removing the plurality of types of resistance unit bodies from the resistor network. It can be electrically separated. Since the resistance value of each of the plurality of types of resistance units is determined, the resistance value of the resistance network 14 is digitally adjusted so that the chip resistor 30 having the required resistance value is obtained. be able to.

  In addition, the plurality of types of resistance unit bodies have the same ratio of one, two, four, eight, sixteen, thirty-two, sixty-four, and 128 resistive film R having the same resistance value. A plurality of types of series resistance unit bodies connected by increasing the number of resistor films R in series, and two, four, eight, and sixteen resistor films R of equal resistance in parallel Since there are a plurality of types of parallel resistance unit bodies connected by increasing the number of resistor films R in a sequence, the resistance value of the entire resistor network 14 can be reduced by selectively fusing the fuse film F. The resistance value can be set finely and digitally.

  By the way, in the chip resistor 10 shown in FIG. 32 described above, the wiring film and the resistance in the region A enclosed by the broken line and in the chip resistor 30 shown in FIG. 38 in the region B enclosed by the broken line. The body membrane R is in a so-called comb-shaped connection mode. Thus, when a large number of resistor films R are connected in parallel to the connection wiring film in a comb-like shape, the resistance value of the entire resistor film R becomes small, and the influence of the resistance value of the wiring film itself can be ignored. Disappear. Therefore, in such a region, as shown in FIG. 41, the wiring film 21 has a laminated two-layer structure (a structure in which the wiring film 29 is laminated on the wiring film 21), and the resistance values of the wiring films 21 and 29 in that portion. The resistance value of the wiring films 21 and 29 in that portion may be reduced so as not to affect the entire resistance network.

When the entire connecting wiring film has a laminated two-layer structure, the fuse film F also has a two-layer structure, and the thickness of the fuse film F increases, which may make it difficult to blow the fuse film F with a laser. . Therefore, at least the connection wiring film excluding the fuse film F may have a laminated two-layer structure in the entire region so as to reduce the resistance value.
In the region of the fuse film F, since the wiring film 21 has a single layer structure, as a manufacturing process, an aluminum wiring film 21 is laminated on the resistor film 20, and the wiring film 21 and the wiring film 21 are formed using a photolithography process. After the resistor film 20 is configured in a predetermined pattern, a region of the patterned fuse film F is masked and a second metal wiring film is laminated on the wiring film 21 by sputtering. .

Alternatively, after the resistive network 14 is formed by patterning, the second-layer conductor film (wiring film 29) is laminated only on the wiring film in a desired region (for example, a comb-shaped portion). Also good.
In the case of a laminated wiring structure, the wiring material of the first layer (lower layer) 21 may be Al, for example, and the wiring material of the second layer (upper layer) 29 may be the same wiring material Al as that of the first layer 21. Alternatively, another wiring material (for example, Cu) may be used.

Meanwhile, in the electric circuit shown in FIG. 40, the resistance unit body having a small resistance value among the reference resistance unit body R / 16 and the resistance unit bodies connected in parallel has a tendency that overcurrent flows, and resistance setting is performed. Sometimes, it is necessary to design a large rated current that can flow through the resistor.
Therefore, in order to disperse the current, the connection structure of the resistor network may be changed so that the electric circuit shown in FIG. 40 has the electric circuit configuration shown in FIG. That is, the resistance unit bodies connected in parallel without the reference resistance unit R / 16 include a configuration 140 in which a minimum resistance value is r and a plurality of resistance unit bodies R1 having a resistance value r are connected in parallel. It turns into a circuit. FIG. 42B is an electric circuit diagram showing a specific resistance value, and is a circuit including a configuration 140 in which a plurality of series connections of 80Ω resistance unit bodies and fuse films F are connected in parallel. . Thereby, distribution of the flowing current can be achieved.

  FIG. 43 is an electric circuit diagram showing a circuit configuration of a resistor network 14 provided in a chip resistor according to still another embodiment of the third invention. The characteristic of the resistance network 14 shown in FIG. 43 is that the circuit configuration is such that a series connection of a plurality of types of resistance unit bodies and a parallel connection of a plurality of types of resistance unit bodies are connected in series. As in the previous embodiment, the plurality of types of resistance unit bodies connected in series have a fuse film F connected in parallel to each resistance unit body, and all of the plurality of types of resistance unit bodies connected in series are all The fuse film F is short-circuited. Therefore, when the fuse film F is melted, the resistance unit body short-circuited by the fuse film F is electrically incorporated into the resistance network 14.

On the other hand, a fuse film F is connected in series to each of a plurality of types of resistance unit bodies connected in parallel. Therefore, by fusing the fuse film F, the resistance unit bodies to which the fuse film F is connected in series can be electrically disconnected from the parallel connection of the resistance unit bodies.
With this configuration, for example, a small resistance of 1 kΩ or less can be made on the parallel connection side, and a resistance circuit of 1 kΩ or more can be made on the series connection side. Therefore, a wide range of resistance circuits from a small resistance of several Ω to a large resistance of several MΩ can be made using the resistance network 14 configured with the same basic design.

In addition, when setting the resistance value with higher accuracy, if the fuse film of the series connection side resistance circuit close to the required resistance value is cut in advance, fine adjustment of the resistance value can be performed by the fuse film of the resistance circuit on the parallel connection side. This can be performed by fusing, and the accuracy of fitting to a desired resistance value is improved.
FIG. 44 is an electric circuit diagram showing a specific configuration example of the resistance network 14 in the chip resistor having a resistance value of 10Ω to 1MΩ.

44 also has a series connection of a plurality of types of resistance unit bodies short-circuited by the fuse film F and a series connection of a plurality of types of resistance unit bodies to which the fuse film F is connected in series. The circuit configuration is as described above.
According to the resistance circuit of FIG. 44, an arbitrary resistance value of 10 to 1 kΩ can be set within an accuracy of 1% on the parallel connection side. In addition, an arbitrary resistance value of 1 k to 1 MΩ can be set within an accuracy of 1% in the circuit on the serial connection side. When using a circuit on the serial connection side, it is possible to set the resistance value with higher accuracy by fusing the fuse film F of the resistance unit body close to the desired resistance value in advance and adjusting it to the desired resistance value. There are advantages.

FIG. 45 is a diagram illustrating a circuit configuration of the electronic apparatus 1 in which another circuit is incorporated in the above-described chip resistor.
The electronic device 1 is, for example, a diode 55 and a resistor network 14 connected in series. This electronic device 1 is a chip-type electronic device including a diode 55. The third invention can be applied not only to the chip type as in this example but also to an electronic device having the above-described resistance network 14.
<Fourth Invention>
(1) Features of the fourth invention For example, the features of the fourth invention are the following C1 to C11.
(C1) including a substrate having an element formation surface and a plurality of side surfaces perpendicular to the element formation surface, a circuit element formed on the substrate, and an external connection electrode formed on the substrate. A chip component having an asymmetric outer shape that indicates the chip direction in view.

According to this configuration, the chip direction of the chip component can be recognized only by making the outer shape of the substrate in the chip component asymmetric in a plan view. That is, the chip direction can be recognized by the outer shape of the chip component without a marking process.
(C2) The chip component according to C1, wherein the asymmetric outer shape has a concave portion or a convex portion that represents the chip direction on one side of the side surface.

According to this configuration, the concave or convex side in the direction connecting one side having the concave or convex part and one side opposite to the one side can be the chip direction.
(C3) The chip component according to C2, wherein the concave portion or the convex portion is disposed at a position shifted from a midpoint of the one side.
According to this configuration, the concave or convex side in the extending direction of the one side can also be the chip direction.
(C4) The chip component according to C2 or C3, wherein the concave portion or the convex portion is rectangular or U-shaped.

A concave portion or a convex portion having a simple shape such as a rectangular shape or a U-shape can be easily formed.
(C5) The chip component according to any one of C2 to C4, further including a protective film that covers the element formation surface and the plurality of side surfaces.
(C6) The chip part according to C5, wherein the protective film covers a portion where the concave portion or the convex portion is formed on the side surface.
(C7) The chip component according to any one of C2 to C6, wherein a corner portion of the concave portion or the convex portion is chamfered on the side surface.

According to this structure, generation | occurrence | production of the chipping (chip) in a corner part can be prevented.
(C8) The chip component according to any one of C1 to C7, wherein the chip direction is a direction corresponding to a polarity of the external connection electrode.
According to this configuration, since the polarity of the external connection electrode can be indicated by the chip direction, the polarity can be grasped by the appearance of the chip component.
(C9) The chip component according to C8, wherein the circuit element includes a diode or a capacitor.
(C10) forming a circuit element on the element formation surface of the substrate and using plasma etching to form a plurality of side surfaces orthogonal to the element formation surface on the substrate, and on one side of the plurality of side surfaces And a step of forming a concave portion or a convex portion representing the chip direction.

According to this method, since the outer shape of the substrate can be made asymmetric to represent the chip direction by the concave portion or the convex portion, a chip component that can recognize the chip direction without a marking step can be manufactured.
(C11) a step of forming a circuit element on an element formation surface of the substrate, and a plurality of side surfaces orthogonal to the element formation surface in the substrate, and a recess representing a chip direction on one side of the plurality of side surfaces Or the process of forming a convex part, The manufacturing method of a chip component.

According to this method, since the outer shape of the substrate can be made asymmetric to represent the chip direction by the concave portion or the convex portion, a chip component that can recognize the chip direction without a marking step can be manufactured.
(2) Embodiment of 4th invention Below, embodiment of the 4th invention is described in detail with reference to an accompanying drawing. The reference numerals shown in FIGS. 47 to 61 are effective only in these drawings, and even if used in other embodiments, they do not indicate the same elements as those in the other embodiments.

FIG. 47A is a schematic perspective view for explaining the configuration of an electronic device according to an embodiment of the fourth invention, and FIG. 47B is a state in which the electronic device is mounted on a circuit board. It is a typical side view which shows.
This electronic device 1 is a minute chip part and has a rectangular parallelepiped shape as shown in FIG. Regarding the dimensions of the electronic device 1, the length L in the long side direction is about 0.3 mm, the width W in the short side direction is about 0.15 mm, and the thickness T is about 0.1 mm.

The electronic device 1 is obtained by forming a large number of electronic devices 1 in a lattice shape on a wafer and then cutting the wafer into individual electronic devices 1.
The electronic device 1 mainly includes a substrate 2, a first connection electrode 3 and a second connection electrode 4 that are external connection electrodes, and an element 5. The first connection electrode 3, the second connection electrode 4, and the element 5 are formed on the substrate 2 by using, for example, a semiconductor manufacturing process. Accordingly, a semiconductor substrate (semiconductor wafer) such as a silicon substrate (silicon wafer) can be used as the substrate 2. The substrate 2 may be another type of substrate such as an insulating substrate.

  The substrate 2 has a substantially rectangular parallelepiped chip shape. In the substrate 2, the upper surface in FIG. 47A is the element formation surface 2A. The element formation surface 2A is the surface of the substrate 2 and has a substantially rectangular shape. The surface opposite to the element formation surface 2A in the thickness direction of the substrate 2 is a back surface 2B. The element formation surface 2A and the back surface 2B have substantially the same shape. In addition to the element formation surface 2A and the back surface 2B, the substrate 2 has a side surface 2C, a side surface 2D, a side surface 2E, and a side surface 2F that extend perpendicular to these surfaces.

  The side surface 2C extends between one end edge in the longitudinal direction of the element formation surface 2A and the back surface 2B (the left front edge in FIG. 47A), and the side surface 2D extends in the longitudinal direction on the element formation surface 2A and the back surface 2B. It is constructed between the other ends in the direction (the edge on the right back side in FIG. 47A). The side surface 2C and the side surface 2D are both end surfaces of the substrate 2 in the longitudinal direction. The side surface 2E is provided between one end edge in the short direction of the element formation surface 2A and the back surface 2B (the left edge on the left side in FIG. 47A), and the side surface 2F includes the element formation surface 2A and the back surface 2B. Between the other edges in the short direction (the edge on the right front side in FIG. 47A). The side surface 2E and the side surface 2F are both end surfaces of the substrate 2 in the lateral direction.

  In the substrate 2, the element formation surface 2 </ b> A, the side surface 2 </ b> C, the side surface 2 </ b> D, the side surface 2 </ b> E, and the side surface 2 </ b> F are covered with the protective film 23. Therefore, strictly speaking, in FIG. 47A, the element formation surface 2A, the side surface 2C, the side surface 2D, the side surface 2E, and the side surface 2F are located on the inner side (back side) of the protective film 23 and are exposed to the outside. Absent. Further, the protective film 23 on the element formation surface 2 </ b> A is covered with a resin film 24. The resin film 24 protrudes from the element formation surface 2A to the end portion on the element formation surface 2A side (the upper end portion in FIG. 47A) of each of the side surface 2C, the side surface 2D, the side surface 2E, and the side surface 2F. The protective film 23 and the resin film 24 will be described in detail later.

  In the substrate 2, the substrate 2 is placed on a portion corresponding to one side A (the side surface 2C, 2D, 2E, or 2F of the substantially rectangular element forming surface 2A, here, the side surface 2C as described later). A recess 10 is formed that is notched in the thickness direction. The side A is also one side of the electronic device 1 in plan view. The recess 10 in FIG. 47 (a) is formed on the side surface 2C and is recessed toward the side surface 2D while extending in the thickness direction of the substrate 2. The recess 10 penetrates the substrate 2 in the thickness direction, and the end of the recess 10 in the thickness direction is exposed from each of the element formation surface 2A and the back surface 2B. The recess 10 is smaller than the side surface 2C in the direction in which the side surface 2C extends (the short direction described above). The shape of the recess 10 in a plan view when the substrate 2 is viewed from the thickness direction (also the thickness direction of the electronic device 1) is a rectangular shape (rectangular shape) that is long in the short direction. The shape of the recess 10 in plan view may be a trapezoidal shape that becomes narrower in the direction in which the recess 10 is recessed (side 2D side), or a triangular shape that becomes narrower in the direction of recess. Alternatively, it may be U-shaped (a shape recessed in a U-shape). In any case, the concave portion 10 having such a simple shape can be easily formed. Moreover, although the recessed part 10 is formed in the side surface 2C here, you may form in at least one of the side surfaces 2C-2F instead of the side surface 2C.

  The concave portion 10 represents the direction (chip direction) of the electronic device 1 when the electronic device 1 is mounted on the circuit board 9 (see FIG. 47B). Since the outline of the electronic device 1 (strictly speaking, the substrate 2) in plan view is a rectangle having a recess 10 on one side A thereof, it has an asymmetric outer shape in the longitudinal direction. That is, the asymmetric outer shape has the concave portion 10 indicating the chip direction on any one of the side surfaces 2C, 2D, 2E, and 2F (one side A). It represents that the concave side in the longitudinal direction is the chip direction. Thus, the chip direction of the electronic device 1 can be recognized only by making the outer shape of the substrate 2 in the electronic device 1 asymmetric in a plan view. That is, the chip direction can be recognized from the outer shape of the electronic device 1 without a marking process. In particular, since the asymmetric outer shape of the electronic device 1 is a rectangle having a concave portion 10 representing the chip direction on one side A, the electronic device 1 has a concave portion 10 side in the longitudinal direction connecting the one side A and the opposite side B. It can be in the chip direction. Therefore, for example, in the plan view, the longitudinal direction of the electronic device 1 is aligned with the left-right direction so that the electronic device 1 can be correctly mounted on the circuit board 9 when the side A is located at the left end. When mounting, it can be grasped from the appearance of the electronic device 1 by the recess 10 that the electronic device 1 must be oriented so that the side A is located at the left end in plan view.

  In the rectangular parallelepiped substrate 2, the corner portion 11 (the portion where the adjacent ones intersect) adjacent to each other on the side surface 2C, the side surface 2D, the side surface 2E, and the side surface 2F has a chamfered round shape. It is shaped (rounded). Further, in the substrate 2, a corner portion 12 (a corner portion in the concave portion 10 in the side surface 2 </ b> C) that forms a boundary between the concave portion 10 and the side surface 2 </ b> C around the concave portion 10 is also shaped into a chamfered round shape. Here, the corner portion 12 exists not only at the boundary between the concave portion 10 and the surrounding side surface 2C (portion other than the concave portion 10) but also at the deepest portion side of the concave portion 10, and is present at four locations in plan view.

Thus, in the outline of the board | substrate 2 in planar view, all the bent parts (corner parts 11 and 12) are round shape. Therefore, the occurrence of chipping can be prevented at the corner portions 11 and 12 in the round shape. Thereby, in the manufacture of the electronic apparatus 1, it is possible to improve the yield (improvement of productivity).
The first connection electrode 3 and the second connection electrode 4 are formed on the element formation surface 2 </ b> A of the substrate 2 and are partially exposed from the resin film 24. Each of the first connection electrode 3 and the second connection electrode 4 is configured, for example, by stacking Ni (nickel), Pd (palladium), and Au (gold) on the element formation surface 2A in this order. The first connection electrode 3 and the second connection electrode 4 are arranged at intervals in the longitudinal direction of the element formation surface 2A, and are long in the short direction of the element formation surface 2A. In FIG. 47A, on the element formation surface 2A, the first connection electrode 3 is provided near the side surface 2C, and the second connection electrode 4 is provided near the side surface 2D. The concave portion 10 of the side surface 2 </ b> C described above is recessed at a depth that does not interfere with the first connection electrode 3. However, in some cases, the first connection electrode 3 may be provided with a recess (becomes a part of the recess 10) according to the recess 10.

  The element 5 is a circuit element, and is formed in a region between the first connection electrode 3 and the second connection electrode 4 on the element formation surface 2A of the substrate 2, and from above by the protective film 23 and the resin film 24. It is covered. The element 5 of this embodiment is a circuit network in which a plurality of thin film resistors (thin film resistors) R made of TiN (titanium nitride) or TiON (titanium oxynitride) are arranged in a matrix on the element formation surface 2A. A configured resistor 56. The element 5 is connected to a wiring film 22 which will be described later, and is connected to the first connection electrode 3 and the second connection electrode 4 via the wiring film 22. Thereby, in the electronic device 1, a resistance circuit including the element 5 is formed between the first connection electrode 3 and the second connection electrode 4. Therefore, the electronic device 1 in this embodiment is a chip resistor.

  As shown in FIG. 47 (b), the first connection electrode 3 and the second connection electrode 4 are opposed to the circuit board 9, and the circuit 13 is electrically and mechanically connected to the circuit (not shown) by the solder 13. Thus, the electronic device 1 can be flip-chip connected to the circuit board 9. The first connection electrode 3 and the second connection electrode 4 that function as external connection electrodes are formed of gold (Au) or are plated with gold in order to improve solder wettability and reliability. It is desirable.

FIG. 48 is a plan view of the electronic device, and is a diagram illustrating a positional relationship between the first connection electrode, the second connection electrode, and the element, and a configuration in plan view of the element.
Referring to FIG. 48, as an example, element 5 that is a resistor network includes eight resistors R arranged in the row direction (longitudinal direction of substrate 2) and the column direction (of substrate 2). It has a total of 352 resistors R composed of 44 resistors R arranged along the width direction. Each resistor R has an equal resistance value.

  A plurality of types of resistance unit bodies (unit resistances) are formed by grouping and electrically connecting a large number of these resistor bodies R every predetermined number of 1 to 64 pieces. The formed plural types of resistance unit bodies are connected in a predetermined manner via the connecting conductor film C. In addition, a plurality of fuse films F that can be blown on the element forming surface 2A of the substrate 2 in order to electrically incorporate the resistance unit into the element 5 or to electrically separate it from the element 5 are provided. Is provided. The plurality of fuse films F and connection conductor films C are arranged along the inner side of the second connection electrode 4 so that the arrangement region is linear. More specifically, a plurality of fuse films F and connecting conductor films C are arranged in a straight line.

49A is a plan view illustrating a part of the element shown in FIG. 48 in an enlarged manner. FIG. 49B is a longitudinal sectional view in the length direction along BB of FIG. 49A drawn to explain the configuration of the resistor in the element. 49C is a longitudinal sectional view in the width direction along CC of FIG. 49A drawn to explain the configuration of the resistor in the element.
The configuration of the resistor R will be described with reference to FIGS. 49A, 49B, and 49C.

The electronic device 1 further includes an insulating film 20 and a resistor film 21 in addition to the wiring film 22, the protective film 23, and the resin film 24 described above (see FIGS. 49B and 49C). The insulating film 20, the resistor film 21, the wiring film 22, the protective film 23, and the resin film 24 are formed on the substrate 2 (element formation surface 2A).
The insulating film 20 is made of SiO ₂ (silicon oxide). The insulating film 20 covers the entire area of the element formation surface 2A of the substrate 2. The insulating film 20 has a thickness of about 10,000 mm.

  The resistor film 21 constitutes the resistor R. The resistor film 21 is made of TiN or TiON, and is laminated on the surface of the insulating film 20. The thickness of the resistor film 21 is about 2000 mm. The resistor film 21 constitutes a plurality of lines (hereinafter referred to as “resistor film line 21 </ b> A”) extending in a line between the first connection electrode 3 and the second connection electrode 4. 21A may be cut at a predetermined position in the line direction (see FIG. 49A).

A wiring film 22 is laminated on the resistor film line 21A. The wiring film 22 is made of Al (aluminum) or an alloy of aluminum and Cu (copper) (AlCu alloy). The thickness of the wiring film 22 is about 8000 mm. The wiring film 22 is laminated on the resistor film line 21A with a constant interval R in the line direction.
The electrical characteristics of the resistor film line 21A and the wiring film 22 having this configuration are shown by circuit symbols as shown in FIG. That is, as shown in FIG. 50A, each of the resistor film lines 21A in the region of the predetermined interval R forms one resistor R having a constant resistance value r.

In the region where the wiring film 22 is laminated, the resistor film lines 21 </ b> A are short-circuited by the wiring film 22 by electrically connecting the resistors R adjacent to each other. Therefore, a resistance circuit is formed which is formed by connecting in series the resistor R of the resistor r shown in FIG.
Further, since the adjacent resistor film lines 21A are connected by the resistor film 21 and the wiring film 22, the resistor network of the element 5 shown in FIG. 49A is shown in FIG. A resistor circuit (consisting of R unit resistors) is formed.

Here, based on the characteristic that the same-shaped and large-sized resistor films 21 formed on the substrate 2 have substantially the same value, a large number of resistors R arranged in a matrix on the substrate 2 have the same resistance. Has a value.
Further, the wiring film 22 laminated on the resistor film line 21A forms a resistor R and also serves as a connecting wiring film for connecting a plurality of resistors R to form a resistance unit body. Plays.

51A is a partially enlarged plan view of a region including a fuse film drawn by enlarging a part of the plan view of the electronic device shown in FIG. 48, and FIG. 51B is a plan view of FIG. It is a figure which shows the cross-sectional structure which follows BB.
As shown in FIGS. 51A and 51B, the above-described fuse film F and connecting conductor film C are also formed by the wiring film 22 laminated on the resistor film 21 forming the resistor R. . That is, on the same layer as the wiring film 22 laminated on the resistor film line 21A forming the resistor R, the fuse film F and the connecting conductor film C are formed of Al or AlCu alloy which is the same metal material as the wiring film 22. Is formed.

  That is, in the same layer laminated on the resistor film 21, the wiring film for forming the resistor R, the fuse film F, the connecting conductor film C, and the element 5 are connected to the first connection electrode 3. A wiring film for connecting to the second connection electrode 4 is formed as the wiring film 22 by using the same metal material (Al or AlCu alloy) by the same manufacturing process (a sputtering and a photolithography process described later). Yes.

The fuse film F is not only a part of the wiring film 22 but also a group (fuse element) of a part of the resistor R (resistor film 21) and a part of the wiring film 22 on the resistor film 21. You may point.
The fuse film F has been described only in the case where the same layer as the connecting conductor film C is used. However, the connecting conductor film C is formed by stacking another conductor film on the conductor film C. The resistance value may be lowered. Even in this case, if the conductor film is not laminated on the fuse film F, the fusing property of the fuse film F does not deteriorate.

FIG. 52 is an electric circuit diagram of an element according to the embodiment of the fourth invention.
Referring to FIG. 52, element 5 includes reference resistance unit R8, resistance unit R64, two resistance units R32, resistance unit R16, resistance unit R8, resistance unit R4, resistance unit R2, The resistance unit body R1, the resistance unit body R / 2, the resistance unit body R / 4, the resistance unit body R / 8, the resistance unit body R / 16, and the resistance unit body R / 32 are arranged in this order from the first connection electrode 3. It is configured by connecting in series. Each of the reference resistance unit R8 and the resistance unit bodies R64 to R2 is configured by connecting in series the same number of resistors R as the last number (“64” in the case of R64). The resistance unit R1 is composed of one resistor R. Each of the resistance unit bodies R / 2 to R / 32 is configured by connecting in parallel the same number of resistor bodies R as the last number of itself (“32” in the case of R / 32). The meaning of the number at the end of the resistance unit body is the same in FIGS. 53 and 54 described later.

One fuse film F is connected in parallel to each of the resistance unit bodies R64 to R / 32 other than the reference resistance unit body R8. The fuse films F are connected in series either directly or via a connecting conductor film C (see FIG. 51A).
As shown in FIG. 52, in a state where all the fuse films F are not blown, the element 5 is composed of eight resistors R provided in series between the first connection electrode 3 and the second connection electrode 4. A resistance circuit of the reference resistance unit R8 (resistance value 8r) is configured. For example, if the resistance value r of one resistor R is r = 80Ω, a chip resistor (electronic device 1) in which the first connection electrode 3 and the second connection electrode 4 are connected by a resistance circuit of 8r = 64Ω. Is configured.

  Further, in a state where all the fuse films F are not blown, a plurality of types of resistance unit bodies other than the reference resistance unit body R8 are short-circuited. That is, 12 types of 13 resistance unit bodies R64 to R / 32 are connected in series to the reference resistance unit body R8, but each resistance unit body is short-circuited by the fuse film F connected in parallel. Therefore, when viewed electrically, each resistance unit is not incorporated in the element 5.

  In the electronic apparatus 1 according to this embodiment, the fuse film F is selectively blown by, for example, laser light according to a required resistance value. Thereby, the resistance unit body in which the fuse films F connected in parallel are melted is incorporated into the element 5. Therefore, the entire resistance value of the element 5 can be a resistance value in which resistance unit bodies corresponding to the blown fuse film F are connected in series and incorporated.

  In particular, in the plurality of types of resistance unit bodies, the resistor R having the same resistance value is one, two, four, eight, sixteen, thirty-two, etc. in series. The number of the series resistor unit bodies connected by increasing the number of resistors and the resistors R having the same resistance value are two, four, eight, sixteen, etc. in parallel. A plurality of types of parallel resistance units connected in increasing numbers are provided. Therefore, by selectively fusing the fuse film F (including the above-described fuse element), the resistance value of the entire element 5 (resistor 56) is adjusted finely and digitally to an arbitrary resistance value. Thus, a desired value of resistance can be generated in the electronic device 1.

FIG. 53 is an electric circuit diagram of an element according to another embodiment of the fourth invention.
Instead of configuring the element 5 by connecting the reference resistance unit R8 and the resistance unit R64 to the resistance unit R / 32 in series as described above, the element 5 may be configured as shown in FIG. Specifically, between the first connection electrode 3 and the second connection electrode 4, the reference resistance unit body R / 16 and the 12 types of resistance unit bodies R / 16, R / 8, R / 4, R / 2, R1 , R2, R4, R8, R16, R32, R64, R128 may be used to form the element 5 in a series connection circuit.

  In this case, the fuse film F is connected in series to each of the 12 types of resistance unit bodies other than the reference resistance unit body R / 16. In a state where all the fuse films F are not blown, each resistance unit body is electrically incorporated into the element 5. If the fuse film F is selectively blown, for example, by laser light, according to the required resistance value, a resistance unit body corresponding to the blown fuse film F (a resistance unit body in which the fuse film F is connected in series) ) Is electrically separated from the element 5, the resistance value of the entire electronic device 1 can be adjusted.

FIG. 54 is an electric circuit diagram of an element according to still another embodiment of the fourth invention.
The element 5 shown in FIG. 54 has a circuit configuration in which a plurality of types of resistance unit bodies are connected in series and a plurality of types of resistance unit bodies are connected in series. As in the previous embodiment, the fuse film F is connected in parallel to each of the plurality of types of resistance unit bodies connected in series, and the plurality of types of resistance unit bodies connected in series are all The fuse film F is short-circuited. Therefore, when the fuse film F is blown, the resistance unit body short-circuited by the blown fuse film F is electrically incorporated into the element 5.

On the other hand, a fuse film F is connected in series to each of a plurality of types of resistance unit bodies connected in parallel. Therefore, by fusing the fuse film F, the resistance unit body to which the blown fuse film F is connected in series can be electrically disconnected from the parallel connection of the resistance unit bodies.
With this configuration, for example, a small resistance of 1 kΩ or less is made on the parallel connection side, and if a resistance circuit of 1 kΩ or more is made on the series connection side, a wide range from a small resistance of several Ω to a large resistance of several MΩ is obtained. Resistor circuits can be made using a network of resistors constructed with an equal basic design.

FIG. 55 is a schematic cross-sectional view of an electronic device.
Next, the electronic device 1 will be described in more detail with reference to FIG. For convenience of explanation, in FIG. 55, the element 5 described above is shown in a simplified manner, and each element other than the substrate 2 is hatched.
Here, the protective film 23 and the resin film 24 described above will be described.

  The protective film 23 is made of, for example, SiN (silicon nitride) and has a thickness of about 3000 mm. The protective film 23 is provided over the entire element formation surface 2A and covers the resistor film 21 and each wiring film 22 (that is, the element 5) on the resistor film 21 from the surface (upper side in FIG. 55) ( That is, an element covering portion 23A that covers the upper surface of each resistor R in the element 5 and a side surface covering portion 23B that covers the entire area of each of the four side surfaces 2C to 2F (see FIG. 47A) of the substrate 2. It has one. The element covering portion 23A and the side surface covering portion 23B are actually substantially the same thickness and are continuous with each other. Therefore, the entire protective film 23 continuously covers the upper surface of the resistor R and the side surfaces 2C to 2F of the substrate 2 with substantially the same thickness.

The element covering portion 23A prevents a short circuit other than the wiring film 22 between the resistors R (short circuit between adjacent resistor film lines 21A).
The side surface covering portion 23B covers not only the entire area of each of the side surfaces 2C to 2F but also the portion of the insulating film 20 exposed at the side surfaces 2C to 2F. The side surface covering portion 23B covers the entire area including the portion where the concave portion 10 is formed on the side surface 2C (see FIG. 47A). The side surface covering portion 23B prevents a short circuit in each of the side surfaces 2C to 2F (a short circuit path is generated on the side surface).

  47A, the protective film 23 continuously covers the element forming surface 2A of the substrate 2 and the four side surfaces 2C to 2F, so that the corner portions 11 and 12 of the substrate 2 are covered. A rounded corner portion 26 is provided. In this case, the element 5 and the wiring film 22 can be protected by the protective film 23 and the occurrence of chipping at the corner portion 26 of the protective film 23 can be prevented.

  Returning to FIG. 55, the resin film 24 protects the electronic apparatus 1 together with the protective film 23, and is made of a resin such as polyimide. The thickness of the resin film 24 is about 5 μm. The resin film 24 covers the entire surface of the element covering portion 23A (the upper surface of the protective film 23) over the entire area, and the element forming surface 2A side in the side surface covering portions 23B on the four side surfaces 2C to 2F of the substrate 2. Is covered (the upper end in FIG. 55). That is, the resin film 24 exposes at least a portion of the side surface covering portion 23B on the four side surfaces 2C to 2F opposite to the element formation surface 2A (lower side in FIG. 55).

  In such a resin film 24, portions that coincide with the four side surfaces 2 </ b> C to 2 </ b> F in a plan view are arc-shaped projecting portions 24 </ b> A that project to the side (outside) of the side surface covering portions 23 </ b> B on these side surfaces. It has become. That is, the resin film 24 (the overhang portion 24A) protrudes beyond the side surface covering portion 23B (the protective film 23) at the side surfaces 2C to 2F. Such a resin film 24 has a round-shaped side surface 24B convex toward the side in the arc-shaped overhanging portion 24A. The overhanging portion 24A covers a corner portion 27 that forms a boundary between the element formation surface 2A and each of the side surfaces 2C to 2F. For this reason, when the electronic device 1 comes into contact with the surrounding object, the overhanging portion 24A first contacts the surrounding object to alleviate the impact caused by the contact. Chipping at the portion 27 can be prevented. In particular, since the overhanging portion 24A has the round-shaped side surface 24B, the impact caused by the contact can be smoothly reduced.

There may be a configuration in which the resin film 24 does not cover the side surface covering portion 23B at all (a configuration in which the entire side surface covering portion 23B is exposed).
In the resin film 24, one opening 25 is formed at two positions separated in a plan view. Each opening 25 is a through-hole that continuously penetrates the resin film 24 and the protective film 23 (element covering portion 23A) in each thickness direction. Therefore, the opening 25 is formed not only in the resin film 24 but also in the protective film 23. A part of the wiring film 22 is exposed from each opening 25. A portion of the wiring film 22 exposed from each opening 25 is a pad region 22A for external connection.

  Of the two openings 25, one opening 25 is filled with the first connection electrode 3, and the other opening 25 is filled with the second connection electrode 4. A part of each of the first connection electrode 3 and the second connection electrode 4 protrudes from the opening 25 on the surface of the resin film 24. The first connection electrode 3 is electrically connected to the wiring film 22 in the pad region 22 </ b> A in the opening 25 through the one opening 25. The second connection electrode 4 is electrically connected to the wiring film 22 in the pad region 22 </ b> A in the opening 25 through the other opening 25. Thereby, each of the first connection electrode 3 and the second connection electrode 4 is electrically connected to the element 5. Here, the wiring film 22 forms wiring connected to each of the group of resistors R (resistor 56), the first connection electrode 3, and the second connection electrode 4.

  Thus, the resin film 24 and the protective film 23 in which the opening 25 is formed are formed so as to expose the first connection electrode 3 and the second connection electrode 4 from the opening 25. Therefore, electrical connection between the electronic device 1 and the circuit board 9 can be achieved via the first connection electrode 3 and the second connection electrode 4 that protrude from the opening 25 on the surface of the resin film 24 (FIG. 47 (b)).

56A to 56F are schematic sectional views showing a method for manufacturing the electronic device shown in FIG.
First, as shown in FIG. 56A, a wafer 30 made of Si is prepared. The wafer 30 is a source of the substrate 2. Therefore, the front surface 30A of the wafer 30 is the element forming surface 2A of the substrate 2, and the back surface 30B of the wafer 30 is the back surface 2B of the substrate 2.

Then, the insulating film 20 made of SiO ₂ or the like is formed on the surface 30A of the wafer 30, and the element 5 (resistor R and wiring film 22) is formed on the insulating film 20. Specifically, first, a TiN or TiON resistor film 21 is formed on the entire surface of the insulating film 20 by sputtering, and an aluminum (Al) wiring film 22 is stacked on the resistor film 21. . Thereafter, the resistor film 21 and the wiring film 22 are selectively removed by, for example, dry etching using a photolithography process. As shown in FIG. A configuration is obtained in which the body membrane lines 21A are arranged in the column direction at regular intervals. At this time, a region in which the resistor film line 21A and the wiring film 22 are partially cut is also formed. Subsequently, the wiring film 22 stacked on the resistor film line 21A is selectively removed. As a result, the element 5 having a configuration in which the wiring film 22 is laminated on the resistor film line 21A with a predetermined interval R is obtained.

Referring to FIG. 56A, the elements 5 are formed at a number of locations on the surface 30 </ b> A of the wafer 30 according to the number of electronic devices 1 formed on one wafer 30.
Next, as illustrated in FIG. 56B, a resist pattern 41 is formed over the entire surface 30 </ b> A of the wafer 30 so as to cover all the elements 5 on the insulating film 20. An opening 42 is formed in the resist pattern 41.

  FIG. 57 is a schematic plan view of a part of a resist pattern used for forming a groove in the step of FIG. 56B. The openings 42 of the resist pattern 41 are regions between the outlines of adjacent electronic devices 1 in plan view (a hatched portion in FIG. 57) when a large number of electronic devices 1 are arranged in a matrix (also in a lattice shape). ). Therefore, the entire shape of the opening 42 is a lattice shape having a plurality of linear portions 42A and 42B orthogonal to each other. Further, any one of the straight portions 42A and 42B (here, the straight portion 42A) has a protruding portion that protrudes orthogonally from the straight portion 42A in accordance with the concave portion 10 (see FIG. 47A) of the electronic device 1. 42C is continuously provided.

  Here, in the electronic device 1, the corner portions 11 and 12 have a round shape (see FIG. 47A). Accordingly, the straight portions 42A and 42B that are orthogonal to each other in the opening 42 are connected while being curved. Further, the linear portion 42A and the protruding portion 42C which are orthogonal to each other are connected while being curved. For this reason, the intersecting portion 43A of the straight portions 42A and 42B and the intersecting portion 43B of the straight portions 42A and the protruding portion 42C have a round shape with rounded corners. Further, the corners of the protruding portion 42C other than the intersecting portion 43B are also rounded.

  Referring to FIG. 56B, each of insulating film 20 and wafer 30 is selectively removed by plasma etching using resist pattern 41 as a mask. Thereby, a groove 44 that penetrates the insulating film 20 and reaches the middle of the thickness of the wafer 30 is formed at a position that coincides with the opening 42 of the resist pattern 41 in plan view. The groove 44 has a side surface 44A that faces each other and a bottom surface 44B that connects a lower end of the facing side surface 44A (an end on the back surface 30B side of the wafer 30). The depth of the groove 44 with respect to the surface 30A of the wafer 30 is about 100 μm, and the width of the groove 44 (the interval between the opposing side surfaces 44A) is about 20 μm.

FIG. 58 (a) is a schematic plan view of the wafer after the grooves are formed in the step of FIG. 56B, and FIG. 58 (b) is a partially enlarged view of FIG. 58 (a).
Referring to FIG. 58B, the overall shape of the groove 44 is a lattice shape that coincides with the opening 42 (see FIG. 57) of the resist pattern 41 in plan view. On the surface 30A of the wafer 30, a rectangular frame portion in the groove 44 surrounds the area where each element 5 is formed. A portion where the element 5 is formed on the wafer 30 is a semi-finished product 50 of the electronic apparatus 1. On the surface 30A of the wafer 30, one semi-finished product 50 is located in a region surrounded by the grooves 44, and these semi-finished products 50 are arranged in a matrix.

  In addition, the groove 44 is formed so as to bite into the middle part of one side A of the semi-finished product 50 in a portion corresponding to the protruding portion 42C (see FIG. 57) in the opening 42 of the resist pattern 41. 50 is formed with the aforementioned recess 10 (see FIG. 47A). Then, according to the intersecting portions 43A and 43B (see FIG. 57) having a round shape in the opening 42 of the resist pattern 41, the corner portions 60 (the corner portions 11 and 12 of the electronic device 1) of the semi-finished product 50 can be seen. ) Is shaped into a round shape. Although this round shape is formed by using plasma etching, silicon etching (normal etching using a chemical solution) may be used instead of plasma etching.

  By etching the wafer 30 in this manner, the outer shape of the semi-finished product 50 (in other words, the final electronic device 1) can be arbitrarily set. As in this embodiment, the corner portion 60 (corner portions 11, 12). ) Has a round shape and can be an asymmetric rectangle having a recess 10 on one side A (see also FIG. 47A). In this case, the electronic device 1 capable of recognizing the chip direction can be manufactured without a marking process (a process of marking a mark or the like indicating the chip direction with a laser or the like).

  After the trench 44 is formed, the resist pattern 41 is removed, and a protective film (SiN) made of SiN is formed on the surface of the element 5 by a CVD (Chemical Vapor Deposition) method as shown in FIG. 56C. Film) 45 is formed. The SiN film 45 has a thickness of about 3000 mm. The SiN film 45 is formed so as to cover not only the entire surface of the element 5 but also the inner surface (side surface 44A and bottom surface 44B) of the groove 44. Since the SiN film 45 is a thin film formed on the side surface 44A and the bottom surface 44B with a substantially constant thickness, the groove 44 is not filled up. Further, since the SiN film 45 may be formed in the entire area of the side surface 44A in the groove 44, it may not be formed on the bottom surface 44B.

Next, as shown in FIG. 56D, a photosensitive resin sheet 46 made of polyimide is attached to the wafer 30 from above the SiN film 45 other than the grooves 44. FIGS. 59A and 59B are schematic perspective views showing a state in which a polyimide sheet is attached to a wafer in the step of FIG. 56D.
Specifically, as shown in FIG. 59A, after a polyimide sheet 46 is covered from the surface 30A side on the wafer 30 (strictly, the SiN film 45 on the wafer 30), FIG. The sheet 46 is pressed against the wafer 30 by the rotating roller 47 as shown in FIG.

  As shown in FIG. 56D, when the sheet 46 is affixed to the entire surface of the SiN film 45 other than the groove 44, a part of the sheet 46 slightly enters the groove 44 side, but on the side surface 44A of the groove 44. The sheet 46 does not reach the bottom surface 44B of the groove 44 only by covering a part of the SiN film 45 on the element 5 side (surface 30A side). Therefore, in the groove 44 between the sheet 46 and the bottom surface 44 </ b> B of the groove 44, a space S having almost the same size as the groove 44 is formed. At this time, the thickness of the sheet 46 is 10 μm to 30 μm.

Next, the sheet 46 is subjected to heat treatment. As a result, the thickness of the sheet 46 is thermally contracted to about 5 μm.
Next, as shown in FIG. 56E, the sheet 46 is patterned, and portions of the sheet 46 that coincide with the groove 44 and each pad region 22A of the wiring film 22 in a plan view are selectively removed. Specifically, the sheet 46 is exposed and developed in the pattern using a mask 62 in which openings 61 having a pattern that matches (matches) the groove 44 and each pad region 22A in plan view. As a result, the sheet 46 is separated above the groove 44 and each pad region 22A, and the edge portion separated in the sheet 46 slightly overlaps the groove 44 side and overlaps the SiN film 45 on the side surface 44A of the groove 44. Therefore, the above-described overhanging portion 24A (having the round-shaped side surface 24B) is naturally formed on the edge portion.

Next, by etching using the sheet 46 thus separated as a mask, portions of the SiN film 45 that correspond to the pad regions 22A in plan view are removed. Thereby, the opening 25 is formed. Here, the SiN film 45 is formed so as to expose each pad region 22A.
Next, a Ni / Pd / Au laminated film constituted by laminating Ni, Pd and Au is formed on the pad region 22A in each opening 25 by electroless plating. At this time, the Ni / Pd / Au laminated film protrudes from the opening 25 to the surface of the sheet 46. Thereby, the Ni / Pd / Au laminated film in each opening 25 becomes the first connection electrode 3 and the second connection electrode 4 shown in FIG. 56F.

  Next, after conducting an energization inspection between the first connection electrode 3 and the second connection electrode 4, the wafer 30 is ground from the back surface 30B. Here, since the entire portion of the portion forming the side surface 44A of the groove 44 in the wafer 30 is covered with the SiN film 45, it is possible to prevent the occurrence of microcracks or the like in the portion during grinding of the wafer 30, and temporarily Even if a microcrack occurs, the microcrack can be prevented from expanding by filling the microcrack with the SiN film 45.

  When the wafer 30 is thinned until it reaches the bottom surface 44B of the groove 44 (strictly speaking, the SiN film 45 on the bottom surface 44B) by grinding, there is no connection between the adjacent semi-finished products 50. The wafer 30 is divided at the boundary, and the semi-finished product 50 becomes the electronic device 1 and is separated individually. Thereby, the electronic device 1 (see FIG. 55) is completed. In each electronic device 1, the portion that formed the side surface 44 </ b> A of the groove 44 becomes one of the side surfaces 2 </ b> C to 2 </ b> F of the substrate 2. Then, the SiN film 45 becomes the protective film 23. Further, the separated sheet 46 becomes the resin film 24.

  Even if the chip size of the electronic device 1 is small, the electronic device 1 can be divided into pieces by grinding the wafer 30 from the back surface 30B after the grooves 44 are formed in this way. Therefore, as compared with the case where the electronic device 1 is divided into pieces by dicing the wafer 30 with a dicing saw as in the prior art, cost reduction and time reduction can be achieved and yield improvement can be achieved by omitting the dicing process.

According to the above, when manufacturing the electronic device 1, the groove 44 for dividing the electronic device 1 one by one is formed on the surface 30 </ b> A (element forming surface 2 </ b> A). If it forms in the boundary of the element 5 in 30A, the side surface 44A of the groove | channel 44 will become the side surfaces 2C-2F of each electronic device 1 after a division | segmentation.
Prior to the division into the electronic device 1, the SiN film 45 (protective film 23) is formed on the side surface 44 </ b> A of the groove 44 and the surface 30 </ b> A of the wafer 30. Here, as shown in FIG. 56C, a CVD protective film (CVD protective film) 23 having substantially the same thickness is continuously formed on the upper surface of the resistor R and the inner surface (side surface 44A and bottom surface 44B) of the resistor R by the CVD method. Formed. In this case, since the formation of the CVD protective film 23 (SiN film 45) is performed in a reduced pressure environment in the course of CVD, the CVD protective film 23 serves as the side surface covering portion 23B and the side surfaces 2C to 2F (grooves 44) of the substrate 2. Can be attached to the entire side surface 44A). Therefore, the protective film 23 can be uniformly formed on the side surface 44 </ b> A of the groove 44 when the electronic device 1 is manufactured.

  Then, after the formation of the protective film 23, as shown in FIG. 56D, the resin film 24 is formed by a sheet 46 that covers the SiN film 45 (the portion of the protective film 23 that becomes the element covering portion 23A) of the element forming surface 2A. Since the resin film 24 exposes at least the side opposite to the element formation surface 2A (the bottom surface 44B side of the groove 44) in the SiN film 45 on the side surface 44A of the groove 44 (the portion that becomes the side surface covering portion 23B of the protective film 23). It is possible to prevent the grooves 44 from being filled with the resin film 24 from the bottom surface 44B side when the resin film 24 is formed (when the electronic apparatus 1 is manufactured).

Specifically, the resin film 24 is formed by sticking a sheet 46 on the protective film 23. In this case, the groove 46 is not filled from the bottom surface 44B side by the sheet 46. Therefore, as shown in FIG. 56F, if the substrate 2 is thinned until it reaches the bottom surface 44B of the groove 44, the substrate 2 can be divided into the individual electronic devices 1 in the groove 44.
As mentioned above, although embodiment of 4th invention was described, 4th invention can also be implemented with another form.

  For example, when the wafer 30 is divided into individual electronic devices 1, the wafer 30 is ground from the back surface 30B side to the bottom surface 44B of the groove 44 (see FIG. 56F). Instead, the portion of the SiN film 45 that covers the bottom surface 44B and the portion of the wafer 30 that coincides with the groove 44 in plan view are selectively etched away from the back surface 30B, thereby removing the wafer 30 individually. The electronic device 1 may be divided.

60A is a plan view of an electronic device, FIG. 60B is a plan view of the electronic device according to the first modification, and FIG. 60C is a second modification. It is a top view of the electronic device which concerns. In each of FIGS. 60A to 60C, the element 5, the protective film 23, and the resin film 24 are not shown for convenience of explanation.
Moreover, the recessed part 10 mentioned above is provided in the position which shifted | deviated from the midpoint P of the one side A in the one side A of the electronic device 1, as shown to Fig.60 (a). When the recess 10 is displaced from the midpoint P, the center 10A of the recess 10 and the midpoint P do not coincide with each other in the direction in which the side A extends. According to this configuration, not only the recess 10 side in the direction (longitudinal direction) connecting the one side A and one side B opposite to the one side A, but also the recess in the extending direction (short direction) of the one side A. The 10 side can also be in the chip direction described above. For example, in a plan view viewed from the element forming surface 2A side, the short side direction of the electronic device 1 and the front-back direction (vertical direction in FIG. 60) are matched, and the long side direction of the electronic device 1 is matched with the left-right direction. When the concave portion 10 is located on the left front side (upper left side in FIG. 60), the electronic device 1 can be correctly mounted on the circuit board 9. Then, when mounting, the orientation of the electronic device 1 must be aligned so that the concave portion 10 is located on the left front side in plan view (when the electronic device 1 is viewed from the back surface 2B of the substrate 2, the right front side). This can be grasped from the appearance of the electronic device 1. That is, it can be understood from the appearance of the electronic device 1 that the orientation of the electronic device 1 in both the longitudinal direction and the short direction must be matched.

  Of course, as shown in FIG. 60 (b), the concave portion 10 may be provided at a position where one side A coincides with the midpoint P (a position where the center 10A of the concave portion 10 coincides with the midpoint P in the short direction). . Moreover, you may provide the convex part 51 which protrudes outward instead of the recessed part 10, as shown in FIG.60 (c). The convex portion 51 may have a rectangular shape in plan view, or may have a U shape (a shape that bulges into a U shape) or a triangular shape. Of course, in the side surface 2 </ b> C, the corner portion (four corner portions in a plan view including the tip side and the root side of the convex portion 51) 52 of the convex portion 51 is also chamfered, like the other corner portions 11. It has become. Here, the side surface covering portion 23 </ b> B (see FIG. 47A) covers the entire area including the portion where the convex portion 51 is formed on the side surface 2 </ b> C, as in the case of the concave portion 10. Moreover, it is preferable that the depth of the recessed part 10 and the height (projection amount) of the convex part 51 are 20 micrometers or less (about 1/5 or less of the width of the 1st connection electrode 3 or the 2nd connection electrode 4). And as for the chamfering amount in each of the corner part 11, the corner part 12, and the corner part 52, it is preferable that the distance of one side is about 20 micrometers or less.

FIG. 61A is a diagram illustrating a circuit configuration of an element according to another embodiment of the electronic device, and FIG. 61B is a diagram illustrating a circuit configuration of an element according to still another embodiment of the electronic device. It is.
In the embodiment described above, since the electronic device 1 is a chip resistor, the element 5 between the first connection electrode 3 and the second connection electrode 4 is the resistor 56, but the diode 55 shown in FIG. Alternatively, as shown in FIG. 61B, a diode 55 and a resistor 56 may be connected in series. The electronic device 1 becomes a chip diode by having the diode 55, and the first connection electrode 3 and the second connection electrode 4 have polarity, but the above-described chip direction is a direction corresponding to the polarity. Thereby, since the polarity of the 1st connection electrode 3 and the 2nd connection electrode 4 can be shown with a chip | tip direction, the said polarity can be grasped | ascertained by the external appearance of the electronic device 1. FIG. That is, it can be seen which side in the chip direction (that is, which of the first connection electrode 3 and the second connection electrode 4) is the positive or negative pole side. Therefore, the electronic device 1 can be correctly mounted on the circuit board 9 (see FIG. 47B) so that the side on which the concave portion 10 and the convex portion 51 (see FIG. 60) described above are provided on the corresponding pole side. Can be.

Of course, the fourth invention can be applied to an element device in which various elements such as a chip capacitor in which a capacitor is used in place of the diode 55 in the element 5 and a chip inductor are formed on the chip-sized substrate 2. .
<Fifth invention>
(1) Features of the fifth invention For example, the features of the fifth invention are the following D1 to D9.
(D1) a step of forming a resistor film on a substrate by sputtering of metal while supplying nitrogen and oxygen, a step of forming a wiring film on the resistor film, and the wiring film and the resistor film. A method of manufacturing a chip component, comprising: a step of patterning simultaneously; and a step of patterning only the wiring film.

According to this method, when the resistor film is formed on the substrate, the supplied nitrogen and oxygen are doped as impurities into the resistor film, so that the resistance value of the formed resistor film is set to a desired value ( Target value).
In addition, since the wiring film is laminated on the resistor film and the wiring film and the resistor film laminated on the resistor film are simultaneously patterned, the resistor film and the wiring film are patterned into the same shape, and then patterned. Since only the wiring film on the resistor film is selectively removed by patterning, it is possible to create a resistor network composed of a resistor film having a desired wiring form, and to make the resistor circuit network finer, and thus chip components. Can be achieved.
(D2) The method of manufacturing a chip component according to D1, wherein in the step of forming the resistor film, silicon is doped into the metal resistor film formed on the substrate by sputtering silicon simultaneously with the metal. .

According to this method, in the step of forming the resistor film, silicon is sputtered simultaneously with the metal, and nitrogen and oxygen are supplied together, so that the metal resistor film is doped with silicon atoms, nitrogen atoms and oxygen atoms. The Thereby, the resistance value of the resistor film can be set to a desired resistance value, and the temperature coefficient of resistance (TCR) can be adjusted to a desired value.
(D3) The method of manufacturing a chip component according to D1 or D2, wherein the step of forming the resistor film includes a step of adjusting a supply flow rate of nitrogen and a supply flow rate of oxygen.

According to this method, by adjusting the supply flow rate of nitrogen and the supply flow rate of oxygen, the amount of nitrogen atoms and oxygen atoms doped in the metal resistor film is adjusted, and the resistance value of the resistor film is, for example, Adjustment is possible in a wide range from 10Ω / □ to 1000Ω / □.
(D4) The step of simultaneously patterning the wiring film and the resistor film includes a plurality of types in which the wiring film electrically connects one or more of the external connection electrodes and the plurality of thin film resistors. A resistance unit body forming wiring film for forming the resistance unit body, a resistance unit body connecting wiring film for connecting the plurality of types of resistance unit bodies in a predetermined mode, and the plurality of types of resistance unit bodies as a resistance circuit. Patterning only to include a plurality of fuse films that can be electrically incorporated into a network or blown to be electrically separated from a resistor network, and patterning only the wiring film is patterned D. selectively removing the wiring film from the wiring film and the resistor film, and patterning so that the underlying resistor film appears as a plurality of thin film resistors, Method of manufacturing a chip component according to any one of to D3.

According to this method, the wiring film is laminated on the resistor film. By patterning the wiring film, the external connection electrode, the resistance unit body forming wiring film for forming the resistance unit body, and the resistance unit body connecting The wiring film and the fuse film can be simultaneously formed in the same layer, and the process can be simplified.
(D5) having a resistor film patterned on a substrate, a wiring film formed so as to partially overlap the resistor film, and a protective film formed on an upper surface of the wiring film; A chip component, wherein a resistor circuit is formed by a unit resistor by a body film and a wiring film.
(D6) The chip component according to D5, wherein the resistor film is made of TiON or TiSiON.
(D7) The chip component according to D5 or D6, wherein the resistor film and the wiring film are patterned together.
(D8) The wiring film formed so as to overlap with the resistance film includes a fuse film, and includes a chip resistor formed so that the fuse film can be blown. Chip parts.
(D9) The chip component according to any one of D5 to D8, wherein an upper surface of the protective film is covered with a resin film.

According to the configuration described in D5 to D9, it is possible to provide a chip component or chip resistor including a resistor circuit having a small and wear resistance value.
(2) Embodiment of Fifth Invention Hereinafter, an embodiment of the fifth invention will be described in detail with reference to the accompanying drawings. The reference numerals shown in FIGS. 62 to 76 are effective only in these drawings, and even if they are used in other embodiments, they do not indicate the same elements as those in the other embodiments.

FIG. 62 (A) is a schematic perspective view showing an external configuration of a chip resistor 10 according to one embodiment made by the manufacturing method of the fifth invention, and FIG. 62 (B) is a chip resistor 10. It is a side view which shows the state mounted on the board | substrate.
Referring to FIG. 62A, a chip resistor 10 according to an embodiment of the fifth invention includes a first connection electrode 12, a second connection electrode 13, and a resistor formed on a substrate 11 as a substrate. And a network 14. The substrate 11 has a substantially rectangular parallelepiped shape in plan view. For example, the length L in the long side direction is 0.3 mm, the width W in the short side direction is 0.15 mm, and the thickness T of the substrate 11 is about 0.1 mm. It is a very small chip.

As shown in FIG. 76, the chip resistor 10 is obtained by forming a large number of chip resistors 10 on a wafer in a lattice shape, and cutting the wafer into individual chip resistors 10. .
On the substrate 11, the first connection electrode 12 is a rectangular electrode that is provided along one short side 111 of the substrate 11 and is long in the direction of the short side 111. The second connection electrode 13 is a rectangular electrode that is provided along the other short side 112 on the substrate 11 and is long in the direction of the short side 112. The resistance network 14 is provided in a central region sandwiched between the first connection electrode 12 and the second connection electrode 13 on the substrate 11. One end side of the resistor network 14 is electrically connected to the first connection electrode 12, and the other end side of the resistor network 14 is electrically connected to the second connection electrode 13. The first connection electrode 12, the second connection electrode 13, and the resistance network 14 are provided on the substrate 11 by using, for example, a semiconductor manufacturing process, as will be described later. Therefore, a semiconductor substrate (semiconductor wafer) such as a silicon substrate (silicon wafer) can be used as the substrate 11. The substrate 11 may be another type of substrate such as an insulating substrate.

  The first connection electrode 12 and the second connection electrode 13 each function as an external connection electrode (external connection pad). In the state where the chip resistor 10 is mounted on the circuit board 15, as shown in FIG. ) And solder and are electrically and mechanically connected. The first connection electrode 12 and the second connection electrode 13 that function as external connection electrodes are made of gold (Au) or plated with gold in order to improve solder wettability and reliability. It is desirable.

FIG. 63 is a plan view of the chip resistor 10, and shows the arrangement relationship of the first connection electrode 12, the second connection electrode 13, and the resistor network 14 and the configuration of the resistor network 14 in plan view.
Referring to FIG. 63, the chip resistor 10 includes a first connection electrode 12 that is disposed along one short side 111 on the upper surface of the substrate and has a substantially rectangular shape in a plan view in the width direction, and the other short side 112 on the upper surface of the substrate. A second connection electrode 13 having a substantially rectangular shape in plan view that is long in the width direction, and a resistor network 14 provided in a rectangular region in plan view between the first connection electrode 12 and the second connection electrode 13; Is included.

  The resistor network 14 includes a plurality of resistors R having the same resistance value arranged in a matrix on the substrate (in the example of FIG. 63, eight resistors along the row direction (longitudinal direction of the substrate)). R is arranged, and 44 resistors are arranged along the column direction (substrate width direction), and a total of 352 resistor R configurations) are provided. One to 64 of these many resistors R are electrically connected to form a plurality of types of resistance unit bodies. The formed plural types of resistance unit bodies are connected in a predetermined manner with a wiring film for connection as a network connection means. Further, a plurality of fuse films F that can be blown in order to electrically incorporate the resistance unit into the resistance network 14 or to be electrically separated from the resistance network 14 are provided. The plurality of fuse films F are arranged along the inner side of the second connection electrode 13 so that the arrangement region is linear. More specifically, a plurality of fuse films F and connection wiring films C are arranged in a straight line.

64A is an enlarged plan view of a part of the resistor network 14 shown in FIG. 63, and FIGS. 64B and 64C are lengths drawn to explain the structure of the resistor R in the resistor network 14. FIG. It is a longitudinal sectional view in the direction and a longitudinal sectional view in the width direction.
The structure of the resistor R will be described with reference to FIGS. 64A, 64B, and 64C.
An insulating layer (SiO ₂ ) 19 is formed on the upper surface of the substrate 11 as a substrate, and a resistor film 20 constituting the resistor R is disposed on the insulating layer 19. The resistor film 20 is made of TiN or TiON. The resistor film 20 includes a plurality of resistor films (hereinafter referred to as “resistor film lines”) extending in a line between the first connection electrode 12 and the second connection electrode 13. The line 20 may be cut at a predetermined position in the line direction. An aluminum film as a wiring film 21 is laminated on the resistor film line 20. The wiring film 21 is laminated on the resistor film line 20 with a constant interval R in the line direction.

  FIG. 65 shows the electrical characteristics of the resistor film line 20 and the wiring film 21 of this configuration by circuit symbols. That is, as shown in FIG. 65A, the resistor film lines 20 in the region of the predetermined interval R each form a resistor R having a constant resistance value r. In the region where the wiring film 21 is laminated, the resistor film line 20 is short-circuited by the wiring film 21. Therefore, a resistance circuit is formed which is formed by connecting in series the resistor R of the resistor r shown in FIG.

Further, since the adjacent resistor film lines 20 are connected to each other by the resistor film 20 and the wiring film 21, the resistor network shown in FIG. 64A constitutes the resistor circuit shown in FIG.
Here, a manufacturing process of the resistor network 14 will be described.
(1) The surface of the substrate 11 is thermally oxidized to form a silicon dioxide (SiO ₂ ) layer as the insulating layer 19.
(2) A resistor film 20 of TiN, TiON, or TiSiON is formed on the entire surface of the insulating layer 19. (Step of forming a resistor film)
The step of forming the resistor film is performed by sputtering as schematically shown in FIG.

That is, as an example, as schematically shown in FIG. 66 (A), a substrate 11 having an insulating layer 19 formed in a high vacuum chamber and a metal (a titanium (Ti) plate 27 in this embodiment) as a target are arranged. Then, argon (Ar) gas is blown in, and at the same time, nitrogen (N ₂ ) and oxygen (O ₂ ) are supplied, and by applying a negative high voltage to the target 27, the argon gas is applied at a high voltage. Becomes a plasma state and is positively ionized, and argon ions collide with the target 27. Thereby, an element of the material, that is, titanium atom (Ti) jumps out from the target 27, and deposits on the insulating layer 19 to form the resistor film 20. At this time, nitrogen atoms (N) and oxygen atoms (O) are doped into the resistor film 20 by the supplied nitrogen and oxygen. The resistor film 20 is made of, for example, TiON.

In the step of forming the resistor film, as schematically shown in FIG. 66B, a titanium (Ti) plate 27 and a silicon (Si) plate 28 are disposed as targets, and the titanium plate 27 and the silicon plate It is good also as a structure by which argon ion collides with 28 and sputtering is performed. In this case, a mixed gas of O ₂ / N ₂ O and N ₂ / N ₂ O is supplied as nitrogen and oxygen. As a result, a TiSiON film is deposited on the insulating layer 19 as the resistor film 20.

In the step of forming the resistor film 20 shown in FIG. 66A, the resistance value of the resistor film 20 can be adjusted to a desired resistance value by adjusting the supply flow rates of nitrogen and oxygen.
In the resistor film formation step shown in FIG. 66B, the resistance value of the resistor film 20 can be adjusted to a desired resistance value by adjusting the supply amounts of nitrogen and oxygen, and resistance. The resistance temperature coefficient (TCR) of the body film 20 can also be adjusted to a target value.

Therefore, as shown in FIG. 66 (B), in sputtering performed while supplying nitrogen and oxygen, if silicon is sputtered simultaneously with sputtering of titanium, which is a metal, silicon and nitrogen are formed on the titanium resistor film. In addition, the resistor film 20 is doped, and both the resistance value and the resistance temperature coefficient (TCR) of the resistor film 20 are set to desired values, so that a highly accurate resistor film can be manufactured.
(3) Next, a step of forming the wiring film 21 on the resistor film 20 is performed. The step of forming the wiring film 21 is performed, for example, by sputtering aluminum (Al).
(4) Thereafter, using a photolithography process, the wiring film 21 and the resistor film 20 are selectively removed by dry etching, for example, and as shown in FIG. A configuration is obtained in which the lines 20 and the wiring films 21 are arranged in the column direction at regular intervals. At this time, a region in which the resistor film line 20 and the wiring film 21 are partially cut is also formed.
(5) Subsequently, the wiring film 21 laminated on the resistor film line 20 is selectively removed. As a result, a configuration in which the wiring film 21 is laminated on the resistor film line 20 with a constant interval R is obtained.
(6) Thereafter, a SiN film 22 as a protective film is deposited, and a polyimide layer 23 as a protective layer is further laminated thereon.

  In this embodiment, the resistor R included in the resistor network 14 formed on the substrate 11 is laminated on the resistor film line 20 and the resistor film line 20 with a certain interval in the line direction. The resistor film line 20 at a constant interval R including the wiring film 21 and not having the wiring film 21 laminated thereon constitutes one resistor R. The resistor film lines 20 constituting the resistor R are all equal in shape and size. Therefore, based on the characteristic that the same-shaped and large-sized resistor films formed on the substrate have substantially the same value, the multiple resistors R arranged in a matrix on the substrate 11 have the same resistance value. doing.

The wiring film 21 laminated on the resistor film line 20 forms a resistor R and also serves as a connecting wiring film for connecting a plurality of resistors R to form a resistance unit body. .
FIG. 67A is a partially enlarged plan view of a region including the fuse film F drawn by enlarging a part of the plan view of the chip resistor 10 shown in FIG. 63, and FIG. It is a figure which shows the cross-section which follows BB of A).

  As shown in FIGS. 67A and 67B, the fuse film F is also formed by the wiring film 21 laminated on the resistor film 20 forming the resistor R. That is, aluminum (Al), which is the same metal material as the wiring film 21, is formed in the same layer as the wiring film 21 stacked on the resistor film line 20 that forms the resistor R. As described above, the wiring film 21 is also used as a connection wiring film 21 for electrically connecting a plurality of resistors R in order to form a resistance unit body.

  That is, in the same layer laminated on the resistor film 20, a wiring film for forming the resistor R, a connecting wiring film for forming the resistance unit body, and a connecting wiring film for forming the resistor network 14 are used. , The fuse film, and the wiring film for connecting the resistor network 14 to the first connection electrode 12 and the second connection electrode 13 are made of the same manufacturing process (sputtering and photolithography) using the same metal material (for example, aluminum). Process). Thereby, the manufacturing process of the chip resistor 10 is simplified, and various wiring films can be simultaneously formed using a common mask. Furthermore, the alignment with the resistor film 20 is also improved.

FIG. 68 shows an arrangement relationship between the connection wiring film C and the fuse film F connecting the plurality of types of resistance unit bodies in the resistance network 14 shown in FIG. It is a figure which shows the connection relation with multiple types of resistance unit bodies diagrammatically.
Referring to FIG. 68, the first connection electrode 12 is connected to one end of a reference resistance unit R8 included in the resistance network 14. The reference resistance unit R8 is composed of eight resistors R connected in series, and the other end is connected to the fuse film F1. One end and the other end of a resistance unit body R64 composed of 64 resistors R connected in series are connected to the fuse film F1 and the connection wiring film C2. One end and the other end of a resistance unit body R32 formed of a series connection of 32 resistors R are connected to the connection wiring film C2 and the fuse film F4. One end and the other end of a resistance unit body R32 composed of a series connection of 32 resistors R are connected to the fuse film F4 and the connection wiring film C5. One end and the other end of a resistance unit body R16 formed of a series connection of 16 resistors R are connected to the connection wiring film C5 and the fuse film F6. One end and the other end of a resistance unit body R8 composed of eight resistors R connected in series are connected to the fuse film F7 and the connection wiring film C9. One end and the other end of a resistance unit body R4 composed of a series connection of four resistors R are connected to the connection wiring film C9 and the fuse film F10. One end and the other end of a resistance unit body R2 composed of a series connection of two resistors R are connected to the fuse film F11 and the connection wiring film C12. One end and the other end of a resistance unit body R1 including one resistor R are connected to the connection wiring film C12 and the fuse film F13. One end and the other end of a resistance unit body R / 2 composed of two resistors R connected in parallel are connected to the fuse film F13 and the connection wiring film C15. One end and the other end of a resistance unit body R / 4 formed of four resistors R connected in parallel are connected to the connection wiring film C15 and the fuse film F16. One end and the other end of a resistance unit body R / 8 formed by parallel connection of eight resistors R are connected to the fuse film F16 and the connection wiring film C18. One end and the other end of a resistance unit body R / 16 formed by parallel connection of 16 resistors R are connected to the connection wiring film C18 and the fuse film F19. The fuse film F19 and the connection wiring film C22 are connected to a resistance unit R / 32 composed of 32 resistors R connected in parallel.

  The plurality of fuse films F and the connection wiring film C are respectively a fuse film F1, a connection wiring film C2, a fuse film F3, a fuse film F4, a connection wiring film C5, a fuse film F6, a fuse film F7, and a connection wiring. Film C8, connecting wiring film C9, fuse film F10, fuse film F11, connecting wiring film C12, fuse film F13, fuse film F14, connecting wiring film C15, fuse film F16, fuse film F17, connecting wiring film C18 The fuse film F19, the fuse film F20, the connection wiring film C21, and the connection wiring film C22 are arranged in a straight line and connected in series. When each fuse film F is melted, the electrical connection with the connection wiring film C adjacent to the fuse film F is cut off.

  This configuration is shown in an electric circuit diagram as shown in FIG. In other words, in a state where all the fuse films F are not blown, the resistance network 14 has a reference resistance composed of eight resistors R provided in series between the first connection electrode 12 and the second connection electrode 13. A resistance circuit of the unit body R8 (resistance value 8r) is configured. For example, if the resistance value r of one resistor R is r = 80Ω, the chip resistor 10 to which the first connection electrode 12 and the second connection electrode 13 are connected is configured by a resistance circuit of 8r = 640Ω. ing.

  A plurality of types of resistance unit bodies other than the reference resistance unit body R8 are connected in parallel to the fuse film F, and the plurality of types of resistance unit bodies are short-circuited by each fuse film F. Yes. That is, 12 types of 13 resistance unit bodies R64 to R / 32 are connected in series to the reference resistance unit body R8, but each resistance unit body is short-circuited by the fuse film F connected in parallel. Therefore, when viewed electrically, each resistance unit is not incorporated in the resistance network 14.

  The chip resistor 10 according to this embodiment selectively melts the fuse film F with, for example, laser light according to a required resistance value. As a result, the resistance unit body in which the fuse films F connected in parallel are melted is incorporated in the resistance network 14. Therefore, the entire resistance value of the resistor network 14 can be a resistor network having a resistance value in which resistance unit bodies corresponding to the blown fuse film F are connected in series.

  In other words, the chip resistor 10 according to the present embodiment selectively blows a fuse film provided corresponding to a plurality of types of resistance unit bodies, so that a plurality of types of resistance unit bodies (for example, F1,. When F4 and F13 are fused, the resistance unit bodies R64, R32, and R1 can be incorporated into the resistor network. Since the resistance values of the plurality of types of resistance units are determined, respectively, the resistance value of the resistance network 14 is digitally adjusted, so that the chip resistor 10 having the required resistance value is obtained. be able to.

  In addition, the plurality of types of resistance unit bodies include one, two, four, eight, sixteen, thirty-two, and sixty-four resistors R having equal resistance values in series. A plurality of types of series resistance units connected by increasing the number of resistors R, and two, four, eight, sixteen, and thirty-two resistors R having the same resistance value in parallel, a geometric sequence A plurality of types of parallel resistance units connected to each other by increasing the number of resistors R are provided, and these units are connected in series in a state of being short-circuited by the fuse film F, so the fuse film F is selected. By fusing, the resistance value of the entire resistor network 14 can be set to an arbitrary resistance value within a wide range from a small resistance value to a large resistance value.

  FIG. 70 is a plan view of a chip resistor 30 according to another embodiment, in which the arrangement relationship of the first connection electrode 12, the second connection electrode 13, and the resistor network 4 and the configuration of the resistor network 14 in plan view are shown. It is shown. The difference between the chip resistor 30 and the chip resistor 10 described above is the connection mode of the resistor R in the resistor network 14. That is, the resistor network 14 of the chip resistor 30 has a large number of resistors R having equal resistance values arranged in a matrix on the substrate (in the configuration of FIG. 70, in the row direction (longitudinal direction of the substrate)). 8 resistors R are arrayed along with 44 resistors along the column direction (substrate width direction), and a total of 352 resistor R configurations). One to 128 of these many resistors R are electrically connected to form a plurality of types of resistance unit bodies. The formed plural types of resistance unit bodies are connected in parallel by a wiring film as a network connection means and a fuse film F. The plurality of fuse films F are arranged along the inner side of the second connection electrode 13 so that the arrangement region is linear, and when the fuse film F is blown, the resistance unit body connected to the fuse film Is electrically separated from the resistor network 14.

Note that the structure of the multiple resistors R constituting the resistor network 14, the structure of the connection wiring film, and the fuse film F are the same as the structures of the corresponding parts in the chip resistor 10 described above. The description here will be omitted.
71 shows a connection mode of a plurality of types of resistance unit bodies in the resistance network shown in FIG. 70, an arrangement relationship of fuse films F connecting them, and a connection relationship of a plurality of types of resistance unit bodies connected to the fuse film F. FIG.

  Referring to FIG. 71, one end of a reference resistance unit R / 16 included in the resistance network 14 is connected to the first connection electrode 12. The reference resistance unit R / 16 is composed of 16 resistors R connected in parallel, and the other end is connected to the connection wiring film C to which the remaining resistor units are connected. One end and the other end of a resistance unit body R128 comprising 128 resistors R connected in series are connected to the fuse film F1 and the connection wiring film C. One end and the other end of a resistance unit body R64 composed of 64 resistors R connected in series are connected to the fuse film F5 and the connection wiring film C. One end and the other end of a resistance unit body R32 formed of a series connection of 32 resistors R are connected to the fuse film F6 and the connection wiring film C. One end and the other end of a resistance unit body R16 composed of 16 resistors R connected in series are connected to the fuse film F7 and the connection wiring film C. One end and the other end of a resistance unit body R8 composed of eight resistors R connected in series are connected to the fuse film F8 and the connection wiring film C. One end and the other end of a resistance unit body R4 formed of a series connection of four resistors R are connected to the fuse film F9 and the connection wiring film C. One end and the other end of a resistance unit body R2 formed by connecting two resistors R in series are connected to the fuse film F10 and the connection wiring film C. One end and the other end of a resistance unit body R1 composed of a series connection of one resistor R are connected to the fuse film F11 and the connection wiring film C. One end and the other end of a resistance unit body R / 2 composed of two resistors R connected in parallel are connected to the fuse film F12 and the connection wiring film C. One end and the other end of a resistance unit body R / 4 composed of four resistors R connected in parallel are connected to the fuse film F13 and the connection wiring film C. The fuse films F14, F15, and F16 are electrically connected, and the fuse films F14, F15, and F16 and the connection wiring film C are connected to a resistance unit R / R composed of eight resistors R connected in parallel. One end and the other end of 8 are connected. The fuse films F17, F18, F19, F20, and F21 are electrically connected, and the fuse films F17 to F21 and the connection wiring film C have a resistance unit body formed of 16 resistors R connected in parallel. One end and the other end of R / 16 are connected.

The fuse film F includes 21 fuse films F <b> 1 to F <b> 21, all of which are connected to the second connection electrode 13.
With this configuration, when one of the fuse films F to which one end of the resistance unit body is connected is melted, the resistance unit body having one end connected to the fuse film F is electrically connected from the resistance network 14. Disconnected.

  The configuration of FIG. 71, that is, the configuration of the resistor network 14 provided in the chip resistor 30 is shown in an electric circuit diagram as shown in FIG. In a state in which all the fuse films F are not blown, the resistance network 14 includes a reference resistance unit body R8, 12 types of resistance unit bodies R / 16, between the first connection electrode 12 and the second connection electrode 13. A series connection circuit is formed with a parallel connection circuit of R / 8, R / 4, R / 2, R1, R2, R4, R8, R16, R32, R64, and R128.

  A fuse film F is connected in series to each of 12 types of resistance unit bodies other than the reference resistance unit body R / 16. Therefore, in the chip resistor 30 having the resistance network 14, if the fuse film F is selectively blown by, for example, laser light according to a required resistance value, a resistance corresponding to the blown fuse film F is obtained. The unit body (resistance unit body in which the fuse film F is connected in series) is electrically separated from the resistance network 14, and the resistance value of the chip resistor 10 can be adjusted.

  In other words, the chip resistor 30 according to this embodiment also removes a plurality of types of resistance unit bodies from the resistor network by selectively fusing fuse films provided corresponding to the plurality of types of resistance unit bodies. It can be electrically separated. Since the resistance value of each of the plurality of types of resistance units is determined, the resistance value of the resistance network 14 is digitally adjusted so that the chip resistor 30 having the required resistance value is obtained. be able to.

  Further, the plurality of types of resistance unit bodies include one, two, four, eight, sixteen, thirty-two, sixty-four, and 128 resistors R having the same resistance value in series. A plurality of types of series resistor units connected by increasing the number of resistors R as well as two, four, eight, and sixteen resistors R having the same resistance value in parallel, in a geometric sequence. Since a plurality of types of parallel resistance unit bodies connected by increasing the number of resistors R are provided, by selectively fusing the fuse film F, the resistance value of the entire resistor network 14 can be made fine and Digitally, any resistance value can be set.

In the electric circuit shown in FIG. 72, among the reference resistance unit R / 16 and the resistance unit bodies connected in parallel, the resistance unit body having a small resistance value tends to flow an overcurrent, and the resistance setting is performed. Sometimes, it is necessary to design a large rated current that can flow through the resistor.
Therefore, in order to disperse the current, the connection structure of the resistor network may be changed so that the electric circuit shown in FIG. 72 has the electric circuit configuration shown in FIG. That is, the resistance unit bodies connected in parallel without the reference resistance unit R / 16 include a configuration 140 in which a minimum resistance value is r and a plurality of resistance unit bodies R1 having a resistance value r are connected in parallel. It turns into a circuit. FIG. 73B is an electric circuit diagram showing a specific resistance value, and is a circuit including a configuration 140 in which a plurality of series connections of 80Ω resistance units and fuse films F are connected in parallel. . Thereby, distribution of the flowing current can be achieved.

  FIG. 74 is an electric circuit diagram showing the circuit configuration of the resistor network 14 provided in the chip resistor according to still another embodiment. A characteristic of the resistance network 14 shown in FIG. 74 is that the circuit configuration is such that a series connection of a plurality of types of resistance unit bodies and a parallel connection of a plurality of types of resistance unit bodies are connected in series. As in the previous embodiment, the plurality of types of resistance unit bodies connected in series are connected to the fuse film F in parallel for each resistance unit body, and the plurality of types of resistance unit bodies connected in series are: All are short-circuited by the fuse film F. Therefore, when the fuse film F is blown, the resistance unit body short-circuited by the fuse film F is electrically incorporated into the resistance network 14.

On the other hand, a fuse film F is connected in series to each of a plurality of types of resistance unit bodies connected in parallel. Therefore, by fusing the fuse film F, the resistance unit bodies to which the fuse film F is connected in series can be electrically disconnected from the parallel connection of the resistance unit bodies.
With this configuration, for example, a small resistance of 1 kΩ or less can be made on the parallel connection side, and a resistance circuit of 1 kΩ or more can be made on the series connection side. Therefore, a wide range of resistance circuits from a small resistance of several Ω to a large resistance of several MΩ can be made using the resistance network 14 configured with the same basic design.

When setting the resistance value with higher accuracy, if the fuse film of the resistance circuit on the series connection side that is close to the required resistance value is cut in advance, fine adjustment of the resistance value can be performed on the fuse film of the resistance circuit on the parallel connection side. This can be performed by fusing, and the accuracy of fitting to a desired resistance value is improved.
FIG. 75 is an electric circuit diagram showing a specific configuration example of the resistance network 14 in the chip resistor having a resistance value of 10Ω to 1MΩ.

75 also includes a series connection of a plurality of types of resistance unit bodies short-circuited by the fuse film F and a series connection of a plurality of types of resistance unit bodies to which the fuse film F is connected in series. The circuit configuration is as described above.
According to the resistance circuit of FIG. 75, an arbitrary resistance value of 10 to 1 kΩ can be set within an accuracy of 1% on the parallel connection side. In addition, an arbitrary resistance value of 1 k to 1 MΩ can be set within an accuracy of 1% in the series connection side circuit. When using a circuit on the serial connection side, it is possible to set the resistance value with higher accuracy by fusing the fuse film F of the resistance unit body close to the desired resistance value in advance and adjusting it to the desired resistance value. There are advantages.

In the above description, the chip resistor manufactured by the manufacturing method of the fifth invention has been described in detail. However, the manufacturing method of the fifth invention is not limited to the chip resistor, but can be applied to other chip components as discrete components, and composite devices including resistors and electronic devices including resistors.
<Sixth Invention>
(1) Features of the sixth invention For example, the features of the sixth invention are the following E1 to E10.
(E1) a substrate having an element formation surface and a side surface; an element formed on the element formation surface of the substrate; an element covering portion covering the element; and a protective film having a side surface covering portion covering the side surface of the substrate; An electronic apparatus comprising: a resin film that covers the element covering portion in a state where the entire side surface covering portion of the protective film or a part of the side surface covering portion opposite to the element forming surface is exposed.

According to this configuration, when manufacturing an electronic device, in a wafer having a plurality of elements formed on the element formation surface, grooves for dividing the electronic device one by one are formed at the element boundaries on the element formation surface. The side surface of the groove becomes the side surface of each divided electronic device. Prior to division into electronic devices, a protective film is formed on the side surface of the groove and the element formation surface, and then a resin film that covers the protective film on the element formation surface (the portion that becomes the element covering portion) is formed. The resin film exposes at least the side opposite to the element forming surface (bottom surface side of the groove) in the protective film on the side surface of the groove (the portion that becomes the side surface covering portion). It is possible to prevent the groove from being buried from the bottom side by the resin film.
(E2) The electronic device according to E1, wherein the resin film has a protruding portion that protrudes laterally from the side surface covering portion of the protective film.

According to this configuration, when the electronic device comes into contact with the surrounding object, the overhanging portion first comes into contact with the surrounding object to alleviate the impact caused by the contact, so that the impact can be prevented from reaching the element or the like. .
(E3) The electronic apparatus according to E1 or E2, wherein the resin film has a round-shaped side surface that protrudes sideways.
According to this structure, the overhang | projection part can relieve | moderate the impact by contact smoothly.
(E4) The corner portion on the side surface of the substrate has a round shape, and the round shape is formed by using plasma etching or silicon etching, according to any one of E1 to E3. Electronic equipment.

According to this structure, generation | occurrence | production of the chipping (chip) in a corner part can be prevented.
(E5) The electronic device according to any one of E1 to E4, wherein the element includes a resistance circuit including a unit resistor.
(E6) E1 including a wiring film formed on the element formation surface and connected to the element, and an external connection electrode connected to the wiring film through a through-hole penetrating the resin film and the protective film. Electronic device as described in any one of -E5.
(E7) The electronic device according to any one of E1 to E6, wherein the resin film is made of a photosensitive resin sheet.
(E8) An element forming step of forming an element on the element forming surface of the substrate, a step of forming a groove around a region where the element is formed, and a protective film covering the surface of the element and the inner surface of the groove A step of attaching a resin sheet from above the protective film, forming a space in the groove between the resin sheet and the bottom surface of the groove, and separating the resin sheet above the groove The step of patterning the resin sheet, and dividing the substrate in the groove by thinning the substrate from the surface opposite to the element formation surface until reaching the bottom surface of the groove The manufacturing method of an electronic device including the process to do.

If a resin sheet is stuck on the protective film as in this method, the groove will not be buried from the bottom side. Therefore, if the substrate is thinned until it reaches the bottom surface of the groove, the substrate can be divided into individual electronic devices in the groove.
(E9) The electron according to E8, wherein the resin sheet is a photosensitive resin sheet, and the step of patterning the resin sheet includes a step of exposing and developing the photosensitive resin sheet in a pattern that matches the groove. Device manufacturing method.

According to this method, the above-described protruding portion can be formed at the edge portion separated in the resin sheet after development.
(E10) The method for manufacturing an electronic device according to E8 or E9, wherein the step of dividing the substrate includes a step of selectively etching a portion of the protective film covering a bottom surface of the groove.
(2) Embodiment of Sixth Invention Hereinafter, an embodiment of the sixth invention will be described in detail with reference to the accompanying drawings. The reference numerals shown in FIGS. 77 to 91 are valid only in these drawings, and even when used in other embodiments, they do not indicate the same elements as those in the other embodiments.

FIG. 77 (a) is a schematic perspective view for explaining the configuration of an electronic device according to one embodiment of the sixth invention, and FIG. 77 (b) is a state where the electronic device is mounted on a circuit board. It is a typical side view which shows.
This electronic device 1 is a minute chip part and has a rectangular parallelepiped shape as shown in FIG. 77 (a). Regarding the dimensions of the electronic device 1, the length L in the long side direction is about 0.3 mm, the width W in the short side direction is about 0.15 mm, and the thickness T is about 0.1 mm.

This electronic device 1 is obtained by forming a large number of electronic devices 1 in a lattice shape on a wafer (silicon wafer) and then cutting the wafer into individual electronic devices 1.
The electronic device 1 mainly includes a substrate 2, a first connection electrode 3 and a second connection electrode 4 that are external connection electrodes, and an element 5. The first connection electrode 3, the second connection electrode 4, and the element 5 are formed on the substrate 2 using a semiconductor manufacturing process. Accordingly, a semiconductor substrate (semiconductor wafer) such as a silicon substrate (silicon wafer) can be used as the substrate 2. The substrate 2 may be another type of substrate such as an insulating substrate.

  The substrate 2 has a substantially rectangular parallelepiped chip shape. In the substrate 2, the upper surface in FIG. 77A is the element formation surface 2A. The element formation surface 2A is the surface of the substrate 2 and has a substantially rectangular shape. The surface opposite to the element formation surface 2A in the thickness direction of the substrate 2 is a back surface 2B. The element formation surface 2A and the back surface 2B have substantially the same shape. In addition to the element formation surface 2A and the back surface 2B, the substrate 2 has a side surface 2C, a side surface 2D, a side surface 2E, and a side surface 2F that extend perpendicular to these surfaces.

  The side surface 2C extends between one end edge in the longitudinal direction of the element forming surface 2A and the back surface 2B (the left front edge in FIG. 77A), and the side surface 2D is the longitudinal length of the element forming surface 2A and the back surface 2B. It is constructed between the other ends in the direction (the edge on the right back side in FIG. 77A). The side surface 2C and the side surface 2D are both end surfaces of the substrate 2 in the longitudinal direction. The side surface 2E is constructed between one end edge in the short direction of the element formation surface 2A and the back surface 2B (the left edge on the left side in FIG. 77A), and the side surface 2F is composed of the element formation surface 2A and the back surface 2B. Between the other ends in the short direction (the end on the right front side in FIG. 77 (a)). The side surface 2E and the side surface 2F are both end surfaces of the substrate 2 in the lateral direction.

  In the substrate 2, the element formation surface 2 </ b> A, the side surface 2 </ b> C, the side surface 2 </ b> D, the side surface 2 </ b> E, and the side surface 2 </ b> F are covered with the protective film 23. Therefore, strictly speaking, in FIG. 77A, the element formation surface 2A, the side surface 2C, the side surface 2D, the side surface 2E, and the side surface 2F are located on the inner side (back side) of the protective film 23 and are exposed to the outside. Absent. Further, the protective film 23 on the element formation surface 2 </ b> A is covered with a resin film 24. The resin film 24 protrudes from the element formation surface 2A to the end portion on the element formation surface 2A side (the upper end portion in FIG. 77A) of each of the side surface 2C, the side surface 2D, the side surface 2E, and the side surface 2F. The protective film 23 and the resin film 24 will be described in detail later.

  In the substrate 2, the substrate 2 is placed on a portion corresponding to one side A (the side surface 2C, 2D, 2E, or 2F of the substantially rectangular element forming surface 2A, here, the side surface 2C as described later). A recess 10 is formed that is notched in the thickness direction. The side A is also one side of the electronic device 1 in plan view. The recess 10 in FIG. 77 (a) is formed on the side surface 2C, and is recessed toward the side surface 2D while extending in the thickness direction of the substrate 2. The recess 10 penetrates the substrate 2 in the thickness direction, and the end of the recess 10 in the thickness direction is exposed from each of the element formation surface 2A and the back surface 2B. The recess 10 is smaller than the side surface 2C in the direction in which the side surface 2C extends (the short direction described above). The shape of the recess 10 in a plan view when the substrate 2 is viewed from the thickness direction (also the thickness direction of the electronic device 1) is a rectangular shape (rectangular shape) that is long in the short direction. The shape of the recess 10 in plan view may be a trapezoidal shape that becomes narrower in the direction in which the recess 10 is recessed (side 2D side), or a triangular shape that becomes narrower in the direction of recess. Alternatively, it may be U-shaped (a shape recessed in a U-shape). In any case, the concave portion 10 having such a simple shape can be easily formed. Moreover, although the recessed part 10 is formed in the side surface 2C here, you may form in at least one of the side surfaces 2C-2F instead of the side surface 2C.

  The concave portion 10 represents the direction (chip direction) of the electronic device 1 when the electronic device 1 is mounted on the circuit board 9 (see FIG. 77B). Since the outline of the electronic device 1 (strictly speaking, the substrate 2) in plan view is a rectangle having a recess 10 on one side A thereof, the outline has an asymmetric outer shape in the longitudinal direction. That is, the asymmetric outer shape has the recess 10 representing the chip direction on any one of the side surfaces 2C, 2D, 2E, and 2F (one side A). It represents that the concave side in the longitudinal direction is the chip direction. Thus, the chip direction of the electronic device 1 can be recognized only by making the outer shape of the substrate 2 in the electronic device 1 asymmetric in a plan view. That is, the chip direction can be recognized from the outer shape of the electronic device 1 without a marking process. In particular, since the asymmetric outer shape of the electronic device 1 is a rectangle having a concave portion 10 representing the chip direction on one side A, the electronic device 1 has a concave portion 10 side in the longitudinal direction connecting the one side A and the opposite side B. It can be in the chip direction. Therefore, for example, when the longitudinal direction of the electronic device 1 is aligned with the left-right direction in plan view, the electronic device 1 can be correctly mounted on the circuit board 9 when the side A is located at the left end. When mounting, it is possible to grasp from the appearance of the electronic device 1 by the recess 10 that the electronic device 1 must be oriented so that the side A is positioned at the left end in plan view.

  In the rectangular parallelepiped substrate 2, the corner portion 11 (the portion where the adjacent ones intersect) adjacent to each other on the side surface 2C, the side surface 2D, the side surface 2E, and the side surface 2F has a chamfered round shape. It is shaped (rounded). Further, in the substrate 2, a corner portion 12 (a corner portion in the concave portion 10 in the side surface 2 </ b> C) that forms a boundary between the concave portion 10 and the side surface 2 </ b> C around the concave portion 10 is also shaped into a chamfered round shape. Here, the corner portion 12 exists not only at the boundary between the concave portion 10 and the surrounding side surface 2C (portion other than the concave portion 10) but also at the deepest portion side of the concave portion 10, and is present at four locations in plan view.

Thus, in the outline of the board | substrate 2 in planar view, all the bent parts (corner parts 11 and 12) are round shape. Therefore, the occurrence of chipping can be prevented at the corner portions 11 and 12 in the round shape. Thereby, in the manufacture of the electronic apparatus 1, it is possible to improve the yield (improvement of productivity).
The first connection electrode 3 and the second connection electrode 4 are formed on the element formation surface 2 </ b> A of the substrate 2 and are partially exposed from the resin film 24. Each of the first connection electrode 3 and the second connection electrode 4 is configured, for example, by stacking Ni (nickel), Pd (palladium), and Au (gold) on the element formation surface 2A in this order. The first connection electrode 3 and the second connection electrode 4 are arranged at intervals in the longitudinal direction of the element formation surface 2A, and are long in the short direction of the element formation surface 2A. In FIG. 77A, on the element formation surface 2A, the first connection electrode 3 is provided near the side surface 2C, and the second connection electrode 4 is provided near the side surface 2D. The concave portion 10 of the side surface 2 </ b> C described above is recessed at a depth that does not interfere with the first connection electrode 3. However, in some cases, the first connection electrode 3 may be provided with a recess (becomes a part of the recess 10) according to the recess 10.

  The element 5 is a circuit element, and is formed in a region between the first connection electrode 3 and the second connection electrode 4 on the element formation surface 2A of the substrate 2, and from above by the protective film 23 and the resin film 24. It is covered. The element 5 of this embodiment is a circuit network in which a plurality of thin film resistors (thin film resistors) R made of TiN (titanium nitride) or TiON (titanium oxynitride) are arranged in a matrix on the element formation surface 2A. A configured resistor 56. The element 5 is connected to a wiring film 22 which will be described later, and is connected to the first connection electrode 3 and the second connection electrode 4 via the wiring film 22. Thereby, in the electronic device 1, a resistance circuit including the element 5 is formed between the first connection electrode 3 and the second connection electrode 4. Therefore, the electronic device 1 in this embodiment is a chip resistor.

  As shown in FIG. 77 (b), the first connection electrode 3 and the second connection electrode 4 are opposed to the circuit board 9, and electrical and mechanical with respect to a circuit (not shown) of the circuit board 9 by the solder 13. Thus, the electronic device 1 can be flip-chip connected to the circuit board 9. The first connection electrode 3 and the second connection electrode 4 that function as external connection electrodes are formed of gold (Au) or are plated with gold in order to improve solder wettability and reliability. It is desirable.

FIG. 78 is a plan view of the electronic apparatus, and is a diagram illustrating a positional relationship between the first connection electrode, the second connection electrode, and the element, and a configuration in plan view of the element.
Referring to FIG. 78, as an example, element 5 that is a resistor network includes eight resistors R arranged in the row direction (longitudinal direction of substrate 2) and the column direction (of substrate 2). It has a total of 352 resistors R composed of 44 resistors R arranged along the width direction. Each resistor R has an equal resistance value.

  A plurality of types of resistance unit bodies (unit resistances) are formed by grouping and electrically connecting a large number of these resistor bodies R every predetermined number of 1 to 64 pieces. The formed plural types of resistance unit bodies are connected in a predetermined manner via the connecting conductor film C. In addition, a plurality of fuse films F that can be blown on the element forming surface 2A of the substrate 2 in order to electrically incorporate the resistance unit into the element 5 or to electrically separate it from the element 5 are provided. Is provided. The plurality of fuse films F and connection conductor films C are arranged along the inner side of the second connection electrode 4 so that the arrangement region is linear. More specifically, a plurality of fuse films F and connecting conductor films C are arranged in a straight line.

79A is a plan view illustrating a part of the element shown in FIG. 78 in an enlarged manner. FIG. 79B is a longitudinal cross-sectional view in the length direction along BB of FIG. 79A drawn to explain the configuration of the resistor in the element. FIG. 79C is a longitudinal cross-sectional view in the width direction along CC of FIG. 79A drawn to explain the configuration of the resistor in the element.
The configuration of the resistor R will be described with reference to FIGS. 79A, 79B, and 79C.

The electronic device 1 further includes an insulating film 20 and a resistor film 21 in addition to the wiring film 22, the protective film 23, and the resin film 24 described above (see FIGS. 79B and 79C). The insulating film 20, the resistor film 21, the wiring film 22, the protective film 23, and the resin film 24 are formed on the substrate 2 (element formation surface 2A).
The insulating film 20 is made of SiO ₂ (silicon oxide). The insulating film 20 covers the entire area of the element formation surface 2A of the substrate 2. The insulating film 20 has a thickness of about 10,000 mm.

  The resistor film 21 constitutes the resistor R. The resistor film 21 is made of TiN or TiON, and is laminated on the surface of the insulating film 20. The thickness of the resistor film 21 is about 2000 mm. The resistor film 21 forms a plurality of lines (hereinafter referred to as “resistor film line 21 </ b> A”) extending in a line between the first connection electrode 3 and the second connection electrode 4. 21A may be cut at a predetermined position in the line direction (see FIG. 79A).

A wiring film 22 is laminated on the resistor film line 21A. The wiring film 22 is made of Al (aluminum) or an alloy of aluminum and Cu (copper) (AlCu alloy). The thickness of the wiring film 22 is about 8000 mm. The wiring film 22 is laminated on the resistor film line 21A with a constant interval R in the line direction.
The electrical characteristics of the resistor film line 21A and the wiring film 22 having this configuration are shown by circuit symbols as shown in FIG. That is, as shown in FIG. 80A, each of the resistor film lines 21A in the region of the predetermined interval R forms one resistor R having a constant resistance value r.

In the region where the wiring film 22 is laminated, the resistor film lines 21 </ b> A are short-circuited by the wiring film 22 by electrically connecting the resistors R adjacent to each other. Therefore, a resistance circuit is formed which is formed by connecting in series the resistor R of the resistor r shown in FIG.
Further, since the adjacent resistor film lines 21A are connected by the resistor film 21 and the wiring film 22, the resistor network of the element 5 shown in FIG. 79A is shown in FIG. A resistor circuit (consisting of R unit resistors) is formed.

Here, based on the characteristic that the same-shaped and large-sized resistor films 21 formed on the substrate 2 have substantially the same value, a large number of resistors R arranged in a matrix on the substrate 2 have the same resistance. Has a value.
Further, the wiring film 22 laminated on the resistor film line 21A forms a resistor R and also serves as a connecting wiring film for connecting a plurality of resistors R to form a resistance unit body. Plays.

81A is a partially enlarged plan view of a region including a fuse film drawn by enlarging a part of the plan view of the electronic device shown in FIG. 78, and FIG. 81B is a plan view of FIG. It is a figure which shows the cross-sectional structure which follows BB.
As shown in FIGS. 81A and 81B, the above-described fuse film F and connecting conductor film C are also formed by the wiring film 22 laminated on the resistor film 21 forming the resistor R. . That is, on the same layer as the wiring film 22 laminated on the resistor film line 21A forming the resistor R, the fuse film F and the connecting conductor film C are formed of Al or AlCu alloy which is the same metal material as the wiring film 22. Is formed.

  That is, in the same layer laminated on the resistor film 21, the wiring film for forming the resistor R, the fuse film F, the connecting conductor film C, and the element 5 are connected to the first connection electrode 3. A wiring film for connecting to the second connection electrode 4 is formed as the wiring film 22 by using the same metal material (Al or AlCu alloy) by the same manufacturing process (a sputtering and a photolithography process described later). Yes.

The fuse film F is not only a part of the wiring film 22 but also a group (fuse element) of a part of the resistor R (resistor film 21) and a part of the wiring film 22 on the resistor film 21. You may point.
The fuse film F has been described only in the case where the same layer as the connecting conductor film C is used. However, the connecting conductor film C is formed by stacking another conductor film on the conductor film C. The resistance value may be lowered. Even in this case, if the conductor film is not laminated on the fuse film F, the fusing property of the fuse film F does not deteriorate.

FIG. 82 is an electric circuit diagram of an element according to the embodiment of the sixth invention.
Referring to FIG. 82, element 5 includes reference resistance unit R8, resistance unit R64, two resistance units R32, resistance unit R16, resistance unit R8, resistance unit R4, resistance unit R2, The resistance unit body R1, the resistance unit body R / 2, the resistance unit body R / 4, the resistance unit body R / 8, the resistance unit body R / 16, and the resistance unit body R / 32 are arranged in this order from the first connection electrode 3. It is configured by connecting in series. Each of the reference resistance unit R8 and the resistance unit bodies R64 to R2 is configured by connecting in series the same number of resistors R as the last number (“64” in the case of R64). The resistance unit R1 is composed of one resistor R. Each of the resistance unit bodies R / 2 to R / 32 is configured by connecting in parallel the same number of resistor bodies R as the last number of itself (“32” in the case of R / 32). The meaning of the number at the end of the resistance unit body is the same in FIGS. 83 and 84 described later.

One fuse film F is connected in parallel to each of the resistance unit bodies R64 to R / 32 other than the reference resistance unit body R8. The fuse films F are connected in series either directly or via a connecting conductor film C (see FIG. 81A).
As shown in FIG. 82, in the state where all the fuse films F are not blown, the element 5 is composed of eight resistors R provided in series between the first connection electrode 3 and the second connection electrode 4. A resistance circuit of the reference resistance unit R8 (resistance value 8r) is configured. For example, if the resistance value r of one resistor R is r = 80Ω, a chip resistor (electronic device 1) in which the first connection electrode 3 and the second connection electrode 4 are connected by a resistance circuit of 8r = 64Ω. Is configured.

  Further, in a state where all the fuse films F are not blown, a plurality of types of resistance unit bodies other than the reference resistance unit body R8 are short-circuited. That is, 12 types of 13 resistance unit bodies R64 to R / 32 are connected in series to the reference resistance unit body R8, but each resistance unit body is short-circuited by the fuse film F connected in parallel. Therefore, when viewed electrically, each resistance unit is not incorporated in the element 5.

  In the electronic apparatus 1 according to this embodiment, the fuse film F is selectively blown by, for example, laser light according to a required resistance value. As a result, the resistance unit body in which the fuse films F connected in parallel are melted is incorporated into the element 5. Therefore, the entire resistance value of the element 5 can be a resistance value in which resistance unit bodies corresponding to the blown fuse film F are connected in series.

  In particular, in the plurality of types of resistance unit bodies, the resistor R having the same resistance value is one, two, four, eight, sixteen, thirty-two, etc. in series. The number of the series resistor unit bodies connected by increasing the number of resistors and the resistors R having the same resistance value are two, four, eight, sixteen, etc. in parallel. A plurality of types of parallel resistance units connected in increasing numbers are provided. Therefore, by selectively fusing the fuse film F (including the above-described fuse element), the resistance value of the entire element 5 (resistor 56) is adjusted finely and digitally to an arbitrary resistance value. Thus, a desired value of resistance can be generated in the electronic device 1.

FIG. 83 is an electric circuit diagram of an element according to another embodiment of the sixth invention.
Instead of configuring the element 5 by connecting the reference resistance unit R8 and the resistance unit R64 to the resistance unit R / 32 in series as described above, the element 5 may be configured as shown in FIG. Specifically, between the first connection electrode 3 and the second connection electrode 4, the reference resistance unit body R / 16 and the 12 types of resistance unit bodies R / 16, R / 8, R / 4, R / 2, R1 , R2, R4, R8, R16, R32, R64, R128 may be used to form the element 5 in a series connection circuit.

  In this case, the fuse film F is connected in series to each of the 12 types of resistance unit bodies other than the reference resistance unit body R / 16. In a state where all the fuse films F are not blown, each resistance unit body is electrically incorporated into the element 5. If the fuse film F is selectively blown by, for example, laser light according to a required resistance value, a resistance unit body corresponding to the blown fuse film F (a resistance unit body in which the fuse film F is connected in series) ) Is electrically separated from the element 5, the resistance value of the entire electronic device 1 can be adjusted.

FIG. 84 is an electric circuit diagram of an element according to still another embodiment of the sixth invention.
The feature of the element 5 shown in FIG. 84 is that it has a circuit configuration in which a plurality of types of resistance unit bodies are connected in series and a plurality of types of resistance unit bodies are connected in series. As in the previous embodiment, the fuse film F is connected in parallel to each of the plurality of types of resistance unit bodies connected in series, and the plurality of types of resistance unit bodies connected in series are all The fuse film F is short-circuited. Therefore, when the fuse film F is blown, the resistance unit body short-circuited by the blown fuse film F is electrically incorporated into the element 5.

On the other hand, a fuse film F is connected in series to each of a plurality of types of resistance unit bodies connected in parallel. Therefore, by fusing the fuse film F, the resistance unit body to which the blown fuse film F is connected in series can be electrically disconnected from the parallel connection of the resistance unit bodies.
With this configuration, for example, a small resistance of 1 kΩ or less is made on the parallel connection side, and if a resistance circuit of 1 kΩ or more is made on the series connection side, a wide range from a small resistance of several Ω to a large resistance of several MΩ is obtained. Resistor circuits can be made using a network of resistors constructed with an equal basic design.

FIG. 85 is a schematic cross-sectional view of an electronic device.
Next, the electronic device 1 will be described in more detail with reference to FIG. For convenience of explanation, in FIG. 85, the element 5 described above is shown in a simplified manner, and each element other than the substrate 2 is hatched.
Here, the protective film 23 and the resin film 24 described above will be described.

  The protective film 23 is made of, for example, SiN (silicon nitride) and has a thickness of about 3000 mm. The protective film 23 is provided over the entire element formation surface 2A and covers the resistor film 21 and each wiring film 22 (that is, the element 5) on the resistor film 21 from the surface (upper side in FIG. 85) ( That is, an element covering portion 23A that covers the upper surface of each resistor R in the element 5 and a side surface covering portion 23B that covers each of the four side surfaces 2C to 2F (see FIG. 77A) of the substrate 2 are provided. It has one. The element covering portion 23A and the side surface covering portion 23B are actually substantially the same thickness and are continuous with each other. Therefore, the entire protective film 23 continuously covers the upper surface of the resistor R and the side surfaces 2C to 2F of the substrate 2 with substantially the same thickness.

The element covering portion 23A prevents a short circuit other than the wiring film 22 between the resistors R (short circuit between adjacent resistor film lines 21A).
The side surface covering portion 23B covers not only the entire area of each of the side surfaces 2C to 2F but also the portion of the insulating film 20 exposed at the side surfaces 2C to 2F. The side surface covering portion 23B covers the entire area including the portion where the concave portion 10 is formed on the side surface 2C (see FIG. 77A). The side surface covering portion 23B prevents a short circuit in each of the side surfaces 2C to 2F (a short circuit path is generated on the side surface).

  Referring to FIG. 77A, the protective film 23 continuously covers the element forming surface 2A of the substrate 2 and the four side surfaces 2C to 2F, so that the corner portions 11 and 12 of the substrate 2 are covered. A rounded corner portion 26 is provided. In this case, the element 5 and the wiring film 22 can be protected by the protective film 23 and the occurrence of chipping at the corner portion 26 of the protective film 23 can be prevented.

  Returning to FIG. 85, the resin film 24 protects the electronic device 1 together with the protective film 23 and is made of a resin such as polyimide. The thickness of the resin film 24 is about 5 μm. The resin film 24 covers the entire surface of the element covering portion 23A (the upper surface of the protective film 23) over the entire area, and the element forming surface 2A side in the side surface covering portions 23B on the four side surfaces 2C to 2F of the substrate 2. Is covered (the upper end in FIG. 85). That is, the resin film 24 exposes at least the portion on the side opposite to the element formation surface 2A (the lower side in FIG. 85) in the side surface covering portion 23B on the four side surfaces 2C to 2F.

  In such a resin film 24, portions that coincide with the four side surfaces 2 </ b> C to 2 </ b> F in a plan view are arc-shaped projecting portions 24 </ b> A that project to the side (outside) of the side surface covering portions 23 </ b> B on these side surfaces. It has become. That is, the resin film 24 (the overhang portion 24A) protrudes beyond the side surface covering portion 23B (the protective film 23) at the side surfaces 2C to 2F. Such a resin film 24 has a round-shaped side surface 24B convex toward the side in the arc-shaped overhanging portion 24A. The overhanging portion 24A covers a corner portion 27 that forms a boundary between the element formation surface 2A and each of the side surfaces 2C to 2F. For this reason, when the electronic device 1 comes into contact with the surrounding object, the overhanging portion 24A first contacts the surrounding object to alleviate the impact caused by the contact. Chipping at the portion 27 can be prevented. In particular, since the overhanging portion 24A has the round-shaped side surface 24B, the impact caused by the contact can be smoothly reduced.

There may be a configuration in which the resin film 24 does not cover the side surface covering portion 23B at all (a configuration in which the entire side surface covering portion 23B is exposed).
In the resin film 24, one opening 25 is formed at two positions separated in a plan view. Each opening 25 is a through-hole that continuously penetrates the resin film 24 and the protective film 23 (element covering portion 23A) in each thickness direction. Therefore, the opening 25 is formed not only in the resin film 24 but also in the protective film 23. A part of the wiring film 22 is exposed from each opening 25. A portion of the wiring film 22 exposed from each opening 25 is a pad region 22A for external connection.

  Of the two openings 25, one opening 25 is filled with the first connection electrode 3, and the other opening 25 is filled with the second connection electrode 4. A part of each of the first connection electrode 3 and the second connection electrode 4 protrudes from the opening 25 on the surface of the resin film 24. The first connection electrode 3 is electrically connected to the wiring film 22 in the pad region 22 </ b> A in the opening 25 through the one opening 25. The second connection electrode 4 is electrically connected to the wiring film 22 in the pad region 22 </ b> A in the opening 25 through the other opening 25. Thereby, each of the first connection electrode 3 and the second connection electrode 4 is electrically connected to the element 5. Here, the wiring film 22 forms wiring connected to each of the group of resistors R (resistor 56), the first connection electrode 3, and the second connection electrode 4.

  Thus, the resin film 24 and the protective film 23 in which the opening 25 is formed are formed so as to expose the first connection electrode 3 and the second connection electrode 4 from the opening 25. Therefore, electrical connection between the electronic device 1 and the circuit board 9 can be achieved via the first connection electrode 3 and the second connection electrode 4 that protrude from the opening 25 on the surface of the resin film 24 (FIG. 77 (b)).

86A to 86F are schematic sectional views showing a method for manufacturing the electronic device shown in FIG.
First, as shown in FIG. 86A, a wafer 30 made of Si is prepared. The wafer 30 is a source of the substrate 2. Therefore, the front surface 30A of the wafer 30 is the element forming surface 2A of the substrate 2, and the back surface 30B of the wafer 30 is the back surface 2B of the substrate 2.

Then, the insulating film 20 made of SiO ₂ or the like is formed on the surface 30A of the wafer 30, and the element 5 (resistor R and wiring film 22) is formed on the insulating film 20. Specifically, first, a TiN or TiON resistor film 21 is formed on the entire surface of the insulating film 20 by sputtering, and an aluminum (Al) wiring film 22 is stacked on the resistor film 21. . Thereafter, using a photolithography process, the resistor film 21 and the wiring film 22 are selectively removed by dry etching, for example, and as shown in FIG. A configuration is obtained in which the body membrane lines 21A are arranged in the column direction at regular intervals. At this time, a region in which the resistor film line 21A and the wiring film 22 are partially cut is also formed. Subsequently, the wiring film 22 stacked on the resistor film line 21A is selectively removed. As a result, the element 5 having a configuration in which the wiring film 22 is laminated on the resistor film line 21A with a predetermined interval R is obtained.

Referring to FIG. 86A, the elements 5 are formed at a number of locations on the surface 30 </ b> A of the wafer 30 in accordance with the number of electronic devices 1 formed on one wafer 30.
Next, as shown in FIG. 86B, a resist pattern 41 is formed over the entire surface 30 </ b> A of the wafer 30 so as to cover all the elements 5 on the insulating film 20. An opening 42 is formed in the resist pattern 41.

  FIG. 87 is a schematic plan view of a part of a resist pattern used for forming a groove in the step of FIG. 86B. The openings 42 of the resist pattern 41 are regions between the outlines of adjacent electronic devices 1 in plan view (a hatched portion in FIG. 87) when a large number of electronic devices 1 are arranged in a matrix (also in a lattice shape). ). Therefore, the entire shape of the opening 42 is a lattice shape having a plurality of linear portions 42A and 42B orthogonal to each other. Further, any one of the straight portions 42A and 42B (here, the straight portion 42A) has a protruding portion that protrudes orthogonally from the straight portion 42A in accordance with the concave portion 10 (see FIG. 77A) of the electronic device 1. 42C is continuously provided.

  Here, in the electronic device 1, the corner parts 11 and 12 are round shape (refer Fig.77 (a)). Accordingly, the straight portions 42A and 42B that are orthogonal to each other in the opening 42 are connected while being curved. Further, the linear portion 42A and the protruding portion 42C which are orthogonal to each other are connected while being curved. For this reason, the intersecting portion 43A of the straight portions 42A and 42B and the intersecting portion 43B of the straight portions 42A and the protruding portion 42C have a round shape with rounded corners. Further, the corners of the protruding portion 42C other than the intersecting portion 43B are also rounded.

  Referring to FIG. 86B, each of insulating film 20 and wafer 30 is selectively removed by plasma etching using resist pattern 41 as a mask. Thereby, a groove 44 that penetrates the insulating film 20 and reaches the middle of the thickness of the wafer 30 is formed at a position that coincides with the opening 42 of the resist pattern 41 in plan view. The groove 44 has a side surface 44A that faces each other and a bottom surface 44B that connects a lower end of the facing side surface 44A (an end on the back surface 30B side of the wafer 30). The depth of the groove 44 with respect to the surface 30A of the wafer 30 is about 100 μm, and the width of the groove 44 (the interval between the opposing side surfaces 44A) is about 20 μm.

FIG. 88 (a) is a schematic plan view of the wafer after the grooves are formed in the step of FIG. 86B, and FIG. 88 (b) is a partially enlarged view of FIG. 88 (a).
Referring to FIG. 88B, the overall shape of the groove 44 is a lattice shape that coincides with the opening 42 (see FIG. 87) of the resist pattern 41 in plan view. On the surface 30A of the wafer 30, a rectangular frame portion in the groove 44 surrounds the area where each element 5 is formed. A portion where the element 5 is formed on the wafer 30 is a semi-finished product 50 of the electronic apparatus 1. On the surface 30A of the wafer 30, one semi-finished product 50 is located in a region surrounded by the grooves 44, and these semi-finished products 50 are arranged in a matrix.

  In addition, the groove 44 is formed so as to bite into the middle part of one side A of the semi-finished product 50 at a portion corresponding to the protruding portion 42C (see FIG. 87) in the opening 42 of the resist pattern 41. 50 is formed with the aforementioned recess 10 (see FIG. 77A). Then, according to the intersecting portions 43A and 43B (see FIG. 87) having a round shape in the opening 42 of the resist pattern 41, the corner portions 60 (the corner portions 11 and 12 of the electronic device 1) of the semi-finished product 50 in the plan view. ) Is shaped into a round shape. Although this round shape is formed by using plasma etching, silicon etching (normal etching using a chemical solution) may be used instead of plasma etching.

  By etching the wafer 30 in this way, the outer shape of the semi-finished product 50 (in other words, the final electronic device 1) can be arbitrarily set. As in this embodiment, the corner portion 60 (corner portions 11 and 12). ) Has a round shape and can be an asymmetric rectangle having a recess 10 on one side A (see also FIG. 77 (a)). In this case, the electronic device 1 capable of recognizing the chip direction can be manufactured without a marking process (a process of marking a mark or the like indicating the chip direction with a laser or the like).

  After the trench 44 is formed, the resist pattern 41 is removed, and as shown in FIG. 86C, a protective film (SiN) made of SiN is formed on the surface of the element 5 by a CVD (Chemical Vapor Deposition) method. Film) 45 is formed. The SiN film 45 has a thickness of about 3000 mm. The SiN film 45 is formed so as to cover not only the entire surface of the element 5 but also the inner surface (side surface 44A and bottom surface 44B) of the groove 44. Since the SiN film 45 is a thin film formed on the side surface 44A and the bottom surface 44B with a substantially constant thickness, the groove 44 is not filled up. Further, since the SiN film 45 may be formed in the entire area of the side surface 44A in the groove 44, it may not be formed on the bottom surface 44B.

Next, as shown in FIG. 86D, a photosensitive resin sheet 46 made of polyimide is attached to the wafer 30 from above the SiN film 45 other than the groove 44. 89 (a) and 89 (b) are schematic perspective views showing a state in which a polyimide sheet is attached to a wafer in the step of FIG. 86D.
Specifically, as shown in FIG. 89A, after the polyimide sheet 46 is covered from the surface 30A side on the wafer 30 (strictly, the SiN film 45 on the wafer 30), FIG. The sheet 46 is pressed against the wafer 30 by the rotating roller 47 as shown in FIG.

  As shown in FIG. 86D, when the sheet 46 is attached to the entire surface of the SiN film 45 other than the groove 44, a part of the sheet 46 slightly enters the groove 44 side, but on the side surface 44A of the groove 44. The sheet 46 does not reach the bottom surface 44B of the groove 44 only by covering a part of the SiN film 45 on the element 5 side (surface 30A side). Therefore, in the groove 44 between the sheet 46 and the bottom surface 44 </ b> B of the groove 44, a space S having almost the same size as the groove 44 is formed. At this time, the thickness of the sheet 46 is 10 μm to 30 μm.

Next, the sheet 46 is subjected to heat treatment. Thereby, the thickness of the sheet 46 is thermally contracted to about 5 μm.
Next, as shown in FIG. 86E, the sheet 46 is patterned, and a portion of the sheet 46 that coincides with the groove 44 and each pad region 22A of the wiring film 22 in a plan view is selectively removed. Specifically, the sheet 46 is exposed and developed in the pattern using the mask 62 in which the opening 61 having a pattern that matches (matches) with the groove 44 and each pad region 22A in plan view. As a result, the sheet 46 is separated above the groove 44 and each pad region 22A, and the edge portion separated in the sheet 46 slightly overlaps the groove 44 side and overlaps the SiN film 45 on the side surface 44A of the groove 44. Therefore, the above-described overhanging portion 24A (having the round-shaped side surface 24B) is naturally formed on the edge portion.

Next, by etching using the sheet 46 thus separated as a mask, portions of the SiN film 45 that correspond to the pad regions 22A in plan view are removed. Thereby, the opening 25 is formed. Here, the SiN film 45 is formed so as to expose each pad region 22A.
Next, a Ni / Pd / Au laminated film constituted by laminating Ni, Pd and Au is formed on the pad region 22A in each opening 25 by electroless plating. At this time, the Ni / Pd / Au laminated film protrudes from the opening 25 to the surface of the sheet 46. Thereby, the Ni / Pd / Au laminated film in each opening 25 becomes the first connection electrode 3 and the second connection electrode 4 shown in FIG. 86F.

  Next, after conducting an energization inspection between the first connection electrode 3 and the second connection electrode 4, the wafer 30 is ground from the back surface 30B. Here, since the entire portion of the portion forming the side surface 44A of the groove 44 in the wafer 30 is covered with the SiN film 45, it is possible to prevent the occurrence of microcracks or the like in the portion during grinding of the wafer 30, and temporarily Even if a microcrack occurs, the microcrack can be prevented from expanding by filling the microcrack with the SiN film 45.

  Then, when the wafer 30 is thinned by grinding until reaching the bottom surface 44B (strictly speaking, the SiN film 45 on the bottom surface 44B) of the groove 44, there is no connection between the adjacent semi-finished products 50. , The wafer 30 is divided, and the semi-finished product 50 becomes the electronic device 1 and is separated individually. Thereby, the electronic device 1 (see FIG. 85) is completed. In each electronic device 1, the portion that formed the side surface 44 </ b> A of the groove 44 becomes one of the side surfaces 2 </ b> C to 2 </ b> F of the substrate 2. Then, the SiN film 45 becomes the protective film 23. Further, the separated sheet 46 becomes the resin film 24.

  Even if the chip size of the electronic device 1 is small, the electronic device 1 can be divided into pieces by grinding the wafer 30 from the back surface 30B after the grooves 44 are formed in this way. Therefore, as compared with the case where the electronic device 1 is divided into pieces by dicing the wafer 30 with a dicing saw as in the prior art, cost reduction and time reduction can be achieved and yield improvement can be achieved by omitting the dicing process.

According to the above, when manufacturing the electronic device 1, the groove 44 for dividing the electronic device 1 one by one is formed on the surface 30 </ b> A (element forming surface 2 </ b> A). If it forms in the boundary of the element 5 in 30A, the side surface 44A of the groove | channel 44 will become the side surfaces 2C-2F of each electronic device 1 after a division | segmentation.
Prior to the division into the electronic device 1, the SiN film 45 (protective film 23) is formed on the side surface 44 </ b> A of the groove 44 and the surface 30 </ b> A of the wafer 30. Here, as shown in FIG. 86C, a CVD protective film (CVD protective film) 23 having substantially the same thickness is continuously formed on the upper surface of the resistor R and the inner surface (side surface 44A and bottom surface 44B) of the resistor R by the CVD method. Formed. In this case, since the formation of the CVD protective film 23 (SiN film 45) is performed in a reduced pressure environment in the course of CVD, the CVD protective film 23 serves as the side surface covering portion 23B and the side surfaces 2C to 2F (grooves 44) of the substrate 2. Can be attached to the entire side surface 44A). Therefore, the protective film 23 can be uniformly formed on the side surface 44 </ b> A of the groove 44 when the electronic device 1 is manufactured.

  Then, after the formation of the protective film 23, as shown in FIG. 86D, the resin film 24 is formed by a sheet 46 that covers the SiN film 45 (the portion of the protective film 23 that becomes the element covering portion 23A) of the element forming surface 2A. Since the resin film 24 exposes at least the side opposite to the element formation surface 2A (the bottom surface 44B side of the groove 44) in the SiN film 45 on the side surface 44A of the groove 44 (the portion that becomes the side surface covering portion 23B of the protective film 23). It is possible to prevent the grooves 44 from being filled with the resin film 24 from the bottom surface 44B side when the resin film 24 is formed (when the electronic apparatus 1 is manufactured).

Specifically, the resin film 24 is formed by sticking a sheet 46 on the protective film 23. In this case, the groove 46 is not filled from the bottom surface 44B side by the sheet 46. Therefore, as shown in FIG. 86F, if the substrate 2 is thinned until it reaches the bottom surface 44B of the groove 44, the substrate 2 can be divided into the individual electronic devices 1 in the groove 44.
As mentioned above, although embodiment of 6th invention was described, 6th invention can also be implemented with another form.

  For example, when the wafer 30 is divided into the individual electronic devices 1, the wafer 30 is ground from the back surface 30B side to the bottom surface 44B of the groove 44 (see FIG. 86F). Instead, the portion of the SiN film 45 that covers the bottom surface 44B and the portion of the wafer 30 that coincides with the groove 44 in plan view are selectively etched away from the back surface 30B, thereby individually removing the wafer 30. The electronic device 1 may be divided.

90A is a plan view of the electronic device, FIG. 90B is a plan view of the electronic device according to the first modification, and FIG. 90C is a second modification. It is a top view of the electronic device which concerns. In each of FIGS. 90 (a) to 14 (c), the element 5, the protective film 23, and the resin film 24 are not shown for convenience of explanation.
Moreover, the recessed part 10 mentioned above is provided in the position which shifted | deviated from the midpoint P of the one side A in the one side A of the electronic device 1, as shown to Fig.90 (a). When the recess 10 is displaced from the midpoint P, the center 10A of the recess 10 and the midpoint P do not coincide with each other in the direction in which the side A extends. According to this configuration, not only the recess 10 side in the direction (longitudinal direction) connecting the one side A and one side B opposite to the one side A, but also the recess in the extending direction (short direction) of the one side A. The 10 side can also be in the chip direction described above. For example, in a plan view viewed from the element forming surface 2A side, the short side direction of the electronic device 1 and the front-back direction (vertical direction in FIG. 90) are matched, and the long direction of the electronic device 1 is matched with the left-right direction. When the concave portion 10 is located on the left front side (upper left side in FIG. 90), the electronic apparatus 1 can be correctly mounted on the circuit board 9. Then, when mounting, the orientation of the electronic device 1 must be aligned so that the concave portion 10 is located on the left front side in plan view (when the electronic device 1 is viewed from the back surface 2B of the substrate 2, the right front side). This can be grasped from the appearance of the electronic device 1. That is, it can be understood from the appearance of the electronic device 1 that the orientation of the electronic device 1 in both the longitudinal direction and the short direction must be matched.

  Of course, as shown in FIG. 90 (b), the concave portion 10 may be provided at a position where one side A coincides with the midpoint P (a position where the center 10A of the concave portion 10 and the midpoint P coincide in the short direction). . Moreover, you may provide the convex part 51 which protrudes outward instead of the recessed part 10, as shown in FIG.90 (c). The convex portion 51 may have a rectangular shape in plan view, or may have a U shape (a shape that bulges into a U shape) or a triangular shape. Of course, in the side surface 2 </ b> C, the corner portion (four corner portions in a plan view including the tip side and the root side of the convex portion 51) 52 of the convex portion 51 is also chamfered, like the other corner portions 11. It has become. Here, the side surface covering portion 23 </ b> B (see FIG. 77A) covers the entire area including the portion where the convex portion 51 is formed on the side surface 2 </ b> C, as in the case of the concave portion 10. Moreover, it is preferable that the depth of the recessed part 10 and the height (projection amount) of the convex part 51 are 20 micrometers or less (about 1/5 or less of the width of the 1st connection electrode 3 or the 2nd connection electrode 4). And as for the chamfering amount in each of the corner part 11, the corner part 12, and the corner part 52, it is preferable that the distance of one side is about 20 micrometers or less.

FIG. 91A is a diagram illustrating a circuit configuration of an element according to another embodiment of the electronic device, and FIG. 91B is a diagram illustrating a circuit configuration of an element according to still another embodiment of the electronic device. It is.
In the embodiment described above, since the electronic device 1 is a chip resistor, the element 5 between the first connection electrode 3 and the second connection electrode 4 is the resistor 56, but the diode 55 shown in FIG. Alternatively, a diode 55 and a resistor 56 may be connected in series as shown in FIG. 91 (b). The electronic device 1 becomes a chip diode by having the diode 55, and the first connection electrode 3 and the second connection electrode 4 have polarity, but the above-described chip direction is a direction corresponding to the polarity. Thereby, since the polarity of the 1st connection electrode 3 and the 2nd connection electrode 4 can be shown with a chip | tip direction, the said polarity can be grasped | ascertained by the external appearance of the electronic device 1. FIG. That is, it can be seen which side in the chip direction (that is, which of the first connection electrode 3 and the second connection electrode 4) is the positive or negative pole side. Therefore, the electronic device 1 can be correctly mounted on the circuit board 9 (see FIG. 77 (b)) so that the side on which the above-described concave portion 10 and convex portion 51 (see FIG. 90) are provided is on the corresponding pole side. Can be.

Of course, the sixth invention can be applied to an element device in which various elements such as a chip capacitor in which a capacitor is used instead of the diode 55 in the element 5 and a chip inductor are formed on the chip-sized substrate 2. .
<Seventh Invention>
(1) Features of the seventh invention For example, the features of the seventh invention are the following F1 to F10.
(F1) A substrate having an element formation surface and a side surface, a resistor formed on the element formation surface of the substrate, and a protective film continuously covering the upper surface of the resistor and the side surface of the substrate with substantially the same thickness Including electronic equipment.

According to this configuration, when an electronic device is manufactured, a groove for dividing the electronic device one by one is formed in the wafer on which the plurality of resistors are formed on the element forming surface, and the resistor is formed on the element forming surface. If formed at the boundary of the region, the side surface of the groove becomes the side surface of the substrate in each electronic device after division. Then, if a protective film having substantially the same thickness is continuously formed on the upper surface of the resistor and the inner surface (side surface and bottom surface) of the resistor by, for example, the CVD method, the protective film serves as the side surface covering portion and covers the entire side surface of the substrate. Can adhere to. Therefore, the protective film can be uniformly formed on the side surface of the groove when the electronic apparatus is manufactured.
(F2) The plurality of resistors are formed on the element formation surface of the substrate, further include a wiring film that electrically connects the plurality of resistors, and the protective film further covers the wiring film The electronic device according to F1, which is formed in

According to this configuration, since the wiring film is covered with the protective film, a short circuit other than the wiring film between the resistors can be prevented.
(F3) The electronic device according to F2, further including a resin film made of a photosensitive resin sheet and covering the protective film.
(F4) The electronic device according to F3, further including an external connection electrode connected to the wiring film through a through-hole penetrating the resin film and the protective film.
(F5) The electronic device according to F4, wherein the resin film and the protective film are formed so as to expose the external connection electrodes.

According to this configuration, electrical connection between the electronic device and the wiring board on which the electronic device is mounted can be achieved via the external connection electrode.
(F6) The electronic device according to any one of F1 to F5, wherein the resistor forms a resistance circuit including unit resistors.
(F7) The electronic device according to any one of F1 to F6, wherein a corner portion on a side surface of the substrate has a round shape.

According to this structure, generation | occurrence | production of the chipping (chip) in a corner part can be prevented.
(F8) A resistor forming step of forming a resistor on the element forming surface of the substrate, a step of forming a groove around the region where the resistor is formed, and covering the surface of the resistor and the inner surface of the groove Forming a protective film by a CVD method, and dividing the substrate in the groove by thinning the substrate from a surface opposite to the element formation surface until reaching the bottom surface of the groove; A method for manufacturing an electronic device, comprising:

According to this method, by forming a protective film on the inner surface (side surface and bottom surface) of the groove by the CVD method, this protective film can be attached to the entire side surface of the substrate as a side surface covering portion. Therefore, the protective film can be uniformly formed on the side surface of the groove when the electronic apparatus is manufactured.
(F9) The method according to F8, further including a step of forming a wiring film for electrically connecting a resistor to the element formation surface of the substrate, wherein the protective film is formed to further cover the wiring film. Manufacturing method of electronic equipment.

In this case, in the completed electronic device, since the wiring film is covered with the protective film, a short circuit other than the wiring film between the resistors can be prevented.
(F10) The manufacturing method of the electronic device according to F9, wherein the protective film is formed so as to expose an external connection pad region of the wiring film.
In this case, electrical connection between the electronic device and the wiring board on which the electronic device is mounted can be achieved via the external connection electrode connected to the external connection pad region.
(2) Embodiment of Seventh Invention Hereinafter, an embodiment of the seventh invention will be described in detail with reference to the accompanying drawings. 92 to 106 are valid only in these drawings, and even if used in other embodiments, they do not indicate the same elements as those in the other embodiments.

FIG. 92A is a schematic perspective view for explaining the configuration of an electronic device according to an embodiment of the seventh invention, and FIG. 92B is a state in which the electronic device is mounted on a circuit board. FIG.
This electronic device 1 is a minute chip part and has a rectangular parallelepiped shape as shown in FIG. Regarding the dimensions of the electronic device 1, the length L in the long side direction is about 0.3 mm, the width W in the short side direction is about 0.15 mm, and the thickness T is about 0.1 mm.

The electronic device 1 is obtained by forming a large number of electronic devices 1 in a lattice shape on a wafer and then cutting the wafer into individual electronic devices 1.
The electronic device 1 mainly includes a substrate 2, a first connection electrode 3 and a second connection electrode 4 that are external connection electrodes, and an element 5. The first connection electrode 3, the second connection electrode 4, and the element 5 are formed on the substrate 2 using a semiconductor manufacturing process. Accordingly, a semiconductor substrate (semiconductor wafer) such as a silicon substrate (silicon wafer) can be used as the substrate 2. The substrate 2 may be another type of substrate such as an insulating substrate.

  The substrate 2 has a substantially rectangular parallelepiped chip shape. In the substrate 2, the upper surface in FIG. 92A is the element formation surface 2A. The element formation surface 2A is the surface of the substrate 2 and has a substantially rectangular shape. The surface opposite to the element formation surface 2A in the thickness direction of the substrate 2 is a back surface 2B. The element formation surface 2A and the back surface 2B have substantially the same shape. In addition to the element formation surface 2A and the back surface 2B, the substrate 2 has a side surface 2C, a side surface 2D, a side surface 2E, and a side surface 2F that extend perpendicular to these surfaces.

  The side surface 2C extends between one end edge in the longitudinal direction of the element formation surface 2A and the back surface 2B (the left front edge in FIG. 92A), and the side surface 2D extends in the longitudinal direction of the element formation surface 2A and the back surface 2B. It is constructed between the other ends in the direction (the edge on the far right side in FIG. 92A). The side surface 2C and the side surface 2D are both end surfaces of the substrate 2 in the longitudinal direction. The side surface 2E is constructed between one edge in the short direction of the element formation surface 2A and the back surface 2B (the left edge on the left side in FIG. 92A), and the side surface 2F is composed of the element formation surface 2A and the back surface 2B. Between the other edges in the short direction (the edge on the right front side in FIG. 92A). The side surface 2E and the side surface 2F are both end surfaces of the substrate 2 in the lateral direction.

  In the substrate 2, the element formation surface 2 </ b> A, the side surface 2 </ b> C, the side surface 2 </ b> D, the side surface 2 </ b> E, and the side surface 2 </ b> F are covered with the protective film 23. Therefore, strictly speaking, in FIG. 92A, the element formation surface 2A, the side surface 2C, the side surface 2D, the side surface 2E, and the side surface 2F are located on the inner side (back side) of the protective film 23 and are exposed to the outside. Absent. Further, the protective film 23 on the element formation surface 2 </ b> A is covered with a resin film 24. The resin film 24 protrudes from the element formation surface 2A to the end portion on the element formation surface 2A side (upper end portion in FIG. 92A) of each of the side surface 2C, side surface 2D, side surface 2E, and side surface 2F. The protective film 23 and the resin film 24 will be described in detail later.

  In the substrate 2, the substrate 2 is placed on a portion corresponding to one side A (the side surface 2C, 2D, 2E, or 2F of the substantially rectangular element forming surface 2A, here, the side surface 2C as described later). A recess 10 is formed that is notched in the thickness direction. The side A is also one side of the electronic device 1 in plan view. The concave portion 10 in FIG. 92A is formed on the side surface 2C, and is recessed toward the side surface 2D while extending in the thickness direction of the substrate 2. The recess 10 penetrates the substrate 2 in the thickness direction, and the end of the recess 10 in the thickness direction is exposed from each of the element formation surface 2A and the back surface 2B. The recess 10 is smaller than the side surface 2C in the direction in which the side surface 2C extends (the short direction described above). The shape of the recess 10 in a plan view when the substrate 2 is viewed from the thickness direction (also the thickness direction of the electronic device 1) is a rectangular shape (rectangular shape) that is long in the short direction. The shape of the recess 10 in plan view may be a trapezoidal shape that becomes narrower in the direction in which the recess 10 is recessed (side 2D side), or a triangular shape that becomes narrower in the direction of recess. Alternatively, it may be U-shaped (a shape recessed in a U-shape). In any case, the concave portion 10 having such a simple shape can be easily formed. Moreover, although the recessed part 10 is formed in the side surface 2C here, you may form in at least one of the side surfaces 2C-2F instead of the side surface 2C.

  The concave portion 10 represents the direction (chip direction) of the electronic device 1 when the electronic device 1 is mounted on the circuit board 9 (see FIG. 92B). Since the outline of the electronic device 1 (strictly speaking, the substrate 2) in plan view is a rectangle having a recess 10 on one side A thereof, it has an asymmetric outer shape in the longitudinal direction. That is, the asymmetric outer shape has the concave portion 10 indicating the chip direction on any one of the side surfaces 2C, 2D, 2E, and 2F (one side A). It represents that the concave side in the longitudinal direction is the chip direction. Thus, the chip direction of the electronic device 1 can be recognized only by making the outer shape of the substrate 2 in the electronic device 1 asymmetric in a plan view. That is, the chip direction can be recognized from the outer shape of the electronic device 1 without a marking process. In particular, since the asymmetric outer shape of the electronic device 1 is a rectangle having a concave portion 10 representing the chip direction on one side A, the electronic device 1 has a concave portion 10 side in the longitudinal direction connecting the one side A and the opposite side B. It can be in the chip direction. Therefore, for example, in the plan view, the longitudinal direction of the electronic device 1 is aligned with the left-right direction so that the electronic device 1 can be correctly mounted on the circuit board 9 when the side A is located at the left end. When mounting, it can be grasped from the appearance of the electronic device 1 by the recess 10 that the electronic device 1 must be oriented so that the side A is located at the left end in plan view.

  In the rectangular parallelepiped substrate 2, the corner portion 11 (the portion where the adjacent ones intersect) adjacent to each other on the side surface 2C, the side surface 2D, the side surface 2E, and the side surface 2F has a chamfered round shape. It is shaped (rounded). Further, in the substrate 2, a corner portion 12 (a corner portion in the concave portion 10 in the side surface 2 </ b> C) that forms a boundary between the concave portion 10 and the side surface 2 </ b> C around the concave portion 10 is also shaped into a chamfered round shape. Here, the corner portion 12 exists not only at the boundary between the concave portion 10 and the surrounding side surface 2C (portion other than the concave portion 10) but also at the deepest portion side of the concave portion 10, and is present at four locations in plan view.

Thus, in the outline of the board | substrate 2 in planar view, all the bent parts (corner parts 11 and 12) are round shape. Therefore, the occurrence of chipping can be prevented at the corner portions 11 and 12 in the round shape. Thereby, in the manufacture of the electronic apparatus 1, it is possible to improve the yield (improvement of productivity).
The first connection electrode 3 and the second connection electrode 4 are formed on the element formation surface 2 </ b> A of the substrate 2 and are partially exposed from the resin film 24. Each of the first connection electrode 3 and the second connection electrode 4 is configured, for example, by stacking Ni (nickel), Pd (palladium), and Au (gold) on the element formation surface 2A in this order. The first connection electrode 3 and the second connection electrode 4 are arranged at intervals in the longitudinal direction of the element formation surface 2A, and are long in the short direction of the element formation surface 2A. In FIG. 92A, on the element formation surface 2A, the first connection electrode 3 is provided near the side surface 2C, and the second connection electrode 4 is provided near the side surface 2D. The concave portion 10 of the side surface 2 </ b> C described above is recessed at a depth that does not interfere with the first connection electrode 3. However, in some cases, the first connection electrode 3 may be provided with a recess (becomes a part of the recess 10) according to the recess 10.

  The element 5 is a circuit element, and is formed in a region between the first connection electrode 3 and the second connection electrode 4 on the element formation surface 2A of the substrate 2, and from above by the protective film 23 and the resin film 24. It is covered. The element 5 of this embodiment is a circuit network in which a plurality of thin film resistors (thin film resistors) R made of TiN (titanium nitride) or TiON (titanium oxynitride) are arranged in a matrix on the element formation surface 2A. A configured resistor 56. The element 5 is connected to a wiring film 22 which will be described later, and is connected to the first connection electrode 3 and the second connection electrode 4 via the wiring film 22. Thereby, in the electronic device 1, a resistance circuit including the element 5 is formed between the first connection electrode 3 and the second connection electrode 4. Therefore, the electronic device 1 in this embodiment is a chip resistor.

  As shown in FIG. 92 (b), the first connection electrode 3 and the second connection electrode 4 are opposed to the circuit board 9, and electrical and mechanical with respect to the circuit (not shown) of the circuit board 9 by the solder 13. Thus, the electronic device 1 can be flip-chip connected to the circuit board 9. The first connection electrode 3 and the second connection electrode 4 that function as external connection electrodes are formed of gold (Au) or are plated with gold in order to improve solder wettability and reliability. It is desirable.

FIG. 93 is a plan view of the electronic device, and is a diagram illustrating a positional relationship between the first connection electrode, the second connection electrode, and the element, and a configuration of the element in a plan view.
Referring to FIG. 93, as an example, element 5 serving as a resistor network includes eight resistors R arranged in the row direction (longitudinal direction of substrate 2) and the column direction (of substrate 2). It has a total of 352 resistors R composed of 44 resistors R arranged along the width direction. Each resistor R has an equal resistance value.

  A plurality of types of resistance unit bodies (unit resistances) are formed by grouping and electrically connecting a large number of these resistor bodies R every predetermined number of 1 to 64 pieces. The formed plural types of resistance unit bodies are connected in a predetermined manner via the connecting conductor film C. In addition, a plurality of fuse films F that can be blown on the element forming surface 2A of the substrate 2 in order to electrically incorporate the resistance unit into the element 5 or to electrically separate it from the element 5 are provided. Is provided. The plurality of fuse films F and connection conductor films C are arranged along the inner side of the second connection electrode 4 so that the arrangement region is linear. More specifically, a plurality of fuse films F and connecting conductor films C are arranged in a straight line.

FIG. 94A is an enlarged plan view showing a part of the element shown in FIG. FIG. 94B is a longitudinal sectional view in the length direction along BB of FIG. 94A drawn for explaining the configuration of the resistor in the element. FIG. 94C is a longitudinal cross-sectional view in the width direction along CC of FIG. 94A drawn to explain the configuration of the resistor in the element.
The configuration of the resistor R will be described with reference to FIGS. 94A, 94B, and 94C.

The electronic device 1 further includes an insulating film 20 and a resistor film 21 in addition to the wiring film 22, the protective film 23, and the resin film 24 described above (see FIGS. 94B and 94C). The insulating film 20, the resistor film 21, the wiring film 22, the protective film 23, and the resin film 24 are formed on the substrate 2 (element formation surface 2A).
The insulating film 20 is made of SiO ₂ (silicon oxide). The insulating film 20 covers the entire area of the element formation surface 2A of the substrate 2. The insulating film 20 has a thickness of about 10,000 mm.

  The resistor film 21 constitutes the resistor R. The resistor film 21 is made of TiN or TiON, and is laminated on the surface of the insulating film 20. The thickness of the resistor film 21 is about 2000 mm. The resistor film 21 forms a plurality of lines (hereinafter referred to as “resistor film line 21 </ b> A”) extending in a line between the first connection electrode 3 and the second connection electrode 4. 21A may be cut at a predetermined position in the line direction (see FIG. 94A).

A wiring film 22 is laminated on the resistor film line 21A. The wiring film 22 is made of Al (aluminum) or an alloy of aluminum and Cu (copper) (AlCu alloy). The thickness of the wiring film 22 is about 8000 mm. The wiring film 22 is laminated on the resistor film line 21A with a constant interval R in the line direction.
FIG. 95 shows the electrical characteristics of the resistor film line 21A and the wiring film 22 having this configuration in terms of circuit symbols. That is, as shown in FIG. 95A, each portion of the resistor film lines 21A in the region of the predetermined interval R forms one resistor R having a constant resistance value r.

In the region where the wiring film 22 is laminated, the resistor film lines 21 </ b> A are short-circuited by the wiring film 22 by electrically connecting the resistors R adjacent to each other. Therefore, a resistor circuit is formed which is formed by connecting the resistors R of the resistor r shown in FIG. 95 (b) in series.
Since the adjacent resistor film lines 21A are connected to each other by the resistor film 21 and the wiring film 22, the resistor network of the element 5 shown in FIG. 94A is shown in FIG. A resistor circuit (consisting of R unit resistors) is formed.

Here, based on the characteristic that the same-shaped and large-sized resistor films 21 formed on the substrate 2 have substantially the same value, a large number of resistors R arranged in a matrix on the substrate 2 have the same resistance. Has a value.
Further, the wiring film 22 laminated on the resistor film line 21A forms a resistor R and also serves as a connecting wiring film for connecting a plurality of resistors R to form a resistance unit body. Plays.

96 (a) is a partially enlarged plan view of a region including a fuse film drawn by enlarging a part of the plan view of the electronic device shown in FIG. 93, and FIG. 96 (b) is a plan view of FIG. It is a figure which shows the cross-sectional structure which follows BB.
As shown in FIGS. 96A and 96B, the above-described fuse film F and connecting conductor film C are also formed by the wiring film 22 laminated on the resistor film 21 that forms the resistor R. . That is, on the same layer as the wiring film 22 laminated on the resistor film line 21A forming the resistor R, the fuse film F and the connecting conductor film C are formed of Al or AlCu alloy which is the same metal material as the wiring film 22. Is formed.

  That is, in the same layer laminated on the resistor film 21, the wiring film for forming the resistor R, the fuse film F, the connecting conductor film C, and the element 5 are connected to the first connection electrode 3. A wiring film for connecting to the second connection electrode 4 is formed as the wiring film 22 by using the same metal material (Al or AlCu alloy) by the same manufacturing process (a sputtering and a photolithography process described later). Yes.

The fuse film F is not only a part of the wiring film 22 but also a group (fuse element) of a part of the resistor R (resistor film 21) and a part of the wiring film 22 on the resistor film 21. You may point.
The fuse film F has been described only in the case where the same layer as the connecting conductor film C is used. However, the connecting conductor film C is formed by stacking another conductor film on the conductor film C. The resistance value may be lowered. Even in this case, if the conductor film is not laminated on the fuse film F, the fusing property of the fuse film F does not deteriorate.

FIG. 97 is an electric circuit diagram of an element according to the embodiment of the seventh invention.
Referring to FIG. 97, element 5 includes reference resistance unit R8, resistance unit R64, two resistance units R32, resistance unit R16, resistance unit R8, resistance unit R4, resistance unit R2, The resistance unit body R1, the resistance unit body R / 2, the resistance unit body R / 4, the resistance unit body R / 8, the resistance unit body R / 16, and the resistance unit body R / 32 are arranged in this order from the first connection electrode 3. It is configured by connecting in series. Each of the reference resistance unit R8 and the resistance unit bodies R64 to R2 is configured by connecting in series the same number of resistors R as the last number (“64” in the case of R64). The resistance unit R1 is composed of one resistor R. Each of the resistance unit bodies R / 2 to R / 32 is configured by connecting in parallel the same number of resistor bodies R as the last number of itself (“32” in the case of R / 32). The meaning of the number at the end of the resistance unit body is the same in FIGS. 98 and 99 described later.

One fuse film F is connected in parallel to each of the resistance unit bodies R64 to R / 32 other than the reference resistance unit body R8. The fuse films F are connected in series either directly or via a connecting conductor film C (see FIG. 96A).
As shown in FIG. 97, in a state where all the fuse films F are not blown, the element 5 is composed of eight resistors R provided in series between the first connection electrode 3 and the second connection electrode 4. A resistance circuit of the reference resistance unit R8 (resistance value 8r) is configured. For example, if the resistance value r of one resistor R is r = 80Ω, a chip resistor (electronic device 1) in which the first connection electrode 3 and the second connection electrode 4 are connected by a resistance circuit of 8r = 64Ω. Is configured.

  Further, in a state where all the fuse films F are not blown, a plurality of types of resistance unit bodies other than the reference resistance unit body R8 are short-circuited. That is, 12 types of 13 resistance unit bodies R64 to R / 32 are connected in series to the reference resistance unit body R8, but each resistance unit body is short-circuited by the fuse film F connected in parallel. Therefore, when viewed electrically, each resistance unit is not incorporated in the element 5.

  In the electronic apparatus 1 according to this embodiment, the fuse film F is selectively blown by, for example, laser light according to a required resistance value. Thereby, the resistance unit body in which the fuse films F connected in parallel are melted is incorporated into the element 5. Therefore, the entire resistance value of the element 5 can be a resistance value in which resistance unit bodies corresponding to the blown fuse film F are connected in series and incorporated.

  In particular, in the plurality of types of resistance unit bodies, the resistor R having the same resistance value is one, two, four, eight, sixteen, thirty-two, etc. in series. The number of the series resistor unit bodies connected by increasing the number of resistors and the resistors R having the same resistance value are two, four, eight, sixteen, etc. in parallel. A plurality of types of parallel resistance units connected in increasing numbers are provided. Therefore, by selectively fusing the fuse film F (including the above-described fuse element), the resistance value of the entire element 5 (resistor 56) is adjusted finely and digitally to an arbitrary resistance value. Thus, a desired value of resistance can be generated in the electronic device 1.

FIG. 98 is an electric circuit diagram of an element according to another embodiment of the seventh invention.
Instead of configuring the element 5 by connecting the reference resistance unit R8 and the resistance unit R64 to the resistance unit R / 32 in series as described above, the element 5 may be configured as shown in FIG. Specifically, between the first connection electrode 3 and the second connection electrode 4, the reference resistance unit body R / 16 and the 12 types of resistance unit bodies R / 16, R / 8, R / 4, R / 2, R1 , R2, R4, R8, R16, R32, R64, R128 may be used to form the element 5 in a series connection circuit.

  In this case, the fuse film F is connected in series to each of the 12 types of resistance unit bodies other than the reference resistance unit body R / 16. In a state where all the fuse films F are not blown, each resistance unit body is electrically incorporated into the element 5. If the fuse film F is selectively blown, for example, by laser light, according to the required resistance value, a resistance unit body corresponding to the blown fuse film F (a resistance unit body in which the fuse film F is connected in series) ) Is electrically separated from the element 5, the resistance value of the entire electronic device 1 can be adjusted.

FIG. 99 is an electric circuit diagram of an element according to still another embodiment of the seventh invention.
The feature of the element 5 shown in FIG. 99 is that it has a circuit configuration in which a series connection of a plurality of types of resistance unit bodies and a parallel connection of a plurality of types of resistance unit bodies are connected in series. As in the previous embodiment, the fuse film F is connected in parallel to each of the plurality of types of resistance unit bodies connected in series, and the plurality of types of resistance unit bodies connected in series are all The fuse film F is short-circuited. Therefore, when the fuse film F is blown, the resistance unit body short-circuited by the blown fuse film F is electrically incorporated into the element 5.

On the other hand, a fuse film F is connected in series to each of a plurality of types of resistance unit bodies connected in parallel. Therefore, by fusing the fuse film F, the resistance unit body to which the blown fuse film F is connected in series can be electrically disconnected from the parallel connection of the resistance unit bodies.
With this configuration, for example, a small resistance of 1 kΩ or less is made on the parallel connection side, and if a resistance circuit of 1 kΩ or more is made on the series connection side, a wide range from a small resistance of several Ω to a large resistance of several MΩ is obtained. Resistor circuits can be made using a network of resistors constructed with an equal basic design.

FIG. 100 is a schematic cross-sectional view of an electronic device.
Next, the electronic device 1 will be described in more detail with reference to FIG. For convenience of explanation, in FIG. 100, the element 5 described above is shown in a simplified manner, and each element other than the substrate 2 is hatched.
Here, the protective film 23 and the resin film 24 described above will be described.

  The protective film 23 is made of, for example, SiN (silicon nitride) and has a thickness of about 3000 mm. The protective film 23 is provided over the entire element forming surface 2A and covers the resistor film 21 and each wiring film 22 (that is, the element 5) on the resistor film 21 from the surface (upper side in FIG. 100) ( That is, an element covering portion 23A that covers the upper surface of each resistor R in the element 5 and a side surface covering portion 23B that covers each of the four side surfaces 2C to 2F of the substrate 2 (see FIG. 92A). It has one. The element covering portion 23A and the side surface covering portion 23B are actually substantially the same thickness and are continuous with each other. Therefore, the entire protective film 23 continuously covers the upper surface of the resistor R and the side surfaces 2C to 2F of the substrate 2 with substantially the same thickness.

The element covering portion 23A prevents a short circuit other than the wiring film 22 between the resistors R (short circuit between adjacent resistor film lines 21A).
The side surface covering portion 23B covers not only the entire area of each of the side surfaces 2C to 2F but also the portion of the insulating film 20 exposed at the side surfaces 2C to 2F. The side surface covering portion 23B covers the entire area including the portion where the recess 10 is formed on the side surface 2C (see FIG. 92A). The side surface covering portion 23B prevents a short circuit in each of the side surfaces 2C to 2F (a short circuit path is generated on the side surface).

  Referring to FIG. 92A, the protective film 23 continuously covers the element formation surface 2A of the substrate 2 and the four side surfaces 2C to 2F, so that the corner portions 11 and 12 of the substrate 2 are covered. A rounded corner portion 26 is provided. In this case, the element 5 and the wiring film 22 can be protected by the protective film 23 and the occurrence of chipping at the corner portion 26 of the protective film 23 can be prevented.

  Returning to FIG. 100, the resin film 24 protects the electronic device 1 together with the protective film 23 and is made of a resin such as polyimide. The thickness of the resin film 24 is about 5 μm. The resin film 24 covers the entire surface of the element covering portion 23A (the upper surface of the protective film 23) over the entire area, and the element forming surface 2A side in the side surface covering portions 23B on the four side surfaces 2C to 2F of the substrate 2. Is covered (the upper end in FIG. 100). That is, the resin film 24 exposes at least the portion on the side opposite to the element formation surface 2A (the lower side in FIG. 100) in the side surface covering portion 23B on the four side surfaces 2C to 2F.

  In such a resin film 24, portions that coincide with the four side surfaces 2 </ b> C to 2 </ b> F in a plan view are arc-shaped projecting portions 24 </ b> A that project to the side (outside) of the side surface covering portions 23 </ b> B on these side surfaces. It has become. That is, the resin film 24 (the overhang portion 24A) protrudes beyond the side surface covering portion 23B (the protective film 23) at the side surfaces 2C to 2F. Such a resin film 24 has a round-shaped side surface 24B convex toward the side in the arc-shaped overhanging portion 24A. The overhanging portion 24A covers a corner portion 27 that forms a boundary between the element formation surface 2A and each of the side surfaces 2C to 2F. For this reason, when the electronic device 1 comes into contact with the surrounding object, the overhanging portion 24A first contacts the surrounding object to alleviate the impact caused by the contact. Chipping at the portion 27 can be prevented. In particular, since the overhanging portion 24A has the round-shaped side surface 24B, the impact caused by the contact can be smoothly reduced.

There may be a configuration in which the resin film 24 does not cover the side surface covering portion 23B at all (a configuration in which the entire side surface covering portion 23B is exposed).
In the resin film 24, one opening 25 is formed at two positions separated in a plan view. Each opening 25 is a through-hole that continuously penetrates the resin film 24 and the protective film 23 (element covering portion 23A) in each thickness direction. Therefore, the opening 25 is formed not only in the resin film 24 but also in the protective film 23. A part of the wiring film 22 is exposed from each opening 25. A portion of the wiring film 22 exposed from each opening 25 is a pad region 22A for external connection.

  Of the two openings 25, one opening 25 is filled with the first connection electrode 3, and the other opening 25 is filled with the second connection electrode 4. A part of each of the first connection electrode 3 and the second connection electrode 4 protrudes from the opening 25 on the surface of the resin film 24. The first connection electrode 3 is electrically connected to the wiring film 22 in the pad region 22 </ b> A in the opening 25 through the one opening 25. The second connection electrode 4 is electrically connected to the wiring film 22 in the pad region 22 </ b> A in the opening 25 through the other opening 25. Thereby, each of the first connection electrode 3 and the second connection electrode 4 is electrically connected to the element 5. Here, the wiring film 22 forms wiring connected to each of the group of resistors R (resistor 56), the first connection electrode 3, and the second connection electrode 4.

  Thus, the resin film 24 and the protective film 23 in which the opening 25 is formed are formed so as to expose the first connection electrode 3 and the second connection electrode 4 from the opening 25. Therefore, electrical connection between the electronic device 1 and the circuit board 9 can be achieved via the first connection electrode 3 and the second connection electrode 4 that protrude from the opening 25 on the surface of the resin film 24 (FIG. 92 (b)).

101A to 101F are schematic sectional views showing a method for manufacturing the electronic device shown in FIG.
First, as shown in FIG. 101A, a wafer 30 is prepared. The wafer 30 is a source of the substrate 2. Therefore, the front surface 30A of the wafer 30 is the element forming surface 2A of the substrate 2, and the back surface 30B of the wafer 30 is the back surface 2B of the substrate 2.

Then, the insulating film 20 made of SiO ₂ or the like is formed on the surface 30A of the wafer 30, and the element 5 (resistor R and wiring film 22) is formed on the insulating film 20. Specifically, first, a TiN or TiON resistor film 21 is formed on the entire surface of the insulating film 20 by sputtering, and an aluminum (Al) wiring film 22 is stacked on the resistor film 21. . Thereafter, using a photolithography process, the resistor film 21 and the wiring film 22 are selectively removed by dry etching, for example, and as shown in FIG. A configuration is obtained in which the body membrane lines 21A are arranged in the column direction at regular intervals. At this time, a region in which the resistor film line 21A and the wiring film 22 are partially cut is also formed. Subsequently, the wiring film 22 stacked on the resistor film line 21A is selectively removed. As a result, the element 5 having a configuration in which the wiring film 22 is laminated on the resistor film line 21A with a predetermined interval R is obtained.

Referring to FIG. 101A, the elements 5 are formed at a number of locations on the surface 30 </ b> A of the wafer 30 according to the number of electronic devices 1 formed on one wafer 30.
Next, as shown in FIG. 101B, a resist pattern 41 is formed over the entire surface 30 </ b> A of the wafer 30 so as to cover all the elements 5 on the insulating film 20. An opening 42 is formed in the resist pattern 41.

  FIG. 102 is a schematic plan view of a part of a resist pattern used for forming a groove in the step of FIG. 101B. The openings 42 of the resist pattern 41 are regions between the outlines of adjacent electronic devices 1 in plan view (a hatched portion in FIG. 102) when a large number of electronic devices 1 are arranged in a matrix (also in a lattice shape). ). Therefore, the entire shape of the opening 42 is a lattice shape having a plurality of linear portions 42A and 42B orthogonal to each other. Further, any one of the straight portions 42A and 42B (here, the straight portion 42A) has a protruding portion that protrudes orthogonally from the straight portion 42A in accordance with the concave portion 10 (see FIG. 92A) of the electronic device 1. 42C is continuously provided.

  Here, in the electronic device 1, the corner parts 11 and 12 are round shape (refer Fig.92 (a)). Accordingly, the straight portions 42A and 42B that are orthogonal to each other in the opening 42 are connected while being curved. Further, the linear portion 42A and the protruding portion 42C which are orthogonal to each other are connected while being curved. For this reason, the intersecting portion 43A of the straight portions 42A and 42B and the intersecting portion 43B of the straight portions 42A and the protruding portion 42C have a round shape with rounded corners. Further, the corners of the protruding portion 42C other than the intersecting portion 43B are also rounded.

  Referring to FIG. 101B, each of insulating film 20 and wafer 30 is selectively removed by plasma etching using resist pattern 41 as a mask. Thereby, a groove 44 that penetrates the insulating film 20 and reaches the middle of the thickness of the wafer 30 is formed at a position that coincides with the opening 42 of the resist pattern 41 in plan view. The groove 44 has a side surface 44A that faces each other and a bottom surface 44B that connects a lower end of the facing side surface 44A (an end on the back surface 30B side of the wafer 30). The depth of the groove 44 with respect to the surface 30A of the wafer 30 is about 100 μm, and the width of the groove 44 (the interval between the opposing side surfaces 44A) is about 20 μm.

FIG. 103 (a) is a schematic plan view of the wafer after the grooves are formed in the step of FIG. 101B, and FIG. 103 (b) is a partially enlarged view of FIG. 103 (a).
Referring to FIG. 103B, the overall shape of the groove 44 is a lattice shape that coincides with the opening 42 (see FIG. 102) of the resist pattern 41 in plan view. On the surface 30A of the wafer 30, a rectangular frame portion in the groove 44 surrounds the area where each element 5 is formed. A portion where the element 5 is formed on the wafer 30 is a semi-finished product 50 of the electronic apparatus 1. On the surface 30A of the wafer 30, one semi-finished product 50 is located in a region surrounded by the grooves 44, and these semi-finished products 50 are arranged in a matrix.

  Further, the groove 44 is formed so as to bite into the middle part of one side A of the semi-finished product 50 at a portion corresponding to the protruding portion 42C (see FIG. 102) in the opening 42 of the resist pattern 41. 50 is formed with the above-described recess 10 (see FIG. 92A). Then, in accordance with the intersecting portions 43A and 43B (see FIG. 102) having a round shape in the opening 42 of the resist pattern 41, the corner portions 60 (the corner portions 11 and 12 of the electronic device 1) of the semi-finished product 50 in a plan view. ) Is shaped into a round shape. Although this round shape is formed by using plasma etching, silicon etching (normal etching using a chemical solution) may be used instead of plasma etching.

  By etching the wafer 30 in this way, the outer shape of the semi-finished product 50 (in other words, the final electronic device 1) can be arbitrarily set. As in this embodiment, the corner portion 60 (corner portions 11 and 12). ) Has a round shape and can be an asymmetric rectangle having a recess 10 on one side A (see also FIG. 92 (a)). In this case, the electronic device 1 capable of recognizing the chip direction can be manufactured without a marking process (a process of marking a mark or the like indicating the chip direction with a laser or the like).

  After the trench 44 is formed, the resist pattern 41 is removed, and a protective film (SiN) made of SiN is formed on the surface of the element 5 by CVD (Chemical Vapor Deposition) as shown in FIG. 101C. Film) 45 is formed. The SiN film 45 has a thickness of about 3000 mm. The SiN film 45 is formed so as to cover not only the entire surface of the element 5 but also the inner surface (side surface 44A and bottom surface 44B) of the groove 44. Since the SiN film 45 is a thin film formed on the side surface 44A and the bottom surface 44B with a substantially constant thickness, the groove 44 is not filled up. Further, since the SiN film 45 may be formed in the entire area of the side surface 44A in the groove 44, it may not be formed on the bottom surface 44B.

Next, as shown in FIG. 101D, a photosensitive resin sheet 46 made of polyimide is attached to the wafer 30 from above the SiN film 45 other than the grooves 44. 104 (a) and 104 (b) are schematic perspective views showing a state in which a polyimide sheet is attached to the wafer in the step of FIG. 101D.
More specifically, as shown in FIG. 104 (a), after a polyimide sheet 46 is placed on the wafer 30 (strictly, the SiN film 45 on the wafer 30) from the surface 30A side, The sheet 46 is pressed against the wafer 30 by the rotating roller 47 as shown in FIG.

  As shown in FIG. 101D, when the sheet 46 is affixed to the entire surface of the SiN film 45 other than the groove 44, a part of the sheet 46 slightly enters the groove 44 side, but on the side surface 44A of the groove 44. The sheet 46 does not reach the bottom surface 44B of the groove 44 only by covering a part of the SiN film 45 on the element 5 side (surface 30A side). Therefore, in the groove 44 between the sheet 46 and the bottom surface 44 </ b> B of the groove 44, a space S having almost the same size as the groove 44 is formed. At this time, the thickness of the sheet 46 is 10 μm to 30 μm.

Next, the sheet 46 is subjected to heat treatment. Thereby, the thickness of the sheet 46 is thermally contracted to about 5 μm.
Next, as shown in FIG. 101E, the sheet 46 is patterned, and the portions of the sheet 46 that coincide with the grooves 44 and the pad regions 22 </ b> A of the wiring film 22 in a plan view are selectively removed. Specifically, the sheet 46 is exposed and developed in the pattern using the mask 62 in which the opening 61 having a pattern that matches (matches) with the groove 44 and each pad region 22A in plan view. As a result, the sheet 46 is separated above the groove 44 and each pad region 22A, and the edge portion separated in the sheet 46 slightly overlaps the groove 44 side and overlaps the SiN film 45 on the side surface 44A of the groove 44. Therefore, the above-described overhanging portion 24A (having the round-shaped side surface 24B) is naturally formed on the edge portion.

Next, by etching using the sheet 46 thus separated as a mask, portions of the SiN film 45 that correspond to the pad regions 22A in plan view are removed. Thereby, the opening 25 is formed. Here, the SiN film 45 is formed so as to expose each pad region 22A.
Next, a Ni / Pd / Au laminated film constituted by laminating Ni, Pd and Au is formed on the pad region 22A in each opening 25 by electroless plating. At this time, the Ni / Pd / Au laminated film protrudes from the opening 25 to the surface of the sheet 46. Thereby, the Ni / Pd / Au laminated film in each opening 25 becomes the first connection electrode 3 and the second connection electrode 4 shown in FIG. 101F.

  Next, after conducting an energization inspection between the first connection electrode 3 and the second connection electrode 4, the wafer 30 is ground from the back surface 30B. Here, since the entire portion of the portion forming the side surface 44A of the groove 44 in the wafer 30 is covered with the SiN film 45, it is possible to prevent the occurrence of microcracks or the like in the portion during grinding of the wafer 30, and temporarily Even if a microcrack occurs, the microcrack can be prevented from expanding by filling the microcrack with the SiN film 45.

  Then, when the wafer 30 is thinned by grinding until reaching the bottom surface 44B (strictly speaking, the SiN film 45 on the bottom surface 44B) of the groove 44, there is no connection between the adjacent semi-finished products 50. , The wafer 30 is divided, and the semi-finished product 50 becomes the electronic device 1 and is separated individually. Thereby, the electronic device 1 (see FIG. 100) is completed. In each electronic device 1, the portion that formed the side surface 44 </ b> A of the groove 44 becomes one of the side surfaces 2 </ b> C to 2 </ b> F of the substrate 2. Then, the SiN film 45 becomes the protective film 23. Further, the separated sheet 46 becomes the resin film 24.

  Even if the chip size of the electronic device 1 is small, the electronic device 1 can be divided into pieces by grinding the wafer 30 from the back surface 30B after the grooves 44 are formed in this way. Therefore, as compared with the case where the electronic device 1 is divided into pieces by dicing the wafer 30 with a dicing saw as in the prior art, cost reduction and time reduction can be achieved and yield improvement can be achieved by omitting the dicing process.

According to the above, when manufacturing the electronic device 1, the groove 44 for dividing the electronic device 1 one by one is formed on the surface 30 </ b> A (element forming surface 2 </ b> A). If it forms in the boundary of the element 5 in 30A, the side surface 44A of the groove | channel 44 will become the side surfaces 2C-2F of each electronic device 1 after a division | segmentation.
Prior to the division into the electronic device 1, the SiN film 45 (protective film 23) is formed on the side surface 44 </ b> A of the groove 44 and the surface 30 </ b> A of the wafer 30. Here, as shown in FIG. 101C, a CVD protective film (CVD protective film) 23 having substantially the same thickness is continuously formed on the upper surface of the resistor R and the inner surface (side surface 44A and bottom surface 44B) of the resistor R by the CVD method. Formed. In this case, since the formation of the CVD protective film 23 (SiN film 45) is performed in a reduced pressure environment in the course of CVD, the CVD protective film 23 serves as the side surface covering portion 23B and the side surfaces 2C to 2F (grooves 44) of the substrate 2. Can be attached to the entire side surface 44A). Therefore, the protective film 23 can be uniformly formed on the side surface 44 </ b> A of the groove 44 when the electronic device 1 is manufactured.

  Then, after the formation of the protective film 23, as shown in FIG. 101D, the resin film 24 is formed by a sheet 46 that covers the SiN film 45 (the portion of the protective film 23 that becomes the element covering portion 23A) of the element forming surface 2A. Since the resin film 24 exposes at least the side opposite to the element formation surface 2A (the bottom surface 44B side of the groove 44) in the SiN film 45 on the side surface 44A of the groove 44 (the portion that becomes the side surface covering portion 23B of the protective film 23). It is possible to prevent the grooves 44 from being filled with the resin film 24 from the bottom surface 44B side when the resin film 24 is formed (when the electronic apparatus 1 is manufactured).

Specifically, the resin film 24 is formed by sticking a sheet 46 on the protective film 23. In this case, the groove 46 is not filled from the bottom surface 44B side by the sheet 46. Therefore, as shown in FIG. 101F, if the substrate 2 is thinned until it reaches the bottom surface 44B of the groove 44, the substrate 2 can be divided into the individual electronic devices 1 in the groove 44.
As mentioned above, although embodiment of 7th invention was described, 7th invention can also be implemented with another form.

  For example, when the wafer 30 is divided into individual electronic devices 1, the wafer 30 is ground from the back surface 30B side to the bottom surface 44B of the groove 44 (see FIG. 101F). Instead, the portion of the SiN film 45 that covers the bottom surface 44B and the portion of the wafer 30 that coincides with the groove 44 in plan view are selectively etched away from the back surface 30B, thereby individually removing the wafer 30. The electronic device 1 may be divided.

105 (a) is a plan view of the electronic device, FIG. 105 (b) is a plan view of the electronic device according to the first modification, and FIG. 105 (c) is a second modification. It is a top view of the electronic device which concerns. In each of FIGS. 105 (a) to 14 (c), the element 5, the protective film 23, and the resin film 24 are not shown for convenience of explanation.
Further, the recess 10 described above is provided at a position shifted from the midpoint P of the side A on one side A of the electronic device 1 as shown in FIG. 105 (a). When the recess 10 is displaced from the midpoint P, the center 10A of the recess 10 and the midpoint P do not coincide with each other in the direction in which the side A extends. According to this configuration, not only the recess 10 side in the direction (longitudinal direction) connecting the one side A and one side B opposite to the one side A, but also the recess in the extending direction (short direction) of the one side A. The 10 side can also be in the chip direction described above. For example, in a plan view viewed from the element forming surface 2A side, the short side direction of the electronic device 1 and the front-back direction (vertical direction in FIG. 105) are matched, and the longitudinal direction of the electronic device 1 is matched with the left-right direction. When the concave portion 10 is located on the left front side (upper left side in FIG. 105), the electronic apparatus 1 can be correctly mounted on the circuit board 9. Then, when mounting, the orientation of the electronic device 1 must be aligned so that the concave portion 10 is located on the left front side in plan view (when the electronic device 1 is viewed from the back surface 2B of the substrate 2, the right front side). This can be grasped from the appearance of the electronic device 1. That is, it can be understood from the appearance of the electronic device 1 that the orientation of the electronic device 1 in both the longitudinal direction and the short direction must be matched.

  Of course, as shown in FIG. 105 (b), the recess 10 may be provided at a position where one side A coincides with the midpoint P (a position where the center 10A of the recess 10 coincides with the midpoint P in the short direction). . Moreover, you may provide the convex part 51 which protrudes outward instead of the recessed part 10, as shown in FIG.105 (c). The convex portion 51 may have a rectangular shape in plan view, or may have a U shape (a shape that bulges into a U shape) or a triangular shape. Of course, in the side surface 2 </ b> C, the corner portion (four corner portions in a plan view including the tip side and the root side of the convex portion 51) 52 of the convex portion 51 is also chamfered, like the other corner portions 11. It has become. Here, the side surface covering portion 23 </ b> B (see FIG. 92A) covers the entire area including the portion where the convex portion 51 is formed on the side surface 2 </ b> C, as in the case of the concave portion 10. Moreover, it is preferable that the depth of the recessed part 10 and the height (projection amount) of the convex part 51 are 20 micrometers or less (about 1/5 or less of the width of the 1st connection electrode 3 or the 2nd connection electrode 4). And as for the chamfering amount in each of the corner part 11, the corner part 12, and the corner part 52, it is preferable that the distance of one side is about 20 micrometers or less.

FIG. 106A is a diagram illustrating a circuit configuration of an element according to another embodiment of the electronic device, and FIG. 106B is a diagram illustrating a circuit configuration of an element according to still another embodiment of the electronic device. It is.
In the embodiment described above, since the electronic device 1 is a chip resistor, the element 5 between the first connection electrode 3 and the second connection electrode 4 is the resistor 56, but the diode 55 shown in FIG. Alternatively, a diode 55 and a resistor 56 may be connected in series as shown in FIG. The electronic device 1 becomes a chip diode by having the diode 55, and the first connection electrode 3 and the second connection electrode 4 have polarity, but the above-described chip direction is a direction corresponding to the polarity. Thereby, since the polarity of the 1st connection electrode 3 and the 2nd connection electrode 4 can be shown with a chip | tip direction, the said polarity can be grasped | ascertained by the external appearance of the electronic device 1. FIG. That is, it can be seen which side in the chip direction (that is, which of the first connection electrode 3 and the second connection electrode 4) is the positive or negative pole side. Therefore, the electronic device 1 can be correctly mounted on the circuit board 9 (see FIG. 92B) so that the side on which the concave portion 10 and the convex portion 51 (see FIG. 105) described above are provided on the corresponding pole side. Can be.

Of course, the seventh invention can be applied to an element device in which various elements such as a chip capacitor in which a capacitor is used instead of the diode 55 in the element 5 and a chip inductor are formed on the chip-sized substrate 2. .
<Eighth Invention>
(1) Features of the eighth invention For example, the features of the eighth invention are the following G1 to G18.
(G1) A substrate having an element formation surface, a resistor formed on the element formation surface, a wiring film connected to the resistor and having a trimming target region, and covering the wiring film in the trimming target region A chip resistor, wherein the insulating film is a CVD insulating film formed by chemical vapor deposition.

  According to this configuration, when laser light is irradiated to the wiring film in the region for laser trimming of the wiring film in the region to be trimmed, the laser light passes through the insulating film on the wiring film in the region. Reach the wiring film. In this case, since the energy of the laser beam is easily concentrated on the wiring film, reliable trimming of the wiring film can be realized. In particular, since this insulating film is a CVD insulating film, the film quality of the insulating film in the entire region to be trimmed can be stabilized, so that reliable trimming of the wiring film can be realized in any part of the region.

In addition, since the wiring film is covered with the insulating film, even if a fragment is generated by laser trimming, the fragment does not become a foreign substance and contacts the wiring film to cause a short circuit. That is, a short circuit caused by trimming can be prevented.
(G2) The chip resistor according to G1, wherein the insulating film has a thickness of 1000 to 5000 mm.

According to this configuration, the energy of the laser beam can be efficiently concentrated on the wiring film, so that reliable trimming of the wiring film can be effectively realized. If the insulating film is thinner than 1000 mm, the effect of efficiently concentrating the energy of the laser light on the wiring film is reduced. Conversely, if the insulating film is thicker than 5000 mm, the insulating film is cut by the laser light. This makes it difficult to trim the wiring film.
(G3) The chip resistor according to G2, wherein the insulating film is a SiN film formed by CVD.
(G4) In any one of G1 to G3, the resistor is formed of a plurality of resistors having the same resistance value, and the connection state of the resistors can be changed in the trimming target region. Chip resistor described.
(G5) The chip resistor according to any one of G1 to G3, wherein the resistor is formed below a wiring film in the trimming target region.
(G6) The chip resistor according to any one of G1 to G5, wherein the insulating film also serves as a protective film that covers the element formation surface.

According to this configuration, the insulating film can surely trim the wiring film, and can prevent not only a short circuit due to the trimming but also protect the element formation surface.
(G7) The chip resistor according to any one of G1 to G6, wherein the wiring film has a fused part in the trimming target region.

According to this configuration, in the chip resistor, the resistance value can be adjusted according to the melted portion.
(G8) The chip resistor according to G7, which includes an insulating layer different from the insulating film between the substrate and the resistor.
(G9) The chip resistor according to G8, wherein a part of the insulating layer is cut together with the wiring film at a location where the wiring film is melted.
(G10) The chip resistor according to any one of G1 to G9, wherein the wiring film includes a wiring arranged in the trimming target region and having a wiring-to-wiring distance larger than a portion other than the trimming target region.

According to this configuration, the resistance value of the chip resistor can be adjusted by trimming (melting) the wiring.
(G11) The chip resistor according to any one of G1 to G10, wherein the wiring film includes aluminum, and the insulating film includes silicon nitride.
According to this configuration, since the generation temperature of silicon nitride in the insulating film during CVD is lower than the melting temperature of aluminum in the wiring film, the insulating film can be formed on the wiring film without melting the wiring film. it can.
(G12) Forming a resistor on the element formation surface of the substrate, forming a wiring film connected to the resistor on the element formation surface, and insulating so as to cover a region to be trimmed of the wiring film Forming a film, and a method of manufacturing a chip resistor.

According to this method, when the wiring film in the region to be trimmed is laser-trimmed to the wiring film in the region to be trimmed, the laser light is transmitted through the insulating film on the wiring film in the region. Reach the wiring film. In this case, since the energy of the laser beam is easily concentrated on the wiring film, reliable trimming of the wiring film can be realized.
In addition, since the wiring film is covered with the insulating film, even if a fragment is generated by laser trimming, the fragment does not become a foreign substance and contacts the wiring film to cause a short circuit. That is, a short circuit caused by trimming can be prevented.
(G13) The method for manufacturing the chip resistor according to G12, wherein the step of forming the insulating film includes a step of forming the insulating film by chemical vapor deposition.

Thereby, since the film quality of the insulating film in the entire area of the trimming target region can be stabilized, reliable trimming of the wiring film can be realized in any part of the region.
(G14) The method for manufacturing a chip resistor according to G12 or G13, wherein the insulating film is formed to a thickness of 1000 to 5000 mm.
Thereby, the energy of the laser beam can be efficiently concentrated on the wiring film, so that reliable trimming of the wiring film can be effectively realized. If the insulating film is thinner than 1000 mm, the effect of efficiently concentrating the energy of the laser light on the wiring film is reduced. Conversely, if the insulating film is thicker than 5000 mm, the insulating film is cut by the laser light. This makes it difficult to trim the wiring film.
(G15) The method of manufacturing a chip resistor according to any one of G12 to G14, wherein the resistor is formed below the wiring film in the trimming target region.
(G16) The insulating film according to any one of G12 to G15, wherein the insulating film is formed to extend to a region other than the trimming target region on the element formation surface, and also serves as a protective film for protecting the element formation surface. Method for manufacturing a chip resistor.

As a result, the insulating film can surely trim the wiring film, and can not only prevent a short circuit due to the trimming but also protect the element formation surface.
(G17) The method of manufacturing a chip resistor according to any one of G12 to G16, further including a step of fusing the wiring film with a laser beam so as to have a necessary resistance value in the trimming target region.

Thereby, the resistance value of the chip resistor can be adjusted.
(G18) The method of manufacturing a chip resistor according to any one of G12 to G17, wherein the step of forming the wiring film includes a step of forming a fuse in the trimming target region.
Thereby, the resistance value of the chip resistor can be adjusted by trimming the fuse.
(2) Embodiment of Eighth Invention Hereinafter, an embodiment of the eighth invention will be described in detail with reference to the accompanying drawings. The reference numerals shown in FIGS. 107 to 123 are effective only in these drawings, and even if they are used in other embodiments, they do not indicate the same elements as those in the other embodiments.

FIG. 107 (a) is a schematic perspective view for explaining the configuration of the chip resistor according to one embodiment of the eighth invention, and FIG. 107 (b) is a diagram showing that the chip resistor is mounted on a circuit board. It is a typical side view which shows the state.
This chip resistor 1 is a minute chip component and has a rectangular parallelepiped shape as shown in FIG. 107 (a). Regarding the dimensions of the chip resistor 1, the length L in the long side direction is about 0.3 mm, the width W in the short side direction is about 0.15 mm, and the thickness T is about 0.1 mm.

The chip resistor 1 is formed by forming a plurality of chip resistors 1 on a substrate in a lattice pattern, forming grooves in the substrate, and then polishing the back surface (or dividing the substrate by the grooves) to obtain individual chips. It is obtained by separating the resistor 1.
The chip resistor 1 mainly includes a substrate 2, a first connection electrode 3 and a second connection electrode 4 serving as external connection electrodes, and an element 5.

  The substrate 2 has a substantially rectangular parallelepiped chip shape. In the substrate 2, the upper surface in FIG. 107 (a) is the element formation surface 2A. The element formation surface 2A is the surface of the substrate 2 and has a substantially rectangular shape. The surface opposite to the element formation surface 2A in the thickness direction of the substrate 2 is a back surface 2B. The element formation surface 2A and the back surface 2B have substantially the same shape. In addition to the element formation surface 2A and the back surface 2B, the substrate 2 has a side surface 2C, a side surface 2D, a side surface 2E, and a side surface 2F that extend perpendicularly to these surfaces and connect these surfaces.

  The side surface 2C extends between one end edge in the longitudinal direction of the element formation surface 2A and the back surface 2B (the left front edge in FIG. 107A), and the side surface 2D extends in the longitudinal direction of the element formation surface 2A and the back surface 2B. It is constructed between the other ends in the direction (the edge on the right back side in FIG. 107 (a)). The side surface 2C and the side surface 2D are both end surfaces of the substrate 2 in the longitudinal direction. The side surface 2E extends between one edge in the short direction of the element formation surface 2A and the back surface 2B (the left edge on the left side in FIG. 107A), and the side surface 2F includes the element formation surface 2A and the back surface 2B. Between the other edges in the short direction (the edge on the right front side in FIG. 107 (a)). The side surface 2E and the side surface 2F are both end surfaces of the substrate 2 in the lateral direction. Each of the side surface 2C and the side surface 2D intersects (strictly, orthogonally) with each of the side surface 2E and the side surface 2F.

  In the substrate 2, the entire element formation surface 2 </ b> A is covered with the insulating film 23. Therefore, strictly speaking, in FIG. 107A, the entire area of the element formation surface 2A is located on the inner side (back side) of the insulating film 23 and is not exposed to the outside. Further, the insulating film 23 on the element formation surface 2A is covered with a resin film 24. The resin film 24 protrudes from the element formation surface 2A to the end portion on the element formation surface 2A side (the upper end portion in FIG. 107A) of each of the side surface 2C, the side surface 2D, the side surface 2E, and the side surface 2F. The insulating film 23 and the resin film 24 will be described in detail later.

  In the rectangular parallelepiped substrate 2, a crossing portion 11 (a corner portion forming a boundary between the adjacent ones) 11 where the adjacent ones of the back surface 2B, the side surface 2C, the side surface 2D, the side surface 2E, and the side surface 2F intersect is chamfered. It is shaped into a round shape and rounded. Here, in each crossing part 11, it is preferable that a round-shaped curvature radius is 20 micrometers or less.

  Thus, in the outline of the board | substrate 2 in each of planar view (bottom view) and side view, all the bent parts (intersection part 11) are round shape. Therefore, chipping can be prevented from occurring at each round-shaped crossing portion 11 (corner portion) when the chip resistor 1 holding the crossing portion 11 is handled or transported. Thereby, in manufacture of the chip resistor 1, a yield improvement (improvement of productivity) can be aimed at.

  The first connection electrode 3 and the second connection electrode 4 are formed on the element formation surface 2 </ b> A of the substrate 2 and are partially exposed from the resin film 24. Each of the first connection electrode 3 and the second connection electrode 4 is configured, for example, by stacking Ni (nickel), Pd (palladium), and Au (gold) on the element formation surface 2A in this order. The first connection electrode 3 and the second connection electrode 4 are arranged at intervals in the longitudinal direction of the element formation surface 2A, and are long in the short direction of the element formation surface 2A. In FIG. 107A, on the element formation surface 2A, the first connection electrode 3 is provided near the side surface 2C, and the second connection electrode 4 is provided near the side surface 2D.

  The element 5 is a circuit element, and is formed in a region between the first connection electrode 3 and the second connection electrode 4 on the element formation surface 2A of the substrate 2, and from above by the insulating film 23 and the resin film 24. It is covered. The element 5 of this embodiment is a circuit network in which a plurality of thin film resistors (thin film resistors) R made of TiN (titanium nitride) or TiON (titanium oxynitride) are arranged in a matrix on the element formation surface 2A. A configured resistor 56. The element 5 (resistor R) is electrically connected to a wiring film 22 described later, and is electrically connected to the first connection electrode 3 and the second connection electrode 4 via the wiring film 22. Thereby, in the chip resistor 1, a resistance circuit including the element 5 is formed between the first connection electrode 3 and the second connection electrode 4.

  As shown in FIG. 107 (b), the first connection electrode 3 and the second connection electrode 4 are opposed to the circuit board 9, and electrical and mechanical to the circuit (not shown) of the circuit board 9 by the solder 13. Thus, the chip resistor 1 can be mounted on the circuit board 9 (flip chip connection). The first connection electrode 3 and the second connection electrode 4 that function as external connection electrodes are formed of gold (Au) or are plated with gold in order to improve solder wettability and reliability. It is desirable.

FIG. 108 is a plan view of the chip resistor, showing the arrangement relationship of the first connection electrode, the second connection electrode and the element, and the configuration of the element in plan view.
Referring to FIG. 108, as an example, element 5 serving as a resistor network includes eight resistors R arranged in the row direction (longitudinal direction of substrate 2) and the column direction (of substrate 2). It has a total of 352 resistors R composed of 44 resistors R arranged along the width direction. Each resistor R has an equal resistance value. That is, the group of resistors R (element 5, resistor 56) is formed of a plurality of resistors R having the same resistance value.

  A plurality of types of resistance unit bodies (unit resistances) are formed by grouping and electrically connecting a large number of these resistor bodies R every predetermined number of 1 to 64 pieces. The formed plural types of resistance unit bodies are connected in a predetermined manner via the connecting conductor film C. Further, a plurality of fuse films (fuses) that can be blown on the element formation surface 2A of the substrate 2 in order to electrically incorporate the resistance unit body into the element 5 or to electrically separate it from the element 5. ) F is provided. The plurality of fuse films F and connection conductor films C are arranged along the inner side of the second connection electrode 4 so that the arrangement region is linear. More specifically, a plurality of fuse films F and connecting conductor films C are arranged in a straight line.

FIG. 109A is an enlarged plan view of a part of the element shown in FIG. FIG. 109B is a longitudinal cross-sectional view in the length direction along BB of FIG. 109A drawn to explain the configuration of the resistor in the element. FIG. 109C is a longitudinal sectional view in the width direction along CC of FIG. 109A drawn to explain the configuration of the resistor in the element.
The configuration of the resistor R will be described with reference to FIGS. 109A, 109B, and 109C.

The chip resistor 1 further includes an insulating layer 20 and a resistor film 21 in addition to the wiring film 22, the insulating film 23, and the resin film 24 described above (see FIGS. 109B and 109C). The insulating layer 20, the resistor film 21, the wiring film 22, the insulating film 23, and the resin film 24 are formed on the substrate 2 (element formation surface 2A).
The insulating layer 20 is made of SiO ₂ (silicon oxide). The insulating layer 20 covers the entire area of the element formation surface 2A of the substrate 2. The insulating layer 20 has a thickness of about 10,000 mm. The insulating layer 20 and the insulating film 23 are different from each other.

  The resistor film 21 constitutes the resistor R. The resistor film 21 is made of TiN or TiON and is laminated on the surface of the insulating layer 20. The thickness of the resistor film 21 is about 2000 mm. The resistor film 21 forms a plurality of lines (hereinafter referred to as “resistor film line 21 </ b> A”) extending in a line between the first connection electrode 3 and the second connection electrode 4. 21A may be cut at a predetermined position in the line direction (see FIG. 109A).

A wiring film 22 is laminated on the resistor film line 21A. The wiring film 22 is made of Al (aluminum) or an alloy of aluminum and Cu (copper) (AlCu alloy). The thickness of the wiring film 22 is about 8000 mm. The wiring film 22 is laminated on the resistor film line 21A with a constant interval R in the line direction.
The electrical characteristics of the resistor film line 21A and the wiring film 22 having this configuration are shown by circuit symbols as shown in FIG. That is, as shown in FIG. 110 (a), each of the resistor film lines 21A in the region of the predetermined interval R forms one resistor R having a constant resistance value r.

In the region where the wiring film 22 is laminated, the resistor film lines 21 </ b> A are short-circuited by the wiring film 22 by electrically connecting the resistors R adjacent to each other. Therefore, a resistor circuit is formed which is formed by connecting the resistors R of the resistor r shown in FIG. 110 (b) in series.
Further, since the adjacent resistor film lines 21A are connected to each other by the resistor film 21 and the wiring film 22, the resistor network of the element 5 shown in FIG. 109A is shown in FIG. A resistor circuit (consisting of R unit resistors) is formed. Thus, the resistor film 21 and the wiring film 22 constitute the element 5.

Here, based on the characteristic that the same-shaped and large-sized resistor films 21 formed on the substrate 2 have substantially the same value, a large number of resistors R arranged in a matrix on the substrate 2 have the same resistance. Has a value.
Further, the wiring film 22 laminated on the resistor film line 21A forms a resistor R and also serves as a connecting wiring film for connecting a plurality of resistors R to form a resistance unit body. Plays.

FIG. 111A is a partially enlarged plan view of a region including a fuse film drawn by enlarging a part of the plan view of the chip resistor shown in FIG. 108, and FIG. 111B is a plan view of FIG. It is a figure which shows the cross-sectional structure which follows BB.
As shown in FIGS. 111A and 111B, the above-described fuse film F and connecting conductor film C are also formed by the wiring film 22 laminated on the resistor film 21 that forms the resistor R. . That is, on the same layer as the wiring film 22 laminated on the resistor film line 21A forming the resistor R, the fuse film F and the connecting conductor film C are formed of Al or AlCu alloy which is the same metal material as the wiring film 22. Is formed.

  That is, in the same layer laminated on the resistor film 21, the wiring film for forming the resistor R, the fuse film F, the connecting conductor film C, and the element 5 are connected to the first connection electrode 3. A wiring film for connecting to the second connection electrode 4 is formed as the wiring film 22 using the same metal material (Al or AlCu alloy). Note that the fuse film F is different from (differentiated from) the wiring film 22 because the fuse film F is formed so as to be easily cut and other circuit elements around the fuse film F. This is because they are arranged so that they do not exist.

  Here, in the wiring film 22, a region where the fuse film F is disposed is referred to as a trimming target region X (see FIGS. 108 and 111 (a)). The trimming target region X is a linear region along the inner side of the second connection electrode 4, and not only the fuse film F but also the connecting conductor film C is disposed in the trimming target region X. In addition, the resistor film 21 is formed below the wiring film 22 in the trimming target region X (see FIG. 111B). The fuse film F is a wiring having a larger inter-wiring distance (separated from the surroundings) than the portion other than the trimming target region X in the wiring film 22.

The fuse film F is not only a part of the wiring film 22 but also a group (fuse element) of a part of the resistor R (resistor film 21) and a part of the wiring film 22 on the resistor film 21. You may point.
The fuse film F has been described only in the case where the same layer as the connecting conductor film C is used. However, the connecting conductor film C is formed by stacking another conductor film on the conductor film C. The resistance value may be lowered. Even in this case, if the conductor film is not laminated on the fuse film F, the fusing property of the fuse film F does not deteriorate.

FIG. 112 is an electric circuit diagram of an element according to the embodiment of the eighth invention.
Referring to FIG. 112, element 5 includes reference resistance unit R8, resistance unit R64, two resistance units R32, resistance unit R16, resistance unit R8, resistance unit R4, resistance unit R2, The resistance unit body R1, the resistance unit body R / 2, the resistance unit body R / 4, the resistance unit body R / 8, the resistance unit body R / 16, and the resistance unit body R / 32 are arranged in this order from the first connection electrode 3. It is configured by connecting in series. Each of the reference resistance unit R8 and the resistance unit bodies R64 to R2 is configured by connecting in series the same number of resistors R as the last number (“64” in the case of R64). The resistance unit R1 is composed of one resistor R. Each of the resistance unit bodies R / 2 to R / 32 is configured by connecting in parallel the same number of resistor bodies R as the last number of itself (“32” in the case of R / 32). The meaning of the number at the end of the resistance unit body is the same in FIGS. 113 and 114 described later.

One fuse film F is connected in parallel to each of the resistance unit bodies R64 to R / 32 other than the reference resistance unit body R8. The fuse films F are connected in series either directly or via a connecting conductor film C (see FIG. 111A).
As shown in FIG. 112, in a state where all the fuse films F are not blown, the element 5 is composed of eight resistors R provided in series between the first connection electrode 3 and the second connection electrode 4. A resistance circuit of the reference resistance unit R8 (resistance value 8r) is configured. For example, if the resistance value r of one resistor R is r = 8Ω, the chip resistor 1 in which the first connection electrode 3 and the second connection electrode 4 are connected by a resistance circuit of 8r = 64Ω is configured. Yes.

  Further, in a state where all the fuse films F are not blown, a plurality of types of resistance unit bodies other than the reference resistance unit body R8 are short-circuited. That is, 12 types of 13 resistance unit bodies R64 to R / 32 are connected in series to the reference resistance unit body R8, but each resistance unit body is short-circuited by the fuse film F connected in parallel. Therefore, when viewed electrically, each resistance unit is not incorporated in the element 5.

  In the chip resistor 1 according to this embodiment, the fuse film F is selectively blown by, for example, laser light according to a required resistance value. Thereby, the resistance unit body in which the fuse films F connected in parallel are melted is incorporated into the element 5. Therefore, the entire resistance value of the element 5 can be a resistance value in which resistance unit bodies corresponding to the blown fuse film F are connected in series and incorporated.

  In particular, in the plurality of types of resistance unit bodies, the resistor R having the same resistance value is one, two, four, eight, sixteen, thirty-two, etc. in series. The number of the series resistor unit bodies connected by increasing the number of resistors and the resistors R having the same resistance value are two, four, eight, sixteen, etc. in parallel. A plurality of types of parallel resistance units connected in increasing numbers are provided. Therefore, by selectively fusing the fuse film F (including the above-described fuse element), the resistance value of the entire element 5 (resistor 56) is adjusted finely and digitally to an arbitrary resistance value. Thus, the chip resistor 1 can generate a desired value of resistance.

FIG. 113 is an electric circuit diagram of an element according to another embodiment of the eighth invention.
Instead of configuring the element 5 by connecting the reference resistance unit R / 16 and the resistance unit R64 to the resistance unit R / 32 in series as described above, the element 5 may be configured as shown in FIG. Absent. Specifically, between the first connection electrode 3 and the second connection electrode 4, the reference resistance unit body R / 16 and the 12 types of resistance unit bodies R / 16, R / 8, R / 4, R / 2, R1 , R2, R4, R8, R16, R32, R64, R128 may be used to form the element 5 in a series connection circuit.

  In this case, the fuse film F is connected in series to each of the 12 types of resistance unit bodies other than the reference resistance unit body R / 16. In a state where all the fuse films F are not blown, each resistance unit body is electrically incorporated into the element 5. If the fuse film F is selectively blown, for example, by laser light, according to the required resistance value, a resistance unit body corresponding to the blown fuse film F (a resistance unit body in which the fuse film F is connected in series) ) Is electrically separated from the element 5, the resistance value of the entire chip resistor 1 can be adjusted.

FIG. 114 is an electric circuit diagram of an element according to still another embodiment of the eighth invention.
The element 5 shown in FIG. 114 has a circuit configuration in which a plurality of types of resistance unit bodies are connected in series and a plurality of types of resistance unit bodies are connected in series. As in the previous embodiment, the fuse film F is connected in parallel to each of the plurality of types of resistance unit bodies connected in series, and the plurality of types of resistance unit bodies connected in series are all The fuse film F is short-circuited. Therefore, when the fuse film F is blown, the resistance unit body short-circuited by the blown fuse film F is electrically incorporated into the element 5.

On the other hand, a fuse film F is connected in series to each of a plurality of types of resistance unit bodies connected in parallel. Therefore, by fusing the fuse film F, the resistance unit body to which the blown fuse film F is connected in series can be electrically disconnected from the parallel connection of the resistance unit bodies.
With this configuration, for example, a small resistance of 1 kΩ or less is made on the parallel connection side, and if a resistance circuit of 1 kΩ or more is made on the series connection side, a wide range from a small resistance of several Ω to a large resistance of several MΩ is obtained. Resistor circuits can be made using a network of resistors constructed with an equal basic design.

As described above, in the chip resistor 1, the connection state of the plurality of resistors R (resistance unit bodies) can be changed in the trimming target region X.
FIG. 115 is a schematic cross-sectional view of a chip resistor.
Next, the chip resistor 1 will be described in more detail with reference to FIG. For convenience of explanation, in FIG. 115, the element 5 described above is simplified and each element other than the substrate 2 is hatched.

Here, the insulating film 23 and the resin film 24 described above will be described.
The insulating film 23 is a film made of, for example, SiN (silicon nitride), and has a thickness of 1000 to 5000 mm (here, about 3000 mm). The insulating film 23 is provided over the entire element formation surface 2A, and covers the resistor film 21 and each wiring film 22 (that is, the element 5) on the resistor film 21 from the surface (upper side in FIG. 115). The upper surface of each resistor R in the element 5 is covered. Therefore, the insulating film 23 also covers the wiring film 22 in the trimming target region X described above (see FIG. 111B). The insulating film 23 is in contact with the element 5 (the wiring film 22 and the resistor film 21), and is also in contact with the insulating layer 20 in a region other than the resistor film 21. Thereby, the insulating film 23 functions as a protective film that covers the entire element forming surface 2A and protects the element 5 and the insulating layer 20.

Further, the insulating film 23 prevents a short circuit between the resistors R other than the wiring film 22 (short circuit between adjacent resistor film lines 21A).
Note that the surface of the end 23A located at the edge of the element formation surface 2A in the insulating film 23 swells toward the side (outside the chip resistor 1 (substrate 2) in the direction along the element formation surface 2A). It is curved so that it comes out.

Although not shown, the insulating film 23 protrudes from the element formation surface 2A and is a portion exposed to the side surfaces 2C to 2F in the insulating layer 20 or a boundary portion with the element formation surface 2A in each of the side surfaces 2C to 2F. May be coated.
The resin film 24 protects the element formation surface 2A of the chip resistor 1 together with the insulating film 23, and is made of a resin such as polyimide. The thickness of the resin film 24 is about 5 μm. The resin film 24 covers the entire surface of the insulating film 23 (including the resistor film 21 and the wiring film 22 covered with the insulating film 23) over the entire area, and the element formation surface on each of the side surfaces 2C to 2F. The boundary part with 2A (upper end part in FIG. 115) and the part exposed to the side surfaces 2C to 2F in the insulating layer 20 are covered. Therefore, portions of the four side surfaces 2C to 2F opposite to the element formation surface 2A (the lower side in FIG. 115) are exposed to the outside as the outer surface of the chip resistor 1.

  Thus, since the insulating film 23 covers the resistor film 21 (thin film resistor R) and the wiring film 22 and the resin film 24 covers the surface of the insulating film 23, the thin film resistor R and the wiring film 22 ( The element formation surface 2 </ b> A) can be double protected by the insulating film 23 and the resin film 24. Furthermore, since the foreign film is prevented from adhering to the thin film resistor R and the wiring film 22 by the insulating film 23 and the resin film 24, a short circuit in the thin film resistor R and the wiring film 22 can be prevented.

  In the resin film 24, portions that coincide with the four side surfaces 2 </ b> C to 2 </ b> F in a plan view are arcuate bulging portions 24 </ b> A that bulge to the side (outside) of the substrate 2 from these side surfaces. That is, the resin film 24 (the bulging portion 24A) protrudes beyond the side surfaces 2C to 2F (corresponding side surfaces) on the side surfaces 2C to 2F. Such a resin film 24 has a round-shaped side surface 24B convex toward the side in the arcuate bulge portion 24A.

  Here, at the intersection 27 that forms the boundary between the element formation surface 2A and each of the side surfaces 2C to 2F, the element formation surface 2A and each of the side surfaces 2C to 2F intersect. It is an angular shape that is different from the round shape (round shape of the intersecting portion 11). Therefore, the bulging portion 24 </ b> A covers each crossing portion 27. In this case, occurrence of chipping at the intersection 27 can be prevented by the resin film 24. Further, since the bulging portion 24A bulges outward (outside the substrate 2 in the direction along the element forming surface 2A) from the side surfaces 2C to 2F at the intersection portion 27, the chip resistor 1 is moved to the surroundings. At the time of contact, the bulging portion 24A first comes into contact with the surrounding thing to alleviate the impact caused by the contact, so that the impact can be prevented from reaching the element 5 and the like. In particular, since the bulging portion 24A has the round-shaped side surface 24B, the impact caused by the contact can be smoothly reduced.

In addition, the resin film 24 is provided in a region away from the intersecting portion 27 side (from the back surface 2B to the element formation surface 2A side) on the side surfaces 2C to 2F. However, there may be a configuration in which the resin film 24 does not cover the side surfaces 2C to 2F (a configuration in which all of the side surfaces 2C to 2F are exposed).
In the resin film 24, one opening 25 is formed at two positions separated in a plan view. Each opening 25 is a through hole that continuously penetrates the resin film 24 and the insulating film 23 in the respective thickness directions. Therefore, the opening 25 is formed not only in the resin film 24 but also in the insulating film 23. A part of the wiring film 22 is exposed from each opening 25. A portion of the wiring film 22 exposed from each opening 25 is a pad region 22A for external connection.

  Of the two openings 25, one opening 25 is filled with the first connection electrode 3, and the other opening 25 is filled with the second connection electrode 4. A part of each of the first connection electrode 3 and the second connection electrode 4 protrudes from the opening 25 on the surface of the resin film 24. The first connection electrode 3 is electrically connected to the wiring film 22 in the pad region 22 </ b> A in the opening 25 through the one opening 25. The second connection electrode 4 is electrically connected to the wiring film 22 in the pad region 22 </ b> A in the opening 25 through the other opening 25. Thereby, each of the first connection electrode 3 and the second connection electrode 4 is electrically connected to the element 5. Here, the wiring film 22 forms wiring connected to each of the group of resistors R (resistor 56), the first connection electrode 3, and the second connection electrode 4.

  As described above, the resin film 24 and the insulating film 23 in which the opening 25 is formed cover the element formation surface 2 </ b> A in a state where the first connection electrode 3 and the second connection electrode 4 are exposed from the opening 25. Therefore, electrical connection between the chip resistor 1 and the circuit board 9 can be achieved via the first connection electrode 3 and the second connection electrode 4 protruding from the opening 25 on the surface of the resin film 24 ( FIG. 107 (b)).

116A to 116G are schematic sectional views showing a method for manufacturing the chip resistor shown in FIG. 115.
First, as shown in FIG. 116A, a substrate 30 as a base of the substrate 2 is prepared. In this case, the front surface 30A of the substrate 30 is the element formation surface 2A of the substrate 2, and the back surface 30B of the substrate 30 is the back surface 2B of the substrate 2.

Then, the insulating layer 20 made of SiO ₂ or the like is formed on the surface 30A of the substrate 30, and the element 5 (the resistor R and the wiring film 22 connected to the resistor R) is formed on the insulating layer 20. Specifically, first, a TiN or TiON resistor film 21 is formed on the entire surface of the insulating layer 20 by sputtering, and an aluminum (Al) wiring film 22 is stacked on the resistor film 21. . Thereafter, using a photolithography process, the resistor film 21 and the wiring film 22 are selectively removed by, for example, dry etching, and as shown in FIG. 109A, a resistor having a certain width in which the resistor film 21 is stacked in a plan view. A configuration is obtained in which the body membrane lines 21A are arranged in the column direction at regular intervals. At this time, a region in which the resistor film line 21A and the wiring film 22 are partially cut is also formed, and the fuse film F and the connecting conductor film C are formed in the trimming target region X (see FIG. 108). ). Subsequently, the wiring film 22 stacked on the resistor film line 21A is selectively removed. As a result, the element 5 having a configuration in which the wiring film 22 is laminated on the resistor film line 21A with a predetermined interval R is obtained.

  Referring to FIG. 116A, the elements 5 are formed at a number of locations on the surface 30 </ b> A of the substrate 30 according to the number of chip resistors 1 formed on one substrate 30. One region where the element 5 (the resistor 56 described above) is formed on the substrate 30 is referred to as a chip resistor region Y. On the surface 30A of the substrate 30, a plurality of chip resistor regions Y each having a resistor 56 (that is, Element 5) is formed. A region between adjacent chip resistor regions Y on the surface 30A of the substrate 30 is referred to as a boundary region Z.

  Next, as shown in FIG. 116A, an insulating film (CVD insulating film) 45 made of SiN is formed over the entire surface 30A of the substrate 30 by a CVD (Chemical Vapor Deposition) method. The formed CVD insulating film 45 has a thickness of 1000 to 5000 mm (here, about 3000 mm). The CVD insulating film 45 covers all of the insulating layer 20 and the element 5 (the resistor film 21 and the wiring film 22) on the insulating layer 20, and is in contact with them. Therefore, the CVD insulating film 45 also covers the wiring film 22 in the above-described trimming target region X (see FIG. 108). Further, since the CVD insulating film 45 is formed over the entire area of the surface 30A of the substrate 30, the CVD insulating film 45 is formed to extend to a region other than the trimming target region X on the surface 30A. Thereby, the CVD insulating film 45 becomes a protective film for protecting the entire surface 30A (including the element 5 on the surface 30A).

Next, as shown in FIG. 116B, a resist pattern 41 is formed over the entire surface 30 </ b> A of the substrate 30 so as to cover the entire CVD insulating film 45. An opening 42 is formed in the resist pattern 41.
117 is a schematic plan view of a part of a resist pattern used for forming a groove in the step of FIG. 116B.

  Referring to FIG. 117, the openings 42 of the resist pattern 41 are viewed in plan view when a large number of chip resistors 1 (in other words, the above-described chip resistor regions Y) are arranged in a matrix (also in a lattice shape). And the area between the outlines of the adjacent chip resistors 1 (the hatched portion in FIG. 117, in other words, the boundary area Z). Therefore, the entire shape of the opening 42 is a lattice shape having a plurality of linear portions 42A and 42B orthogonal to each other.

In the resist pattern 41, the straight portions 42A and 42B orthogonal to each other in the opening 42 are connected to each other while maintaining a state orthogonal to each other (without bending). Therefore, the intersecting portion 43 of the straight portions 42A and 42B is pointed so as to form approximately 90 ° in plan view.
Referring to FIG. 116B, each of CVD insulating film 45, insulating layer 20, and substrate 30 is selectively removed by plasma etching using resist pattern 41 as a mask. As a result, the material of the substrate 30 is removed in the boundary region Z between the adjacent elements 5 (chip resistor region Y). As a result, a groove 44 that penetrates the CVD insulating film 45 and the insulating layer 20 and reaches the middle of the thickness of the substrate 30 is formed at a position (boundary region Z) that coincides with the opening 42 of the resist pattern 41 in plan view. The The groove 44 has a side surface 44A that faces each other and a bottom surface 44B that connects a lower end of the facing side surface 44A (an end on the back surface 30B side of the substrate 30). The depth of the groove 44 with respect to the surface 30A of the substrate 30 is about 100 μm, and the width of the groove 44 (the interval between the opposing side surfaces 44A) is about 20 μm.

118 (a) is a schematic plan view of the substrate after the grooves are formed in the step of FIG. 116B, and FIG. 118 (b) is a partially enlarged view of FIG. 118 (a).
Referring to FIG. 118B, the overall shape of the groove 44 is a lattice shape that coincides with the opening 42 (see FIG. 117) of the resist pattern 41 in plan view. On the surface 30A of the substrate 30, the rectangular frame portion (boundary region Z) in the groove 44 surrounds the chip resistor region Y where the elements 5 are formed. A portion where the element 5 is formed on the substrate 30 is a semi-finished product 50 of the chip resistor 1. On the surface 30 </ b> A of the substrate 30, the semi-finished products 50 are located one by one in the chip resistor region Y surrounded by the grooves 44, and these semi-finished products 50 are arranged in a matrix.

Then, according to the sharply intersecting portion 43 (see FIG. 117) in the opening 42 of the resist pattern 41, the corner portion 60 (corresponding to the intersecting portion 11 of the chip resistor 1) of the semi-finished product 50 in plan view is substantially perpendicular. Pointed to.
After the trench 44 is formed as shown in FIG. 116B, the resist pattern 41 is removed, and the CVD insulating film 45 is selectively removed by etching using the mask 65 as shown in FIG. 116C. In the mask 65, an opening 66 is formed in a portion of the CVD insulating film 45 that coincides with each pad region 22A (see FIG. 115) in plan view. As a result, a portion corresponding to the opening 66 in the CVD insulating film 45 is removed by etching, and the opening 25 is formed in the portion. As a result, the CVD insulating film 45 is formed so as to expose each pad region 22A in the opening 25. Two openings 25 are formed for one semi-finished product 50.

FIG. 119A is a schematic cross-sectional view during the manufacture of the chip resistor according to one embodiment of the eighth invention. FIG. 119B is a schematic cross-sectional view during the manufacture of the chip resistor according to the comparative example.
In each semi-finished product 50, after forming the two openings 25 in the CVD insulating film 45 as shown in FIG. 116C, the probe 70 of the resistance measuring device (not shown) is brought into contact with the pad region 22A of each opening 25, The entire resistance value of the element 5 is detected. Then, as shown in FIG. 119A, by irradiating the arbitrary fuse film F with the laser light L through the CVD insulating film 45, the wiring film 22 in the above-mentioned trimming target region X is trimmed with the laser light L. The fuse film F is blown. The blown fuse film F is a portion trimmed (fused) in the wiring film 22 in the trimming target region X described above. Thus, by fusing (trimming) the fuse film F so as to have a necessary resistance value, the resistance value of the entire semi-finished product 50 (in other words, the chip resistor 1) can be adjusted as described above.

  The power (energy) of the laser beam L in this embodiment is 1.2 μJ to 2.7 μJ, and the spot diameter of the laser beam L is 3 μm to 5 μm. Further, when the laser light L is transmitted through the CVD insulating film 45, the portion of the CVD insulating film 45 through which the laser light L is transmitted is cut, and the resistor film 21 is also melted at the place where the wiring film 22 is melted. A part of the insulating layer 20 is cut off together with the wiring film 22.

  As described above, the entire wiring film 22 constituting the fuse film F is covered with the CVD insulating film 45. For this reason, the laser light L applied to the wiring film 22 in the trimming target region X passes through the CVD insulating film 45 in the trimming target region X and then reaches the wiring film 22 (fuse film F). In this way, the energy of the laser beam L can be efficiently concentrated (accumulated) in the fuse film F, so that the fuse film F can be surely and quickly blown (laser trimming) by the laser beam L. In addition, since the CVD insulating film 45 is in contact with the wiring film 22, the wiring film 22 is reliably covered with the CVD insulating film 45, so that the energy of the laser beam can be efficiently concentrated on the wiring film 22. Thus, reliable trimming of the wiring film 22 can be effectively realized.

In addition, since the wiring film 22 is covered with the CVD insulating film 45, even if a fragment is generated by laser trimming, the fragment becomes a foreign substance 68 and contacts the wiring film 22 (element 5) to cause a short circuit. Absent. That is, a short circuit caused by trimming can be prevented.
As described above, with respect to fusing of the fuse film F (in other words, trimming of the wiring film 22 in the fuse film F), the fusing property is improved and the yield is improved, so that the productivity of the chip resistor 1 is improved. Can do.

  Here, since the CVD insulating film 45 is formed by the CVD method, the CVD insulating film 45 (particularly, compared with the case where the same material as the CVD insulating film 45 is pasted on the wiring film 22 to form the film). The film quality of the CVD insulating film 45) in the entire trimming target region X can be stabilized. Thereby, the wiring film 22 can be covered with the CVD insulating film 45 without leakage. Therefore, reliable trimming of the wiring film 22 can be realized in any part of the trimming target region X. That is, by using such a CVD insulating film 45, it is possible to reliably improve the fusing property and the yield of the fuse film F.

  Further, as described above, the CVD insulating film 45 desirably has a thickness of 1000 to 5000 mm. In this case, since the energy of the laser beam can be efficiently concentrated on the wiring film 22, reliable trimming of the wiring film 22 can be effectively realized. When the CVD insulating film 45 is thinner than 1000 mm, the effect of efficiently concentrating the energy of the laser light L on the fuse film F is reduced. On the contrary, if the CVD insulating film 45 is thicker than 5000 mm, it becomes difficult to cut the CVD insulating film 45 with the laser light L, so that the fuse film F is difficult to be blown (trimmed).

Further, since the SiN generation temperature of the CVD insulating film 45 at the time of CVD is lower than the melting temperature of Al or AlCu alloy of the wiring film 22, the CVD insulating film 45 is formed on the wiring film 22 without melting the wiring film 22. Can be formed. On the contrary, if the CVD insulating film 45 is SiO ₂ (silicon oxide), the generation temperature of SiO ₂ is higher than the melting temperature of Al or AlCu alloy, so that the wiring film is formed when the CVD insulating film 45 made of SiO ₂ is generated. As a result, the CVD insulating film 45 cannot be formed on the wiring film 22.

  Unlike the above eighth invention, as shown in FIG. 119B, in the case of the comparative example in which the wiring film 22 is exposed without being covered with the CVD insulating film 45, the energy of the laser light L is the fuse. The film cannot be concentrated (accumulated) in the film F and is dispersed around the fuse film F. Specifically, the energy of the laser beam L is reflected on the surface of the wiring film 22, dispersed in the wiring film 22, or absorbed by the resistor film 21 and the insulating layer 20. For this reason, it is difficult to reliably blow the fuse film F with the laser beam L, and it takes time to blow the fuse film F. Furthermore, since the wiring film 22 (element 5) is exposed, the foreign matter 68 described above may adhere to the element 5 and a short circuit may occur in the element 5.

Then, after adjusting the resistance value of the entire semi-finished product 50 as described above, a photosensitive resin sheet 46 made of polyimide is pasted onto the substrate 30 from above the CVD insulating film 45 as shown in FIG. 116D. To wear.
120 (a) and 120 (b) are schematic perspective views showing a state in which a polyimide sheet is attached to the substrate in the process of FIG. 116D.

Specifically, as shown in FIG. 120 (a), after a polyimide sheet 46 is placed on the substrate 30 (strictly, the CVD insulating film 45 on the substrate 30) from the surface 30A side, FIG. The sheet 46 is pressed against the substrate 30 by the rotating roller 47 as shown in FIG.
As shown in FIG. 116D, when the sheet 46 is attached to the entire surface of the CVD insulating film 45, a part of the sheet 46 slightly enters the groove 44 side, but the side surface 44A of the groove 44 on the element 5 side ( The sheet 46 does not reach the bottom surface 44B of the groove 44 only by covering a part of the surface 30A side). Therefore, in the groove 44 between the sheet 46 and the bottom surface 44 </ b> B of the groove 44, a space S having almost the same size as the groove 44 is formed. At this time, the thickness of the sheet 46 is 10 μm to 30 μm. A part of the sheet 46 enters each opening 25 of the CVD insulating film 45 and closes the opening 25.

Next, the sheet 46 is subjected to heat treatment. Thereby, the thickness of the sheet 46 is thermally contracted to about 5 μm.
Next, as shown in FIG. 116E, the sheet 46 is patterned, and portions of the sheet 46 that coincide with the grooves 44 and the pad regions 22A (openings 25) of the wiring film 22 in a plan view are selectively removed. Specifically, the sheet 46 is exposed and developed in the pattern using the mask 62 in which the opening 61 having a pattern that matches (matches) with the groove 44 and each pad region 22A in plan view. As a result, the sheet 46 is separated above the groove 44 and each pad region 22A, and the edge portion separated in the sheet 46 overlaps with the side surface 44A of the groove 44 while hanging slightly to the groove 44 side. The bulging portion 24A (having the round-shaped side surface 24B) described above is naturally formed. By forming the bulging portion 24 </ b> A, the above-described intersecting portion 27 is covered with the sheet 46.

At this time, portions of the sheet 46 that have entered the respective openings 25 of the CVD insulating film 45 are also removed, so that the openings 25 are opened.
Next, a Ni / Pd / Au laminated film constituted by laminating Ni, Pd and Au is formed on the pad region 22A in each opening 25 by electroless plating. At this time, the Ni / Pd / Au laminated film protrudes from the opening 25 to the surface of the sheet 46. Thereby, the Ni / Pd / Au laminated film in each opening 25 becomes the first connection electrode 3 and the second connection electrode 4 shown in FIG. 116F.

Next, after a current inspection between the first connection electrode 3 and the second connection electrode 4 is performed, the substrate 30 is ground from the back surface 30B.
Specifically, after forming the groove 44, as shown in FIG. 116G, a thin plate-like support base 71 made of PET (polyethylene terephthalate) is connected to the first connection in each semi-finished product 50 via the adhesive 72. Each semi-finished product 50 is supported by the support base material 71 by being stuck to the electrode 3 and the second connection electrode 4 side (that is, the element formation surface 2A). Here, for example, a laminate sheet can be used as the support substrate 71 in which the adhesive 72 is integrated.

  In a state where each semi-finished product 50 is supported by the support base 71, the substrate 30 is ground from the back surface 30B side. When the substrate 30 is thinned by grinding until the bottom surface 44B (see FIG. 116F) of the groove 44 is reached, there is no connection between the adjacent semi-finished products 50. The products 50 are separated individually. That is, the substrate 30 is cut (divided) in the groove 44 (in other words, the boundary region Z), and thereby the individual semi-finished products 50 are cut out.

Thereafter, the back surface 30B of the substrate 30 in each semi-finished product 50 is polished and mirror-finished.
In each semi-finished product 50, the portion that formed the side surface 44A of the groove 44 becomes one of the side surfaces 2C to 2F of the substrate 2 in the chip resistor 1, and the back surface 30B becomes the back surface 2B. That is, the step of forming the groove 44 described above (see FIG. 116B) is included in the step of forming the side surfaces 2C to 2F. Then, the CVD insulating film 45 becomes the insulating film 23. Further, the separated sheet 46 becomes the resin film 24.

  Even if the chip size of the chip resistor 1 is small, the semi-finished product 50 (chip resistor 1) is separated by grinding the substrate 30 from the back surface 30B after the grooves 44 are formed in this way. can do. Therefore, as compared with the conventional case where the chip resistor 1 is divided into individual pieces by dicing the substrate 30 with a dicing saw, the cost can be reduced and the time can be shortened and the yield can be improved by omitting the dicing process.

FIG. 121 is a schematic perspective view showing a semi-finished chip resistor immediately after the step of FIG. 116G.
In the state immediately after separating the semi-finished products 50, each semi-finished product 50 continues to stick to the support base 71 and is supported by the support base 71 as shown in FIG. 121. At this time, in each semi-finished product 50, the back surface 30 </ b> B (back surface 2 </ b> B) side is exposed from the support base material 71. In the semi-finished product 50, as shown in the enlarged view of the part surrounded by the broken-line circle in FIG. Pointed to.

FIG. 122 is a first schematic diagram showing a process subsequent to that in FIG. 116G. FIG. 123 is a second schematic diagram showing a process subsequent to that in FIG. 116G.
Referring to FIG. 122, as described above, the semi-finished products 50 are individually separated by grinding from the back surface 30B, and then the side of the support base 71 opposite to the side on which the semi-finished product 50 is adhered (in FIG. 122). The rotation shaft 75 is connected to the gravity center position of the lower side surface. The rotating shaft 75 can rotate in both the clockwise direction CW and the counterclockwise direction CCW around the axis by receiving a driving force from a motor (not shown). The support base 71 in a state of supporting the semi-finished product 50 rotates together with the rotation shaft 75 (integral rotation) in a plane along the back surface 30B of the semi-finished product 50.

  And the etching nozzle 76 is arrange | positioned so that the side which the semi-finished product 50 adhered in the support base material 71 may be faced. The etching nozzle 76 is, for example, a tubular shape extending in parallel with the support base 71, and a supply port 77 is formed at a position facing the semi-finished product 50. The etching nozzle 76 is connected to a tank (not shown) filled with a chemical solution or the like. Referring to FIG. 123, etching nozzle 76 can swing around fulcrum P on the side opposite to supply port 77 side, as indicated by a broken line arrow, in a state parallel to support substrate 71. The rotating shaft 75 and the etching nozzle 76 constitute a part of the spin etcher 80.

  After the semi-finished product 50 is individually separated and the back surface 30B is polished, the support base 71 rotates in a predetermined pattern in one or both of the clockwise direction CW and the counterclockwise direction CCW, and the etching nozzle 76 swings. In this state, the etching agent (etching liquid) is uniformly sprayed from the supply port 77 of the etching nozzle 76 to the back surface 2B side of each semi-finished product 50 supported by the support base 71. Thereby, each semi-finished product 50 supported by the support base material 71 is isotropically subjected to chemical etching (wet etching) from the back surface 2B side. In particular, in each semi-finished product 50, the intersections 11 between adjacent ones of the back surface 2B, the side surface 2C, the side surface 2D, the side surface 2E, and the side surface 2F are isotropically etched. When the intersection 11 before the etching is pointed (see FIG. 121), the corner of each intersection 11 is likely to be scraped due to crystal defects or the like accompanying the etching, so that each intersection 11 is finally etched by isotropic etching. Specifically, it is shaped into a round shape (see an enlarged portion surrounded by a broken-line circle in FIG. 123). Further, the isotropic etching is performed in a state where the support base material 71 is rotated, so that the etching agent is uniformly bathed on the intersecting portions 11 of the respective semi-finished products 50, and thus the intersecting portions 11 of the respective semi-finished products 50. Can be uniformly shaped into a round shape. Further, isotropic etching is performed on the plurality of semi-finished products 50 (chip resistors 1) supported by the support base 71. Thereby, in the some semi-finished product 50, the cross | intersection part 11 of each semi-finished product 50 can be shaped in round shape at once.

  In the isotropic etching, the etching solution is preferably sprayed toward the back surface 2B side of each semi-finished product 50 (spray spray). If the etching solution remains liquid, not only the intersection 11 but also the back surface 2B, the side surface 2C, the side surface 2D, the side surface 2E, and the side surface 2F will be etched. When the liquid is discharged, the mist-like etching liquid easily adheres to the crossing portion 11 and the crossing portion 11 is preferentially etched. Therefore, the back surface 2B, the side surface 2C, the side surface 2D, the side surface 2E, and the side surface 2F Each crossing portion 11 can be shaped into a round shape while suppressing etching.

  When each intersection 11 becomes round, the etching process is completed, and the chip resistor 1 (see FIG. 115) is completed. Thereafter, a rinse solution (water) is poured onto the chip resistor 1 from the etching nozzle 76, and the chip resistor 1 is cleaned. At this time, the support base 71 may be rotating, or the etching nozzle 76 may be swung. The chip resistor 1 is peeled off from the support base 71 after being cleaned, and mounted on the circuit board 9 (see FIG. 107 (b)) described above, for example.

Here, the etching solution may be either acidic or alkaline, but when the crossing portion 11 is isotropically etched, it is preferable to use an acidic etching solution. When an alkaline etching solution is used, the crossing portions 11 are anisotropically etched, so that it takes time to make each crossing portion 11 round as compared with the case where an acidic etching solution is used. As an example of an acidic etching solution, a mixture of H ₂ SO ₄ (sulfuric acid) and CH ₃ COOH (acetic acid) in a base solution of HF (hydrogen fluoride) and HNO ₃ (nitric acid) is used. In this etching solution, the viscosity is adjusted with sulfuric acid, and the etching rate is adjusted with acetic acid.

Although the embodiment of the eighth invention has been described above, the eighth invention can also be implemented in other forms.
For example, when the substrate 30 is divided into individual chip resistors 1, the substrate 30 is ground from the back surface 30B side to the bottom surface 44B of the groove 44 (see FIG. 116F). Instead, the substrate 30 may be divided into individual chip resistors 1 by selectively removing the portion of the substrate 30 that coincides with the groove 44 in plan view from the back surface 30B. Further, the substrate 30 may be diced by a dicing blade (not shown) and divided into individual chip resistors 1.

  In addition, the chip resistor 1 (the first connection electrode 3, the second connection electrode 4, the element 5 and the like) may be formed on the substrate 2 using a semiconductor manufacturing process. In this case, the substrate 2 and the substrate 30 are A substrate made of Si (silicon) may be used.

10, 30 Chip resistor 11 Substrate 12 First connection electrode 13 Second connection electrode 14 Resistance network 20 Resistor film 21 Conductor film (wiring film)
R resistor F fuse film C conductive film for connection

Claims (15)

A silicon substrate having one surface as a mounting surface and the other surface on the opposite side, the side surface of which is formed linearly;
A protective film covering the one surface and both side surfaces of the substrate and having openings formed therein;
Covering the protective film on the one surface of the substrate, a resin film in which an opening is formed in communication with the opening of different made of a material, and the protective film and the protective film,
A first connection electrode and a second connection electrode which are formed only on the one surface of the substrate and are disposed in the opening of the protective film and the resin film ;
A resistance network connected to the first connection electrode and the second connection electrode,
The resistor network is:
A plurality of resistors having equal resistance values arranged in a matrix on the substrate;
A plurality of types of resistance units configured by electrically connecting one or more of the resistors;
Network connection means for connecting the plurality of types of resistance units in a predetermined manner;
A plurality of fuse films provided individually corresponding to the resistance unit bodies, wherein the resistance unit bodies are electrically incorporated into the resistance network, or are blown to be electrically separated from the resistance network; and
Including
The resistor is
A resistive film line extending over the substrate;
On the resistance film line, including a conductor film laminated with a certain interval in the line direction,
In a plan view, the resistor film lines at the constant interval where the conductor films are not stacked are one resistor so that the resistor film lines and the conductor films having a constant width are alternately arranged at regular intervals. Comprising
The other surface of the substrate is a polished surface;
The first connection electrode and the second connection electrode protrude upward from the opening of the protective film and the resin film , and have a portion larger than the opening in plan view,
The portion of the protective film that covers both side surfaces of the substrate has an end portion that is flush with the other surface of the substrate on the other surface of the substrate.
The chip resistor according to claim 1, wherein the resin film has an arcuate projecting portion projecting outward from the protective film on the side surface of the substrate in a cross-sectional view.   The conductor film of the resistor, the connection conductor film included in the resistance unit body, the connection conductor film included in the circuit network connection means, and the fuse film include a metal film of the same material formed in the same layer. The chip resistor according to claim 1, wherein:   3. The chip resistor according to claim 1, wherein the resistance unit includes a plurality of the resistors connected in series. 4.   The chip resistor according to claim 1, wherein the resistance unit includes a plurality of the resistors connected in parallel.   5. The chip according to claim 1, wherein the plurality of types of resistance unit bodies are set with the number of the connected resistance bodies, and the resistance values thereof form a geometric progression. 6. Resistor.   The chip resistor according to claim 1, wherein the circuit network connecting means includes a conductive film for connection for connecting the plurality of types of resistance unit bodies in series.   The chip resistor according to any one of claims 1 to 6, wherein the circuit network connecting means includes a conductive film for connection for connecting the plurality of types of resistance unit bodies in parallel.   8. The chip resistor according to claim 1, wherein the plurality of fuse films are arranged linearly along one end of the matrix arrangement of the plurality of resistors. 9.   9. The resistor unit according to claim 1, wherein the resistor unit includes a predetermined number of resistors and includes a reference resistor unit that is incorporated into the resistor network and cannot be separated. Chip resistor.   10. The chip resistor according to claim 1, wherein the resistance film line of the resistor is formed of TiN, TiON, or TiSiON.   The chip resistor according to claim 1, wherein the resistance film line and the conductor film are formed by patterning all together. The chip resistor according to claim 1, wherein the protective film is made of SiN, and the resin film is made of polyimide. A silicon substrate having one surface as a mounting surface and the other surface on the opposite side, the side surface of which is formed linearly;
A protective film covering the one surface and both side surfaces of the substrate and having openings formed therein;
Covering the protective film on the one surface of the substrate, a resin film in which an opening is formed in communication with the opening of different made of a material, and the protective film and the protective film,
A first connection electrode and a second connection electrode which are formed only on the one surface of the substrate and are arranged in the opening of the protective film and the resin film ;
A resistor network having a plurality of resistors formed on the one surface of the substrate, having one end connected to the first connection electrode and the other end connected by a wiring film connected to the second connection electrode. When,
A plurality of fuse films that can be blown to electrically incorporate the resistor into the resistor network or to electrically isolate it from the resistor network;
Including
The other surface of the substrate is a polished surface;
The first connection electrode and the second connection electrode protrude upward from the opening of the protective film and the resin film , and have a portion larger than the opening in plan view,
The portion of the protective film that covers both side surfaces of the substrate has an end portion that is flush with the other surface of the substrate on the other surface of the substrate,
The electronic device according to claim 1, wherein the resin film has an arcuate projecting portion that projects outward from the protective film on the side surface of the substrate in a cross-sectional view.   The electronic device according to claim 13, wherein the resistor is made of TiON or TiSiON.   15. The electronic apparatus according to claim 13, wherein the resistor and the wiring film are patterned at once.

Images