DE10136714C1 - Integrated digital circuit has unit for checking signal in circuit for error during normal mode, changing to special mode with lower operating frequency and failure probability if error detected - Google Patents

Abstract

The integrated digital circuit has a unit for checking a signal in the digital circuit for an error during a normal operating mode of the circuit and for changing over to a special mode with a lower than normal operating frequency if an error is detected. The special operating mode has a lower failure probability than the normal operating mode. AN Independent claim is also included for the following: a method of operating an inventive device.

Description

The invention relates to an integrated digital circuit and a method for operating an integrated Digital circuit.

Integrated digital circuits are becoming increasingly higher integrated and working with increasingly higher ones Operating frequencies. On the one hand, this trend always leads more powerful digital circuits on smaller and smaller ones Area and thus to new applications.

On the other hand, higher integration and higher throw Operating frequency problems.

For digital logic circuits with structure sizes below 0.25 µm represents the crosstalk from neighboring conductor tracks on the chip of the integral circuit arrangement considerable disturbance for the signal traffic within the Logic circuit. If the logic circuit with a Operating frequency of 1 GHz and above is clocked faulty due to capacitive coupling of interference signals Useful signals occur on the chip.

According to [1] were used to correct errors Useful signals of an integrated digital logic circuit so-called repeater modules are introduced into the signal path. These repeater modules are after relatively short Signal sections introduced into the signal path and fresh the disturbed signal.

Alternatively or additionally, shielding cables can be used according to [1] be provided between signal-carrying lines.  

Both solutions are characterized by an increased space requirement and cause a significant increase in the Chip area, especially if repeater modules or Shielding cables are used across the board and systematically become.

Redundant systems can be used to detect errors on a chip are used in which all critical circuit blocks are interpreted twice, and where the results of two same blocks are compared with each other, see [2].

However, it is not possible to detect faulty signals a repeat of the transfer process in the correct form to get because the crosstalk is not a statistical one Process is. When retransmitting the same Signals under the same conditions can cause errors in occur again in the same way.

Document [5] describes a framework for digital signal processing (DSP), in which a supplied voltage is scaled beyond a critical voltage that is required to match the critical delay due to the transmission paths and the throughput performance. In this case, a noisy voltage signal, which has been generated by means of a filter, is applied to a forward predictor of degree N _p with low complexity, which generates a prediction output, whereby for an input signal (n) from the previous signals (n-1 ), (n - 2),. , ., (0) a prediction signal _p (n) using the formula:

is determined, the value of which is then the value of (n) is subtracted, which is used to determine a prediction error. This value is then fed to a decision block. In the decision block is determined whether the value (s) was faulty.  

In document [6] a system is described that a test unit by means of which it is determined whether the output a combinatorial unit and the value of State variable of a subsequent time cycle as Output of this unit are faulty or not, whereby in the event of an error detection, the clock for the circuit is switched off (set to logic "0"), so that the Circuit is deactivated until the output of the combinatorial unit are correct. The test unit is on the input side with the outputs of the test unit and coupled on the output side to a converter unit which converts the Output of the test unit in a bit value depending on the Converts outputs of the test unit. The converter unit in turn is on the output side with a signal memory coupled to the output of the converter unit buffered and on the output side with an AND gate is coupled, at the second input of the clock as Working clock signal is applied and the output side with is coupled to the clock input of the combinatorial unit, which controls the timing of the combinatorial unit becomes.

The object of the invention is therefore an integrated Digital circuit and a method of operating a Specify digital circuit with the help of simple and nevertheless reliable way of error-free signal transmission can be guaranteed.

The part of the task relating to the device is performed by solved the features of claim 1.

An integrated digital circuit contains one unit to check a signal of the digital circuit for a Error during normal operating mode of the Digital circuit.  

Usually the normal operating mode has a high one Operating frequency. Preferably an operating frequency be provided between 400 MHz and 6 GHz, which too Crosstalk effects can result.  

The signal to be checked can be used to detect an error be provided with an error-detecting code, in simplest design with a parity check bit.

The unit is designed to switch to one Special operating mode when an error is detected.

The special operating mode points towards that Normal operating mode has a lower susceptibility to faults. As a result, the occurrence of errors is largely due to the Normal operating mode limited.

The special operating mode is distinguished from that Normal operating mode advantageously by a lower one Operating frequency off. The operating frequency of the Special operating mode in the range of about 20 to 80 percent of the Operating frequency of the normal operating mode.

Since with increasing operating frequency the extent of Crosstalk increases with a reduced Operating frequency an operation of the digital circuit reached in which the crosstalk and thus also the Error rate of the signals kept low or even can be excluded.

The invention solves the crosstalk problem the use of two modes of operation and in particular Use of two clock frequencies to implement fault-tolerant IC circuits.

The first - higher - clock frequency allows very fast Processing speeds, however, has a certain of Zero different probability of error regarding their Signals due to the capacitive coupling between neighboring lines.  

The second clock frequency is significantly lower. she leads to a slower processing speed, but ensures error-free signal transmission.

With the digital circuit, the signal to be monitored is now - at least during normal operating mode - continuously transient errors checked, preferably by the Use and evaluation of an error-detecting code for the signal transmission. An overview of usable error-detecting codes can be found in [3].

Preferably, a switching block of the digital circuit provides that Signal.

The switch block can be used as a filter or as Multiplier be formed.

The signal provided by the switch block is preferred transferred to another switch block and there further processed. Both switching blocks are on one common chip arranged. The transmission path between the switch blocks but also the switch block itself usually exposed to capacitive interference.

The unit is preferably designed to control the Switch block in such a way that the switch block after the Detect the error in the transmitted signal from the unit is caused, the signal in the special operating mode of the Output digital circuit again. As soon as a mistake is discovered, the circuit is reset and the the same process is repeated with a slower clock frequency.

This ensures a safe, error-free transmission of the previous achieved as a faulty transmitted signal.

Such a resumption of the calculation process after the Allowing errors to occur is preferred  regularly the state of the circuit in a memory, preferably so-called latches, temporarily stored. This Storage of the relevant signal data is also used as a checkpoint designated. The regular storage of data from the Digital switching takes place as described in [2].

This can be done initially in normal operating mode faulty signal accessed again in special operating mode and the same signal can be transmitted again.

The circuit block of the digital circuit preferably contains the Storage.

The unit is preferably also designed for Switch from special operating mode to Normal operating mode after sending the signal again in special operating mode.

This allows for further data transmission as well as further Data processing in turn due to the high Operating frequency guaranteed high Data processing speed can be achieved.

The digital circuit preferably has structure sizes less than 1 µm, in particular less than 0.25 µm. these are Structure sizes in which the crosstalk at high Operating frequencies and / or low supply voltage reached a high level and thus becomes considerably problematic.

The part of the task concerning the procedure is carried out by the Features of claim 13 solved.

Here, during a normal operating mode Digital circuit checked a signal for an error. Of the normal operating mode becomes a special operating mode switched when an error is detected. The  Special operating mode points towards the normal operating mode a lower susceptibility to failure.

The digital circuit is preferably used in normal operation initially operated with the higher of the two clock frequencies.

As soon as an error is detected, the clock frequency is up reset a lower value. The system will be there reset to the last saved checkpoint - this process is also known as rollback. The Resetting takes place as described in [4]. Then the critical cycle repeated with the reduced clock frequency and then the clock frequency back to the original higher value increased until the next error is recognized.

In an advantageous development of the invention Operating states of the digital circuit in time intervals saved. To retransmit a signal, press accessed the contents of the memory.

Further advantageous developments of the invention are through the subclaims marked.

With regard to the advantages of the method according to the invention and its further training is based on the comments on the Device claims referenced.

Embodiments of the invention are in the figures are shown and explained in more detail below.

Show it

Fig. 1 is a block diagram of a digital circuit according to an embodiment of the invention, and

Fig. 2 is a flow chart according to an embodiment of the method according to the invention.

Fig. 1 is a block diagram showing a digital circuit 1 according to the invention.

A switching block 2 of the digital circuit 1 , for example a digital filter, is usually supplied with a digital input signal X.

An output signal Y is fed to a further switching block 6 for further processing. The output signal Y of the switching block 2 may be noisy due to strong crosstalk, which is due to the high operating frequency of the digital circuit.

Generally it can be said that the amplitude of the Interference peaks with short cable lengths only with higher ones Operating frequencies increased significantly, whereas long ones Lines in the cm range are already low Operating frequencies Interference peaks occur at a high level.

A typical level limit for permitted interference peaks is according to this embodiment 0.4 volts. Will in Normal operating mode an operating frequency of f = 600 MHz is selected, then on 1 cm long bus lines Interference signals with an amplitude of 0.8 volts can be expected.

Therefore, on such lines with the appearance of logical errors. However, the Operating frequency reduced to below 50 MHz, so the Noise level below 0.3 volts.

It is therefore possible to use the special operating mode, for example with an operating frequency of 40 MHz and with this operating frequency a signal interference-free, but with to transmit correspondingly lower speed.  

The digital circuit 1 designed as a VLSI circuit and in particular the switching block 2 is operated at an operating frequency CLK. The operating frequency CLK used is controlled via a controllable changeover switch 4 - optionally formed as a multiplexer - from two work cycles supplied by a clock generator 5 - a work cycle high f (high) with approximately 1 GHz and a work cycle low f (low) with approximately 200 MHz - selected.

In the normal operating mode, the digital circuit 1 is operated at the high duty cycle high f (high) in order to achieve high transmission and processing speeds.

The output signal Y is also fed to a checking unit 3 . This checking unit - also called an error detector - continuously monitors the error-free nature of the digital circuit 1 and in particular the error-free status of the output signal Y. Intermediate results of the digital circuit in particular are checked by means of a parity check.

The checking unit 3 in turn controls the changeover switch 4 as follows:
If an error is detected by the checking unit 3 , the system switches from the normal operating mode to the special operating mode with the lower operating cycle low f (low). For this purpose, the checking unit 3 controls the changeover switch 4 accordingly with a clock selection signal, so that in the following the digital circuit 1 and in particular the switching block 2 is operated with an operating frequency CLK which corresponds to the low operating cycle low f (low).

At the same time, the signal selection roll - also called rollback signal - brings about the switching state of the switching block 2 to the last correct switching state, which is stored as a checkpoint in a memory 21 of the switching block. This means that the previous signal can be transmitted again at a low operating frequency and thus interference-free against crosstalk.

The previous VLSI digital circuit is a simple 4-bit microprocessor with internal Checkpoint registers and implemented parity check.

The synthesis of this digital circuit for a 0.18 µm Technology results in an additional space requirement of 60% compared to an equivalent reference circuit without Error detection and checkpoint register, but the same Switching speed.

Fig. 2 shows a flow diagram according to an embodiment of the method according to the invention.

Step S1 marks the start of the operation of one digital circuit according to the invention.

In a first step S1, a Operating frequency selected for operation. This - usually very high - operating frequency characterizes you Normal operating mode, which has a high data speed allowed.

In a further step S3 is on a predetermined Switching point of the digital circuit a signal by means of a Parity bit checks checked for an error.

If it is recognized in a step S4 that no error in the checked signal is present (N), again with step S3 proceed and the next signal on the selected one Checked circuit point.

However, in step S4 with regard to a checked signal recognizing that there is an error, in step S5 of  the normal operating mode to a special operating mode switched at which the operating frequency for the Digital circuit is significantly reduced.

In a further step S6 is finally on Register accessed in which the last previous error-free signal state is stored. This signal is now again at the lower operating frequency transfer. But it can also be a longer one Act signal or data sequence, which at this point too is subsumed under the term signal.

The operating frequency is then again in step S2 increased to a high below Achieve processing speed.  

The following publications are cited in this document:
[1] AB Kahng et al, Interconnect Tuning Strategies for High-Performance IC's, Proc. Design, Automation and Testing in Europe, Paris, February 1998
[2] Coactive Scheduling and Checkpoint Determination during High Level Synthesis of Self-Recovering Microarchitectures, A. Orailoglu and R. Karri, IEEE Trans. On VLSI 20, 304, 1994
[3] Design and Synthesis of Self-Checking VLSI Circuits, N. Jha and S.-J. Wang, IEEE Trans. CAD 12, 878, 1993
[4] Fast Self-Recovering Controllers, A. Hertwig et al., IEEE VLSI Conference 1998, p. 296
[5] Energy Efficient Signal Processing via Algorithmic Noise Tolerance, R. Hedge and NR Shanbhag, IEEE "Proceedings of International Symposium on Lower Power Electronics and Design" 1999, p. 30-35
[6] Low-level Error Recovery Mechanism for Self-Checking Sequential Circuits, M. Favalli, C. Metra, IEEE "Proceedings of International Symposium on Defect and Fault Tolerance in VLSI Systems" 1999, p. 234-242

LIST OF REFERENCE NUMBERS

1

digital circuit

2

switching block

21

Storage

3

Checking unit

4

switch

5

clock generator

6

Another switch block
X input signal
Y output signal
CLK operating frequency
F (high) work cycle high
F (low) duty cycle low
Sel clock selection
Roll signal selection

Claims (16)

1. Integrated digital circuit,
with a unit for checking a signal of the digital circuit for an error during a normal operating mode of the digital circuit,
which unit is designed to switch to a special operating mode if an error is detected,
in which the special operating mode has a lower operating frequency than the normal operating mode,
in which the special operating mode is less susceptible to malfunction than the normal operating mode. 2. Integrated digital circuit according to claim 1, with a switching block that delivers the signal. 3. Integrated digital circuit according to claim 2, with another switching block for processing the signal. 4. Integrated digital circuit according to claim 2 or claim 3, where the circuit block acts as a multiplier or as a filter is trained. 5. Integrated digital circuit according to one of the preceding Expectations, has structure sizes smaller than 1 µm. 6. Integrated digital circuit according to one of the preceding Expectations, has structure sizes smaller than 0.25 µm. 7. Integrated digital circuit according to one of the preceding Expectations,  where the normal operating mode is an operating frequency between 400 MHz and 6 GHz. 8. Integrated digital circuit any of the previous Expectations, at which the operating frequency of the special operating mode between 20 and 80 percent of the operating frequency of the Normal operating mode. 9. Integrated digital circuit according to one of claims 2 till 8, in which the unit is designed to control the Switch block in such a way that the switch block after the Detection of the error in the transmitted signal by the unit is caused, the signal in the special operating mode of the Output digital circuit again. 10. Integrated digital circuit according to claim 9, in which the unit is designed to switch from the Special operating mode in the normal operating mode after a retransmission of the signal in special operating mode. 11. Integrated digital circuit according to one of the previous claims, with a memory for storing operating states of the Digital circuit. 12. Integrated digital circuit according to claim 11, where the switch block contains the memory. 13. Method for operating an integrated digital circuit,
in which a signal is checked for an error during a normal operating mode of the digital circuit,
in which a switch is made from the normal operating mode to a special operating mode when an error is detected,
in which the special operating mode has a lower operating frequency than the normal operating mode,
in which the special operating mode is less susceptible to faults than the normal operating mode. 14. Operating method according to claim 13 where the signal is retransmitted in special operating mode becomes. 15. Operating method according to claim 14, in which after the retransmission of the signal in Special operating mode back to normal operating mode is switched. 16. Operating method according to claim 14 or claim 15,
in the operating states of the digital circuit are stored in time intervals, and
in which the content of the memory is accessed to retransmit the signal.