CN213581764U - Time interval measuring device - Google Patents
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- CN213581764U CN213581764U CN202022586714.9U CN202022586714U CN213581764U CN 213581764 U CN213581764 U CN 213581764U CN 202022586714 U CN202022586714 U CN 202022586714U CN 213581764 U CN213581764 U CN 213581764U
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Abstract
The utility model provides a time interval measuring device, which comprises a signal conditioning module, a measuring module and a data transmission module; the signal to be measured is input into the signal conditioning module, and the signal conditioning module conditions the signal to be measured, converts the conditioned signal into a standard signal and sends the standard signal to the measuring module; the measurement module calculates measurement data, converts the measurement data into binary codes and sends the binary codes to the data transmission module; the data transmission module transmits the measured data to the single chip microcomputer to complete the processing of the measured data, and the display of the measured data is completed through the display after the processing is completed. The utility model discloses measuring module adopts the FPGA chip, not only can solve circuit system miniaturization, low-power consumption, high reliability scheduling problem, and development cycle is short moreover, and development software drops into fewly.
Description
Technical Field
The utility model relates to a time interval measures technical field, especially relates to a time interval measuring device based on differential delay technique.
Background
The measurement of time intervals is a basic content in the field of electronic measurement, and a lot of time measurement and synchronization problems are involved in numerous fields such as satellite navigation, high-speed digital communication, precision positioning, high-energy physics, modern astronomy, geodetic measurement and the like, and with the rapid development of the professional fields, the requirements on the measurement resolution and precision of time and frequency are higher and higher, so that the subject research of time interval measurement has high academic value and wide market application prospect.
With the rapid development of advanced technology in the 20 th century, especially in the aerospace field, such as the aspects of navigation positioning of GPS and Beidou, launching and control of rockets, accurate guided weapons and the like, the requirement on time standard is higher and higher, and almost no about 10 years, the requirement is improved by an order of magnitude; meanwhile, the development of the high and new technical field also puts high requirements on the accuracy and stability of the time base standard.
The rise of quantum physics research has promoted the development of atomic time based on the transition frequency of atoms, and considering that the accuracy of atomic time is only equal to the physical properties of atoms, namely the accuracy and stability of atomic frequency standard, the atomic clock designed based on high-precision atomic frequency standard is quite accurate. At present, the precision of a cesium atomic clock designed by a cesium atomic frequency standard reaches the femtosecond order, the same order can be realized when international atoms are established according to the principle, and the development of the technologies provides a solid theoretical basis for a precise time measurement technology.
The time interval measurement technology also plays an important role in the basic research fields of atomic nucleus and particle physics research and the like. For example, in particle physics experiments, the time range for time-of-flight measurements is typically on the order of tens of nanoseconds, while the time range for drift time measurements is on the order of hundreds of nanoseconds. In general, particle physics experiments require that the time resolution and measurement accuracy of time measurement systems be as high as possible, both currently at the level of around 25 ps.
In defense science and technology, high-precision time synchronization is also an important research topic. The method can not be used for high-precision time measurement no matter burst confidential communication, accurate positioning of airplanes and missiles, combat readiness early warning, coordination work among radar networks and cooperative operation among various weapons. With the development of science and technology, the requirements of the fields on the time synchronization technology are higher and higher, and the time interval measurement, particularly the short time interval measurement technology with high resolution and high stability, can play an increasingly important role in the fields of national defense safety, aerospace measurement and control, digital communication networks and the like.
From the method of time interval measurement technology implementation, the ASIC chip based on CMOS technology implementation is mainly applied internationally, and the measurement precision is high, but the process requirement is strict, the design period is long, the development cost is high, and the design is not flexible enough. In terms of the current development situation of the time interval measurement technology in China, due to a certain gap between the semiconductor industry and the developed countries in China, the time interval measurement technology cannot be developed by an ASIC circuit based on a CMOS process completely in a short time.
SUMMERY OF THE UTILITY MODEL
The utility model discloses a FPGA chip has solved FPGA and has not only solved circuit system miniaturization, low-power consumption, high reliability scheduling problem, has overcome the design cycle length of ordinary ASIC design, the big, the poor shortcoming of flexibility of investment.
The utility model adopts the technical scheme as follows:
the invention provides a time interval measuring device, which comprises a signal conditioning module, a measuring module and a data transmission module, wherein the signal conditioning module is used for conditioning a signal; the signal to be measured is input into the signal conditioning module, and the signal conditioning module conditions the signal to be measured, converts the conditioned signal into a standard signal and sends the standard signal to the measuring module; the measurement module calculates measurement data, converts the measurement data into binary codes and sends the binary codes to the data transmission module; the data transmission module transmits the measured data to the single chip microcomputer to complete the processing of the measured data, and the display of the measured data is completed through the display after the processing is completed.
Further, the signals to be tested comprise a start signal and an end signal of the time interval to be tested and a clock signal generated by the crystal oscillator circuit.
Further, the measuring module comprises a rough measuring unit, a fine measuring unit and a data processing unit; the rough measurement unit is used for calculating the period number between the starting signal and the ending signal in the time interval to be measured and transmitting period data to the data processing unit; the fine measurement unit measures a time interval less than one period by using a delay unit in the measurement module to obtain differential delay line data and transmits the delay line data to the data processing unit; the data processing unit calculates the measurement data of the time interval according to the period data and the delay line data and sends the measurement data to the data transmission module.
Furthermore, the measurement module adopts an FPGA chip, a delay unit is configured in the FPGA chip, the differential delay line comprises two groups of delay units, the start signal and the stop signal respectively pass through the differential delay line, the delay time of the start signal passing through the differential delay line is longer than the delay time of the stop signal passing through the differential delay line, and the difference between the start signal and the stop signal is the data of the differential delay line.
Further, the clock signal is multiplied by a phase-locked loop PLL inside the FPGA to be used as a reference frequency signal for time interval measurement.
Furthermore, the single chip microcomputer adopts an MSP430 chip and is in serial port communication with the computer through a level conversion circuit.
Furthermore, the time interval measuring device also comprises a power supply module, and the power supply module supplies voltage to the FPGA chip and the singlechip.
Further, the voltage provided by the power module includes 3.3V and 1.5V.
Furthermore, the crystal oscillator circuit adopts a 20MHz crystal oscillator source, and filters the power supply of the crystal oscillator through an LC filter.
Further, the display is characterized by adopting an LCD display.
The beneficial effects of the utility model reside in that, adopt FPGA chip development cycle short, development software drops into fewly, is particularly suitable for using in the product demand occasion of small batch, many varieties.
Drawings
FIG. 1 is a block diagram of the time interval measuring device of the present invention;
FIG. 2 is a block diagram of the crystal oscillator circuit of the present invention;
FIG. 3 is a schematic diagram of the setup time and hold time of the present invention;
FIG. 4 is a circuit diagram of the fine measurement unit of the present invention;
fig. 5 is a circuit diagram of the power module of the present invention.
Detailed Description
The utility model provides a time interval measuring device, it is right below with the accompanying drawing the utility model discloses a detailed implementation carries out further detailed description.
Fig. 1 is a block diagram of the time interval measuring device of the present invention, which requires three input signals, a start signal and an end signal of any time interval, and a clock signal with a reference frequency of 20MHz (to ensure the accuracy and stability of the system clock). The clock signal is derived from the crystal oscillator circuit, and as shown in fig. 2, in order to stabilize the output frequency of the crystal oscillator, an LC filter is used to filter the power supply of the crystal oscillator, thereby reducing the interference as much as possible. The clock signal obtains a 200MHz clock through a phase-locked loop PLL inside the FPGA, and the clock is used as a frequency reference for measurement.
The start signal, the end signal and the clock signal are sent to the signal conditioning module, and the signal conditioning module is mainly used for converting the signal to be measured into a standard signal which can be identified by the measuring module through operations such as amplification, filtering and the like. The signal to be measured may be a sine wave signal or a pulse signal. For a sinusoidal signal to be measured, the sinusoidal signal needs to be shaped into a square wave, and necessary filtering and amplification processing are performed to adapt to the requirements of the measurement module. In a specific embodiment, the signal conditioning module adopts two paths of differential amplifiers of MC10116 as two cascaded amplifiers, and then uses one path of differential amplifier as a Schmitt trigger to realize the shaping of the signal to be measured.
The utility model discloses measuring module adopts the FPGA chip, preferably adopts EP1C6Q240C8 chip, including three unit, coarse measurement unit, smart measuring element and data processing unit. The basic principle of Time interval measurement is to measure a large Time interval by using a small Time interval, and the principle of a coarse measurement unit is to count the number n of clock cycles in a Time interval T to be measured by using a counter, so as to improve the range of a TDC (Time to Digital Converter). The principle of the fine measurement unit is that a small delay inside the FPGA is used for measuring a time interval less than one period, and the fine measurement unit is used for improving the precision of the TDC.
The coarse measurement unit is used for clock counting the number of periods starting between the end signals. The coarse measurement unit is actually a counter, which starts and ends counting under the control of a start signal and an end signal, and transmits the output result to the data processing unit. However, in terms of implementation, the digital circuit has certain requirements on the relationship between data and clock, namely, the Setup time (Setup time) and Hold time (Hold time) must be satisfied, otherwise, the output state is unstable and the result is unpredictable.
The setup time refers to the time before the rising edge of the clock signal of the flip-flop comes, the data is stable and unchanged, and if the setup time is not enough, the data cannot be driven into the flip-flop when the rising edge comes, as shown in fig. 3. The hold time is the time after the rising edge of the clock signal of the flip-flop the data is stable and does not change, and if the hold time is not enough, the data can not be driven into the flip-flop.
The coarse measurement unit preferably adopts a double counter, that is, a small counter is used to drive a large counter, and the large counter is used for counting by using a carry signal of the small counter as an enabling end. The rough measurement unit performs rough measurement on the interval between the start and the end, and outputs the count result to the data processing unit.
The fine measurement unit is a core part of the measurement module, and because the measurement accuracy, nonlinearity and other indexes depend on the fine measurement unit, the measurement accuracy of the fine measurement unit determines the accuracy of the whole TDC system. The fine measurement unit measures a time interval less than one period by using a delay unit inside the FPGA to obtain differential delay line data, and transmits the delay line data to the data processing unit.
The utility model discloses well thin measuring unit is also differential delay line, adopts differential delay interpolation method to measure time interval, measures time signal and the clock rising edge asynchronous part, and the working condition of this thick measuring unit of output control is exactly the beginning and the stopping of control measuring unit. And the fine measurement unit transmits the data to the data processing module. And the data processing module calculates corresponding parameters according to the data of the delay line.
The differential delay interpolation method respectively passes a start signal and an end signal of a measured time interval through two delay chains, wherein the quantization delay time of each delay unit in the delay chain through which the start signal passes is slightly longer than that of each delay unit in the delay chain through which the stop signal passes. For this reason, a theoretical coincidence point C appears at a certain time when the two signals pass through the respective quantization delay circuits. The measured time interval can be calculated from the number of delay levels that have elapsed when coincidence occurs. The fine measurement unit circuit structure is shown in fig. 4.
The differential delay line structure is composed of two groups of delay units, wherein the delay time of one group of delay units is tau1The delay time of another group of delay units is tau2A DQ flip-flop is collocated between each pair of delay cells. The delay cells are level triggered and the flip-flops are edge triggered. With this differential delay line structure, the final system resolution is:
τ＝τ1-τ2
wherein tau is1Is slightly larger than tau2。
The data processing unit completes two functions, namely, calculating a measurement result according to the measurement value of the rough measurement unit and the measurement value of the fine measurement unit. Secondly, the result is converted into a binary code with fixed length and is transmitted to a data transmission module. The data transmission module transmits the measured data to the single chip microcomputer to complete the processing of the measured data, and the display of the measured data is completed through the display after the processing is completed.
The single chip microcomputer preferably adopts an MSP430F449 chip. The MSP430F449 single-chip microcomputer has a full-duplex serial communication port, so that serial communication between the single-chip microcomputer and a computer can be conveniently carried out. The serial communication needs to satisfy certain conditions, because the serial port of the computer is RS232 level, and the serial port of the single chip microcomputer is TTL level, a level conversion circuit must be arranged between the serial port of the computer and the serial port of the single chip microcomputer, and a special chip MAX232 is preferably adopted for conversion, and the MAX232 chip is an IC chip which is produced by MAXIM company and comprises two paths of receivers and drivers. The MAX232 chip is internally provided with a power supply voltage converter which can convert the input voltage into +/-10V voltage required by RS-232C output level.
The voltage required by the measuring device is 3.3V and 1.5V, wherein the core voltage of the FPGA chip needs 1.5V, the voltage required by I/O is 3.3V, and the voltage required by the single chip microcomputer MSP430F449 is 3.3V. The power module adopts an LT3080 chip, LT3080 is a tri-state voltage stabilizing device with a novel framework and capable of adjusting output voltage by changing the resistance value of a third pin, and the tri-state voltage stabilizing device is used for realizing parallel heat dissipation and effectively reducing the temperature rise of the device in the voltage reduction process. The chip uses an internal constant current source reference, and can realize the parallel connection of a plurality of voltage stabilizers for providing larger current. LT3080 has a wide range of voltage inputs from 2V to 38V, and on-chip trimming references allow for high accuracy of the output voltage. The power supply chip has the advantages of wide voltage input and output range, extremely high voltage accuracy, low power supply noise, high ripple rejection, few peripheral devices and the like, so that the power supply chip is widely used in many occasions, and can completely meet the requirement of voltage conversion in the specific embodiment due to the excellent performance of the power supply chip. Fig. 5 is a circuit diagram of the power module.
The above description is only for the best mode of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention.
Those skilled in the art will appreciate that the invention may be practiced without these specific details.
Claims (6)
1. A time interval measuring device is characterized by comprising a signal conditioning module, a measuring module and a data transmission module; the signal to be measured is input into the signal conditioning module, and the signal conditioning module conditions the signal to be measured, converts the conditioned signal into a standard signal and sends the standard signal to the measuring module; the measurement module calculates measurement data, converts the measurement data into binary codes and sends the binary codes to the data transmission module; the data transmission module transmits the measured data to the single chip microcomputer to complete the processing of the measured data, and the display of the measured data is completed through the display after the processing is completed;
the signals to be measured comprise a start signal and an end signal of a time interval to be measured and a clock signal generated by a crystal oscillator circuit;
the measuring module comprises a rough measuring unit, a fine measuring unit and a data processing unit; the rough measurement unit is used for calculating the period number between the starting signal and the ending signal in the time interval to be measured and transmitting period data to the data processing unit; the fine measurement unit measures a time interval less than one period by using a delay unit in the measurement module to obtain differential delay line data and transmits the delay line data to the data processing unit; the data processing unit calculates the measurement data of the time interval according to the period data and the delay line data and sends the measurement data to the data transmission module.
2. The time interval measuring device as claimed in claim 1, wherein the measuring module is an FPGA chip, the FPGA chip is configured with delay units therein, the differential delay line includes two sets of delay units, the start signal and the stop signal respectively pass through the differential delay line, wherein the delay time of the start signal passing through the differential delay line is longer than the delay time of the stop signal passing through the differential delay line, and the difference between the two is the differential delay line data.
3. A time interval measuring device according to claim 2, wherein the clock signal is multiplied by a phase locked loop PLL internal to the FPGA as a reference frequency signal for the time interval measurement.
4. The time interval measuring device as claimed in claim 2, wherein the single chip microcomputer uses an MSP430 chip and is in serial communication with the computer through a level conversion circuit.
5. The interval measuring device of claim 4, further comprising a power module, wherein the power module provides voltage to the FPGA chip and the single chip.
6. A time interval measuring device according to claim 5, wherein said crystal oscillator circuit employs a 20MHz crystal oscillator source, and the power supply of the crystal oscillator is filtered by an LC filter.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113934132A (en) * | 2021-10-12 | 2022-01-14 | 湖南师范大学 | High-precision time synchronization system and synchronization method based on Beidou clock signal |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113934132A (en) * | 2021-10-12 | 2022-01-14 | 湖南师范大学 | High-precision time synchronization system and synchronization method based on Beidou clock signal |
| CN113934132B (en) * | 2021-10-12 | 2022-05-27 | 湖南师范大学 | High-precision time synchronization system and synchronization method based on Beidou clock signal |
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