CN107819456B - High-precision delay generator based on FPGA carry chain - Google Patents
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Abstract
The invention discloses a high-precision delay generator based on an FPGA carry chain, which comprises a communication and control interface module, a coarse delay generation module and a fine delay generation module, wherein the communication and control interface module comprises the following three parts: the communication and control interface module is used for receiving digital delay information, generating a delay trigger signal and generating a reset signal; the coarse delay generating module generates an initial delay difference with a large dynamic range according to coarse delay precision; the fine delay generating module generates high-precision compensation delay difference with fine delay precision; the sum of the initial delay difference and the compensation delay difference constitutes the overall delay difference. The main structure of the fine delay generation module is a Vernier delay loop constructed by a carry chain, and the tail end of the carry chain is connected back to the head end to form an oscillation loop structure. The high-precision delay generator designed based on the FPGA on-chip resources has reconfigurability and strong system integration capability, and can realize the unification of high resolution and large dynamic range.
Description
Technical Field
The invention belongs to the technical field of high-precision automatic test instruments, and particularly relates to a high-precision delay generator based on an FPGA carry chain.
Background
The high-precision time delay generator is used for generating two electric pulse signals with a certain time interval, and the size of the interval is set by digital programming. The method has important application value in the fields of high-precision automatic test instruments such as a Very Large Scale Integration (VLSI) function test, a phase-locked loop (PLL) test, an Integrated Circuit (IC) pulse characteristic test, a time-to-digital converter (TDC) test, a clock synthesizer test and the like. In addition, the functional module is also a key functional module required by large-scale instruments such as certain high-energy physical experiment devices, event coincidence systems, nuclear medicine imaging devices and the like.
However, there are few companies currently on the market that can provide sub-nanosecond precision delay generators, of which the AD9501 model delay chip manufactured by ADI is an excellent representative of these few products, which provides a minimum delay resolution of 10ps and a delay precision of 53ps, but a dynamic operating range of only 8 bits, corresponding to a maximum adjustable delay of only 2.5 ns. In addition, due to the characteristics of Application Specific Integrated Chips (ASICs), systems developed by using such chips as delay generators have a long marketing period, are difficult to adapt to the changing requirements of functional parameters, and have poor flexibility.
Due to the reconfigurable characteristic of the field programmable logic array (FPGA), the flexibility suitable for various specific application environments is improved, the market-oriented speed of products can be accelerated, and the research and development cost can be remarkably saved. As described above, the high-precision delay generator is a key component module in the technical field of high-precision automatic testing, and thus the degree of flexibility of integration with the whole system is also an important factor for measuring the application value of the delay generator, which determines that the delay generator based on the FPGA platform has a wide application prospect. However, the variety of logic resources in the FPGA is limited, which severely limits the degree of freedom of design, and thus the current scheme is still very deficient for realizing a high-precision delayer based on the logic resources in the FPGA chip.
Disclosure of Invention
The invention aims to provide a delay generator with high resolution and large dynamic range based on an FPGA carry chain.
The technical solution for realizing the purpose of the invention is as follows: the utility model provides a high accuracy delay generator based on FPGA carry chain, includes communication and control interface module, thick time delay generation module, thin time delay generation module three part, wherein:
the communication and control interface module receives digital delay information from a PC, generates a delay trigger signal and generates a reset signal after the work of the delayer is finished;
the coarse delay generating module generates an initial delay difference with coarse delay precision, and determines the dynamic working range of the whole delay generator;
the fine delay generating module generates compensation delay difference with fine delay precision, and determines the delay resolution of the whole delay generator; the sum of the initial delay difference and the compensation delay difference constitutes the overall delay difference.
Further, the digital delay information received by the communication and control interface module from the PC is a combination of values (m, n), where m represents coarse digital delay information and n represents fine digital delay information; the expected delay difference, r, is expressed as Δ TcRepresenting the resolution, r, of the coarse delay generating modulefRepresenting the resolution of the fine delay generating module, then
Wherein the operator
Meaning taking an integer no greater than x.
Furthermore, the coarse delay generation module comprises an enabling control unit, a multiplexer and a pulse extraction unit, after the enabling control unit judges that the effective delay trigger signal is received, the multiplexer is controlled to communicate a clock signal to the pulse extraction unit, and the pulse extraction unit generates a coarse leading output signal and a coarse lagging output signal.
Furthermore, the pulse extraction unit comprises two counters, two comparators and two pulse shaping units, and the pulse extraction unit is provided with two input ports which are respectively connected with the clock ports of the two counters; since the input signal is an oscillating signal, the oscillating signal can drive the corresponding counter to count up 1 time on each rising edge of the signal; a corresponding comparator is arranged behind each counter, one input end of each comparator is connected with the output end of the counter, and the other input end of each comparator is a fixed preset value; when the result of the counter is larger than or equal to the preset value, the comparator outputs high level to trigger the pulse shaping unit to generate a delay output signal.
Furthermore, the pulse shaping unit comprises 1D flip-flop and 1 delay buffer, a data port of the D flip-flop is connected with a fixed high level, a clock port is connected with a signal to be shaped, an output port is connected with an input end of the delay buffer, and the total amount of the processed signals is TpAfter the delay, the output port of the D flip-flop is accessed to the clear port of the D flip-flop.
Furthermore, one input end of each comparator is connected with the output end of the counter, the other input end of each comparator is a fixed preset value, one comparator controls to output a coarse leading signal and the preset value is 0, and the other comparator controls to output a coarse lagging signal and the preset value is m.
Furthermore, the fine delay generating module comprises a Vernier delay ring and a pulse extracting unit, wherein a coarse leading output signal of the coarse delay generating module is connected into a fast delay ring in the Vernier delay ring, and a coarse lagging output signal is connected into a slow delay ring in the Vernier delay ring, and is respectively propagated in corresponding rings to form continuous oscillation signals; the pulse extraction unit respectively judges the oscillation times of the signals in the two rings and extracts and outputs the oscillation signals when the oscillation times reach n, wherein the extracted signal in the fast delay ring is output in a fine lead mode, and the extracted signal in the slow delay ring is output in a fine lag mode.
Furthermore, the Vernier delay loop comprises a fast delay loop and a slow delay loop, the Vernier delay loop is formed by a carry chain in the FPGA, and the tail end of the carry chain is connected back to the head end to form an oscillation loop structure; each delay loop comprises a pulse shaping unit, a carry chain and a multiplexer, and the fast delay loop comprises p basic delay units and generates an oscillation period TfThe slow delay loop comprises q basic delay units and generates an oscillation period Ts(ii) a Construction time guarantee p<q, then T is obtainedf<Ts(ii) a The structure of the pulse shaping unit in the delay loop is completely the same as that of the pulse shaping unit in the coarse delay generation module, and the pulse shaping unit is used for stabilizing the duty ratio of the oscillation signal when the oscillation signal is transmitted in the delay loop; the multiplexer is used for disconnecting the loop circuit and resetting the internal state after receiving the reset signal.
Furthermore, the circuit structures of the pulse extraction unit in the fine delay generation module and the pulse extraction unit in the coarse delay generation module are completely the same, but the preset values of the two comparators in the pulse extraction unit of the fine delay generation module are both n.
Compared with the prior art, the invention has the following remarkable advantages: (1) as most large-scale instruments such as automatic test instruments, high-energy nuclear experimental devices, nuclear medicine imaging devices and the like generally adopt the FPGA as a main control unit, the FPGA-based delay generator is convenient for realizing system integration, and the development and application cost is obviously reduced; (2) the time delay generator adopts a method of combining coarse time delay and fine time delay, the digit of a counter used by the coarse time delay is easy to expand, and compared with the existing delay chip, the time delay generator can realize the unification of high resolution and large dynamic range; (3) carry chain (carry chain) is designed specially in FPGA for realizing fast addition, comparison and other functional operations, the delay amount of its basic unit is very small, and it provides a feasible idea for realizing high-precision delay generator.
Drawings
Fig. 1 is a schematic structural diagram of a high-precision delay generator based on an FPGA carry chain according to the present invention.
Fig. 2 is a timing diagram of the operation of the high-precision delay generator according to the embodiment of the present invention.
Fig. 3 is a circuit diagram of a pulse decimation unit according to an embodiment of the present invention.
Fig. 4 is a circuit structure diagram of a Vernier delay loop according to an embodiment of the present invention.
Fig. 5 is a schematic diagram of a method for designing a Vernier delay loop based on a two-step method according to an embodiment of the present invention.
FIG. 6 is a graph of the measured nonlinear error of the example of the present invention, wherein (a) is a graph of the measured nonlinear error DNL of the example, and (b) is a graph of the measured nonlinear error INL of the example.
Detailed Description
With reference to fig. 1, the high-precision delay generator based on the FPGA carry chain of the present invention includes three parts, namely a communication and control interface module, a coarse delay generating module, and a fine delay generating module, wherein:
the communication and control interface module receives digital delay information from a PC, generates a delay trigger signal and generates a reset signal after the work of a delayer is finished;
the digital delay information received by the communication and control interface module from the PC is a numerical combination (m, n), wherein m represents coarse digital delay information, and n represents fine digital delay information; the expected delay difference, r, is expressed as Δ TcRepresenting the resolution, r, of the coarse delay generating modulefRepresenting the resolution of the fine delay generating module, then
Wherein the operator
Meaning taking an integer no greater than x.
Secondly, the coarse delay generating module generates an initial delay difference with coarse delay precision, and determines the dynamic working range of the whole delay generator;
the coarse delay generation module comprises an enabling control unit, a multiplexer and a pulse extraction unit, after the enabling control unit judges that an effective delay trigger signal is received, the multiplexer is controlled to communicate a clock signal to the pulse extraction unit, and the pulse extraction unit generates coarse leading output signals and coarse lagging output signals.
The pulse extraction unit comprises two counters, two comparators and two pulse shaping units, and is provided with two input ports which are respectively connected with clock ports of the two counters; since the input signal is an oscillating signal, the oscillating signal can drive the corresponding counter to count up 1 time on each rising edge of the signal; a corresponding comparator is arranged behind each counter, one input end of each comparator is connected with the output end of the counter, and the other input end of each comparator is a fixed preset value; when the result of the counter is larger than or equal to the preset value, the comparator outputs high level to trigger the pulse shaping unit to generate a delay output signal.
The pulse shaping unit comprises 1D trigger and 1 delay buffer, the data port of the D trigger is connected with a fixed high level, the clock port is connected with a signal to be shaped, the output port is connected with the input end of the delay buffer, and the total amount of the processed signals is TpAfter the delay, the output port of the D flip-flop is accessed to the clear port of the D flip-flop.
One input end of each comparator is connected with the output end of the counter, the other input end of each comparator is a fixed preset value, one comparator controls output of the rough leading signal and the preset value is 0, and the other comparator controls output of the rough lagging signal and the preset value is m.
Thirdly, the fine delay generation module generates compensation delay difference with fine delay precision, and determines the delay resolution of the whole delay generator; the sum of the initial delay difference and the compensation delay difference constitutes the overall delay difference.
The fine delay generating module comprises a Vernier delay ring and a pulse extracting unit, wherein a coarse leading output signal of the coarse delay generating module is connected into a fast delay ring in the Vernier delay ring, and a coarse lagging output signal of the coarse delay generating module is connected into a slow delay ring in the Vernier delay ring, and is respectively propagated in corresponding rings to form continuous oscillation signals; the pulse extraction unit respectively judges the oscillation times of the signals in the two rings and extracts and outputs the oscillation signals when the oscillation times reach n, wherein the extracted signal in the fast delay ring is output in a fine lead mode, and the extracted signal in the slow delay ring is output in a fine lag mode.
The Vernier delay loop comprises a fast delay loop and a slow delay loop, the Vernier delay loop is formed by an FPGA internal carry chain, and the tail end of the carry chain is connected back to the head end to form an oscillation loop structure; each delay loop comprises a pulse shaping unit, a carry chain and a multiplexer, and the fast delay loop comprises p basic delay units and generates an oscillation period TfThe slow delay loop comprises q basic delay units and generates an oscillation period Ts(ii) a Construction time guarantee p<q, then T is obtainedf<Ts(ii) a The structure of the pulse shaping unit in the delay loop is completely the same as that of the pulse shaping unit in the coarse delay generation module, and the pulse shaping unit is used for stabilizing the duty ratio of the oscillation signal when the oscillation signal is transmitted in the delay loop; the multiplexer is used for disconnecting the loop circuit and resetting the internal state after receiving the reset signal.
The circuit structures of the pulse extraction unit in the fine delay generation module and the pulse extraction unit in the coarse delay generation module are completely the same, but the preset values of two comparators in the pulse extraction unit of the fine delay generation module are both n.
Example 1
As shown in fig. 1, the present invention provides a high-precision delay generator based on an FPGA carry chain, which includes three parts, a communication and control interface module, a coarse delay generating module and a fine delay generating module. The communication and control interface module functions to receive digital delay information from the PC, generate a delay trigger signal, and generate a reset signal after the operation of the delay is completed. The function of the coarse delay generation module is to generate delay difference with a larger dynamic range by coarse delay precision. The function of the fine delay generation module is to generate high-precision compensation delay difference with fine delay precision. The sum of the coarse delay difference and the fine delay difference constitutes the overall delay difference. The delay resolution of the whole delay generator is determined by the fine delay generating module, and the dynamic working range is determined by the coarse delay generating module.
As shown in the timing diagram of fig. 2, the operation principle of the delay generator is:
(1) the communication and control interface module receives digital delay information from the PC terminal and generates a delay trigger signal to output to the coarse delay generation module. The digital delay information is a combined value (m, n) calculated by the PC end according to the coarse delay resolution, the fine delay resolution and the delay difference Delta T required to be obtained of the delay generator, wherein m corresponds to the coarse delay information, and n corresponds to the fine delay information. By (r)c,rf) Represents the combined resolution, where rcRepresenting the resolution, r, of the coarse delay generating modulefRepresenting the resolution of the fine delay generation module. The formula of the PC-side calculation (m, n) is:
wherein
Represents an integer no greater than x.
(2) After receiving the delay trigger signal, the coarse delay generation module starts a coarse counter to work, and when the counter value is 0And outputting a first pulse signal as a coarse leading signal, and outputting a second pulse signal as a coarse lagging signal when the counter value is m. By TclkRepresenting the size of the clock cycle driving the coarse counter, then rc＝Tclk. The working mode ensures that the delay difference between the coarse leading signal and the coarse lagging signal output by the coarse delay generating module is m.TclkBoth signals are coupled to a fine delay generation module.
(3) The fine delay generation module generates a fine delay difference based on Vernier principle, and comprises two oscillation rings with different oscillation periods. The coarse leading signal is switched into the fast oscillation loop and the coarse lagging signal is switched into the slow oscillation loop. By TfIndicating the period of oscillation, T, of the fast oscillating ringsIndicating the period of oscillation of the slow oscillating loop. After two signals circulate in respective oscillation rings once, the signal in the fast oscillation ring will lead the signal in the slow oscillation ring by 1 time difference of fine resolution: r isf＝Ts-Tf. The oscillation signals in the two oscillation rings respectively drive two different fine counters to work, when the value of the fine counter becomes n, the oscillation signal in the oscillation ring corresponding to the fine counter is extracted as an output signal, and the fine delay difference generated by the extraction is as follows: n (T)s-Tf). The output signal of the fast oscillation ring is used as a fine leading signal, and the output signal of the slow oscillation ring is used as a fine lagging signal. Combining the coarse delay provided in step (2), the delay difference between the two signals is: Δ T ═ m.Tclk+n·(Ts-Tf) Which is equal to the amount of delay expected to be achieved by the digital programming.
(4) After the time delay generator finishes working, the communication and control interface module generates a reset signal, resets the coarse time delay generating module and the fine time delay generating module, and waits for the start of the next working state.
An FPGA chip model used in one embodiment of the present invention is EP3SE110F1152I3 (Stratix iii series chip manufactured by Altera corporation). The design tool is Quartus II 13.1 version, which provides a complete set of solutions for logic function description, compilation, placement, routing, and post-engineering tuning.
The coarse delay generation module is composed of an enable control unit, a multiplexer and a pulse extraction unit, and the structure of the coarse delay generation module is shown in fig. 1. The function of the enabling control unit is: and when the effective time delay trigger signal is judged to be received, the multiplexer is controlled to communicate the clock signal to the pulse extraction unit so as to drive the pulse extraction unit to start working. The pulse decimation unit comprises two counters, two comparators and two pulse shaping units, and the specific circuit implementation thereof is shown in fig. 3. It has two input ports connected to the clock ports of two counters. Since the input signal is an oscillating signal, it can drive the corresponding counter to count up 1 time on each rising edge of the signal. And a corresponding comparator is arranged behind each counter, one input end of the comparator is connected with the output end of the counter, and the other input end of the comparator is a fixed preset value. When the result of the counter is larger than or equal to the preset value, the comparator outputs high level to trigger the pulse shaping unit to generate a delay output signal. The preset value of the comparator for controlling the output of the rough leading signal is 0, and the preset value of the comparator for controlling the output of the rough lagging signal is m. Since the comparator outputs a high level of a continuous type, it needs a pulse shaping unit to convert it into a pulse signal having a certain width. It is composed of 1D trigger and 1 delay buffer, the data port of D trigger is connected with fixed high level, the clock port is connected with signal to be shaped, the output port is connected with input end of delay buffer, and the total quantity of T passed through itpAnd accessing the emptying port of the D trigger after the delay.
The fine delay generation module consists of a Vernier delay loop and a pulse extraction unit. The specific circuit implementation of the Vernier delay loop is shown in fig. 4, and it includes two delay lines with different delay precisions, i.e. fast and slow delay lines. The delay line is formed based on a carry chain in the FPGA, the delay amount of a basic delay unit of the delay line is very small, and the delay line is the best on-chip resource for realizing the high-precision delay line. In the technical scheme provided by the invention, the tail end of the delay line is connected back to the head end of the delay line to form an oscillating ring structure. Each delay loop is composed of a pulse shaping unit, a carry chain and a multiplexer. The fast delay loop includes p basic delay units, andthe slow delay loop comprises q basic delay units, and constructs a time order p<q, two oscillation rings with different oscillation periods can be formed, and the oscillation period satisfies Tf<Ts. The structure of the pulse shaping unit is completely the same as that of the pulse shaping unit in the coarse delay generation module, and the pulse shaping unit has the function of stabilizing the duty ratio of the oscillation signal when the oscillation signal is transmitted in the ring. The multiplexer is used for disconnecting the loop circuit and resetting the internal state thereof after receiving the reset signal so as to prepare for the next work.
Due to the characteristics of the internal logic resource structure of the FPGA, the oscillation period of the delay ring is not easy to control, and it is very difficult to obtain an oscillation ring with the expected fine resolution. This example presents a design idea based on a two-step process, the process of which is shown in fig. 5. Firstly, establishing an independent Quartus II project, designing an oscillation ring which is based on a carry chain and comprises n basic delay units by using logic lock and design partition tools, requiring n > q > p, and exporting layout and wiring information after compiling. And secondly, establishing a new Quartus II project, repeatedly utilizing logic lock and design partition tools to lead the oscillation ring structure into two different logic areas in the chip, further obtaining two delay line loops with similar structures, and finely adjusting the oscillation period difference of the two delay rings on the basis. Through the first step of operation, the two delay rings can be ensured to have the same circuit structure, including the specific realization of the LUT and the connection mode between the LUT and the LUT, so that the LUT and the LUT are ensured to have the same oscillation period as much as possible, and a foundation is provided for the fine adjustment of the oscillation period difference in the second step. In a second operation, using an Engineering Change Orders (ECO) tool, the loop iteratively finds a delay loop with a longer period of oscillation, and then disconnects the connection at its end connected to the pulse shaping module, shortens the length of one elementary delay unit and reconnects it to the pulse shaping module until the desired difference in period of oscillation is obtained. In order to observe the oscillation period of each delay ring and the mutual relation between the oscillation period and the delay ring, two paths of signals can be led out of the chip from the fine adjustment position, and the signals are accessed into an oscilloscope with a dual-channel function to be obtained visually. For example, in fig. 5, through the fine tuning process, the resulting fast oscillation loop includes p basic delay units, and the resulting slow oscillation loop includes q basic delay units.
The structure of the pulse extraction unit of the fine delay generation module is completely the same as that of the pulse extraction unit of the coarse delay generation module, and the only difference is that preset values of two comparators in the pulse extraction unit of the fine delay generation module are all n. The control method comprises the steps of controlling the signals in the fast oscillating ring and the slow oscillating ring in the Vernier delay ring to oscillate n times respectively, and then extracting corresponding oscillating signals to be used as fine leading signals and fine lagging signals. Thereby adding a delay quantity n (T) on the basis of the coarse delays-Tf) So that the total delay amount is Δ T ═ m · Tclk+n·(Ts-Tf)。
Aiming at the embodiment provided by the invention, the clock working frequency of the slow delay generation module is set to be 500MHz, so the slow delay resolution is 2 ns. The data width of the counter and the comparator of the pulse extraction unit of the coarse delay generation module are both 16 bits, so that the dynamic working range is 2ns × 65536 — 131 μ s, and it can be seen that the dynamic working range is greatly expanded compared with the existing product. If a larger dynamic working range is needed, only the data width of the counter and the comparator needs to be expanded, and the upgrading potential is huge, convenient and flexible. The resolution of the fine delay generation module is determined by the specific oscillation period of the fast and slow oscillation rings in the Vernier delay ring, and is related to the number p and q of the basic delay units obtained in design, and is generally obtained by measurement of an oscilloscope. This embodiment uses an oscilloscope model 740Zi from legrooy corporation as the test device, which provides a direct measurement of the delay difference of the two-channel signal and contains the results of the usual statistical parameters. The method for determining the resolution of the fine delay comprises the following steps of (1) using Delta T (n) to represent the delay difference measured by an oscilloscope under the condition that the digital information of the fine delay is n: let m be 0 and N be increased until the first minimum value N is found, which makes the delay difference larger than the coarse delay precision (2 ns in this embodiment)minThen, the calculation formula of the fine delay precision is: r isf＝△T(Nmin)/Nmin. In addition, to measure the performance of the delayer, the nonlinearityError is an important reference index. It can be expressed in Differential Nonlinearity (DNL) and Integral Nonlinearity (INL).
For the high-precision delay generator of this embodiment, the compiled result report shows that the LUT resource consumption is 1134 and the register consumption is 146, which indicates that the resource overhead required for implementing the technique of the present invention is very small. The results of the INL and DNL measurements are shown in FIG. 6, in which FIG. 6(a) is a graph of the non-linear error DNL measured in the examples and FIG. 6(b) is a graph of the non-linear error INL measured in the examples. The range of INL and DNL results was (-0.18LSB,0.24LSB) \ (-0.02LSB,0.01 LSB). The graph covers the fine delay profile results within a coarse delay resolution, where N corresponds to the maximum delay positionmin52, the actual delay result is 2010ps, so the fine delay resolution is 2010/52-38.6 ps.
Claims (5)
1. The utility model provides a high accuracy delay generator based on FPGA carry chain which characterized in that, includes communication and control interface module, thick time delay generation module, thin time delay generation module three part, wherein:
the communication and control interface module receives digital delay information from a PC, generates a delay trigger signal and generates a reset signal after the work of the delayer is finished;
the coarse delay generating module generates an initial delay difference with coarse delay precision, and determines the dynamic working range of the whole delay generator;
the fine delay generating module generates compensation delay difference with fine delay precision, and determines the delay resolution of the whole delay generator; the sum of the initial delay difference and the compensation delay difference forms an integral delay difference;
the digital delay information received by the communication and control interface module from the PC is a numerical combination (m, n), wherein m represents coarse digital delay information, and n represents fine digital delay information; the expected delay difference, r, is represented by Δ TcRepresenting the resolution, r, of the coarse delay generating modulefRepresenting the resolution of the fine delay generating module, then
Wherein the operator
Representing taking an integer not greater than x;
the coarse delay generating module comprises an enabling control unit, a multiplexer and a pulse extracting unit, wherein after the enabling control unit judges that an effective delay trigger signal is received, the multiplexer is controlled to communicate a clock signal to the pulse extracting unit, and the pulse extracting unit generates coarse leading output signals and coarse lagging output signals;
the fine delay generating module comprises a Vernier delay ring and a pulse extracting unit, wherein a coarse leading output signal of the coarse delay generating module is connected into a fast delay ring in the Vernier delay ring, and a coarse lagging output signal of the coarse delay generating module is connected into a slow delay ring in the Vernier delay ring, and is respectively propagated in corresponding rings to form continuous oscillation signals; the pulse extraction unit respectively judges the oscillation times of the signals in the two rings and extracts and outputs the oscillation signals when the oscillation times reach n, wherein the extracted signal in the fast delay ring is output in a fine lead mode, and the extracted signal in the slow delay ring is output in a fine lag mode;
the Vernier delay loop comprises a fast delay loop and a slow delay loop, the Vernier delay loop is formed by an FPGA internal carry chain, and the tail end of the carry chain is connected back to the head end to form an oscillation loop structure; each delay loop comprises a pulse shaping unit, a carry chain and a multiplexer, and the fast delay loop comprises p basic delay units and generates an oscillation period TfThe slow delay loop comprises q basic delay units and generates an oscillation period Ts(ii) a When p is less than q during construction, T is obtainedf＜Ts(ii) a The structure of the pulse shaping unit in the delay loop is completely the same as that of the pulse shaping unit in the coarse delay generation module, and the pulse shaping unit is used for stabilizing the duty ratio of the oscillation signal when the oscillation signal is transmitted in the delay loop; multiple purposeThe way selector is used for disconnecting the loop circuit and resetting the internal state after receiving the reset signal.
2. The FPGA carry chain-based high-precision delay generator according to claim 1, wherein the pulse extraction unit comprises two counters, two comparators and two pulse shaping units, and the pulse extraction unit has two input ports respectively connected to the clock ports of the two counters; since the input signal is an oscillating signal, the oscillating signal can drive the corresponding counter to count up 1 time on each rising edge of the signal; a corresponding comparator is arranged behind each counter, one input end of each comparator is connected with the output end of the counter, and the other input end of each comparator is a fixed preset value; when the result of the counter is larger than or equal to the preset value, the comparator outputs high level to trigger the pulse shaping unit to generate a delay output signal.
3. The FPGA carry chain-based high-precision delay generator according to claim 2, wherein the pulse shaping unit comprises 1D flip-flop and 1 delay buffer, a data port of the D flip-flop is connected with a fixed high level, a clock port is connected with a signal to be shaped, and an output port is connected with an input end of the delay buffer and passes through a total of TpAfter the delay, the output port of the D flip-flop is accessed to the clear port of the D flip-flop.
4. The FPGA carry chain-based high precision delay generator of claim 2, wherein one input terminal of each comparator is connected to the output terminal of the counter, and the other input terminal is a fixed preset value, wherein one comparator controls the output of the coarse lead signal and the preset value is 0, and the other comparator controls the output of the coarse lag signal and the preset value is m.
5. The FPGA carry chain-based high-precision delay generator according to claim 1, wherein the pulse extraction units in the fine delay generation module and the coarse delay generation module have the same circuit structure, but the preset values of the two comparators in the pulse extraction units of the fine delay generation module are both n.
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| CN109743125B (en) * | 2019-01-31 | 2024-05-17 | 上海创远仪器技术股份有限公司 | Circuit structure for realizing accurate delay processing aiming at ultra-large bandwidth wireless channel simulation |
| CN112968690B (en) * | 2021-02-09 | 2022-12-23 | 天津大学 | High-precision low-jitter delay pulse generator |
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