CN211125038U - Write operation circuit and semiconductor memory - Google Patents

Abstract

An embodiment of the present application provides a write operation circuit and a semiconductor memory, including: a data judgment module for determining whether to flip the current input data according to the previous input data of the semiconductor memory and the number of bits of data change in the current input data to generate flip identification data and intermediate data; the data buffer module is used for determining the initial state of the global bus according to the enable signal and the intermediate data; and the data receiving module is used for receiving the global bus data on the global bus, receiving the overturning identification data through the overturning identification signal line, decoding the global bus data according to the overturning identification data, writing the decoded data into a storage block stored in the semiconductor, and determining whether the global bus data is overturned. The technical scheme of the embodiment of the application can reduce the turnover frequency of the internal global bus, greatly compress the current and reduce the power consumption under the TriState architecture.

Description

Write operation circuit and semiconductor memory

Technical Field

The present application relates to the field of semiconductor memory technologies, and in particular, to a write operation circuit and a semiconductor memory.

Background

This section is intended to provide a background or context to the embodiments of the application that are recited in the claims. The description herein is not admitted to be prior art by inclusion in this section.

The semiconductor Memory includes a Static Random Access Memory (SRAM), a Dynamic Random Access Memory (DRAM), a Synchronous Dynamic Random Access Memory (SDRAM), a Read-Only Memory (ROM), and a flash Memory.

In the DRAM protocol of Joint Electron Device Engineering Council (JEDEC), there are specific requirements for DRAM speed and power saving. How to save more power for the DRAM and ensure the integrity of the signal and the reliability of data transmission and storage is an urgent problem to be solved in the industry.

SUMMERY OF THE UTILITY MODEL

Embodiments of the present application provide a write operation circuit, a semiconductor memory, and a write operation method, so as to solve or alleviate one or more technical problems in the prior art.

In a first aspect, an embodiment of the present application provides a write operation circuit applied to a semiconductor memory, including:

a data judgment module for determining whether to flip the current input data according to the previous input data of the semiconductor memory and the number of bits of data change in the current input data to generate flip identification data and intermediate data;

the data buffer module is connected with the data judgment module and used for determining the initial state of the global bus according to the enabling signal and the intermediate data;

and the data receiving module is connected with the storage block, receives the global bus data on the global bus, receives the overturning identification data through the overturning identification signal line, decodes the global bus data according to the overturning identification data, writes the decoded data into the storage block stored by the semiconductor, and determines whether the global bus data is overturned or not.

In one embodiment, the data judgment module is used for determining change marking data according to the change between the current input data and the previous input data; and under the condition that the high digit in the change marking data is larger than a preset value, outputting the turnover data of the current input data as intermediate data, and setting the turnover identification data to be high; and under the condition that the high digit in the change marking data is less than or equal to the preset value, outputting the original current input data as intermediate data, and setting the overturn identification data to be low.

In one embodiment, the data determination module includes;

the data comparison unit is used for setting the change marking data to be low under the condition that the current input data and the previous input data are not changed; setting the change mark data to be high under the condition that the current input data and the previous input data are changed;

the data judgment unit is used for setting the turning identification data to be high under the condition that the digit of the data with high level in the changing identification data is greater than a preset value; and setting the turnover identification data to be low under the condition that the digit of the data which is high in the change marking data is less than or equal to a preset value;

the data selector receives the overturning identification data through the overturning identification signal line, and is used for outputting the overturning data of the current input data as intermediate data under the condition that the overturning identification data is high; and outputting the original current input data as intermediate data in the case that the flip flag data is low.

In one embodiment, the data comparison unit includes;

the latch is used for latching the state of the previous input data and a previous clock signal corresponding to the previous input data;

the state comparator is connected with the latch and is used for setting the change mark data to be low under the condition that the state of the current input data and the state of the previous input data are not changed; and setting the change flag data to be high when the state of the current input data and the state of the previous input data are changed.

In one embodiment, the change mark data and the middle data are divided into M groups, the flip identification data is M bits, the M bits of flip identification data correspond to the M groups of change mark data one to one, and the M bits of flip identification data correspond to the M groups of middle data one to one, where M is an integer greater than 1.

In one embodiment, each set of change mark data is N bits, where N is an integer greater than 1, and the data judgment module is configured to output, as a corresponding set of intermediate data, the inverted data of the input set of change mark data when the number of bits of data that is high in the input set of change mark data is greater than N/2, and set the one-bit inverted flag data corresponding to the input set of change mark data to high; and under the condition that the bit number of high data in the input group of change mark data is less than or equal to N/2, outputting the input group of change mark data as a corresponding group of intermediate data, and setting the one-bit upset identification data corresponding to the input group of change mark data to be low.

In one embodiment, the data selector includes M data selection units, the data selection unit including:

the input end of the second inverter receives the overturning identification data through the overturning identification signal line;

the input end of the third inverter is connected to the data judging unit and used for receiving current input data from the data judging unit;

the input end of the first transmission gate is connected to the output end of the third phase inverter, the output end of the first transmission gate is connected to the data buffer module and used for outputting intermediate data to the data buffer module, the reverse control end of the first transmission gate is connected to the output end of the second phase inverter, and the positive control end of the first transmission gate receives the overturning identification data through the overturning identification signal line;

and the input end of the second transmission gate is connected with the data judgment unit and is used for receiving current input data from the data judgment unit, the output end of the second transmission gate is connected with the data buffer module and is used for outputting intermediate data to the data buffer module, the reverse control end of the second transmission gate receives the overturning identification data through the overturning identification signal line, and the positive control end of the second transmission gate is connected with the output end of the second phase inverter.

In one embodiment, the global bus data is M groups, M bit flip identification data corresponds to the M groups of global bus data one to one, the data receiving module includes M data receiving units, the data receiving units are connected to the storage block, and the data receiving units are configured to decode the corresponding groups of global bus data according to the one bit flip identification data.

In one embodiment, a data receiving unit includes:

the input end of the fourth inverter receives the overturning identification data through the overturning identification signal line;

the input end of the fifth inverter receives global bus data through a global bus;

the input end of the third transmission gate is connected to the output end of the fifth phase inverter, the output end of the third transmission gate is connected with the storage block and used for outputting decoded data to the storage block, the inverse control end of the third transmission gate is connected to the output end of the fourth phase inverter, and the positive control end of the third transmission gate receives the overturning identification data through the overturning identification signal line;

and the input end of the fourth transmission gate receives global bus data through a global bus, the output end of the fourth transmission gate is connected with the storage block and used for outputting decoded data to the storage block, the inverse control end of the fourth transmission gate receives the overturning identification data through an overturning identification signal line, and the positive control end of the fourth transmission gate is connected with the output end of the fourth phase inverter.

In one embodiment, a data buffering module includes;

the two input ends of the logic NAND gates respectively receive an enable signal and current input data;

a plurality of fifth inverters, an input terminal of which receives the enable signal;

the two input ends of the logic NOR gates respectively receive the current input data and are connected to the fifth inverter;

the grid electrode of the PMOS transistor is connected with the output end of the logic NAND gate, and the drain electrode of the PMOS transistor is connected with the global bus;

and the grid electrode of the NMOS transistor is connected with the output end of the logic NOR gate, and the drain electrode of the NMOS transistor is connected with the global bus and the drain electrode of the NMOS transistor.

In a second aspect, embodiments of the present application provide a semiconductor memory including any one of the above write operation circuits.

By adopting the technical scheme, the embodiment of the application can reduce the turnover frequency of the internal global bus, greatly compress the current and reduce the power consumption under a TriState (TriState) architecture.

The foregoing summary is provided for the purpose of description only and is not intended to be limiting in any way. In addition to the illustrative aspects, embodiments, and features described above, further aspects, embodiments, and features of the present application will be readily apparent by reference to the drawings and following detailed description.

Drawings

In the drawings, like reference numerals refer to the same or similar parts or elements throughout the several views unless otherwise specified. The figures are not necessarily to scale. It is appreciated that these drawings depict only some embodiments in accordance with the disclosure and are therefore not to be considered limiting of its scope.

Fig. 1 is a block diagram schematically showing the structure of a semiconductor memory portion of one embodiment of the present embodiment;

fig. 2 is a block diagram schematically showing the structure of a semiconductor memory portion of another embodiment of the present embodiment;

FIG. 3 is a block diagram schematically illustrating a data determination module according to an embodiment of the present invention

FIG. 4 schematically shows a block diagram of a data comparison unit of an embodiment of the present embodiment;

FIG. 5 schematically shows a circuit diagram of a data buffering module according to an embodiment of the present embodiment;

FIG. 6 schematically shows a block diagram of a data selection unit of an embodiment of the present embodiment;

FIG. 7 is a block diagram schematically illustrating a data receiving module according to an embodiment of the present invention

Fig. 8 schematically shows a block diagram of a data receiving unit according to an embodiment of the present invention.

Description of reference numerals:

20: a semiconductor memory;

21: a serial-to-parallel conversion circuit;

22: a data buffer module;

23: a data judgment module;

24: a DQ port;

25: a data receiving module;

26: a storage block;

221: a PMOS tube;

222: an NMOS tube;

223; a logic NAND gate;

224; a logical NOR gate;

225, a step of mixing; a fifth inverter;

231: a data judgment unit;

232: a data selector;

233: a data comparison unit;

233A: a latch;

233B; a state comparator;

232': a data selection unit;

232A: a second inverter;

232B: a third inverter;

232C: a first transmission gate;

232D: a second transmission gate;

250: a data receiving unit;

251: a fourth inverter;

252: a fifth inverter;

253: a third transmission gate;

254: and a fourth transmission gate.

Detailed Description

Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The same reference numerals denote the same or similar parts in the drawings, and thus, a repetitive description thereof will be omitted.

Fig. 1 schematically shows a block diagram of a structure of a semiconductor memory portion of one embodiment of the present embodiment. As shown in fig. 1, the semiconductor memory 20 includes a DQ port 24, a memory block (Bank)26, and a write operation circuit. The write operation circuit includes a Global Bus (Global Bus), a flip Flag (Flag) signal line, a serial-parallel conversion circuit 21, a Data determination module 23, a Data Buffer module (Data Buffer) 22, and a Data receiving module 25. In one embodiment, the semiconductor memory 20 is a DRAM, such as a fourth generation Double Data Rate SDRAM (DDR 4).

In one example, as shown in FIG. 1, 8 bits of first input data DQ <7:0> input from DQ port 24 are passed through the write operation circuitry to write data (i.e., decoded data) D <127:0> into memory block 26. An Active command opens a uniquely specified memory block 26, and a write operation can be performed to only one memory block 26. That is, when one Bank among eight memory blocks 26 (i.e., Bank <7:0>) is active, the other banks are inactive. It should be noted that the number of memory blocks 26, the number of data bits per memory block 26, and the number and number of data bits of the DQ port 24 are not limited in this embodiment. For example: the DQ port 24 may also be one, serving as input 8-bit first input data; the DQ ports 24 may also be two, i.e., each DQ port 24 is used to input 8 bits of first input data DQ <7:0> or DQ <15:8>, which in turn is input 16 bits of first input data DQ <15:0 >.

For example, as shown in FIG. 2, the first input data DQ <7:0> is written to a set of memory blocks Bank <7:0> by one of the write operation circuits described above; the first input data DQ <15:8> is written to another set of memory blocks Bank <15:8> by another write operation circuit as described above. Accordingly, of the eight memory blocks 26 corresponding to DQ <15:8> (i.e., Bank <15:8>), only one Bank is active and the other banks are inactive.

In one example, the write operation circuit may include a serial-to-parallel conversion circuit 21. The serial-to-parallel conversion circuit 21 is connected between the DQ port 24 and the data judgment module 24, and is configured to perform serial-to-parallel conversion on first input data of the DQ port 24 to generate second input data. For example: the serial-parallel conversion circuit 21 performs serial-parallel conversion on the 8-bit first input data DQ <7:0> to generate 128-bit second input data D2' <127:0> corresponding to Bank 0.

The semiconductor memory 20 has an array structure, and each unit structure may be the same, but the data output from each unit may be different due to the difference in the input data. The write operation circuit of the present embodiment will be described below by taking one of the memory blocks as an example.

As shown in fig. 1 and 2, the write operation circuit of the present embodiment includes a data judgment block 23 for determining whether to flip the present input data to generate the flip flag data and the intermediate data, based on the number of bits of data change in the previous input data and the present input data of the semiconductor memory 20.

In one example, the current input data may be current second input data, such as D2' <127:0 >.

The writing operation is carried out along with the clock signal, the previous writing operation corresponds to the previous clock signal, and then previous input data is input, and the current writing operation corresponds to the current clock signal, and then current input data is input. Therefore, the data determining module 23 is further configured to determine whether to flip the current input data according to the previous input data and the number of bits of data change in the current input data, so as to output the intermediate data and the Flag data for transmission by the Flag signal line.

In one embodiment, the data determining module 23 is configured to determine change marking data according to a change between current input data and previous input data; and under the condition that the high digit in the change marking data is larger than a preset value, outputting the turning data of the current input data as intermediate data, and setting Flag data to be high; and under the condition that the high digit in the change mark data is less than or equal to the preset value, outputting the original current input data as intermediate data, and setting Flag data to be low.

For example: the change flag data is 8 bits. If the number of bits equal to "1" in the change Flag data exceeds half, that is, exceeds 4 bits (e.g., 5 bits), Flag becomes 1, and the first intermediate data output is equal to the inverted data of the change Flag data. If the number of bits in the written data equal to "1" is less than half, for example, the data equal to "1" has 3 bits, Flag is equal to 0, and the first intermediate data output is equal to the original change Flag data.

Where data high may be data equal to "1" and data low may be data equal to "0". The flipping of data may be understood as a change from "0" to "1", or, from "1" to "0". The inversion of the data line or the signal line may be understood as a high level to a low level, or a low level to a high level.

In one embodiment, as shown in fig. 3, the data judging module 23 may include a data comparing unit 233, a data judging unit 231, and a data selector 232.

An input of the data comparison unit 233 receives input data. For example, an input terminal of the data comparing unit 233 may be connected to an output terminal of the serial-parallel conversion circuit 21 to receive the second input data. The data comparing unit 23 is used for setting the change flag data (such as D3' <127:0>) to be low when the current input data and the previous input data are not changed; and setting the change flag data to high in the case that the current input data and the previous input data are changed.

In one embodiment, as shown in fig. 4, the data comparing unit 233 includes a latch 233A and a state comparator 233B. The latch 233A is used for latching the state of the previous input data and the previous Clock signal (Pre-Clock) corresponding to the previous input data; the state comparator 233B is connected to the latch 233A, and configured to set the change flag data to low when the state of the current input data and the state of the previous input data are not changed; and setting the change flag data to be high when the state of the current input data and the state of the previous input data are changed.

The input terminal of the data judging unit 231 is connected to the output terminal of the data comparing unit 233 to receive the change mark data; the output terminal of the data judging unit 231 is connected to a Flag signal line. The data judgment unit 231 is configured to set Flag data high if the number of bits of data that is high in the change Flag data is greater than a preset value; and setting Flag data to be low in the case where the number of bits of data that is high in the change Flag data is equal to or less than a preset value.

The input terminal of the data selector 232 receives Flag data through the Flag signal line and receives the current input data. The output of the data selector 232 is connected to the intermediate. The data selector 232 is configured to output the flip data of the currently input data as intermediate data when the Flag data is high; and outputting the original current input data as intermediate data in the case where the Flag data is high.

In one example, the multi-bit change Flag data is not grouped, i.e., the Flag data may be one bit. In one example, the multi-bit change flag data may be grouped. For example: in one embodiment, the change Flag data and the intermediate data are divided into M groups, the Flag data are M bits, the M bit Flag data correspond to the M groups of change Flag data one to one, and the M bit Flag data correspond to the M groups of intermediate data one to one, where M is an integer greater than 1.

Further, each set of change Flag data may be N bits, where N is an integer greater than 1, and the data determining module 23 is configured to, when the bit number of the high data in the input set of change Flag data is greater than N/2, output the inverted data of the input set of change Flag data as a corresponding set of intermediate data, and set the one-bit Flag data corresponding to the input set of change Flag data to be high; and outputting the input set of change Flag data as a corresponding set of intermediate data and setting one bit Flag data corresponding to the input set of change Flag data low when the number of bits of data high in the input set of change Flag data is not more than N/2.

For example: the change Flag data D3' <127:0> is divided into 16 groups, each of which is 8 bits, and each of which corresponds to one bit Flag data. Accordingly, the Flag data is 16 bits, such as Flag <15:0 >. The intermediate data D1' <127:0> would also be divided into 16 groups accordingly. Each bit Flag data corresponds to a set of intermediate data. For a set of change Flag data D3 '< 127:120>, if the number of bits equal to "1" in D3' <127:120> is greater than 4 bits, the corresponding Flag <15> <1, and the output set of intermediate data D1 '< 120:127> is equal to the flipped data of D3' <127:120 >; if the number of bits equal to "1" in the change Flag data is less than or equal to 4 bits, the corresponding Flag <15> is 0, and the output set of intermediate data D1 '< 120:127> is D3' <127:120 >. Similarly, for a set of change Flag data D3 '< 15:8>, if the number of bits equal to "1" in D3' <15:8> is greater than 4 bits, the corresponding Flag <1>, and the output set of intermediate data D1 '< 15:8> is equal to the flipped data of D3' <15:8 >; if the number of bits equal to "1" in the change Flag data is less than or equal to 4 bits, the corresponding Flag <1> is 0, and the output set of intermediate data D1 '< 15:8> is D3' <15:8 >. For a set of change Flag data D3 '< 7:0>, if the number of bits equal to "1" in D3' <7:0> is greater than 4 bits, the corresponding Flag <0> is 1, and the output set of intermediate data D1 '< 7:0> is equal to the flip data of D3' <7:0 >; if the number of bits equal to "1" in the change Flag data is less than or equal to 4 bits, the corresponding Flag <0> is 0, and the output set of intermediate data D1 '< 7:0> is D3' <7:0 >.

Further, as shown in fig. 1 and 2, the write operation circuit further includes a data buffer module 22. The data buffer module 22 receives an Enable (Enable) signal and is connected to the data judgment module 23 to receive the intermediate data. The data buffer module 22 is used for determining the initial state of the global bus according to the Enable signal and the intermediate data. That is, in the present embodiment, the semiconductor memory 20 employs a global bus transfer structure of a TriState type (TriState).

Fig. 5 schematically shows a circuit diagram (corresponding to one memory block 26) of the data buffer module 22 of one embodiment of the present embodiment. As shown in fig. 5, the data buffer module 22 includes a plurality of pmos (positive Channel Metal oxide semiconductor) transistors 221, a plurality of nmos (negative Channel Metal oxide semiconductor) transistors 222, a plurality of logic nand gates 223, a plurality of fifth inverters 225 and a plurality of logic nor gates 224.

Two input ends of the logic nand gate 223 receive an enable signal and intermediate data respectively; an input of the fifth inverter 225 receives the enable signal; two input terminals of the logic nor gate 224 receive the intermediate data and are connected to the fifth inverter 225; the gate of the PMOS transistor 221 is connected to the output of the logic nand gate 223, and the drain is connected to the global bus; the gate of the NMOS transistor 222 is connected to the output of the logic nor gate 224, and the drain is connected to the global bus; the drain of the PMOS transistor 221 and the drain of the NMOS transistor 222 are connected together.

It should be noted that the PMOS transistor 221, the nmos (negative Channel Metal oxide semiconductor) transistor 222, the nand gate 223, the fifth inverter 225, and the nor gate 224 are multiple groups, and each group corresponds to one bit of intermediate data.

In the related art, under the TriState architecture, the global bus is inverted along with the jump of the input data during the write operation. If the input data is "1", the information "1" is transmitted through the internal global bus. If the input data is "0", then "0" is transmitted through the internal global bus. Thus, if the previous input data is all "1" and the intermediate data is all "0", each global bus is toggling. In the semiconductor memory 20 shown in fig. 2, for a global bus of 256-bit width, 256 bits of global are inverted, and the line transfer current is large. Therefore, in the related art, under the TriState architecture, when the amount of data that changes before and after being transmitted in the global bus is too large at the time of the write operation, the number of the global bus that is inverted is too large, so that the current is increased.

In the embodiment of the present application, through the data determining module 23, in the write operation process, if the number of bits of data change between the current input data and the previous input data is too large, a Flag data is generated to invert (flip) all the current input data, so that the number of flip times of the global bus is greatly reduced, even no flip occurs, and thus the current can be saved.

In one embodiment, the data selector 232 includes M data selection units 232 ', each data selection unit 232' for processing one bit of Flag data and a set of current input data. For example: there may be 16 data selection units 232', corresponding to 16 sets of current input data and one bit of Flag data, respectively.

Fig. 6 shows one implementation of the data selection unit 232'. As shown in fig. 6, the data selection unit 232' includes a second inverter 232A, a third inverter 232B, a first transmission gate 232C, and a second transmission gate 232D.

The input end of the second inverter 232A receives Flag data through a Flag signal line; the input terminal of the third inverter 232B receives the current input data; an input end of the first transmission gate 232C is connected to an output end of the third inverter 232B, an output end of the first transmission gate 232C is connected to the data buffering module 22, and is configured to output intermediate data to the data buffering module 22, an inverted control end (an upper control end in fig. 6) of the first transmission gate 232C is connected to an output end of the second inverter 232A, and a positive control end (a lower control end in fig. 6) of the first transmission gate 232C receives Flag data through a Flag signal line; the input end of the second transmission gate 232D receives the current input data, the output end of the second transmission gate 232D is connected to the data buffering module 22 and is configured to output the intermediate data to the data buffering module 22, the inverse control end of the second transmission gate 232D receives the Flag data through the Flag signal line, and the positive control end of the second transmission gate 232D is connected to the output end of the second inverter 232A.

Taking Flag <0> and the current input data D2 ' <7:0> as an example, as shown in fig. 6, when Flag is 1, the intermediate data D1 ' <7:0> is the flip data of the current input data D2 ' <7:0 >; when Flag is 0, the intermediate data D1 '< 7:0> is the current input data D2' <7:0 >.

It should be noted that a set of the third inverter 232B, the first transmission gate 232C and the second transmission gate 232D is used for processing a current input data bit and outputting a corresponding intermediate data bit. That is, corresponding to the 8-bit current input data D2 '< 7:0>, there should also be 8 sets of the third inverter 232B, the first transfer gate 232C and the second transfer gate 232D, thereby outputting 8-bit intermediate data D1' <7:0 >.

As shown in fig. 1, fig. 2, and fig. 7, the write operation circuit in the present embodiment further includes a data receiving block 25. The input end of the data receiving module 25 is connected to the global bus and the flip identification signal line, and the output end of the data receiving module 25 is connected to the storage block 26, and is configured to determine whether to flip the global bus data (decode the global bus data) according to the Flag data, and write the decoded data (write data) into the storage block 26. For example: outputting the turning data of the global bus data as write data under the condition that the Flag data is high; and outputting the original global bus data as write data in the case where the Flag data is low.

Thereby, the write data is restored as the input data of the semiconductor memory. Further, data and functions of external ports of the semiconductor memory 20, such as the DQ port 24 and the DBI port (not shown in the drawings), are not changed.

In one embodiment, the data receiving module 25 may include a plurality of data receiving units 250, each data receiving unit 250 being configured to process one bit of Flag data and one set of global bus data. For example: the number of the data receiving units 250 may be 16, corresponding to 16 sets of global bus data and one bit of Flag data, respectively. Fig. 8 shows one implementation of the data receiving unit 250.

As shown in fig. 8, the data receiving unit 250 includes a fourth inverter 251, a fifth inverter 252, a third transmission gate 253, and a fourth transmission gate 254.

The input end of the fourth inverter 251 receives Flag data through a Flag signal line; the input of the fifth inverter 252 receives global bus data via the global bus; an input end of the third transmission gate 253 is connected to an output end of the fifth inverter 252, an output end of the third transmission gate 253 is connected to the memory block 26 and is used for outputting write data to the memory block 26, an inverted control end (an upper control end in fig. 8) of the third transmission gate 253 is connected to an output end of the third inverting 251 unit, and a positive control end of the third transmission gate 253 receives Flag data through a Flag signal line; an input terminal of the fourth transmission gate 254 receives global bus data through a global bus, an output terminal of the fourth transmission gate 254 is connected to the memory block 26 for outputting write data to the memory block 26, an inverted control terminal (upper control terminal in fig. 8) of the fourth transmission gate 254 receives Flag data through a Flag signal line, and an positive control terminal (lower control terminal in fig. 8) of the fourth transmission gate 254 is connected to an output terminal of the fourth inverter 251.

Taking Flag <0> and global bus data D '< 7:0> as an example, as shown in fig. 8, when Flag is 1, write data D <7:0> is flip data of the global bus data D' <7:0 >; when Flag is equal to 0, the write data D <7:0> is the global bus data D '< 7:0>, i.e. D <7:0> -D' <7:0 >.

It should be noted that a set of the fifth inverter 252, the third transmission gate 253, and the fourth transmission gate 254 is used for processing one bit of global bus data and outputting one bit of corresponding write data. That is, corresponding to the 8 bits of global bus data D' <7:0>, the fifth inverter 252, the third transfer gate 253, and the fourth transfer gate 254 should have 8 sets, and then 8 bits of write data D <7:0> are outputted.

According to the semiconductor memory 20 of the present embodiment, during the process of writing data (for example, all the first input data are 1, all the second input data are 0) into the semiconductor memory 20, the global bus data is 256 bits, if 256 bits of global bus inversion is required, only 32 bits of Flag data are inverted, and the write current is greatly compressed.

In practical applications, the semiconductor memory 20 of the present embodiment further includes other structures such as a sense amplifier, which are all related to the prior art and are not repeated herein.

The write operation circuit provided by the embodiment of the application is applied to a semiconductor memory with a TriState global bus transmission structure, can reduce the turnover frequency of an internal global bus before data is written into a memory block, can greatly compress current, and reduces power consumption.

In the description herein, reference to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the application. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.

Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. One skilled in the relevant art will recognize, however, that the subject matter of the present application can be practiced without one or more of the specific details, or with other methods, components, materials, devices, steps, and so forth. In other instances, well-known structures, methods, devices, implementations, materials, or operations are not shown or described in detail to avoid obscuring aspects of the application.

The terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.

Furthermore, while the spirit and principles of the application have been described with reference to several particular embodiments, it is to be understood that the application is not limited to the disclosed embodiments, nor is the division of aspects, which is merely for convenience of presentation, to imply that features in these aspects cannot be combined to advantage. The application is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive various changes or substitutions within the technical scope of the present application, and these should be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims (10)

1. A write operation circuit applied to a semiconductor memory, comprising:

the data judgment module is used for determining whether the current input data is overturned according to the number of bits of data change in the previous input data and the current input data of the semiconductor memory so as to generate overturning identification data and intermediate data;

the data buffer module is connected with the data judgment module and used for determining the initial state of the global bus according to an enabling signal and the intermediate data;

and the data receiving module is connected with the storage block, receives the global bus data on the global bus, receives the overturning identification data through the overturning identification signal line, and is used for decoding the global bus data according to the overturning identification data and writing the decoded data into the storage block stored in the semiconductor, wherein the decoding comprises determining whether the global bus data is overturned.

2. The write operation circuit according to claim 1, wherein the data determination module is configured to determine change flag data according to a change between the current input data and the previous input data; and the data judgment module is also used for inputting a preset value and outputting the turning identification data and the intermediate data according to the change marking data and the preset value.

3. The write operation circuit according to claim 2, wherein the data judging means includes;

the data comparison unit is used for outputting the change marking data according to the number of bits of data change in the current input data and the previous input data;

the input end of the data judgment unit is connected with the output end of the data comparison unit so as to receive the change marking data, the output end of the data judgment unit is connected with the turnover identification signal line, and the data judgment unit is used for inputting the preset value and outputting the turnover identification data according to the change marking data and the preset value;

and the input end of the data selector receives the overturning identification data through the overturning identification signal line, and the data selector is used for generating the intermediate data according to the overturning identification data and the current input data.

4. The write operation circuit according to claim 3, wherein the data comparison unit includes;

the latch is used for latching the state of the previous input data and a previous clock signal corresponding to the previous input data;

and the state comparator is connected with the latch and used for outputting the change marking data according to whether the state of the current input data and the state of the previous input data are changed.

5. The write operation circuit according to claim 2, wherein the change flag data and the intermediate data are each divided into M groups, the flip flag data are M bits, the M bit flip flag data correspond one-to-one to the M groups of change flag data, and the M bit flip flag data correspond one-to-one to the M groups of intermediate data, where M is an integer greater than 1.

6. The write operation circuit according to claim 3, wherein the data selector includes M data selection units, the data selection unit including:

the input end of the second inverter receives the overturning identification data through the overturning identification signal line;

the input end of the third inverter is connected to the data judging unit and used for receiving the current input data from the data judging unit;

a first transmission gate, an input end of which is connected to an output end of the third inverter, an output end of which is connected to the data buffer module and is configured to output the intermediate data to the data buffer module, an inverse control end of which is connected to an output end of the second inverter, and an positive control end of which receives the flip flag data through the flip flag signal line;

the input end of the second transmission gate is connected with the data judging unit and used for receiving the current input data from the data judging unit, the output end of the second transmission gate is connected with the data buffering module and used for outputting the intermediate data to the data buffering module, the reverse control end of the second transmission gate receives the overturning identification data through the overturning identification signal line, and the positive control end of the second transmission gate is connected with the output end of the second phase inverter.

7. The write operation circuit according to claim 1, wherein the global bus data is M groups, M bit flip flag data corresponds to M groups of global bus data one to one, the data receiving module includes M data receiving units, the data receiving units are connected to the memory block, and the data receiving unit is configured to perform the decoding on the corresponding group of global bus data according to the one bit flip flag data.

8. The write operation circuit according to claim 7, wherein the data receiving unit includes:

the input end of the fourth inverter receives the overturning identification data through the overturning identification signal line;

a fifth inverter, an input of which receives the global bus data through the global bus;

an input end of the third transmission gate is connected to an output end of the fifth inverter, an output end of the third transmission gate is connected to the storage block and used for outputting decoded data to the storage block, an inverted control end of the third transmission gate is connected to an output end of the fourth inverter, and an positive control end of the third transmission gate receives the flip identification data through the flip identification signal line;

and the input end of the fourth transmission gate receives the global bus data through the global bus, the output end of the fourth transmission gate is connected with the storage block and used for outputting the decoded data to the storage block, the reverse control end of the fourth transmission gate receives the overturning identification data through the overturning identification signal line, and the positive control end of the fourth transmission gate is connected with the output end of the fourth phase inverter.

9. The write operation circuit according to any one of claims 1 to 8, wherein the data buffer module includes;

a plurality of logic nand gates, two input ends of the logic nand gates respectively receiving the enable signal and the current input data;

a plurality of fifth inverters, an input of which receives the enable signal;

a plurality of logic NOR gates, two input ends of which respectively receive the current input data and are connected to the fifth inverter;

the grid electrodes of the PMOS transistors are connected to the output end of the logic NAND gate, and the drain electrodes of the PMOS transistors are connected to the global bus;

a plurality of NMOS transistors, wherein the gates of the NMOS transistors are connected to the output end of the logic NOR gate, and the drains of the NMOS transistors are connected to the global bus and the drains of the NMOS transistors.

10. A semiconductor memory characterized by comprising the write operation circuit according to any one of claims 1 to 9.

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