CN210575117U - Write operation circuit and semiconductor memory - Google Patents

Abstract

The embodiment of the application at least provides a write operation circuit and a semiconductor memory. The write operation circuit includes: the serial-parallel conversion circuit is used for performing serial-parallel conversion on first DBI data of the DBI port to generate second DBI data for being transmitted by the DBI signal line and generating input data of the data buffer module according to the second DBI data and input data of the DQ port; the data buffer module is used for determining whether the global bus is overturned according to the input data of the data buffer module; the DBI decoding module is used for decoding the global bus data according to the second DBI data and writing the decoded data into the storage block, and the decoding comprises the step of determining whether the global bus data is turned over or not; and the precharge module is connected to the precharge signal line and used for setting the initial state of the global bus to be high. According to the technical scheme of the embodiment of the application, the turnover times of the global bus can be reduced under the Precharge pull-up structure, so that the current is greatly compressed, and the power consumption is reduced.

Description

Write operation circuit and semiconductor memory

Technical Field

The present application relates to the field of semiconductor memory technologies, and in particular, to a write operation circuit and a semiconductor memory.

Background

This section is intended to provide a background or context to the embodiments of the application that are recited in the claims. The description herein is not admitted to be prior art by inclusion in this section.

The semiconductor Memory includes a Static Random Access Memory (SRAM), a Dynamic Random Access Memory (DRAM), a Synchronous Dynamic Random Access Memory (SDRAM), a Read-Only Memory (ROM), and a flash Memory.

In the DRAM protocol of Joint Electron Device Engineering Council (JEDEC), there are specific requirements for DRAM speed and power saving. How to save more power for the DRAM and ensure the integrity of the signal and the reliability of data transmission and storage is an urgent problem to be solved in the industry.

SUMMERY OF THE UTILITY MODEL

Embodiments of the present application provide a write operation circuit and a semiconductor memory to solve or alleviate one or more technical problems in the prior art.

In a first aspect, an embodiment of the present application provides a write operation circuit, which is applied to a semiconductor memory, where the semiconductor memory includes a DQ port, a DBI port, and a memory block, and the write operation circuit includes:

the serial-parallel conversion circuit is connected to the DBI port and the DQ port and used for performing serial-parallel conversion on first DBI data of the DBI port to generate second DBI data for transmission of a DBI signal line and generating input data of the data buffer module according to the second DBI data and input data of the DQ port;

the data buffer module comprises a plurality of NMOS transistors, the grid electrodes of the NMOS transistors are connected to the serial-parallel conversion circuit so as to receive input data of the data buffer module, the drain electrodes of the NMOS transistors are connected to the global bus, and the data buffer module is used for determining whether the global bus is turned over or not according to the input data of the data buffer module;

the DBI decoding module is connected to the storage block, receives the global bus data on the global bus, receives second DBI data through a DBI signal line, decodes the global bus data according to the second DBI data, writes the decoded data into the storage block, and determines whether to overturn the global bus data;

and the precharge module is connected to the precharge signal line and used for setting the initial state of the global bus to be high.

In one embodiment, in the case that the number of bits of data that is low in the external data is greater than a preset value, the first DBI data is set to be high, and the input data of the DQ port is flip data of the external data; under the condition that the bit number of the data which is low in the external data is less than or equal to a preset value, the first DBI data is set to be low, and the input data of the DQ port is the external data; and the serial-parallel conversion circuit is used for performing serial-parallel conversion on the input data of the DQ port to generate converted data, inverting the converted data to generate the input data of the data buffer module under the condition that the second DBI data is high, and taking the converted data as the input data of the data buffer module under the condition that the second DBI data is low.

In one embodiment, the serial-to-parallel conversion circuit is configured to perform serial-to-parallel conversion on one-bit first DBI data to generate M-bit second DBI data, the global bus data is divided into M groups, and the M-bit second DBI data and the M groups of global bus data are in one-to-one correspondence; the DBI decoding module comprises M DBI decoding sub-modules, the DBI decoding sub-modules are connected to the storage block, and each DBI decoding sub-module is used for decoding the global bus data of the corresponding group according to one bit of second DBI data; wherein M is an integer greater than 1.

In one embodiment, the DBI decoding sub-module includes:

the input end of the first inverter is connected to the DBI signal line;

the input end of the decoding unit is connected to the global bus, and the output end of the decoding unit is connected to the storage block and used for outputting the turnover data of the global bus data under the condition that the second DBI data is high; and outputting the original global bus data if the second DBI data is low.

In one embodiment, a decoding unit includes:

the input end of the second inverter is connected to the global bus;

the two input ends of the first logic AND gate are respectively connected with the output end of the first inverter and the output end of the second inverter;

two input ends of the second logic AND gate are respectively connected with the DBI signal line and the global bus;

and two input ends of the logic NOR gate are respectively connected with the output end of the first logic AND gate and the output end of the second logic AND gate, and the output end of the logic NOR gate is connected with the storage block.

In one embodiment, the precharge module includes a plurality of PMOS transistors whose gates are connected to the precharge signal line, whose drains are connected to the global bus, and a plurality of holding circuits whose input and output terminals are connected to the global bus.

In a second aspect, embodiments of the present application provide a semiconductor memory, which includes a DQ port, a DBI port, a memory block, and a write operation circuit of any one of the above.

By adopting the technical scheme, the embodiment of the application can reduce the turnover frequency of the global bus under the Precharge pull-up structure, thereby greatly compressing the current and reducing the power consumption.

The foregoing summary is provided for the purpose of description only and is not intended to be limiting in any way. In addition to the illustrative aspects, embodiments, and features described above, further aspects, embodiments, and features of the present application will be readily apparent by reference to the drawings and following detailed description.

Drawings

In the drawings, like reference numerals refer to the same or similar parts or elements throughout the several views unless otherwise specified. The figures are not necessarily to scale. It is appreciated that these drawings depict only some embodiments in accordance with the disclosure and are therefore not to be considered limiting of its scope.

Fig. 1 is a block diagram schematically showing the structure of a semiconductor memory portion of one embodiment of the present embodiment;

fig. 2 is a block diagram schematically showing the structure of a semiconductor memory portion of another embodiment of the present embodiment;

FIG. 3 schematically illustrates a schematic diagram of the DBI function;

FIG. 4 schematically shows a circuit diagram (corresponding to one memory block) of a data buffer module and a precharge module according to an embodiment of the present embodiment;

FIG. 5 schematically shows a circuit diagram (corresponding to a plurality of memory blocks) of a data buffer module and a precharge module according to an embodiment of the present embodiment;

fig. 6 schematically shows a block diagram of a DBI decoding module according to an embodiment of the present embodiment;

fig. 7 schematically shows a block diagram of a DBI decoding submodule according to an embodiment of the present embodiment.

Description of reference numerals:

10: a controller;

20: a semiconductor memory;

21: a serial-to-parallel conversion circuit;

22: a data buffer module;

23: a DBI decoding module;

24: a DQ port;

25: a DBI port;

26: a storage block;

27: a pre-charge module;

221: a PMOS tube;

222: an NMOS tube;

223: a holding circuit;

230: a DBI decoding sub-module;

231: a first inverter;

232: a decoding unit;

232A: a second inverter;

232B: a first logical AND gate;

232C: a second logical AND gate;

232D: a logical nor gate.

Detailed Description

Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The same reference numerals denote the same or similar parts in the drawings, and thus, a repetitive description thereof will be omitted.

Fig. 1 schematically shows a block diagram of a structure of a semiconductor memory portion of one embodiment of the present embodiment. As shown in fig. 1, the semiconductor memory 20 includes a DQ port 24, a Data Bus Inversion (DBI) port 25, a memory block (Bank)26, and a write operation circuit including a Global Bus (Global Bus), a DBI signal line, a serial-parallel conversion circuit 21, a Data Buffer block (Data Buffer)22, and a DBI decoding block (Decoder) 23. In one embodiment, the semiconductor memory is a DRAM, such as a fourth generation Double data rate SDRAM 4 (DDR 4).

In one example, as shown in FIG. 1, 8 bits of input data DQ <7:0> input from DQ port 24 are passed through the write operation circuitry to write data D <127:0> to memory block 26. An Active command opens a uniquely specified memory block 26, and a write operation can be performed to only one memory block 26. That is, when one Bank among eight memory blocks 26 (i.e., Bank <7:0>) is active, the other banks are inactive. It should be noted that the number of memory blocks 26, the number of data bits per memory block 26, and the number and number of data bits of the DQ port 24 are not limited in this embodiment. For example: one DQ port 24 may be used as input 16-bit input data; the DQ ports 24 may also be two, i.e., each DQ port 24 serves as input 8-bit input data DQ <7:0> or DQ <15:8 >.

In another example, as shown in fig. 2, of the 16-bit input data DQ <15:0> inputted from the DQ port 24, the input data DQ <7:0> is written to a set of memory blocks Bank <7:0> by one of the write operation circuits described above; the input data DQ <15:8> is written to another set of memory blocks Bank <15:8> by another write operation circuit as described above. Accordingly, of the eight memory blocks 26 corresponding to DQ <15:8> (i.e., Bank <15:8>), when one Bank is active, the other Bank is inactive.

The function of the DBI port 25 is described below in connection with fig. 3. An On-die termination (ODT) of the semiconductor memory 20 may sink current from the DQ port 24 through the ground pin, preventing signals from forming reflections On internal circuitry of the semiconductor memory 20. The ODT is sized to match the controller 10 during operation of the semiconductor memory 20. In one example, the ODT structure is a pull-up structure, and when the data of the DQ port 24 is "0", the leakage current through the ODT is large, which may increase power consumption. Therefore, in the case that the number of bits of the data that is low in the external data is greater than the preset value, the first DBI data of the DBI port 25 is set to be high, and the external data is flipped to obtain the input data of the DQ port; and under the condition that the bit number of the data which is low in the external data is less than or equal to a preset value, the first DBI data is set to be low, and the input data of the DQ port is the external data.

For example: in the external data written to the DQ port 24, if there is more data of "0", each bit of the external data is inverted and input to the semiconductor memory 20, and the first DBI data of the DBI port is set to high to indicate that the input data is inverted external data. For example: if the input data DQ <7:0> is <11111111> and the first DBI data is equal to 0, it means that the input data DQ <7:0> is the original external data, i.e., the external data is also <11111111 >; if the input data DQ <7:0> is <11111111> and the first DBI data is equal to 1, it means that the input data DQ <7:0> is the data after the external data is flipped, i.e., the external data is <00000000 >. The same holds true for the input data DQ <15:8> of the DQ port 24. Accordingly, the data "1" is more of the input data DQ <15:0> of the DQ port 24, and power consumption can be reduced.

Where data high may be data equal to "1" and data low may be data equal to "0". The flipping of data may be understood as a change from "0" to "1", or, from "1" to "0". The inversion of the data line or the signal line may be understood as a high level to a low level, or a low level to a high level.

The semiconductor memory 20 has an array structure, and each unit structure may be the same, but the data output from each unit may be different due to the difference in the input data. The write operation circuit of the present embodiment will be described below by taking one of the memory blocks as an example.

As shown in fig. 1, the serial-to-parallel conversion circuit 21 is connected to the DBI port 25, and is configured to perform serial-to-parallel conversion on the first DBI data of the DBI port 25 to generate second DBI data for transmission on the DBI signal line. The serial-to-parallel conversion circuit 21 is connected to the DQ port 24, and is configured to generate input data of the data buffer module 22 according to the second DBI data and the input data DQ of the DQ port.

In one embodiment, the serial-to-parallel conversion circuit 21 is configured to perform serial-to-parallel conversion on the input data of the DQ port 24 to generate converted data, and determine whether to flip the converted data according to the second DBI data to generate the input data of the data buffer module.

For example: the serial-parallel conversion circuit 21 performs serial-parallel conversion on the input 8-bit input data DQ <7:0> to generate 128-bit converted data, then determines whether to flip the converted data according to the 16-bit second DBI data DBI <0:15>, and further outputs 128-bit input data D2' <127:0> to the data buffer module 22.

In one example, the 128-bit converted data is divided into 16 groups, each group of the converted data is 8 bits, one bit of the second DBI data corresponds to one group of the 8-bit converted data, and a group of 8-bit input data D2' is generated.

It should be noted that the serial-to-parallel conversion circuit 21 may include two serial-to-parallel conversion modules, which are respectively used for performing serial-to-parallel conversion on the input data of the DQ port 24 and the first DBI data, and the embodiment is not limited thereto.

The Precharge module 27 is connected to a Precharge signal line (Precharge) for setting an initial state of the global bus to high. That is, in the present embodiment, the semiconductor memory 20 employs a Precharge pull-up (High) global bus transfer structure.

Fig. 4 schematically shows a circuit diagram (corresponding to one memory block 26) of the data buffer module 22 of one embodiment of the present embodiment. Fig. 5 schematically shows a circuit diagram (corresponding to 8 memory blocks 26) of the data buffer module 22 of one embodiment of the present embodiment.

As shown in fig. 4 and 5, the data buffer module 22 includes a plurality of NMOS (Negative Channel metal oxide Semiconductor) transistors 222, and the precharge module 27 includes a plurality of PMOS (Positive Channel metal oxide Semiconductor) transistors 221 and a plurality of hold (hold) circuits 223. Wherein, the grid of the PMOS transistor 221 is connected to the pre-charge signal line, and the drain of the PMOS transistor 221 is connected to the global bus; the gate of the NMOS transistor 222 is connected to the serial-to-parallel conversion circuit 21 to receive the input data of the data buffer module 22, and the drain of the NMOS transistor 222 is connected to the global bus, so that the data buffer module 22 will determine whether to flip the global bus according to the input data of the data buffer module 22; the input and output terminals of the hold circuit 223 are connected to the global bus, thereby forming a positive feedback circuit.

The Precharge is used for setting the initial state of each global bus to be high, and the specific process is that the Precharge generates a pull-up pulse (pulse, about 2 ns), a certain corresponding global bus is pulled up for a while, the holding circuit 223 forms positive feedback and locks the global bus at a high level, but the pull-up and pull-down current capability of the holding circuit 223 is relatively weak; when a global bus needs to be changed to a low level, a data line corresponding to the global bus (i.e., a data line connected to the gate of the corresponding NMOS transistor 222) is pulled up (also a pulse, about 2 ns), so that the corresponding NMOS transistor 222 pulls down the global bus for a moment (the pull-down capability is greater than the pull-up capability of the holding circuit 223), and then locks the global bus to a low level through positive feedback, thereby completing the flipping operation of the data line.

Since the data of "0" is more in the input data D2 '< 127:0> (i.e., the data on the data line connected to the gate of the NMOS transistor 222) of the data buffer module 22, the number of global buses to be inverted is less, and the data of "1" is more in the global bus data D1' <127:0 >. Therefore, the IDD4W (write current) of the semiconductor memory will be reduced, so that the power consumption of the semiconductor memory can be reduced. That is, if there is more data of "1" in the global bus data, IDD4W can be reduced, thereby reducing power consumption.

Since the input data DQ <7:0> of the DQ port 24 includes more data of "1", and since it is not decoded yet at this time, the 128-bit global bus data D1' <127:0> includes more data of "1". Accordingly, in the semiconductor memory 20 shown in fig. 2, the input data DQ <15:0> includes a large amount of data "1", and since it is not decoded yet at this time, the 256-bit global bus data (including the 128-bit global bus data corresponding to DQ <7:0> and the 128-bit global bus data corresponding to DQ <15:8>) includes a large amount of data "1".

Further, the DBI decoding module 23 receives the second DBI data through the DBI signal line and receives the global bus data through the global bus by being connected to the storage block 26. The DBI decoding module 23 is configured to decode the global bus data according to the second DBI data, and write the decoded data into the storage block 26, where the decoding includes determining whether to flip the global bus data. The decoded data is the write data, such as D <127:0 >. That is, more data is transferred on the global bus as a "1" before the data is written to the memory block 26.

In the related art, when the DBI function is enabled (enable), when the semiconductor memory performs a write operation and input data just enters the semiconductor memory, the semiconductor memory decodes the input data according to the state of the DBI port. If the state of DBI is "1", all input data will be inverted (flipped); if the state of DBI is "0", all the input data is not inverted, i.e., the original value. This decoded block is located at the position where the input data has just entered the semiconductor memory, i.e. before the block for serial-to-parallel conversion. Therefore, in the related art, the number of data "0" transmitted by the internal global bus of the semiconductor memory is large, which results in an excessively large IDD4W and high power consumption.

In one embodiment, the first DBI data has only one bit, and the serial-to-parallel conversion circuit 21 is configured to perform serial-to-parallel conversion on the one-bit first DBI data to generate M-bit second DBI data. For example: the serial-to-parallel conversion circuit 21 may perform serial-to-parallel conversion on the data of the one-bit DBI port 25 to generate 16-bit second DBI data DBI <15:0 >.

The global bus data is divided into M groups, and the M-bit second DBI data corresponds to the M groups of global bus data one to one. As shown in fig. 6, the DBI decoding module 23 includes M DBI decoding sub-modules 230, each DBI decoding sub-module 230 is connected to one storage block 26, and each DBI decoding sub-module 230 is configured to decode a corresponding group of global bus data according to one bit of second DBI data; wherein M is an integer greater than 1.

The DBI decoding module 23 outputs the roll-over data of the global bus data when the second DBI data is high; and outputting the original global bus data if the second DBI data is low.

For example: the global bus data D1' <127:0> is divided into 16 groups, each group of global bus data is 8 bits, and correspondingly, the second DBI data is 16 bits, such as DBI <15:0 >. Each set of global bus data corresponds to one bit of DBI data. Then, when DBI <15> is 1, the decoded data output from the DBI decoding block 23, that is, the write data D <127:120> written to the memory block 26 (e.g., Bank0) is the global bus data D1' <127:120 >; when DBI <15> is 0, the write data D <127:120> is the global bus data D1' <127:120 >. Similarly, when DBI <1> is 1, the write data D <15:8> is the flip data of the global bus data D1' <15:8 >; when DBI <1> is 0, the write data D <15:8> is the global bus data D1' <15:8 >. When DBI <0> is 1, the write data D <7:0> is the flip data of the global bus data D1' <7:0 >; when DBI <0> is 0, the write data D <7:0> is the global bus data D1' <7:0 >.

In one example, the global bus is multi-root and is divided into M groups (M is an integer greater than 1), each global bus transferring one bit of global bus data. For example: the number of the global buses is 128, and the 128 global buses are divided into 16 groups. The global bus <0> transfers global bus data D1' <0 >; the global bus <1> transfers global bus data D1' <1 >; … …, respectively; the global bus <127> transfers global bus data D1' <127 >.

In one example, the number of DBI signal lines is 16, each DBI signal line transmits 1-bit second DBI data, e.g., DBI signal line <0> transmits second DBI data DBI <0> for characterizing whether write data D <7:0> is data after global bus data D1' <7:0> is inverted; the DBI signal line <1> carries second DBI data DBI <1> representing whether the write data D <8:15> are inverted data of the global bus data D1' <8:15 >; … …, respectively; the DBI signal line <15> carries second DBI data DBI <15> that is used to characterize whether the write data D <120:127> is inverted data of the global bus data D1' <120:127 >.

According to the semiconductor memory 20 of the present embodiment, when DQ <7:0> is input <11111111> for the first time and the first DBI data is equal to 0; when <11111111> is input for the second time and the first DBI data is equal to 1, each corresponding set of global bus data (8 bits) will be <11111111> until written into the memory block 26, and only one bit of the second DBI data corresponding thereto is equal to 1. Therefore, in this embodiment, when the global bus data is 256 bits (including 128 bits of global bus data corresponding to DQ <7:0> and 128 bits of global bus data corresponding to DQ <15:8>), if the 256 bits of global bus data are required to be flipped, it will become that only 32 bits of second DBI data are flipped, and the IDD4W current will be greatly compressed.

In one embodiment, as shown in fig. 7, the DBI decoding sub-module 230 may include a first inverter 231 and a decoding unit 232. The input end of the first inverter 231 is connected to the DBI signal line, the input end of the decoding unit 232 is connected to the global bus, and the output end of the decoding unit 232 is connected to the storage block 26, and is configured to output the inverted data of the global bus data when the second DBI data is high; and outputting the original global bus data if the second DBI data is low.

In one embodiment, the decoding unit 232 includes: a second inverter 232A, a first logic and gate 232B, a second logic and gate 232C, and a logic nor gate 232D. Wherein, the input end of the second inverter 232A is connected to the global bus; two input ends of the first logic and gate 232B are respectively connected to the output end of the first inverter 231 and the output end of the second inverter 232A; two input ends of the second logic and gate 232C are connected to the DBI signal line and the global bus, respectively; two input terminals of the logic nor gate 232D are respectively connected to the output terminal of the first logic and gate 232B and the output terminal of the second logic and gate 232C, and an output terminal of the logic nor gate 232D is connected to the memory block 26.

As shown in fig. 7, taking the decoding units 232 corresponding to DBI <0>, the write data D <7:0> and the global bus data D1 '< 7:0> as an example, when DBI <0> is 1, D <7> is equal to the flip data of D1' <7>, … …, D <1> is equal to the flip data of D1 '< 1>, and D <0> is equal to the flip data of D1' <0 >; when DBI <0> is 0, D <7> is equal to D1 ' <7>, … …, D <1> is equal to D1 ' <1>, and D <0> is equal to D1 ' <0 >.

It should be noted that each DBI decoding sub-module 230 is the same, but the input data is different, and the output data is different. Fig. 7 shows the structure of one of the DBI decoding sub-modules 230, where data input to the DBI decoding sub-module are D1' <7:0> and DBI <0>, and data output is D <7:0 >. In addition, the implementation circuit of the DBI decoding sub-module 230 is not limited in this embodiment, as long as the inverted data of the global bus data can be output when the second DBI data is 1, and the global bus data can be output when the second DBI data is 0.

In practical applications, the semiconductor memory 20 of the present embodiment further includes other structures such as a sense amplifier, a precharge circuit, etc., which are all the prior art and are not repeated herein.

The write operation circuit provided by the embodiment of the application is applied to a semiconductor memory with a Precharge pull-up global bus transmission structure, and the DBI decoding module is arranged between the serial-parallel conversion circuit and the storage block, so that more data which are transmitted as '1' on a global bus can be realized before the data are written into the storage block, the turnover frequency of the internal global bus is reduced, the current can be greatly compressed, and the power consumption is reduced.

In the description herein, reference to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the application. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.

Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. One skilled in the relevant art will recognize, however, that the subject matter of the present application can be practiced without one or more of the specific details, or with other methods, components, materials, devices, steps, and so forth. In other instances, well-known structures, methods, devices, implementations, materials, or operations are not shown or described in detail to avoid obscuring aspects of the application.

The terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.

Furthermore, while the spirit and principles of the application have been described with reference to several particular embodiments, it is to be understood that the application is not limited to the disclosed embodiments, nor is the division of aspects, which is merely for convenience of presentation, to imply that features in these aspects cannot be combined to advantage. The application is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive various changes or substitutions within the technical scope of the present application, and these should be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims (7)

1. A write operation circuit applied to a semiconductor memory, wherein the semiconductor memory comprises a DQ port, a DBI port and a memory block, the write operation circuit comprising:

the serial-parallel conversion circuit is connected to the DBI port and the DQ port and is used for performing serial-parallel conversion on first DBI data of the DBI port to generate second DBI data for transmission of a DBI signal line and generating input data of a data buffer module according to the second DBI data and the input data of the DQ port;

the data buffer module comprises a plurality of NMOS transistors, the grid electrodes of the NMOS transistors are connected to the serial-parallel conversion circuit so as to receive input data of the data buffer module, the drain electrodes of the NMOS transistors are connected to a global bus, and the data buffer module is used for determining whether to overturn the global bus according to the input data of the data buffer module;

the DBI decoding module is connected to the storage block, receives the global bus data on the global bus, receives the second DBI data through the DBI signal line, decodes the global bus data according to the second DBI data, and writes the decoded data into the storage block, wherein the decoding comprises determining whether to turn over the global bus data;

and the precharge module is connected to a precharge signal line and used for setting the initial state of the global bus to be high.

2. The write operation circuit according to claim 1, wherein in a case where a bit number of data that is low in external data is greater than a preset value, the first DBI data is set high, and input data of the DQ port is flip data of the external data; when the number of bits of data which is low in the external data is less than or equal to the preset value, the first DBI data is set to be low, and the input data of the DQ port is the external data; and the serial-to-parallel conversion circuit is used for performing serial-to-parallel conversion on the input data of the DQ port to generate converted data, inverting the converted data to generate the input data of the data buffer module when the second DBI data is high, and taking the converted data as the input data of the data buffer module when the second DBI data is low.

3. The write operation circuit according to claim 1, wherein the serial-to-parallel conversion circuit is configured to perform serial-to-parallel conversion on one-bit first DBI data to generate M-bit second DBI data, the global bus data is divided into M groups, and the M-bit second DBI data corresponds to the M groups of global bus data one to one; the DBI decoding module comprises M DBI decoding sub-modules, the DBI decoding sub-modules are connected to the storage block, and each DBI decoding sub-module is used for decoding the global bus data of the corresponding group according to one bit of second DBI data; wherein M is an integer greater than 1.

4. The write operation circuit of claim 3, wherein the DBI decoding submodule comprises:

a first inverter, an input end of which is connected to the DBI signal line;

the input end of the decoding unit is connected to the global bus, and the output end of the decoding unit is connected to the storage block and used for outputting the turnover data of the global bus data under the condition that the second DBI data is high; and outputting the original global bus data if the second DBI data is low.

5. The write operation circuit according to claim 4, wherein the decoding unit includes:

the input end of the second inverter is connected to the global bus;

the two input ends of the first logic AND gate are respectively connected with the output end of the first inverter and the output end of the second inverter;

two input ends of the second logic AND gate are respectively connected to the DBI signal line and the global bus;

and two input ends of the logic NOR gate are respectively connected to the output end of the first logic AND gate and the output end of the second logic AND gate, and the output end of the logic NOR gate is connected to the storage block.

6. The write operation circuit according to any one of claims 1 to 5, wherein the precharge module includes a plurality of PMOS transistors and a plurality of hold circuits, gates of the PMOS transistors are connected to the precharge signal line, drains of the PMOS transistors are connected to the global bus, and input and output terminals of the hold circuits are connected to the global bus.

7. A semiconductor memory characterized by comprising a DQ port, a DBI port, a memory block, and the write operation circuit of any one of claims 1 to 6.

Images