CN210667806U - Read operation circuit and semiconductor memory - Google Patents
Read operation circuit and semiconductor memory Download PDFInfo
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- CN210667806U CN210667806U CN201921804727.XU CN201921804727U CN210667806U CN 210667806 U CN210667806 U CN 210667806U CN 201921804727 U CN201921804727 U CN 201921804727U CN 210667806 U CN210667806 U CN 210667806U
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Abstract
The embodiment of the application at least provides a read operation circuit and a semiconductor memory. The read operation circuit includes: the data judgment module is used for reading out the read data from the storage block and determining whether to turn over the current read data according to the number of bits of data change in the previous read data and the current read data so as to output global bus data for global bus transmission and turn over identification data for turn over identification signal line transmission; the data receiving module is used for determining whether global bus data are overturned or not according to the overturning identification data so as to output cache data; the parallel-serial conversion circuit is used for performing parallel-serial conversion on the cache data to generate output data of a DQ port; and the data buffer module is used for determining the initial state of the global bus according to the enable signal and the current read data. The technical scheme of the embodiment of the application can reduce the turnover frequency of the internal global bus, greatly compress the current and reduce the power consumption under the TriState architecture.
Description
Technical Field
The present disclosure relates to the field of semiconductor memory technologies, and in particular, to a read operation circuit and a semiconductor memory.
Background
This section is intended to provide a background or context to the embodiments of the application that are recited in the claims. The description herein is not admitted to be prior art by inclusion in this section.
The semiconductor Memory includes a Static Random Access Memory (SRAM), a Dynamic Random Access Memory (DRAM), a Synchronous Dynamic Random Access Memory (SDRAM), a Read-Only Memory (ROM), and a flash Memory.
In the DRAM protocol of Joint Electron Device Engineering Council (JEDEC), there are specific requirements for DRAM speed and power saving. How to save more power for the DRAM and ensure the integrity of the signal and the reliability of data transmission and storage is an urgent problem to be solved in the industry.
SUMMERY OF THE UTILITY MODEL
Embodiments of the present application provide a read operation circuit and a semiconductor memory to solve or alleviate one or more technical problems in the prior art.
In a first aspect, an embodiment of the present application provides a read operation circuit, which is applied to a semiconductor memory, where the semiconductor memory includes a DQ port and a memory block, and the read operation circuit includes:
the data judgment module is connected with the storage block and used for reading out the read data from the storage block and determining whether to turn over the current read data according to the number of bits of data change in the previous read data and the current read data so as to output global bus data for global bus transmission and turn over identification data for turn over identification signal line transmission;
the data receiving module is connected with the global bus and the turnover identification signal line and used for determining whether the global bus data is turned over or not according to the turnover identification data so as to output cache data;
the parallel-serial conversion circuit is connected between the data receiving module and the DQ port and used for performing parallel-serial conversion on the cache data to generate output data of the DQ port;
and the data buffer module is connected to the storage block through the global bus, and also receives an enabling signal and is used for determining the initial state of the global bus according to the enabling signal and the current read data.
In one embodiment, the data judgment module is used for determining change marking data according to the change between the current read data and the previous read data; and under the condition that the high digit in the change marking data is larger than a preset value, outputting the turning data of the currently read data as global bus data, and setting the turning identification data to be high; and under the condition that the high bit number in the change marking data is less than or equal to the preset value, outputting the original current read data as global bus data, and setting the overturn identification data to be low.
In one embodiment, the data determination module comprises:
the input end of the data comparison unit is connected with the storage block and is used for setting the change mark data to be low under the condition that the current read data and the previous read data are not changed; setting the change mark data to be high under the condition that the current read data and the previous read data are changed;
the data judgment unit is used for setting the turning identification data to be high under the condition that the digit of the data with high level in the changing identification data is greater than a preset value; and setting the turnover identification data to be low under the condition that the digit of the data which is high in the change marking data is less than or equal to a preset value;
the data selector is used for outputting the turnover data of the currently read data as global bus data under the condition that the turnover identification data is high; and outputting the original current read data as global bus data in the case that the flip flag data is low.
In one embodiment, the data comparison unit includes;
the latch is connected with the storage block and used for latching the state of the previous read data and a previous clock signal corresponding to the previous read data;
the state comparator is connected with the storage block and the latch and is used for setting the change mark data to be low under the condition that the state of the current read data and the state of the previous read data are not changed; and setting the change flag data to high when the state of the current read data and the state of the previous read data are changed.
In one embodiment, the change flag data and the global bus data are divided into M groups, the flip flag data are M bits, the M bit flip flag data correspond to the M groups of change flag data one to one, and the M bit flip flag data correspond to the M groups of global bus data one to one, where M is an integer greater than 1.
In one embodiment, each set of change mark data is N bits, where N is an integer greater than 1, and the data determination module is configured to output, as a set of corresponding global bus data, the inverted data of the input set of change mark data when the number of bits of data that is high in the input set of change mark data is greater than N/2, and set a bit inverted flag data corresponding to the input set of change mark data to high; and under the condition that the bit number of high data in the input group of change mark data is less than or equal to N/2, outputting the input group of change mark data as a corresponding group of global bus data, and setting one bit of flip identification data corresponding to the input group of change mark data to be low.
In one embodiment, the data selector includes M data selection units, the data selection unit including:
the input end of the first inverter receives the overturning mark data through the overturning mark signal line;
the input end of the second inverter receives the current read data;
the input end of the first transmission gate is connected to the output end of the second phase inverter, the output end of the first transmission gate is connected with the global bus and used for outputting global bus data, the inverse control end of the first transmission gate is connected to the output end of the first phase inverter, and the positive control end of the first transmission gate receives the overturning identification data through the overturning identification signal line;
and the input end of the second transmission gate receives the current read data, the output end of the second transmission gate is connected with the global bus and used for outputting the global bus data, the inverse control end of the second transmission gate receives the overturning identification data through the overturning identification signal line, and the positive control end of the second transmission gate is connected with the output end of the first phase inverter.
In one embodiment, the data receiving module is configured to output the roll-over data of the global bus data as cache data when the roll-over identification data is high; and outputting the original global bus data as cache data under the condition that the turnover identification data is low.
In one embodiment, the data receiving module includes a plurality of data receiving units, the data receiving units including:
the input end of the third inverter receives the overturning identification data through the overturning identification signal line;
the input end of the fourth inverter receives global bus data through a global bus;
the input end of the third transmission gate is connected to the output end of the fourth phase inverter, the output end of the third transmission gate is connected with the parallel-serial conversion circuit and used for outputting cache data to the parallel-serial conversion circuit, the inverse control end of the third transmission gate is connected to the output end of the third phase inverter, and the positive control end of the third transmission gate receives the overturning identification data through the overturning identification signal line;
and the input end of the fourth transmission gate receives global bus data through a global bus, the output end of the fourth transmission gate is connected with the parallel-serial conversion circuit and used for outputting cache data to the parallel-serial conversion circuit, the inverse control end of the fourth transmission gate receives the overturning identification data through an overturning identification signal line, and the positive control end of the fourth transmission gate is connected to the output end of the third phase inverter.
In one embodiment, a data buffering module includes;
the two input ends of the logic NAND gates respectively receive the enable signal and the current read data;
a plurality of fifth inverters, an input terminal of which receives the enable signal;
the two input ends of the logic NOR gates respectively receive the current read data and are connected to the fifth inverter;
the grid electrode of the PMOS transistor is connected with the output end of the logic NAND gate, and the drain electrode of the PMOS transistor is connected with the global bus;
and the grid electrode of the NMOS transistor is connected with the output end of the logic NOR gate, and the drain electrode of the NMOS transistor is connected with the global bus and the drain electrode of the NMOS transistor.
In a second aspect, an embodiment of the present application provides a semiconductor memory, which includes a DQ port, a memory block, and a read operation circuit of any one of the above.
By adopting the technical scheme, the embodiment of the application can reduce the turnover frequency of the internal global bus, greatly compress the current and reduce the power consumption under a TriState (TriState) architecture.
The foregoing summary is provided for the purpose of description only and is not intended to be limiting in any way. In addition to the illustrative aspects, embodiments, and features described above, further aspects, embodiments, and features of the present application will be readily apparent by reference to the drawings and following detailed description.
Drawings
In the drawings, like reference numerals refer to the same or similar parts or elements throughout the several views unless otherwise specified. The figures are not necessarily to scale. It is appreciated that these drawings depict only some embodiments in accordance with the disclosure and are therefore not to be considered limiting of its scope.
Fig. 1 is a block diagram schematically showing the structure of a semiconductor memory portion of one embodiment of the present embodiment;
fig. 2 is a block diagram schematically showing the structure of a semiconductor memory portion of another embodiment of the present embodiment;
FIG. 3 is a block diagram schematically illustrating a data determination module according to an embodiment of the present invention;
FIG. 4 schematically shows a block diagram of a data comparison unit of an embodiment of the present embodiment;
FIG. 5 schematically shows a circuit diagram of a data buffering module according to an embodiment of the present embodiment;
FIG. 6 schematically shows a block diagram of a data selection unit of an embodiment of the present embodiment;
FIG. 7 is a block diagram schematically illustrating a data receiving module according to an embodiment of the present invention
Fig. 8 schematically shows a block diagram of a data receiving unit according to an embodiment of the present invention.
Description of reference numerals:
20: a semiconductor memory;
21: a parallel-to-serial conversion circuit;
22: a data buffer module;
23: a data judgment module;
24: a DQ port;
25: a data receiving module;
26: a storage block;
221: a PMOS tube;
222: an NMOS tube;
223; a logic NAND gate;
224; a logical NOR gate;
225, a step of mixing; a fifth inverter;
231: a data judgment unit;
232: a data selector;
233: a data comparison unit;
233A: a latch;
233B; a state comparator;
232': a data selection unit;
232A: a first inverter;
232B: a second inverter;
232C: a first transmission gate;
232D: a second transmission gate;
233A; a latch;
233B; a state comparator;
250: a data receiving unit;
251: a third inverter;
252: a fourth inverter;
253: a third transmission gate;
254: and a fourth transmission gate.
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The same reference numerals denote the same or similar parts in the drawings, and thus, a repetitive description thereof will be omitted.
Fig. 1 schematically shows a block diagram of a structure of a semiconductor memory portion of one embodiment of the present embodiment. As shown in fig. 1, the semiconductor memory 20 includes a DQ port 24, a memory block (Bank)26, and a read operation circuit. The read operation circuit includes a Global Bus (Global Bus), a flip Flag (Flag) signal line, a Data determination module 23, a Data Buffer module (Data Buffer)22, a Data receiving module 25, and a parallel-serial conversion circuit 21. In one embodiment, the semiconductor memory 20 is a DRAM, such as a fourth generation Double Data Rate SDRAM (DDR 4).
In one example, as shown in FIG. 1, a one-time Active command opens a uniquely specified memory block 26, and a read operation can only be performed for one memory block 26. That is, when one Bank among the eight memory blocks 26 (i.e., Bank <7:0>) is active, the other banks are inactive. Through the read operation circuit, the read data D <127:0> in the memory block 26 outputs 8-bit output data DQ <7:0> through the DQ port 24. It should be noted that the number of memory blocks 26, the number of data bits per memory block 26, and the number and number of data bits of the DQ port 24 are not limited in this embodiment. For example: one DQ port 24 may be used to output 16-bit output data; the DQ ports 24 may also be two, i.e. each DQ port 24 is used to output 8 bits of output data.
For example, as shown in FIG. 2, the output data DQ <7:0> is obtained by performing a read operation on a set of memory blocks Bank <7:0> by one of the read operation circuits described above; the output data DQ <15:8> is obtained by performing a read operation on another set of memory blocks Bank <15:8> by another read operation circuit as described above. Accordingly, of the eight memory blocks 26 corresponding to DQ <15:8> (i.e., Bank <15:8>), when one Bank is active, the other Bank is inactive.
The semiconductor memory 20 has an array structure, and each unit structure may be the same, but the data output from each unit may be different due to the difference in the input data. The following describes the read operation circuit of this embodiment by taking one of the memory blocks as an example.
The data judgment module 23 is connected to the memory block 26 and is used for reading out the read data, such as D <127:0>, from the memory block 26. The reading operation is carried out along with the clock signal, the previous reading operation corresponds to the previous clock signal, the previous reading data is read, and the current reading operation corresponds to the current clock signal, and the current reading data is read. Therefore, the data determining module 23 is further configured to determine whether to flip the current read data according to the previous read data and the number of bits of data change in the current read data, so as to output global bus data for global bus transmission and Flag data for Flag signal line transmission.
In one embodiment, the data determining module 23 is configured to determine change marking data according to a change between current read data and previous read data; and under the condition that the high digit in the change marking data is larger than a preset value, outputting the turning data of the currently read data as global bus data, and setting Flag data to be high; and under the condition that the high bit number in the change marking data is less than or equal to the preset value, outputting the original current read data as global bus data, and setting Flag data to be low.
Where data high may be data equal to "1" and data low may be data equal to "0". The flipping of data may be understood as a change from "0" to "1", or, from "1" to "0". The inversion of the data line or the signal line may be understood as a high level to a low level, or a low level to a high level.
In one embodiment, as shown in fig. 3, the data judging module 23 may include a data comparing unit 233, a data judging unit 231, and a data selector 232.
An input of the data comparison unit 233 is connected to the memory block 26 to receive the read data. For example, the input terminal of the data comparing unit 233 may receive the current read data through a Local Bus (Local Bus). The data comparing unit 23 is used for setting the change flag data (such as D3' <127:0>) to be low when the current read data and the previous read data are not changed; and setting the change flag data to high in the case where the current read data and the previous read data are changed.
In one embodiment, as shown in fig. 4, the data comparing unit 233 includes a latch 233A and a state comparator 233B. Latch 233A is connected to memory block 26, such as may be connected to Local Bus, for latching the state of the previous read data, and the previous Clock signal (Pre-Clock) corresponding to the previous read data; the state comparator 233B is connected to the memory block 26, as may be connected to Local Bus; the state comparator 233B is further connected to the latch 233A, and is configured to set the change flag data to low when the state of the current read data and the state of the previous read data do not change; and setting the change flag data to high when the state of the current read data and the state of the previous read data are changed.
The input terminal of the data judging unit 231 is connected to the output terminal of the data comparing unit 233 to receive the change mark data; the output terminal of the data judging unit 231 is connected to a Flag signal line. The data judgment unit 231 is configured to set Flag data high if the number of bits of data that is high in the change Flag data is greater than a preset value; and setting Flag data to be low in the case where the number of bits of data that is high in the change Flag data is equal to or less than a preset value.
The input terminal of the data selector 232 receives Flag data through the Flag signal line, and can receive the current read data through Local Bus. The output of the data selector 232 is connected to the global bus. The data selector 232 is configured to output the flip data of the current read data as global bus data when the Flag data is high; and outputting the original current read data as global bus data in the case that the Flag data is high.
In one example, the multi-bit change Flag data is not grouped, i.e., the Flag data may be one bit. In one example, the multi-bit change flag data may be grouped. For example: in one embodiment, the change Flag data and the global bus data are divided into M groups, the Flag data are M bits, the M bit Flag data correspond to the M groups of change Flag data one to one, and the M bit Flag data correspond to the M groups of global bus data one to one, where M is an integer greater than 1.
Further, each group of change Flag data may be N bits, where N is an integer greater than 1, and the data determining module 23 is configured to, when the bit number of the high data in the input group of change Flag data is greater than N/2, output the inverted data of the input group of change Flag data as a corresponding group of global bus data, and set the one-bit Flag data corresponding to the input group of change Flag data to be high; and under the condition that the bit number of the data which is high in the input group of change mark data is less than or equal to N/2, outputting the input group of change mark data as a corresponding group of global bus data, and setting one bit Flag data corresponding to the input group of change mark data to be low.
For example: the change Flag data D3' <127:0> is divided into 16 groups, each of which is 8 bits, and each of which corresponds to one bit Flag data. Accordingly, the Flag data is 16 bits, such as Flag <15:0 >. The global bus data D1' <127:0> would also be divided into 16 sets accordingly. Each bit Flag data corresponds to a set of global bus data. For a set of change Flag data D3 ' <127:120>, if the number of bits equal to "1" in D3 ' <127:120> is greater than 4 bits, the corresponding Flag <15> <1, and the output set of global bus data D1 ' <120:127> is equal to the flip data of the current read data D <127:120 >; if the number of bits equal to "1" in D3 '< 127:120> is less than or equal to 4 bits, the corresponding Flag <15> is 0, and the output set of global bus data D1' <120:127> is D <127:120 >.
Then, when Flag <15> is 1, the global bus data D1' <127 output from the data judging module 23: 120> is the flip data of the current read data D <127:120> of memory block 26 (e.g., Bank 0); when Flag <15> is 0, the global bus data D1' <127 output from the data judging module 23: 120> is the current data D <127:120> of the memory block 26 (e.g., Bank0), i.e., the global bus data D1' <127:120> -D <127:120 >. Similarly, when Flag <1>, the global bus data D1' <15:8> output from the data judging module 23 is the inverted data of the current read data D <15:8> of the memory block 26 (e.g., Bank 0); when Flag <1> is 0, the global bus data D1 '< 15:8> output from the data determining module 23 is the current read data D <15:8>, i.e. the global bus data D1' <15:8> -D <15:8 >. When Flag <0> <1, the global bus data D1' <7:0> output from the data judgment module 23 is the flip data of the current read data D <7:0> of the memory block 26 (e.g., Bank 0); when Flag <0> is 0, the global bus data D1' <7 output from the data judging module 23: 0> is the current read data D <7:0> of the memory block 26 (e.g., Bank0), i.e., the global bus data D1' <7:0> -D <7:0 >.
In one example, the global bus is multi-root and is divided into M groups (M is an integer greater than 1), each global bus transferring one bit of global bus data. For example: the number of the global buses is 128, and the 128 global buses are divided into 16 groups. The global bus <0> transfers global bus data D1' <0 >; the global bus <1> transfers global bus data D1' <1 >; … …, respectively; the global bus <127> transfers global bus data D1' <127 >.
In one example, the Flag signal lines are 16, each of which transmits 1-bit Flag data, such as Flag signal line <0> transmits Flag data Flag <0>, and corresponds to global bus data D1 '< 7:0> to characterize whether D1' <7:0> is the data after flipping; the Flag signal line <1> transmits Flag data Flag <1> and corresponds to global bus data D1 '< 15:8> to represent whether D1' <15:8> is data after being flipped; … …, respectively; the Flag signal line <15> transfers Flag data Flag <15> and, corresponding to the global bus data D1 '< 127:120>, characterizes whether D1' <127:120> is data after flip.
The data buffer module 22 is connected to the memory block 26 through the global bus and receives an Enable (Enable) signal for determining an initial state of the global bus according to the Enable signal and current read data. That is, in the present embodiment, the semiconductor memory 20 employs a global bus transfer structure of a TriState type (TriState).
Fig. 5 schematically shows a circuit diagram (corresponding to one memory block 26) of the data buffer module 22 of one embodiment of the present embodiment. As shown in fig. 5, the data buffer module 22 includes a plurality of PMOS (Positive Channel Metal oxide Semiconductor) transistors 221, a plurality of NMOS (Negative Channel Metal oxide Semiconductor) transistors 222, a plurality of logic nand gates 223, a plurality of fifth inverters 225, and a plurality of logic nor gates 224.
Two input ends of the logic nand gate 223 receive an enable signal and current read data respectively; an input of the fifth inverter 225 receives the enable signal; two input terminals of the logic nor gate 224 respectively receive the current read data and are connected to the fifth inverter 225; the gate of the PMOS transistor 221 is connected to the output of the logic nand gate 223, and the drain is connected to the global bus; the gate of the NMOS transistor 222 is connected to the output of the logic nor gate 224, and the drain is connected to the global bus; the drain of the PMOS transistor 221 and the drain of the NMOS transistor 222 are connected together.
It should be noted that the PMOS transistor 221, the NMOS (Negative Channel Metal oxide semiconductor) transistor 222, the nand gate 223, the fifth inverter 225, and the nor gate 224 are multiple groups, and each group corresponds to one bit of read data.
In the related art, under the TriState architecture, the global bus is inverted along with the jump of the read data during the read operation. If the read data is "1", information "1" is transmitted through the internal global bus. If the read data is "0", then "0" is transferred over the internal global bus. Thus, if the previous read data are all "1" and the current read data are all "0", each global bus is toggling. In the semiconductor memory 20 shown in fig. 2, for a global bus of 256-bit width, 256 bits of global are inverted, and the line transfer current is large. Therefore, in the related art, under the TriState architecture, when the amount of data that changes before and after being transmitted in the global bus is too large at the time of reading, the number of the global bus that is inverted is too large, so that the current is increased.
In the embodiment of the present application, through the data determining module 23, when the global bus is in the reading process, if the number of bits of data changes between the current read data and the previous read data is too large, a Flag data is generated to invert (flip) all the current read data, so that the number of flip times of the global bus is greatly reduced, even no flip occurs, and thus the current can be saved.
In one example, the data judging unit 231 may include a plurality of data judging subunits, each for processing a set of change Flag data and further outputting one-bit Flag data. For example: the number of the data selection unit subunits can be 16, which respectively correspond to 16 groups of change Flag data, and then 16-bit Flag data is output, wherein each group of change Flag data can have 8 bits.
In one embodiment, the data selector 232 includes M data selection units 232 ', each data selection unit 232' for processing one bit of Flag data and a set of currently read data. For example: there may be 16 data selection units 232', corresponding to 16 sets of current read data and one bit of Flag data, respectively, and each set of current read data may have 8 bits.
Fig. 6 shows one implementation of the data selection unit 232'. As shown in fig. 6, the data selection unit 232' includes a first inverter 232A, a second inverter 232B, a first transmission gate 232C, and a second transmission gate 232D.
The input end of the first inverter 232A receives Flag data through a Flag signal line; the input terminal of the second inverter 232B receives the current read data; an input end of the first transmission gate 232C is connected to an output end of the second inverter 232B, an output end of the first transmission gate 232C is connected to the global bus for outputting global bus data, an inverted control end (an upper control end in fig. 6) of the first transmission gate 232C is connected to an output end of the first inverter 232A, and a positive control end (a lower control end in fig. 6) of the first transmission gate 232C receives Flag data through a Flag signal line; the input end of the second transmission gate 232D receives the current read data, the output end of the second transmission gate 232D is connected to the global bus for outputting the global bus data, the inverse control end of the second transmission gate 232D receives the Flag data through the Flag signal line, and the positive control end of the second transmission gate 232D is connected to the output end of the first inverter 232A.
Taking Flag <0> and current read data D <7:0> as an example, as shown in fig. 6, when Flag is 1, the global bus data D1' <7:0> is the flip data of the current read data D <7:0 >; when Flag is equal to 0, the global bus data D1' <7:0> is the current read data D <7:0 >.
It should be noted that a set of the second inverter 232B, the first transmission gate 232C and the second transmission gate 232D is used for processing a bit of currently read data and outputting a bit of corresponding global bus data. That is, corresponding to the 8 bits of the current read data D <7:0>, there should be 8 sets of the second inverter 232A, the first transfer gate 232C and the second transfer gate 232D, and 8 bits of the global bus data D1' <7:0> are outputted.
As shown in fig. 1, fig. 2 and fig. 7, the read operation circuit in this embodiment further includes a data receiving module 25, which is respectively connected to the global bus and the Flag signal, and is configured to determine whether to flip the global bus data according to the Flag data to output the buffered data, such as D2' <127:0 >. For example: outputting the turnover data of the global bus data as cache data under the condition that the Flag data is high; and outputting the original global bus data as the cache data in the case where the Flag data is low.
Thus, the buffered data is restored to the current read data in memory block 26. Further, data and functions of external ports of the semiconductor memory 20, such as the DQ port 24 and the DBI port (not shown in the drawings), are not changed.
In one embodiment, the data receiving module 25 may include a plurality of data receiving units 250, each data receiving unit 250 being configured to process one bit of Flag data and one set of global bus data. For example: the number of the data receiving units 250 may be 16, corresponding to 16 sets of global bus data and one bit of Flag data, respectively. Fig. 8 shows one implementation of the data receiving unit 250.
As shown in fig. 8, the data receiving unit 250 includes a third inverter 251, a fourth inverter 252, a third transmission gate 253, and a fourth transmission gate 254.
The input end of the third inverter 251 receives Flag data through a Flag signal line; the input of the fourth inverter 252 receives global bus data via the global bus; an input end of the third transmission gate 253 is connected to an output end of the fourth inverter 252, an output end of the third transmission gate 253 is connected to the parallel-serial conversion circuit 21 and is used for outputting buffer data to the parallel-serial conversion circuit 21, an inverted control end (an upper control end in fig. 8) of the third transmission gate 253 is connected to an output end of the third inverting 251 device, and a positive control end of the third transmission gate 253 receives Flag data through a Flag signal line; an input terminal of the fourth transmission gate 254 receives global bus data through a global bus, an output terminal of the fourth transmission gate 254 is connected to the parallel-to-serial conversion circuit 21 for outputting buffer data to the parallel-to-serial conversion circuit 21, an inverted control terminal (upper control terminal in fig. 8) of the fourth transmission gate 254 receives Flag data through a Flag signal line, and a positive control terminal (lower control terminal in fig. 8) of the fourth transmission gate 254 is connected to an output terminal of the third inverter 251.
Taking Flag <0> and global bus data D1 ' <7:0> as an example, as shown in fig. 8, when Flag is 1, the cache data D2 ' <7:0> is the flip data of the global bus data D1 ' <7:0 >; when Flag is equal to 0, the cache data D2 '< 7:0> is the global bus data D1' <7:0>, i.e., D2 '< 7:0> -D1' <7:0 >.
It should be noted that a set of the fourth inverter 252, the third transmission gate 253, and the fourth transmission gate 254 is used for processing one bit of global bus data and outputting one bit of corresponding buffered data. That is, corresponding to the 8-bit global bus data D1 '< 7:0>, there should be 8 sets of the fourth inverter 252, the third transfer gate 253 and the fourth transfer gate 254, and then 8-bit buffer data D2' <7:0> is outputted.
As shown in fig. 1 and 2, the read operation circuit of the present embodiment further includes a parallel-to-serial conversion circuit 21. The parallel-serial conversion circuit 21 is connected to the data receiving module 25, and is configured to perform parallel-serial conversion on the buffered data to generate output data of the DQ port 24. For example: the parallel-serial conversion circuit 21 performs parallel-serial conversion on the 128-bit buffer data D2' <127:0> corresponding to Bank0, and generates 8-bit output data DQ <7:0 >.
According to the semiconductor memory 20 of the present embodiment, during the process of reading data from the semiconductor memory 20 (for example, all the first input data are 1; all the second input data are 0), the global bus data is 256 bits, if 256 bits of global bus inversion is required, only 32 bits of Flag data are inverted, and the write current is greatly compressed.
In practical applications, the semiconductor memory 20 of the present embodiment further includes other structures such as a sense amplifier, which are all related to the prior art and are not repeated herein.
The read operation circuit provided by the embodiment of the application is applied to a semiconductor memory with a TriState global bus transmission structure, can reduce the turnover frequency of an internal global bus, can greatly compress current and reduce power consumption.
In the description herein, reference to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the application. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.
Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. One skilled in the relevant art will recognize, however, that the subject matter of the present application can be practiced without one or more of the specific details, or with other methods, components, materials, devices, steps, and so forth. In other instances, well-known structures, methods, devices, implementations, materials, or operations are not shown or described in detail to avoid obscuring aspects of the application.
The terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.
Furthermore, while the spirit and principles of the application have been described with reference to several particular embodiments, it is to be understood that the application is not limited to the disclosed embodiments, nor is the division of aspects, which is merely for convenience of presentation, to imply that features in these aspects cannot be combined to advantage. The application is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.
The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive various changes or substitutions within the technical scope of the present application, and these should be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (11)
1. A read operation circuit applied to a semiconductor memory, wherein the semiconductor memory comprises a DQ port and a memory block, the read operation circuit comprising:
the data judgment module is connected with the storage block and used for reading out read data from the storage block and determining whether to turn over the current read data according to the number of bits of data change in the previous read data and the current read data so as to output global bus data for global bus transmission and turn over identification data for turn over identification signal line transmission;
the data receiving module is connected with the global bus and the turnover identification signal line and used for determining whether the global bus data is turned over or not according to the turnover identification data so as to output cache data;
the parallel-serial conversion circuit is connected between the data receiving module and the DQ port and used for performing parallel-serial conversion on the cache data to generate output data of the DQ port;
and the data buffer module is connected to the storage block through the global bus, and also receives an enable signal and is used for determining the initial state of the global bus according to the enable signal and the current read data.
2. The read operation circuit of claim 1, wherein the data determining module is configured to determine change flag data according to a change between the current read data and the previous read data; and when the high bit number in the change mark data is larger than a preset value, outputting the turnover data of the current read data as the global bus data, and setting the turnover identification data to be high; and under the condition that the number of high bits in the change marking data is less than or equal to the preset value, outputting the original current read data as the global bus data, and setting the overturn identification data to be low.
3. The read operation circuit of claim 2, wherein the data determining module comprises:
the input end of the data comparison unit is connected to the storage block and is used for setting the change mark data to be low under the condition that the current read data and the previous read data are not changed; and setting the change mark data to be high when the current read data and the previous read data are changed;
the input end of the data judgment unit is connected with the output end of the data comparison unit so as to receive the change marking data, the output end of the data judgment unit is connected with the turnover identification signal line, and the data judgment unit is used for setting the turnover identification data to be high under the condition that the digit of the data which is high in the change marking data is greater than a preset value; and setting the flip identification data to be low when the number of bits of the data which is high in the change mark data is less than or equal to the preset value;
the input end of the data selector receives the overturning identification data through the overturning identification signal line, the output end of the data selector is connected with the global bus, and the data selector is used for outputting the overturning data of the current read data as the global bus data under the condition that the overturning identification data is high; and outputting the original current read data as the global bus data under the condition that the turnover identification data is low.
4. The read operation circuit according to claim 3, wherein the data comparison unit includes;
the latch is connected with the storage block and used for latching the state of the previous read data and a previous clock signal corresponding to the previous read data;
a state comparator connected to the memory block and the latch, for setting the change flag data to low when the state of the current read data and the state of the previous read data are not changed; and setting the change flag data to be high when the state of the current read data and the state of the previous read data are changed.
5. The read operation circuit according to claim 2, wherein the change flag data and the global bus data are each divided into M groups, the flip flag data are M bits, M bit flip flag data correspond one-to-one to M groups of change flag data, and M bit flip flag data correspond one-to-one to M groups of global bus data, where M is an integer greater than 1.
6. The read operation circuit according to claim 5, wherein each set of change flag data is N bits, where N is an integer greater than 1, and the data determination module is configured to output, as a corresponding set of global bus data, the inverted data of the input set of change flag data when the number of bits of data that is high in the input set of change flag data is greater than N/2, and set the one-bit inverted flag data corresponding to the input set of change flag data high; and under the condition that the bit number of high data in the input group of change mark data is less than or equal to N/2, outputting the input group of change mark data as a corresponding group of global bus data, and setting one bit of flip identification data corresponding to the input group of change mark data to be low.
7. The read operation circuit of claim 3, wherein the data selector comprises M data selection units, the data selection units comprising:
the input end of the first inverter receives the overturning mark data through the overturning mark signal line;
a second inverter, an input end of the second inverter receiving the current read data;
the input end of the first transmission gate is connected to the output end of the second phase inverter, the output end of the first transmission gate is connected with the global bus and used for outputting the global bus data, the reverse control end of the first transmission gate is connected to the output end of the first phase inverter, and the positive control end of the first transmission gate receives the overturning identification data through the overturning identification signal line;
and the input end of the second transmission gate receives the current read data, the output end of the second transmission gate is connected with the global bus and used for outputting the global bus data, the reverse control end of the second transmission gate receives the overturning identification data through the overturning identification signal line, and the positive control end of the second transmission gate is connected with the output end of the first phase inverter.
8. The read operation circuit according to claim 1, wherein the data receiving module is configured to output the roll-over data of the global bus data as the cache data if the roll-over identification data is high; and outputting the original global bus data as the cache data under the condition that the turnover identification data is low.
9. The read operation circuit of claim 1, wherein the data receiving module comprises a plurality of data receiving units, the data receiving units comprising:
a third inverter, an input end of which receives the flip identification data through the flip identification signal line;
a fourth inverter, an input of which receives the global bus data through the global bus;
an input end of the third transmission gate is connected to an output end of the fourth inverter, an output end of the third transmission gate is connected to the parallel-serial conversion circuit and used for outputting the cache data to the parallel-serial conversion circuit, an inverted control end of the third transmission gate is connected to an output end of the third inverter, and a positive control end of the third transmission gate receives the flip identification data through the flip identification signal line;
and the input end of the fourth transmission gate receives the global bus data through the global bus, the output end of the fourth transmission gate is connected with the parallel-serial conversion circuit and used for outputting the cache data to the parallel-serial conversion circuit, the reverse control end of the fourth transmission gate receives the overturning identification data through the overturning identification signal line, and the positive control end of the fourth transmission gate is connected with the output end of the third phase inverter.
10. The read operation circuit according to any one of claims 1 to 9, wherein the data buffer module includes;
a plurality of logic nand gates, two input ends of the logic nand gates respectively receiving the enable signal and the current read data;
a plurality of fifth inverters, an input of which receives the enable signal;
a plurality of logic NOR gates, two input ends of which respectively receive the current read data and are connected to the fifth inverter;
the grid electrodes of the PMOS transistors are connected to the output end of the logic NAND gate, and the drain electrodes of the PMOS transistors are connected to the global bus;
a plurality of NMOS transistors, wherein the gates of the NMOS transistors are connected to the output end of the logic NOR gate, and the drains of the NMOS transistors are connected to the global bus and the drains of the NMOS transistors.
11. A semiconductor memory comprising a DQ port, a memory block, and the read operation circuit according to any one of claims 1 to 10.
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| CN201921804727.XU CN210667806U (en) | 2019-10-25 | 2019-10-25 | Read operation circuit and semiconductor memory |
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| CN112712842A (en) * | 2019-10-25 | 2021-04-27 | 长鑫存储技术(上海)有限公司 | Read operation circuit, semiconductor memory and read operation method |
| WO2022217844A1 (en) * | 2021-04-13 | 2022-10-20 | 长鑫存储技术有限公司 | Data transmission circuit and method, and storage apparatus |
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| CN112712842A (en) * | 2019-10-25 | 2021-04-27 | 长鑫存储技术(上海)有限公司 | Read operation circuit, semiconductor memory and read operation method |
| WO2021077780A1 (en) * | 2019-10-25 | 2021-04-29 | 长鑫存储技术有限公司 | Read operation circuit, semiconductor memory and read operation method |
| US11880597B2 (en) | 2019-10-25 | 2024-01-23 | Changxin Memory Technologies, Inc. | Read operation circuit, semiconductor memory, and read operation method |
| EP4180934A4 (en) * | 2021-03-26 | 2024-03-06 | Changxin Memory Tech Inc | Data transmission circuit and method, and storage device |
| WO2022217844A1 (en) * | 2021-04-13 | 2022-10-20 | 长鑫存储技术有限公司 | Data transmission circuit and method, and storage apparatus |
| WO2022217797A1 (en) * | 2021-04-13 | 2022-10-20 | 长鑫存储技术有限公司 | Data transmission circuit, method, and storage apparatus |
| WO2022217792A1 (en) * | 2021-04-13 | 2022-10-20 | 长鑫存储技术有限公司 | Data transmission circuit and method, and storage device |
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