CN1752924A - Real random number generator based on oscillator - Google Patents

Abstract

The present invention relates to a ture random number generator based on oscillator. It is formed from the following components: slow clock generator, quick clock generator, sample hold circuit and postprocessor. Said invention also provides the concrete action of the above-mentioned every component, and working principle of said ture random number generator and its application.

Description

Real random number generator based on oscillator

Technical field

The invention belongs to information security and technical field of integrated circuits, be specifically related to a kind of with the real random number generator in the cryptographic system of IC regime making, can be used in the various cryptographic systems,, also can be used for producing various random seeds or initial password for cryptographic algorithm provides key.

Background technology

Advanced information society presses for contemporary cryptology.At present, various communication networks have greatly changed people's life and working method.Along with the continuous development of informationized society, the status of information in society is more and more important, and everyone life is all closely related with generation, storage, processing and the transmission of information, the thing that the safety of information has become everybody to be concerned about with privacy problem.Information security issue is also paid close attention to more owing to Internet, particularly Development of E-business in commercial and financial field.

Real random number generator has very important application in the contemporary cryptology field.It is the important component part during cryptographic system hardware is realized.With respect to pseudorandom number generator, the random series that real random number generator produced can't be predicted, and can not reproduce, therefore can the better protection transmission of Information.General people utilize the noise source of occurring in nature to produce true random number, produce true random number and mainly realized by three kinds of methods in Circuits System: 1) utilize the Resistance Thermal Noise source directly to amplify; 2) utilization has the sampling of the oscillator of jittering noise; 3) utilize the chaos system of discrete time to shine upon.These three kinds of methods all are based on Analog Circuit Design, produce high performance random series, for cryptographic algorithm provides key.

The random series that is used as key generally is binary code stream.Perfect cryptographic system requires to be used as the sequence long enough of key, two identical group keys can not occur.Simultaneously, performance must be very good at random for the random series of composition key, and information can't be decoded after encrypted like this.If the performance at random of key is good inadequately, before encrypting and the information after encrypting when still having some correlativitys, the analyst just might utilize this correlativity so, by the algorithm of iteration or the like, decodes the information after encrypting, and obtains to encrypt preceding information.

Desirable random series requires the distribution of " 0 " and " 1 " completely random, and single order, second order and high-order related coefficient are enough little, and performance also needs to satisfy the requirement of some other complicated standard at random.Yet, because more extraneous nonideal factor affecting, for example from the interference of power supply or other parts circuit noise (so sometimes noise amplitude is very big and be periodic), the capital influences the operate as normal of real random number generator, the random series degradation that makes real random number generator output.Therefore,, need add the circuit of an aftertreatment, random series be handled, increase the entropy of random series, further improve its performance at random, reach the needs of application by certain algorithm for the random series that true random source produces.

Summary of the invention

The objective of the invention is to propose a kind of real random number generator, it can produce high performance random series, for cryptographic algorithm provides key.

The real random number generator that the present invention proposes is made up of the slow clock generator that has jittering noise, fast clock generator, sampling hold circuit and preprocessor; Slow clock generator can produce the slow clock of one-period random variation, and the r.m.s. that its cycle changes is far longer than the cycle of fast clock; Fast clock is produced by fast clock generator, has the fixing cycle; Under the control of slow clock, sampling hold circuit is sampled to fast clock, obtains random series, and then is input to post processing circuitry, by random series being carried out a series of entropy accumulating operations, exports high performance true random number.

Among the present invention, the cycle that the slow clock that has a jittering noise refers to slow clock is not what fix, and its cycle is near a variation average period, and the distance of each slow clock period from average period be uncertain, and it meets Gaussian distribution.The r.m.s. of this dither cycle requires bigger more than 5 times (as 5-10 doubly) than the cycle of fast clock, and when each slow clock period was sampled fast clock like this, the probability of getting " 0 " or " 1 " was the same, reaches very at random.

Described slow clock generator is made up of a noise amplifier circuit, a hysteresis loop comparator and a feedback regulating circuit.The output of noise amplifier circuit connects hysteresis loop comparator, the slow clock of output cycle random variation.Feedback regulating circuit is regulated the output voltage of noise amplifier by slow clock control simultaneously.

Described noise amplifier circuit is made of an operational amplifier, a noise source and a negative feedback network; Described noise source is made of two resistance, is connected on the positive-negative input end of amplifier; Described negative feedback network is made of two resistance.These two resistance one ends are connected on the noise resistance of operational amplifier negative input end jointly, and the other end is connected on operational amplifier output terminal and ground respectively, constitutes a negative feedback network, the gain of stablizing amplifier.

Described feedback regulating circuit is made up of a charge pump and a Miller equivalent capacity circuit.Slow clock control charge pump discharges and recharges for the Miller equivalent capacity, regulates the voltage of operational amplifier negative input end; Described Miller equivalent capacity circuit is made up of a phase inverter and an electric capacity.Electric capacity connects the input and output of phase inverter, constitutes the Miller capacitance of an equivalence at the input end of phase inverter.The output of the input termination charge pump of phase inverter, the noise resistance of output termination operational amplifier negative input end.

Among the present invention, noise resistance is connected on the input end of operational amplifier, and in the input end of the operational amplifier noise signal by a small margin that superposeed, the output voltage of operational amplifier has the noise dither of certain amplitude like this.When slow clock was high level, charge pump control capacitance charging improved the voltage of operational amplifier anode, make operational amplifier output voltage raise, when being elevated to the high threshold of hysteresis loop comparator, slow clock becomes low level again.Equally, when slow clock is low level, the discharge of charge pump control capacitance, the operational amplifier output voltage reduces, and slow clock becomes high level during to the low threshold value of hysteresis loop comparator.Therefore such loop can produce the slow clock of a fixed frequency.Because the introducing of Resistance Thermal Noise, after amplifying, make the output of operational amplifier have certain noise dither, therefore in the output of operational amplifier during near the threshold value of hysteresis loop comparator, slow clock when saltus step just can't predict, the edge that is slow clock has certain shake, and the cycle can change, and centre frequency is exactly the intrinsic oscillation frequency in loop.

The fast clock generator that the present invention proposes can be that the ring that multistage inverter stage joint group becomes shakes, voltage controlled oscillator or other any type of oscillator.Require the frequency of oscillator essential enough fast, make that the shake r.m.s. of slow clock period is more than 5 times of fast clock period.The dutycycle of clock of will seeking quickness simultaneously will be very near 50%, when sampling, the probability of adopting " 0 " and " 1 " could be accurately near 50% like this.

The sampling hold circuit that the present invention proposes can be d type flip flop, T trigger and other any type of can realize sampling keep the circuit of function.

The preprocessor that the present invention proposes comprises a linear feedback shift register and several XOR gate.Wherein, linear feedback shift register is composed in series by several registers, and the output of afterbody register feeds back to the input of linear feedback shift register; When each in the random series is input to linear feedback shift register,, output to an input end of next stage XOR gate then all with the output XOR of last register; The input of other input end is the output of certain one-level register in the linear feedback shift register; Can from linear feedback shift register, choose the output of some registers and carry out XOR, and then be input to the first order register of linear feedback shift register with the input random series.Random series entropy from linear feedback shift register output improves like this, and performance is greatly improved at random.

Description of drawings

Fig. 1 is the concrete block diagram of real random number generator.

Fig. 2 is the process flow diagram of real random number generator work.

Fig. 3 is the physical circuit block diagram of slow clock generator.

Fig. 4 is the waveform of operational amplifier output terminal in the slow clock generator.

Fig. 5 is the physical circuit figure of preprocessor.

Embodiment

Fig. 1 has shown the block diagram of a real random number generator 600, comprises the fast clock generator of a slow clock generator 100,150, a sampling hold circuit 160 and a preprocessor 500.Slow clock generator 100 produces the slow clock of cycle random variation, and fast clock generator 150 produces a clock of vibration at a high speed, and its cycle is far smaller than the standard deviation that the slow clock period changes.In sampling hold circuit 160, under the control of slow clock, fast clock is sampled, obtain one " 0 " and " 1 " stochastic distribution random series.The random series that produces is input to preprocessor 500, under the control of slow clock, after the processing that a series of entropys of whole sequence process add up, obtains high performance true random number.

Fig. 2 is a process flow diagram of real random number generator 600 work.At first produce a noise signal, the noise in this circuit is mainly provided by two noise resistances.Pass through slow clock generating circuit then, produced the slow clock signal of one-period random variation.Another oscillator will produce fast clock at a high speed simultaneously, and frequency is far longer than slow clock, and generally the former frequency is more than 10 times of latter's frequency.In sampling hold circuit, slow clock is sampled to fast clock, obtains a random series then.Random series obtains final true random number through behind the preprocessor, the random number of output and slow clock synchronization.

Fig. 3 shows it is the circuit block diagram of slow clock generator 100 in the real random number generator, is made up of two noise resistances 108 and 109, operational amplifier 102, hysteresis loop comparator 103, charge pump 104, phase inverter 107, electric capacity 106 and two resistance 110 and 111 that constitute feedback.Direct current biasing 112 provides common mode voltage for the positive-negative input end of operational amplifier 102, makes operational amplifier 102 be biased in suitable working point.Two noise resistances 108,109 are connected on the positive-negative input end of amplifier respectively.Feedback resistance 110 and 111 constitutes a negative feedback network, and the gain of stablizing operational amplifier 102 makes the thermonoise of resistance 110 and 111 amplify certain multiple.Operational amplifier 102 can be any circuit structure high gain operational amplifier, and can steady operation after constituting feedback.The output of operational amplifier 102 connects hysteresis loop comparator 103, and the output of operational amplifier 102 swings back and forth between the height threshold value of hysteresis loop comparator 103, relatively the slow clock of back output.Hysteresis loop comparator 103 can be the hysteresis loop comparator with two different threshold values of any circuit structure, requires the hysteresis interval between threshold value to reach designing requirement, makes the centre frequency of slow clock reach design load.The switch that slow clock discharges and recharges as charge pump 104 simultaneously, when slow clock was high level, control charge pump 104 gave electric capacity 106 chargings with fixed current; When slow clock was low level, charge pump 104 was again with identical current discharge.Charge pump 104 also can be any circuit structure that can realize that the switch Control current discharges and recharges.Electric capacity behind the charge pump 104 is the Miller capacitance of equivalence, is made up of phase inverter 107 and electric capacity 106.Electric capacity 106 connects the input/output terminal of phase inverter 107, and electric capacity 106 is multiply by in the gain that equivalent electric capacity to charge pump 104 output terminals is phase inverter 107.We can access enough big equivalent capacity like this, make charge pump 104 to pass through operational amplifier 102 again with this voltage amplification with the change in voltage of very little rate adaptation operational amplifier 102 positive input terminals.Like this, one of the output voltage of operational amplifier 102 swings up and down, and the triangular wave of the Resistance Thermal Noise of the amplification that superposeed, and its amplitude of fluctuation is the height threshold value of hysteresis loop comparator 103.

Fig. 4 is the roughly waveform of operational amplifier 102 output terminals, is the triangular waveform of the thermonoise that superposeed.V among the figure _THAnd V _TLIt is respectively the height threshold value of hysteresis loop comparator.S is the slope of triangular wave, T _{CLK_SLOW}It is the cycle of slow clock.We can obtain:

T _{CLK_SLOW}＝t ₁+t ₂ (6.1)

t ₁And t ₂Independent random changes with noise voltage, and we can obtain simultaneously

V(t)＝-V _TL+St+v _n(t) (6.2)

V (t) is the time dependent function of output voltage, v _n(t) be Resistance Thermal Noise after amplifying, can release:

$t_1=\frac{V_{\mathrm{TH}}+\left|V_{\mathrm{TL}}\right|-v_n\left(t\right)}{s}---\left(6.3\right)$

Because v _n(t) average is 0, so,

$E\left\{T_{\mathrm{CLK}\_\mathrm{SLOW}}\right\}=\frac{2}{s}(V_{\mathrm{TH}}-V_{\mathrm{TL}})---\left(6.4\right)$

$\mathrm{\σ}\left\{T_{\mathrm{CLK}\_\mathrm{SLOW}}\right\}=\frac{\sqrt{2}}{s}\mathrm{\σ}\left\{v_n\right\}---\left(6.5\right)$

E{T _{CLK_SLOW}Be the average period of slow clock, σ { T _{CLK_SLOW}Be the standard deviation that changes the slow clock period, σ { v _nIt is the root-mean-square valve of amplifying the back noise voltage.By formula (6.5) we as can be seen, σ { T _{CLK_SLOW}And σ { v _nBe directly proportional, be inversely proportional to S.σ { v _nAnd these two values of S all be that we can obtain with some parameter correlation of circuit:

$S=\±\frac{I_{\mathrm{SAT}}}{G_{\mathrm{inv}}{C}_1}G---\left(6.6\right)$

$\mathrm{\σ}\left\{v_n\right\}=\sqrt{{4\mathrm{kTB}}_W{2R}_{\mathrm{noise}}{G}^2}---\left(6.7\right)$

I _SATBe the charging current of charge pump 104, C ₁Be the size of electric capacity 106, G _InvBe the gain of phase inverter 107, G is the gain after operational amplifier 102 closed loops, B _WNoise bandwidth.To (6.7), we just can reasonably select the concrete parameter of other parts in the circuit behind the standard deviation of determining good slow clock period variation by formula (6.4).As the size of noise resistance 108 and 109, the closed loop gain of operational amplifier 102, bandwidth, the charging current of charge pump 104, size of the gain of phase inverter 107 and Miller capacitance 106 or the like.

Fig. 5 has shown concrete preprocessor 500 circuit diagrams.It is made up of a linear feedback shift register and several XORs 501.Linear feedback shift register is made of several d type flip flop 502 series connection, can select any suitable d type flip flop 502 numbers.

The random series of sampling hold circuit 160 outputs is input to an end of first order XOR gate 501, the output terminal Q of certain one-level d type flip flop 502 in the other end wiring feedback shift register of XOR gate 501.First order XOR gate 501 outputs to second level XOR gate 501, and the signal of another grade d type flip flop 502Q end feedback in the other end input wires feedback shift register of second level XOR gate 501, output termination next stage XOR gate 501.The input end of afterbody XOR gate 501 connects the output of one-level XOR gate 501 and the output terminal Q of afterbody d type flip flop 502 respectively.The output of afterbody XOR gate 501 connects the input end of first order d type flip flop 502.

The present invention can adopt a plurality of XOR gate 501, the output terminal Q of certain one-level d type flip flop 502 in the random series of an input termination sampling hold circuit 160 outputs of first order XOR gate 501 and the linear feedback shift register.The input end of afterbody XOR gate 501 connects the output of one-level XOR gate 501 and the output terminal Q of afterbody d type flip flop 502 respectively.

Two input ends of middle some grades of XOR gate 501, the output of a termination upper level XOR gate 501, the output terminal Q of d type flip flop 502 not at the same level in the other end difference wiring feedback shift register.

D type flip flops at different levels 502 in the linear feedback shift register are worked under slow clock control.The random series of sampling hold circuit 160 outputs is input to first order XOR gate 501, latchs output from afterbody d type flip flop 502.What xor operation each random order that is input to preprocessor 500 all passes through, and the entropy of random series obtains increasing, and performance is improved greatly at random, can reach the requirement of application standard.

Claims (5)

1, a kind of real random number generator based on oscillator is characterized in that being made up of the slow clock generator that has jittering noise, fast clock generator, sampling hold circuit and preprocessor; Slow clock generator can produce the slow clock of one-period random variation, and the r.m.s. that its cycle changes is far longer than the cycle of fast clock; Fast clock is produced by fast clock generator, has the fixing cycle; Under the control of slow clock, sampling hold circuit is sampled to fast clock, obtains random series, and then is input to post processing circuitry, by random series being carried out a series of entropy accumulating operations, exports high performance true random number.

2,, it is characterized in that described slow clock generator is made up of a noise amplifier circuit, a hysteresis loop comparator and a feedback regulating circuit according to the described real random number generator of claim 1; The output of noise amplifier circuit connects hysteresis loop comparator, the slow clock of output cycle random variation; Feedback regulating circuit is regulated the output voltage of noise amplifier by slow clock control simultaneously.

3, real random number generator according to claim 2 is characterized in that described noise amplifier circuit is made of an operational amplifier, a noise source and a negative feedback network; Described noise source is made of two resistance, is connected on the positive-negative input end of operational amplifier; Described negative feedback network is made of two resistance, and these two resistance one ends are connected on the noise resistance of operational amplifier negative input end jointly, and the other end is connected on operational amplifier output terminal and ground respectively, constitutes a negative feedback network, the gain of stablizing amplifier.

4, real random number generator according to claim 2, it is characterized in that described feedback regulating circuit is made up of a charge pump and a Miller equivalent capacity circuit, slow clock control charge pump discharges and recharges for the Miller equivalent capacity, regulates the voltage of operational amplifier negative input end; Described Miller equivalent capacity circuit is made up of a phase inverter and an electric capacity, electric capacity connects the input and output of phase inverter, constitute the Miller capacitance of an equivalence at the input end of phase inverter, the output of the input termination charge pump of phase inverter, the noise resistance of output termination operational amplifier negative input end.

5, real random number generator according to claim 1 is characterized in that preprocessor is made up of a linear feedback shift register and several XOR gate; Wherein, linear feedback shift register is composed in series by several registers, and the output of afterbody register feeds back to the input of linear feedback shift register; When each in the random series is input to linear feedback shift register,, output to an input end of next stage XOR gate then all with the output XOR of last register; The input of other input end is the output of certain one-level register in the linear feedback shift register; Can from linear feedback shift register, choose the output of some registers and carry out XOR, and then be input to the first order register of linear feedback shift register with the input random series.

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