CN103034472A - True random number generator - Google Patents
True random number generator Download PDFInfo
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- CN103034472A CN103034472A CN2012105353922A CN201210535392A CN103034472A CN 103034472 A CN103034472 A CN 103034472A CN 2012105353922 A CN2012105353922 A CN 2012105353922A CN 201210535392 A CN201210535392 A CN 201210535392A CN 103034472 A CN103034472 A CN 103034472A
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Abstract
The invention relates to a true random number generator, which comprises a bias circuit for generating two bias voltages VC2 and VR, a random number sampling clock circuit for generating a first sampling clock and a second sampling clock with a fixed frequency under the control of the bias voltage VC2, a variable frequency clock circuit for generating a variable frequency clock with randomly changing frequencies under the control of the first sampling clock and the bias voltage VR, and a random number sampling and post-processing circuit for sampling the variable frequency clock CLKV to obtain a random sequence under the control of the second sampling clock, and carrying out the entropy-accumulation operation on the random sequence. The entropy-accumulation operation on the generated true random numbers is carried out, thus the random performance of the random numbers is improved, and the needs of a high-performance encryption system are met.
Description
Technical field
The invention belongs to the design field of information security chip, particularly the real random number generator in the information security chip encryption system.Can provide key for generation of the random seed of pseudo-random algorithm and for cryptographic algorithm.
Background technology
Safety chip is widely used in the every field of information society, and its major function comprises the safe storage of user's critical data, encryption, deciphering and identification etc.Just because of the importance of data in the safety chip, data in the safety chip are encrypted becomes one of important means of guaranteeing data security.
Tandom number generator has very important application in data encryption system, it is the important component part in the encryption system.Existing tandom number generator is to utilize specific random number algorithm and seed, by the random number sequence of software computing generation.Although it has certain randomness, because random number algorithm and seed are fixed, so this random number sequence can be predicted, reproduce, be actually pseudo-random number sequence, can't satisfy high performance encryption system.
True random number is the random number sequence of utilizing natural noise source to produce, compare pseudo-random number sequence its have unpredictable, the characteristics that can't reappear.The randomness of true random number need to satisfy some testing standards, such as FIPS-140, and the AIS31 standard.But, produce at present the circuit of true random number, because some imperfection factors that exist in the implementation procedure can't realize high performance true random number.
Summary of the invention
The object of the invention is to improve the at random performance of the random number that produces in the encryption system.
A kind of real random number generator, it comprises: biasing circuit, for generation of first a bias voltage VC
2With the second bias voltage VR; The the first bias voltage VC that provides at biasing circuit is provided the random number sampling clock generation circuit
2Lower the first sampling clock and the second sampling clock that produces fixed frequency of control; The variable frequency clock circuit is used for producing the variable frequency clock that a frequency accidental changes under the control of the second bias voltage VR that the first sampling clock and biasing circuit provide, and the frequency change of variable frequency clock is obeyed evenly and distributed; Random number sampling and post processing circuitry are used under the control of the second sampling clock, to variable frequency clock CLK
VSample, obtain random series, and random series is carried out the entropy accumulating operation.
The specific embodiment of the present invention is because the true random number that will produce, and improves the at random performance of random number through the entropy accumulating operation, and the demand of high performance encryption system is satisfied in the security that can further improve thus encryption system.
Description of drawings
Fig. 1 is the circuit diagram of the embodiment of a kind of real random number generator of the present invention.
Internal signal waveforms figure when Fig. 2 is circuit working shown in Figure 1.
Embodiment
Below in conjunction with drawings and Examples invention is described in detail.
As shown in Figure 1, the embodiment of a kind of real random number generator of the present invention, it comprises: variable frequency clock circuit 100, random number sampling clock generation circuit 200, random number sampling and post processing circuitry 300 and biasing circuit 400.
The the first bias voltage VC that provides at biasing circuit 400 is provided random number sampling clock generation circuit 200
2Lower the first sampling clock and the second sampling clock that produces fixed frequency of control; Wherein, the second sampling clock can be that the first sampling clock is through obtaining after the frequency division;
Variable frequency clock circuit 100 is used for producing the variable frequency clock that a frequency accidental changes under the control of the second bias voltage VR that the first sampling clock and biasing circuit 400 provide, and the frequency change of variable frequency clock is obeyed equally distributed;
Random number sampling and post processing circuitry 300 are used under the control of the second sampling clock, to variable frequency clock CLK
VSample, obtain random series, and then by post processing circuitry random series is carried out the entropy accumulating operation.
The specific embodiment of the present invention is the variable frequency clock that a frequency accidental changes owing to what produce, and the frequency of this variable frequency clock is obeyed equally distributed, then to this variable frequency clock sample to a random series, and then the sampling of process random number is carried out the entropy accumulating operation with post processing circuitry 300, thereby, improve the at random performance of random number, the demand of high performance encryption system is satisfied in the security that has also improved thus encryption system.
Optimize, variable frequency clock circuit 100 can comprise: Discrete Chaotic Map circuit 1001, noise amplifier circuit 1002 and voltage controlled oscillator 1003;
Discrete Chaotic Map circuit 1001, for the electric current that produces a random variation under the control of the first sampling clock, the variation of size of current is obeyed evenly and is distributed;
Voltage controlled oscillator 1003 amplifies the control voltage VC of electricity 1002 outputs at noise
1Control under, produce the variable frequency clock CLK that frequency accidental changes
V
The specific embodiment of the present invention is when producing true random number, a plurality of factors such as Resistance Thermal Noise amplification, jitter clock sampling and Discrete Chaotic Map have been introduced simultaneously, so that real random number generator of the present invention can produce high performance true random number, can further improve thus the security of encryption system, satisfy the demand of high performance encryption system.
Concrete, biasing circuit 400 can comprise: a constant current source I
REF, resistance R 1 and R2, the first operational amplifier and the second operational amplifier.Constant current source I
REF, resistance R 1 and R2 be connected in series between the VDD-to-VSS successively; The normal phase input end contact resistance R1 of the first operational amplifier and the node between the R2; The normal phase input end of the second operational amplifier connects constant current source I
REFAnd the node between the resistance R 1; The output terminal of the first operational amplifier is exported the first bias voltage VC
2, and it is fed back to the inverting input of the first operational amplifier; The output terminal of the second operational amplifier is exported the second bias voltage VR, and it is fed back to the inverting input of the second operational amplifier.
Concrete, random number sampling clock generation circuit 200 can comprise: a voltage controlled oscillator 2001 and a frequency divider.
Voltage controlled oscillator 2001 receives the first bias voltage VC of biasing circuit 400 outputs
2, voltage controlled oscillator 2001 outputs the first sampling clock CLK
SHTo Discrete Chaotic Map circuit 1001 and frequency divider, the first sampling clock CLK
SHThrough output the second sampling clock CL behind the frequency divider frequency division
TRNG
Concrete, Discrete Chaotic Map circuit 1001 can comprise: three constant current sources, three discrete chaos electric current mappings 1,2,3 and sampling hold circuit.
Three constant current sources are respectively three discrete chaos electric current mappings 1,2,3 provides reference current, three discrete chaos electric current mapping 1,2,3 cascades, sampling hold circuit is sampled to the output current of discrete chaos electric current mapping 3, and divide two-way output with sample rate current, one the tunnel feeds back to the input end of the discrete chaos electric current mapping of cascade, and another road exports noise amplifier circuit 1002 to.Need to prove, adopt 3 discrete chaos electric current mapping cascades in the specific embodiment of the present invention, only just described as an embodiment, but do not consist of restriction, in the practical application, carry out cascade more than or equal to two discrete chaos electric current mappings and get final product.
Noise source resistance R 3 is connected between the output terminal of the normal phase input end of operational amplifier of noise amplifier circuit 1002 and biasing circuit 400 second operational amplifiers, and noise source resistance R 4 is connected between the output terminal of the inverting input of operational amplifier of noise amplifier circuit 1002 and Discrete Chaotic Map circuit 1001; Feedback resistance R5 is connected between the output terminal of the second operational amplifier of the output terminal of Discrete Chaotic Map circuit 1001 and biasing circuit 400, and feedback resistance R6 is connected between the output terminal of operational amplifier of the output terminal of Discrete Chaotic Map circuit 1001 and noise amplifier circuit 1002.
Concrete, the random number sampling can comprise with post processing circuitry 300: T trigger and post processing circuitry.The T trigger receives the variable frequency clock CLK of variable frequency clock circuit 100 outputs
V, the output terminal of T trigger connects the input end of post processing circuitry, and T trigger and post processing circuitry all receive the second sampling clock CLK of random number sampling clock generation circuit 200 outputs
TRNG
In the specific embodiment of the present invention, Discrete Chaotic Map circuit 1001 has utilized the unsettled characteristics of discrete chaos electric current mapping track.Sampling hold circuit is at the first sampling clock CLK
SHControl under the output current of discrete chaos electric current mapping is sampled, again sample rate current is fed back to the input end of discrete chaos electric current mapping, realize the continuous interative computation of electric current, produce the electric current I of a random variation
CHAOSDiscrete chaos electric current is mapped in the process of electric current interative computation very sensitive to the perturbation of current value, and the perturbation meeting of electric current changes the following track of interative computation fully, and the variation of the electric current that makes is unpredictable.
Noise amplifier circuit converts the random current of Discrete Chaotic Map circuit output to voltage, and the Resistance Thermal Noise voltage generation control voltage VC1 after the stack amplification, and control voltage controlled oscillator 1003 produces a variable frequency clock CLK
VThe voltage controlled oscillator 2001 of random number sampling clock generation circuit 200 produces first a sampling clock CLK who is used for the fixed frequency of control Discrete Chaotic Map circuit 1001 under the control of a constant voltage VC2
SH, behind its process 1/N frequency divider frequency division, produce the second sampling clock CLK that is used for the sampling of control random number and post processing circuitry 300
TRNGRandom number sampling and post processing circuitry 300 are at the second sampling clock CLK
TRNGControl under variable frequency clock is sampled, produce random number sequence, by post processing circuitry the random series that produces is carried out the entropy accumulating operation again, export final true random number.
During work, its inner oscillogram as shown in Figure 2.
Wherein, the function expression of the discrete chaos electric current mapping of Discrete Chaotic Map circuit 1001
I
OUT＝|I
REF-K·I
IN| (4.1)
By initial I
INThrough the I that obtains after the once-through operation
OUTI as next time computing
IN, continuous repeated iterative operation.Work as coefficient
The time, I
OUTCan be at [0, I
REF] interval interior stochastic distribution, and COEFFICIENT K is more near 2, I
OUTAt [0, I
REF] interval interior the distribution near even distribution.K value in the function expression of the discrete chaos electric current mapping of each of cascade is different.Wherein, can find out from (4.1) formula, for some definite I
REFWith K value, electric current I
OUTWill be at [0, I
REF] interior random variation, the scope of this variation is specific.
Resistance Thermal Noise voltage in the noise amplifier circuit 1002 is V
N, the sample rate current of Discrete Chaotic Map circuit 1001 outputs is I
CHAOS, the second bias voltage that biasing circuit 400 provides is VR, and comparer is operated in the closed loop magnifying state, and closed loop gain is
The output voltage of noise amplifier circuit 1002 is VC
1
VC
1＝VR+V
NG-I
CHAOSR
6 (4.2)
Can be found out the thermonoise and the sampling voltage of discrete chaos electric current on feedback resistance that have superposeed in the output voltage of noise amplifier circuit 1002 after amplifying by formula (4.2).Voltage controlled oscillator in the variable frequency clock circuit 100 produces a frequency accidental conversion and has the variable frequency clock of larger shake under the control of noise amplifier circuit 1002 output voltages.
Bias voltage VR and the VC of biasing circuit 400 outputs
2
VR＝I
REF(R
1+R
2) (5.1)
VC
2＝I
REFR
2 (5.2)
Make R
1+ R
2=2R
6, R
2=3R
1
VC then
1=(2I
REF-I
CHAOS) R
6+ V
NG (5.3)
By I
CHAOS∈ [0, I
REF],
So control voltage of voltage controlled oscillator in the variable frequency clock circuit 100
VC
1∈[I
REFR
6+V
N·G，2I
REFR
6+V
N·G] (5.4)
The control voltage of voltage controlled oscillator in the random number sampling clock generation circuit 200
Voltage controlled oscillator 1003 in the variable frequency clock circuit 100 has identical gain G with voltage controlled oscillator 2001 in the random number sampling clock generation circuit 200
VCOWith identical centre frequency f
C
If the control of the voltage controlled oscillator in the random number sampling clock generation circuit 200 voltage
The time, oscillator output clock CLK
SHFrequency be f
0, through the random number sampling clock CLK that exports behind the frequency divider
TRNGFrequency be f
0/ N.The frequency of variable frequency clock is f
1
f
1∈[f
0-(0.5I
REFR
6+V
N·G)G
VO，f
0+(0.5I
REFR
6+V
N·G)G
VCO ] (5.6)
In random number sampling and the post processing circuitry at sampling clock CLK
TRNGTo variable frequency clock CLK
VSampled value be " 0 " or " 1 ", by CLK
TRNGN CLK in cycle
SHCorresponding variable frequency clock frequency f
1, variable frequency clock shake accumulation, the original levels of voltage controlled oscillator and the response time of voltage controlled oscillator jointly determine, thereby guarantee the randomness of the random series that produces.Wherein, can find out from (5.6) formula, for some definite I
REF, G, G
VCO, V
NAnd f
0Value, frequency f
1The scope that changes is specific.
Above-mentioned embodiment illustrates but does not limit the present invention that those skilled in the art can design a plurality of examples that replace within the scope of the claims.The those skilled in the art should be appreciated that there not being violation within the defined scope of the present invention, can make suitable adjustment, modification etc. such as appended claims to specific implementation.Therefore, all according to the spirit and principles in the present invention, any modifications and variations of doing are all within the defined scope of the present invention of appended claims.
Claims (10)
1. a real random number generator is characterized in that, described real random number generator comprises:
Biasing circuit is for generation of first a bias voltage VC
2With the second bias voltage VR;
Described the first bias voltage VC that provides at described biasing circuit is provided the random number sampling clock generation circuit
2Lower the first sampling clock and the second sampling clock that produces fixed frequency of control;
The variable frequency clock circuit is used for producing the variable frequency clock that a frequency accidental changes under the control of described the second bias voltage VR that described the first sampling clock and described biasing circuit provide, and the frequency change of described variable frequency clock is obeyed evenly and distributed;
Random number sampling and post processing circuitry are used under the control of described the second sampling clock, to described variable frequency clock CLK
VSample, obtain random series, and described random series is carried out the entropy accumulating operation.
2. real random number generator according to claim 1, wherein, described variable frequency clock circuit comprises:
The Discrete Chaotic Map circuit, for the electric current that produces a random variation under the control of described the first sampling clock, the variation of size of current is obeyed evenly and is distributed;
Noise amplifier circuit, be used under the control of described the second bias voltage VR that described biasing circuit provides, the current conversion of the random variation of described Discrete Chaotic Map circuit output is become voltage, and the Resistance Thermal Noise voltage of stack after amplifying, control voltage VC produced
1
Voltage controlled oscillator amplifies the control voltage VC of electricity output at described noise
1Control under, produce the variable frequency clock CLK that frequency accidental changes
V
3. real random number generator according to claim 2, wherein, described Discrete Chaotic Map circuit comprises: at least two constant current sources, at least two discrete chaos electric currents mappings and sampling hold circuit;
Described at least two constant current sources are respectively described at least two discrete chaos electric current mappings reference current are provided;
Described at least two discrete chaos electric current mapping cascades;
Described sampling hold circuit is sampled to the electric current of the output terminal of described two discrete chaos electric current mappings of cascade at least, and divide two-way output with described sample rate current, one the tunnel feeds back to the input end of the discrete chaos electric current mapping of described cascade, and another road exports described noise amplifier circuit to.
4. real random number generator according to claim 3, wherein, the function expression of the discrete chaos electric current mapping of described Discrete Chaotic Map circuit is:
I
OUT＝|I
REF-K·I
IN|
By initial I
INThrough the I that obtains after the once-through operation
OUTI as next time computing
IN, through at least twice repeated iterative operation, work as coefficient
The time, I
OUTCan be at [0, I
REF] interval interior stochastic distribution, and COEFFICIENT K is more near 2, I
OUTAt [0, I
REF] interval interior the distribution near even distribution, the K value in the function expression of the discrete chaos electric current mapping of each of cascade is different.
5. real random number generator according to claim 2, wherein, described noise amplifier circuit comprises: operational amplifier, two noise source resistance R 3 and R4, two feedback resistance R5 and R6;
The normal phase input end of the operational amplifier of described noise amplifier circuit receives the second bias voltage of described biasing circuit by described noise source resistance R 3;
Described noise source resistance R 4 is connected between the output terminal of the inverting input of operational amplifier of described noise amplifier circuit and described Discrete Chaotic Map circuit;
Described feedback resistance R5 is connected between the output terminal of output the second bias voltage in the output terminal of described Discrete Chaotic Map circuit and the described biasing circuit;
Described feedback resistance R6 is connected between the output terminal of operational amplifier of the output terminal of described Discrete Chaotic Map circuit and described noise amplifier circuit.
6. real random number generator according to claim 5, wherein, the Resistance Thermal Noise voltage in the described noise amplifier circuit is V
N, the sample rate current of described Discrete Chaotic Map circuit output is I
CHAOS, the second bias voltage that described biasing circuit provides is VR, and comparer is operated in the closed loop magnifying state, and closed loop gain is
The output voltage of described noise amplifier circuit is VC
1
7. real random number generator according to claim 1, wherein, described biasing circuit comprises: a constant current source I
REF, resistance R 1 and R2, the first operational amplifier and the second operational amplifier;
Described constant current source I
REF, resistance R 1 and R2 be connected in series between the VDD-to-VSS successively; The normal phase input end of described the first operational amplifier connects the node between described resistance R 1 and the R2; The normal phase input end of described the second operational amplifier connects described constant current source I
REFAnd the node between the described resistance R 1; The output terminal of described the first operational amplifier is exported described the first bias voltage VC
2, and with described the first bias voltage VC
2Feed back to the inverting input of described the first operational amplifier; The output terminal of described the second operational amplifier is exported described the second bias voltage VR, and described the second bias voltage VR is fed back to the inverting input of described the second operational amplifier.
8. real random number generator according to claim 1, wherein, the random number sampling clock generation circuit comprises: a voltage controlled oscillator and a frequency divider;
Described voltage controlled oscillator receives the first bias voltage VC of biasing circuit output
2, described voltage controlled oscillator is exported the first sampling clock CLK
SHTo described variable frequency clock circuit and frequency divider, described the first sampling clock CLK
SHThrough described the second sampling clock CL of output behind the described frequency divider frequency division
TRNG
9. real random number generator according to claim 1, wherein, the voltage controlled oscillator in the described variable frequency clock circuit has identical gain and identical centre frequency with voltage controlled oscillator in the described random number sampling clock generation circuit.
10. real random number generator according to claim 1, wherein, described random number sampling comprises with post processing circuitry: T trigger and post processing circuitry;
Described T trigger receives the variable frequency clock CLK of described variable frequency clock circuit output
VThe output terminal of described T trigger connects the input end of described post processing circuitry, described post processing circuitry is used for described random series is carried out the entropy accumulating operation, and described T trigger and described post processing circuitry all receive the second sampling clock CLK of described random number sampling clock generation circuit output
TRNG
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| CN104598198A (en) * | 2013-10-30 | 2015-05-06 | 国民技术股份有限公司 | True random number generator |
| CN105659207A (en) * | 2013-10-31 | 2016-06-08 | 西门子公司 | Design of a circuit suitable for generating random bits and circuit for generating random bits |
| CN105912301A (en) * | 2015-02-24 | 2016-08-31 | 英飞凌科技股份有限公司 | Random number generator |
| CN106464236A (en) * | 2014-05-12 | 2017-02-22 | 高通股份有限公司 | Entropy source |
| CN106817591A (en) * | 2017-01-03 | 2017-06-09 | 硅谷数模半导体（北京）有限公司 | Data transmission system, method and apparatus |
| CN107769923A (en) * | 2016-08-23 | 2018-03-06 | 中国科学院声学研究所 | A kind of true random-number generating method based on cpu clock and USB independent clocks |
| CN110764735A (en) * | 2019-10-31 | 2020-02-07 | 太原理工大学 | True random number generator based on self-feedback chaotic light |
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| CN104598198B (en) * | 2013-10-30 | 2018-04-27 | 国民技术股份有限公司 | A kind of real random number generator |
| CN104598198A (en) * | 2013-10-30 | 2015-05-06 | 国民技术股份有限公司 | True random number generator |
| CN105659207A (en) * | 2013-10-31 | 2016-06-08 | 西门子公司 | Design of a circuit suitable for generating random bits and circuit for generating random bits |
| US10157248B2 (en) | 2013-10-31 | 2018-12-18 | Siemens Aktiengesellschaft | Circuit suitable for generating random bits and circuit for generating random bits |
| CN105659207B (en) * | 2013-10-31 | 2018-05-22 | 西门子公司 | Circuit suitable for the structure for generating the circuit of random order and for generating random order |
| CN106464236A (en) * | 2014-05-12 | 2017-02-22 | 高通股份有限公司 | Entropy source |
| CN105912301A (en) * | 2015-02-24 | 2016-08-31 | 英飞凌科技股份有限公司 | Random number generator |
| CN105912301B (en) * | 2015-02-24 | 2018-12-18 | 英飞凌科技股份有限公司 | Random number generator |
| CN107769923A (en) * | 2016-08-23 | 2018-03-06 | 中国科学院声学研究所 | A kind of true random-number generating method based on cpu clock and USB independent clocks |
| CN107769923B (en) * | 2016-08-23 | 2019-11-19 | 中国科学院声学研究所 | A kind of true random-number generating method based on cpu clock and USB independent clock |
| CN106817591A (en) * | 2017-01-03 | 2017-06-09 | 硅谷数模半导体（北京）有限公司 | Data transmission system, method and apparatus |
| CN106817591B (en) * | 2017-01-03 | 2019-10-22 | 硅谷数模半导体（北京）有限公司 | Data transmission system, method and apparatus |
| CN110764735A (en) * | 2019-10-31 | 2020-02-07 | 太原理工大学 | True random number generator based on self-feedback chaotic light |
| CN110764735B (en) * | 2019-10-31 | 2023-03-31 | 太原理工大学 | True random number generator based on self-feedback chaotic light |
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