CN103034472B - A kind of real random number generator - Google Patents
A kind of real random number generator Download PDFInfo
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- CN103034472B CN103034472B CN201210535392.2A CN201210535392A CN103034472B CN 103034472 B CN103034472 B CN 103034472B CN 201210535392 A CN201210535392 A CN 201210535392A CN 103034472 B CN103034472 B CN 103034472B
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Abstract
A kind of real random number generator comprises: biasing circuit, for generation of two biased VC
2and VR; Random number sampling clock generation circuit, at bias voltage VC
2control lower the first sampling clock and the second sampling clock that produce fixed frequency; Variable frequency clock circuit, for producing the variable frequency clock of a frequency accidental change under the control of the first sampling clock and bias voltage VR, the frequency change of variable frequency clock is obeyed and is uniformly distributed; Random number sampling and post processing circuitry, under the control of the second sampling clock, to variable frequency clock CLK
vcarry out sampling and obtain random series, and entropy accumulating operation is carried out to random series.By the true random number of generation through entropy accumulating operation, thus improve the random performance of random number, thus meet the demand of high performance encryption system.
Description
Technical field
The invention belongs to the design field of information security chip, the real random number generator particularly in information security chip encryption system.May be used for producing the random seed of pseudo-random algorithm and provide key for cryptographic algorithm.
Background technology
Safety chip is widely used in the every field of information society, and its major function comprises safe storage to user's critical data, encryption, deciphering and identification etc.Just because of the importance of data in safety chip, data in safety chip are encrypted and become one of important means guaranteeing data security.
Tandom number generator has very important application in data encryption system, and it is the important component part in encryption system.Existing tandom number generator utilizes specific random number algorithm and seed, the random number sequence produced by software computing.Although it has certain randomness, because random number algorithm and seed are fixing, so this random number sequence can be predicted, reproduce, be actually pseudo-random number sequence, high performance encryption system cannot be met.
True random number is the random number sequence utilizing natural noise source to produce, and it has unpredictable to compare pseudo-random number sequence, the feature that cannot reappear.Some testing standards of randomness demand fulfillment of true random number, as FIPS-140, AIS31 standard.But, produce the circuit of true random number at present, because some the imperfection factors existed in implementation procedure cannot realize high performance true random number.
Summary of the invention
The object of the invention is to the random performance improving the random number produced in encryption system.
A kind of real random number generator, it comprises: biasing circuit, for generation of a first bias voltage VC
2with the second bias voltage VR; Random number sampling clock generation circuit, for the first bias voltage VC provided at biasing circuit
2control lower the first sampling clock and the second sampling clock that produce fixed frequency; Variable frequency clock circuit, for producing the variable frequency clock of a frequency accidental change under the control of the second bias voltage VR that provides at the first sampling clock and biasing circuit, the frequency change of variable frequency clock is obeyed and is uniformly distributed; Random number sampling and post processing circuitry, under the control of the second sampling clock, to variable frequency clock CLK
vsample, obtain random series, and entropy accumulating operation is carried out to random series.
The true random number of the specific embodiment of the present invention owing to producing, improves the random performance of random number, further can improve the security of encryption system thus, meet the demand of high performance encryption system through entropy accumulating operation.
Accompanying drawing explanation
Fig. 1 is the circuit diagram of the embodiment of a kind of real random number generator of the present invention.
Fig. 2 is internal signal waveforms figure during circuit working shown in Fig. 1.
Embodiment
Below in conjunction with drawings and Examples, invention is described in detail.
As shown in Figure 1, the embodiment of a kind of real random number generator of the present invention, it comprises: the sampling of variable frequency clock circuit 100, random number sampling clock generation circuit 200, random number and post processing circuitry 300 and biasing circuit 400.
Biasing circuit 400, for generation of a first bias voltage VC
2with the second bias voltage VR;
Random number sampling clock generation circuit 200, for the first bias voltage VC provided at biasing circuit 400
2control lower the first sampling clock and the second sampling clock that produce fixed frequency; Wherein, the second sampling clock can be that the first sampling clock obtains after frequency division;
Variable frequency clock circuit 100, for producing the variable frequency clock of a frequency accidental change under the control of the second bias voltage VR that provides at the first sampling clock and biasing circuit 400, the frequency change of variable frequency clock is obeyed equally distributed;
Random number sampling and post processing circuitry 300, under the control of the second sampling clock, to variable frequency clock CLK
vsample, obtain random series, and then by post processing circuitry, entropy accumulating operation is carried out to random series.
The specific embodiment of the present invention is the variable frequency clock that a frequency accidental changes due to what produce, and the frequency of this variable frequency clock is obeyed equally distributed, then to this variable frequency clock sample to a random series, and then carry out entropy accumulating operation through random number sampling with post processing circuitry 300, thus, improve the random performance of random number, also improve the security of encryption system thus, meet the demand of high performance encryption system.
Optimize, variable frequency clock circuit 100 can comprise: Discrete Chaotic Map circuit 1001, noise amplifier circuit 1002 and voltage controlled oscillator 1003;
Discrete Chaotic Map circuit 1001, for producing the electric current of a random variation under the control of the first sampling clock, the change of size of current is obeyed and is uniformly distributed;
Noise amplifier circuit 1002, for under the control of the second bias voltage VR that provides at biasing circuit 400, the electric current of the random variation exported by Discrete Chaotic Map circuit 1001 converts voltage to, and the Resistance Thermal Noise voltage after superposition amplification, thus produce control voltage VC
1;
Voltage controlled oscillator 1003, amplifies the control voltage VC of electricity 1002 output at noise
1control under, produce the variable frequency clock CLK of frequency accidental change
v.
The specific embodiment of the present invention is when producing true random number, introduce multiple factors such as Resistance Thermal Noise amplification, jitter clock sampling and Discrete Chaotic Map simultaneously, make real random number generator of the present invention can produce high performance true random number, further can improve the security of encryption system thus, meet the demand of high performance encryption system.
Concrete, biasing circuit 400 can comprise: a constant current source I
rEF, resistance R1 and R2, the first operational amplifier and the second operational amplifier.Constant current source I
rEF, resistance R1 and R2 be sequentially connected in series between VDD-to-VSS; Node between normal phase input end contact resistance R1 and R2 of the first operational amplifier; The normal phase input end of the second operational amplifier connects constant current source I
rEFand the node between resistance R1; The output terminal of the first operational amplifier exports the first bias voltage VC
2, and fed back to the inverting input of the first operational amplifier; The output terminal of the second operational amplifier exports the second bias voltage VR, and is fed back to the inverting input of the second operational amplifier.
Concrete, random number sampling clock generation circuit 200 can comprise: a voltage controlled oscillator 2001 and a frequency divider.
Voltage controlled oscillator 2001 receives the first bias voltage VC that biasing circuit 400 exports
2, voltage controlled oscillator 2001 exports the first sampling clock CLK
sHto Discrete Chaotic Map circuit 1001 and frequency divider, the first sampling clock CLK
sHthe second sampling clock CL is exported after frequency divider frequency division
tRNG.
Concrete, Discrete Chaotic Map circuit 1001 can comprise: three constant current sources, three scattered date electric currents map 1,2,3 and sampling hold circuit.
Three constant current sources are respectively three scattered date electric currents mappings 1,2,3 provides reference current, three scattered date electric currents map 1,2,3 cascades, sampling hold circuit is sampled to the output current that scattered date electric current maps 3, and divide two-way to export sample rate current, the input end that the scattered date electric current that one tunnel feeds back to cascade maps, another road exports noise amplifier circuit 1002 to.It should be noted that, adopt 3 scattered date electric currents to map cascade in the specific embodiment of the present invention, only just described as an embodiment, but do not form restriction, in practical application, be more than or equal to two scattered date electric currents mappings and carry out cascade.
Noise amplifier circuit 1002 can comprise: operational amplifier, two noise source resistance R3 and R4, two feedback resistance R5 and R6.
Noise source resistance R3 is connected between the normal phase input end of the operational amplifier of noise amplifier circuit 1002 and the output terminal of biasing circuit 400 second operational amplifier, and noise source resistance R4 is connected between the inverting input of the operational amplifier of noise amplifier circuit 1002 and the output terminal of Discrete Chaotic Map circuit 1001; Feedback resistance R5 is connected between the output terminal of the output terminal of Discrete Chaotic Map circuit 1001 and the second operational amplifier of biasing circuit 400, and feedback resistance R6 is connected between the output terminal of the output terminal of Discrete Chaotic Map circuit 1001 and the operational amplifier of noise amplifier circuit 1002.
Concrete, random number sampling can comprise with post processing circuitry 300: T trigger and post processing circuitry.T trigger receives the variable frequency clock CLK that variable frequency clock circuit 100 exports
v, the output terminal of T trigger connects the input end of post processing circuitry, and T trigger and post processing circuitry all receive the second sampling clock CLK that random number sampling clock generation circuit 200 exports
tRNG.
In the specific embodiment of the present invention, Discrete Chaotic Map circuit 1001 make use of the feature of scattered date electric current mapping trajectories instability.Sampling hold circuit is at the first sampling clock CLK
sHcontrol under the output current that scattered date electric current maps is sampled, then sample rate current is fed back to the input end that scattered date electric current maps, realizes the continuous interative computation of electric current, produce the electric current I of a random variation
cHAOS.Scattered date electric current is mapped in the process of electric current interative computation very sensitive to the perturbation of current value, and the perturbation of electric current can change the Future Trajectory of interative computation completely, and the change of the electric current made is unpredictable.
Noise amplifier circuit converts the random current that Discrete Chaotic Map circuit exports to voltage, and the Resistance Thermal Noise voltage after superposition amplification produces control voltage VC1, controls voltage controlled oscillator 1003, produces a variable frequency clock CLK
v.The voltage controlled oscillator 2001 of random number sampling clock generation circuit 200 produces one for controlling the first sampling clock CLK of the fixed frequency of Discrete Chaotic Map circuit 1001 under the control of a constant voltage VC2
sH, it is after 1/N frequency divider frequency division, produces the second sampling clock CLK for controlling random number sampling and post processing circuitry 300
tRNG.Random number sampling and post processing circuitry 300 are at the second sampling clock CLK
tRNGcontrol under variable frequency clock is sampled, produce random number sequence, then by post processing circuitry to produce random series carry out entropy accumulating operation, export final true random number.
During work, its inner oscillogram as shown in Figure 2.
Wherein, the function expression of the scattered date electric current mapping of Discrete Chaotic Map circuit 1001
I
OUT＝|I
REF-K·I
IN|(4.1)
By initial I
iNthe I obtained after once-through operation
oUTas the I of computing next time
iN, continuous repeated iterative operation.Work as coefficient
time, I
oUTcan at [0, I
rEF] interval interior stochastic distribution, and COEFFICIENT K is more close to 2, I
oUTat [0, I
rEF] interval interior more close being uniformly distributed that distribute.K value in the function expression of each scattered date electric current mapping of cascade is different.Wherein, as can be seen from (4.1) formula, for some I determined
rEFwith K value, electric current I
oUTwill at [0, I
rEF] interior random variation, the scope of this change is specific.
Resistance Thermal Noise voltage in noise amplifier circuit 1002 is V
n, the sample rate current that Discrete Chaotic Map circuit 1001 exports is I
cHAOS, the second bias voltage that biasing circuit 400 provides is VR, and comparer is operated in closed loop magnifying state, and closed loop gain is
the output voltage of noise amplifier circuit 1002 is VC
1
VC
1＝VR+V
NG-I
CHAOSR
6(4.2)
Can be found out in the output voltage of noise amplifier circuit 1002 by formula (4.2) and superpose the thermonoise after amplifying and the sampling voltage of scattered date electric current on feedback resistance.Voltage controlled oscillator in variable frequency clock circuit 100 produces a frequency accidental conversion and has the variable frequency clock of larger shake under the control of noise amplifier circuit 1002 output voltage.
Bias voltage VR and VC that biasing circuit 400 exports
2
VR＝I
REF(R
1+R
2)(5.1)
VC
2＝I
REFR
2(5.2)
Make R
1+ R
2=2R
6, R
2=3R
1.
Then VC
1=(2I
rEF-I
cHAOS) R
6+ V
ng (5.3)
By I
cHAOS∈ [0, I
rEF],
So the control voltage of voltage controlled oscillator in variable frequency clock circuit 100
VC
1∈[I
REFR
6+V
N·G，2I
REFR
6+V
N·G](5.4)
The control voltage of voltage controlled oscillator in random number sampling clock generation circuit 200
Voltage controlled oscillator 1003 in variable frequency clock circuit 100 and the voltage controlled oscillator 2001 in random number sampling clock generation circuit 200 have identical gain G
vCOwith identical centre frequency f
c.
If the voltage controlled oscillator control voltage in random number sampling clock generation circuit 200
time, oscillator output clock CLK
sHfrequency be f
0, the random number sampling clock CLK exported after frequency divider
tRNGfrequency be f
0/ N.The frequency of variable frequency clock is f
1
f
1∈[f
0-(0.5I
REFR
6+V
N·G)G
VO，f
0+(0.5I
REFR
6+V
N·G)G
VCO](5.6)
Random number sampling with post processing circuitry at sampling clock CLK
tRNGto variable frequency clock CLK
vsampled value be " 0 " or " 1 ", by CLK
tRNGn number of CLK in cycle
sHcorresponding variable frequency clock frequency f
1, the accumulation of variable frequency clock shake, the original levels of voltage controlled oscillator and the response time of voltage controlled oscillator jointly determine, thus guarantee the randomness of produced random series.Wherein, as can be seen from (5.6) formula, for some I determined
rEF, G, G
vCO, V
nand f
0value, frequency f
1the scope of change is specific.
Above-mentioned embodiment illustrates but does not limit the present invention, and those skilled in the art can design within the scope of the claims and multiplely replace example.Those skilled in the art it should be appreciated that not violating within scope of the present invention as defined in the appended claims, can make suitable adjustment, amendment etc. to specific implementation.Therefore, all according to the spirit and principles in the present invention, any modifications and variations done, within the scope of the present invention all defined at appended claims.
Claims (8)
1. a real random number generator, is characterized in that, described real random number generator comprises:
Biasing circuit, for generation of a first bias voltage VC
2with the second bias voltage VR;
Random number sampling clock generation circuit, for the described first bias voltage VC provided at described biasing circuit
2control lower the first sampling clock and the second sampling clock that produce fixed frequency;
Variable frequency clock circuit, for producing the variable frequency clock of a frequency accidental change under the control of described second bias voltage VR that provides at described first sampling clock and described biasing circuit, the frequency change of described variable frequency clock is obeyed and is uniformly distributed;
Random number sampling and post processing circuitry, under the control of described second sampling clock, to described variable frequency clock CLK
vsample, obtain random series, and entropy accumulating operation is carried out to described random series;
Wherein, described variable frequency clock circuit comprises:
Discrete Chaotic Map circuit, for producing the electric current of a random variation under the control of described first sampling clock, the change of size of current is obeyed and is uniformly distributed;
Noise amplifier circuit, for under the control of described second bias voltage VR that provides at described biasing circuit, the electric current of the random variation exported by described Discrete Chaotic Map circuit converts voltage to, and the Resistance Thermal Noise voltage after superposition amplification, produce control voltage VC
1;
Voltage controlled oscillator, amplifies the control voltage VC of electricity output at described noise
1control under, produce the variable frequency clock CLK of frequency accidental change
v.
2. real random number generator according to claim 1, wherein, described Discrete Chaotic Map circuit comprises: at least two constant current sources, at least two scattered date electric currents map and sampling hold circuit;
Described in described at least two constant current sources are respectively, at least two scattered date electric currents map and provide reference current;
Described at least two scattered date electric currents map cascade;
Described sampling hold circuit is sampled to the electric current of the output terminal of at least two scattered date electric current mappings described in cascade, and divide two-way to export described sample rate current, the input end that the scattered date electric current that one tunnel feeds back to described cascade maps, another road exports described noise amplifier circuit to.
3. real random number generator according to claim 1, wherein, described noise amplifier circuit comprises: operational amplifier, two noise source resistance R3 and R4, two feedback resistance R5 and R6;
The normal phase input end of the operational amplifier of described noise amplifier circuit receives the second bias voltage of described biasing circuit by described noise source resistance R3;
Described noise source resistance R4 is connected between the inverting input of the operational amplifier of described noise amplifier circuit and the output terminal of described Discrete Chaotic Map circuit;
Described feedback resistance R5 be connected to export the second bias voltage in the output terminal of described Discrete Chaotic Map circuit and described biasing circuit output terminal between;
Described feedback resistance R6 is connected between the output terminal of the output terminal of described Discrete Chaotic Map circuit and the operational amplifier of described noise amplifier circuit.
4. real random number generator according to claim 3, wherein, the Resistance Thermal Noise voltage in described noise amplifier circuit is V
n, the sample rate current that described Discrete Chaotic Map circuit exports is I
cHAOS, the second bias voltage that described biasing circuit provides is VR, and comparer is operated in closed loop magnifying state, and closed loop gain is
the output voltage of described noise amplifier circuit is VC
1.
5. real random number generator according to claim 1, wherein, described biasing circuit comprises: a constant current source I
rEF, resistance R1 and R2, the first operational amplifier and the second operational amplifier;
Described constant current source I
rEF, resistance R1 and R2 be sequentially connected in series between VDD-to-VSS; The normal phase input end of described first operational amplifier connects the node between described resistance R1 and R2; The normal phase input end of described second operational amplifier connects described constant current source I
rEFand the node between described resistance R1; The output terminal of described first operational amplifier exports described first bias voltage VC
2, and by described first bias voltage VC
2feed back to the inverting input of described first operational amplifier; The output terminal of described second operational amplifier exports described second bias voltage VR, and described second bias voltage VR is fed back to the inverting input of described second operational amplifier.
6. real random number generator according to claim 1, wherein, random number sampling clock generation circuit comprises: a voltage controlled oscillator and a frequency divider;
Described voltage controlled oscillator receives the first bias voltage VC that biasing circuit exports
2, described voltage controlled oscillator exports the first sampling clock CLK
sHto described variable frequency clock circuit and frequency divider, described first sampling clock CLK
sHdescribed second sampling clock CL is exported after described frequency divider frequency division
tRNG.
7. real random number generator according to claim 1, wherein, described variable frequency clock circuit comprises voltage controlled oscillator, and described random number sampling clock generation circuit comprises voltage controlled oscillator, and above-mentioned two voltage controlled oscillators have identical gain and identical centre frequency.
8. real random number generator according to claim 1, wherein, described random number sampling comprises with post processing circuitry: T trigger and post processing circuitry;
Described T trigger receives the variable frequency clock CLK that described variable frequency clock circuit exports
vthe output terminal of described T trigger connects the input end of described post processing circuitry, described post processing circuitry is used for carrying out entropy accumulating operation to described random series, and described T trigger and described post processing circuitry all receive the second sampling clock CLK that described random number sampling clock generation circuit exports
tRNG, described random number sampling and post processing circuitry are at sampling clock CLK
tRNGinterior to variable frequency clock CLK
vsample.
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| CN104598198B (en) * | 2013-10-30 | 2018-04-27 | 国民技术股份有限公司 | A kind of real random number generator |
| DE102013222218A1 (en) * | 2013-10-31 | 2014-05-22 | Siemens Aktiengesellschaft | Method for constructing circuit used for generating random bits used in asymmetric authentication method, involves linking specific functions with a pretext of a related function as another function, to perform fixed point free mapping |
| US20150324171A1 (en) * | 2014-05-12 | 2015-11-12 | Qualcomm Incorporated | Entropy source |
| DE102015102602A1 (en) * | 2015-02-24 | 2016-08-25 | Infineon Technologies Ag | Random number generator |
| CN107769923B (en) * | 2016-08-23 | 2019-11-19 | 中国科学院声学研究所 | A kind of true random-number generating method based on cpu clock and USB independent clock |
| CN106817591B (en) * | 2017-01-03 | 2019-10-22 | 硅谷数模半导体（北京）有限公司 | Data transmission system, method and apparatus |
| CN110764735B (en) * | 2019-10-31 | 2023-03-31 | 太原理工大学 | True random number generator based on self-feedback chaotic light |
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| CN1752924A (en) * | 2005-08-18 | 2006-03-29 | 上海微科集成电路有限公司 | Real random number generator based on oscillator |
| CN102662625A (en) * | 2012-04-06 | 2012-09-12 | 国网电力科学研究院 | True random number generator and realization method thereof |
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| CN1752924A (en) * | 2005-08-18 | 2006-03-29 | 上海微科集成电路有限公司 | Real random number generator based on oscillator |
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