CN117891415A - P2L data management method and device of storage device - Google Patents

Abstract

The invention provides a P2L data management method and a device of a storage device, wherein a group of 2 adjacent P2L mapping entries are used for representing a plurality of continuous P2L mapping records, each P2L mapping entry only comprises a physical address and logic mapping data, and the number of bytes occupied by the physical address and the logic mapping data is the same, namely, the data structure of the P2L mapping entry is not required to be changed, so that the data structure of the P2L mapping entry can be realized without re-writing codes on the basis of improving the mapping record density of a P2L mapping table. For a flash memory device having partial map entries already written with data, since the data structure for representing consecutive pieces of P2L map records is the same as the partial map entries already written with data, no modification may be required for the partial P2L map entries in the P2L map table already generated, and thermal update may be implemented to increase the map record density of the P2L map table.

Description

P2L data management method and device of storage device

Technical Field

The present invention relates to the field of storage devices, and in particular, to a method and an apparatus for managing P2L data in a storage device.

Background

Nand Flash is a nonvolatile storage medium and is widely used in Flash memory products (hereinafter referred to as Flash memory) such as SD, eMMC, UFS, SSD. As known in the art, flash memory storage products have three characteristics: 1. after erasing, the page can be written with new data only after being erased; 2. the read/write operation is at page granularity, and the erase operation is at block granularity; 3. each block has a limited number of erasures. Based on the above characteristics, the flash memory storage product cannot be directly connected with the file system of the host like a conventional magnetic Disk, but requires the use of a Flash Translation Layer (FTL) to hide the problem of inconsistent interfaces caused by the three characteristics of the flash memory, so that the file system can access the flash memory like a Hard Disk Drive (HDD). The FTL mainly comprises three functional modules of address mapping, garbage collection and wear leveling. The address mapping records the mapping relationship between logical addresses and physical addresses. In order to reduce the effect of write amplification due to the post-erase write characteristics, a remote update technique is proposed at the FTL layer to reduce the overhead of erase and data movement. Since off-site updates may create some dead space, when the flash memory does not have enough space left, the system may trigger a garbage collection operation to recover the dead space. To avoid physical failures due to frequent erase and write operations, wear leveling techniques have been proposed to uniformly wear out all blocks to extend flash life.

In order to implement the above three functional modules, in the prior art, an L2P (logical_2_physical) table and a P2L (physical_2_logical) table need to be established, where the L2P records a mapping relationship between a logical address and a physical address, the recorded content is a physical address, and an address offset of the table is in a one-to-one correspondence relationship with the logical address; the P2L records the mapping relation between physical addresses and logical addresses, the recorded content is the logical addresses, and the address offset of the table is in one-to-one correspondence with the physical addresses. Address mapping is initiated by the host, and mainly comprises read and write operations: during the reading operation, the logical address is used to obtain the physical address from the L2P table, and the corresponding data is read from the physical address. During writing operation, the information in the table is acquired from the L2P table by using the logical address, if the logical address is 0x7fff, the logical address is idle, namely the logical address is not allocated with the corresponding physical address, then a new physical address is allocated to the writing request, if the block being allocated is allocated completely, a new block is allocated, otherwise, the next page physical address is allocated from the block being allocated, then the newly allocated physical address is updated to the L2P table, and the logical address corresponding to the newly allocated physical address on P2L is updated. In the writing operation, the logical address is used to obtain the information in the table from the L2P table, if the logical address has a physical address (called an old physical address) corresponding to the logical address, the logical address of the old physical address on the P2L table is invalidated, and the specific operation is to modify the table entry corresponding to the old physical address in the P2L table into 0xffff, which indicates that the old physical address is in an invalid state. Garbage Collection (GC) is actively initiated by flash memory devices, and mainly includes erase, move operations: when judging that a certain block meets the Garbage Collection (GC) condition, scanning a P2L table of the block to be subjected to garbage collection, judging whether each page is in an invalid state by identifying whether flag data in an entry corresponding to each physical page in the P2L table is 0xffff, judging whether each page is in a valid state by identifying whether flag data in an entry corresponding to each physical page in the P2L table is 0x0000, and if the page is in the valid state, indicating that the page is valid data, generating a moving operation, wherein the moving operation is similar to a writing operation. And after the selected block is scanned and the useful data is moved to a new address, performing an erasing operation to complete garbage collection. Wherein the erase operation first modifies the P2L table, initializes the P2L table of the physical block to be erased to 0x7fff, indicating an idle state. As to the prior art for identifying whether a physical address is valid in the P2L mapping table, reference may be made to patent document 1, as shown in fig. 4, the mapping table including descriptive flag data representing a mapping relationship between a physical address and a logical address and a data state of a page corresponding to the physical address. More specifically, referring to the mapping table in fig. 4, the physical address P2 corresponds to the logical address L2, and the page data state of the physical address P2 is the valid state 0x0000.

As can be seen from the above description, the P2L table is an indispensable data structure in the operation process of the flash memory device, so that the flash memory device needs to allocate corresponding storage units for storing the corresponding P2L table, and therefore, how to reduce the storage space required for storing the P2L table is a direction that needs to be optimized. By searching, patent document 2 discloses a scheme capable of improving the mapping record density in a cache L2P mapping table, the scheme is applied to optimize the cache space occupied by the L2P mapping table, the principle is to adjust the data structure of the L2P mapping entries, each original L2P mapping entry only comprises a logical address and a corresponding physical address (i.e. mapping record), in patent document 2, a length field is added to each mapping entry, for a plurality of continuous L2P mapping records, the L2P mapping entries are combined into one L2P mapping entry, each L2P mapping entry after adjustment comprises the minimum logical address, the physical address corresponding to the minimum logical address, and the number (i.e. length) of the continuous L2P mapping records of the length field record, and the scheme realizes that a plurality of L2P mapping records are recorded by using one L2P mapping entry, thereby improving the mapping record density in the cache L2P mapping table.

The inventor researches how to improve the mapping recording density of the P2L mapping table on the basis of the scheme provided by patent document 2 for improving the mapping recording density in the cache L2P mapping table, and finds that the scheme of patent document 2 still has the following defects in the research process:

1. while each original mapping entry only includes a pair of logical addresses and a corresponding physical address (i.e., a mapping record), in the solution in patent document 2, to newly increase a field in each mapping entry, the data structure of the mapping entry needs to be adjusted, and after each mapping entry needs to have a field added, the programming task of implementing the mapping table becomes more complex. For example, it is necessary to modify the code of an existing map entry data structure and write new code to implement a new data structure for the map entry.

2. Since in patent document 2, a length field needs to be added to each mapping entry, that is, unlike the original mapping entry data structure, in order to achieve the effect of improving the mapping record density in the cache mapping table, all contents of the mapping table in the flash memory must be updated completely, which means that, in a flash memory device having some mapping entries written with data, the effect of improving the mapping record density in the cache mapping table can only be achieved after the flash memory device is formatted, that is, thermal update cannot be achieved.

3. For a mapping entry with length of 1, the length field of the mapping entry needs to be maintained during writing operation, that is, the mapping entry is set to 1, which increases maintenance overhead.

Patent document 1: chinese patent, patent name, data management method and mapping table updating method in nonvolatile memory device, grant bulletin number, CN101458961B, grant bulletin day, 2014-06-18.

Patent document 2: chinese patent, patent name, method for increasing the density of mapping information in address mapping table, grant bulletin number, CN107066393B, grant bulletin day, 2020-06-09.

Disclosure of Invention

The invention aims to provide a P2L data management method and device of a storage device, which can realize the data structure of a P2L mapping entry without re-writing codes on the basis of improving the mapping record density of a P2L mapping table, and can realize thermal update to improve the mapping record density of the P2L mapping table for a flash memory device (i.e. the storage device) with partial mapping entries written with data.

In order to achieve the above object, the following technical scheme is provided:

in a first aspect, a P2L data management method of a storage device is provided, the method comprising:

when writing data, dividing the data according to page units, sequentially writing the data into blocks with a plurality of continuous free pages in a flash memory according to the sequence from low logical addresses to high logical addresses, and generating one to a plurality of P2L mapping entries according to one P2L mapping record corresponding to each stored page of data; if no cross-block write occurs during the write, the P2L mapping records are contiguous and can be consolidated into a set of 2 adjacent P2L mapping entries; if the cross-block writing is generated during writing, the P2L mapping records corresponding to the data stored in the same block are continuous, and all the corresponding P2L mapping records can be combined into a group of 2 adjacent P2L mapping entries; thus, if a cross-block store is generated and distributed across S blocks when writing a data page, 2S or 2S-1P 2L mapping entries are generated altogether, and a P2L mapping table is established based on the P2L mapping entries;

Each P2L mapping entry only comprises a physical address and logic mapping data, wherein the number of bytes occupied by the physical address and the logic mapping data is the same; for a P2L mapping entry consisting of only 1P 2L mapping record, the logic mapping data is a logic address corresponding to a physical address for indicating the P2L mapping entry;

for each set of 2 adjacent P2L map entries that are merged from multiple P2L map records: the physical addresses of the adjacent 2P 2L mapping entries in the same group are the same; the logic mapping data of the first P2L mapping entry in the same group is used for indicating the minimum logic address in a plurality of P2L mapping records of the group; the logical mapping data of the second P2L mapping entry in the same group is the number data of the plurality of P2L mapping records for indicating the combination.

As a further improvement, the top N bits of the number data are preset flag symbols, and the number formed by the other bits of the number data except the top N bits is used for indicating the number of the plurality of P2L mapping records combined and located, and N is a natural number.

As a further improvement, the method further comprises:

when writing data, skipping the logic address range with the highest N bits in the logic address being the same as the preset sign.

As a further improvement, the method further includes a process of calculating the logical address corresponding to the target physical address from the P2L mapping table, and the process specifically includes:

retrieving the P2L mapping table, wherein when the target physical address can be directly retrieved from the physical addresses of the P2L mapping entries, the logical address corresponding to the physical address of the P2L mapping entry is used as the logical address corresponding to the target physical address;

retrieving the P2L mapping table, and comparing the target physical address with the physical address range represented by each mapping entry to judge whether the target physical address PAA falls in the physical address range represented by a certain group of 2 adjacent P2L mapping entries under the condition that the target physical address cannot be directly retrieved from the physical addresses of the P2L mapping entries;

for a group of 2 adjacent P2L mapping entries with the number N of a certain combined plurality of P2L mapping records, the physical address PAA1 stored in the first P2L mapping entry is LAA1, and when PAA > PAA1 and PAA < = paa1+n-1, the calculation method of the logical address LAA corresponding to the target physical address PAA indicates that the target physical address hits the group of 2 adjacent P2L mapping entries in the P2L mapping table is: laa=laa1+paa-PAA 1, and addressing of the logical address can be completed through calculation.

As a further improvement, in performing the garbage collection operation, the method further comprises:

acquiring a block head physical address of a target block; the target block is a block needing garbage recovery;

acquiring all P2L mapping entries which belong to the same target block as the block head physical address in a P2L mapping table;

calculating each physical address and the corresponding logical address contained in each P2L mapping entry from all P2L mapping entries belonging to a target block with the block head physical address so as to recover all P2L mapping records of the block and serve as a target P2L mapping record set;

loading L2P mapping records corresponding to all logical addresses corresponding to the target P2L mapping record set from an L2P mapping table in the flash memory into a memory to be used as the target L2P mapping record set;

comparing the P2L mapping record and the L2P mapping record with the same logical address in the target P2L mapping record set and the target L2P mapping record set, and generating a moving operation if the P2L mapping record and the L2P mapping record point to the same physical address, which indicates that the page pointed to by the physical address is valid data;

and after the valid data in the target block are all moved to the new address, executing an erasing operation to complete garbage collection of the target block.

As a further improvement, in performing the garbage collection operation, the method further comprises:

acquiring a block head physical address of a target block; the target block is a block needing garbage recovery;

acquiring all P2L mapping entries which belong to the same target block as the block head physical address in a P2L mapping table;

when detecting that all P2L mapping entries belonging to the same target block only comprise 2 adjacent P2L mapping entries belonging to the same group, and indicating that the number of the combined P2L mapping records is equal to the number of pages of the target block according to logic mapping data of a second P2L mapping entry in the 2 adjacent P2L mapping entries of the group, loading L2P mapping records corresponding to all logic addresses contained in all P2L mapping entries of the target block from an L2P mapping table in a flash memory to a memory as a target L2P mapping record set;

sequentially adding 1 to physical addresses contained in all P2L mapping entries of a target block, respectively calculating physical addresses contained in all P2L mapping entries of the target block and corresponding logical addresses thereof, so as to obtain a P2L mapping record corresponding to the current calculation and delete the P2L mapping record obtained by the previous calculation when each calculation is performed, and comparing the P2L mapping record with L2P mapping records with the same logical addresses in a target L2P mapping record set when each calculation is performed, and generating a moving operation if the two mapping records point to the same physical addresses, wherein the page pointed by the physical address is valid data;

And after the valid data in the target block are all moved to the new address, executing an erasing operation to complete garbage collection of the target block.

As a further improvement, the method further comprises:

when writing data, if the number of pages of the written data is N, the number of continuous free pages in a block with a plurality of continuous free pages in a storage device is M, and when N is more than M, the data needs to be stored in a cross-block mode, namely the rest data pages are required to be written into other blocks with a plurality of continuous free pages in sequence from low to high according to logic addresses until all the data pages are written into the storage device;

if the data page is written into the data page, the block-crossing storage is generated, the logic mapping data of the second P2L mapping entry in each group of 2 adjacent P2L mapping entries indicates the number of the P2L mapping records in which the combination is located, namely the number of the data page stored in the corresponding block.

As a further improvement, each group of adjacent 2P 2L mapping entries stores a number of consecutive P2L mapping records; if one P2L map record MPRec1 with physical address PAA being P, its logical address LAA being L, if the other P2L map record MPRec2 with physical address PAA being p+1, its logical address LAA being l+1, the P2L map records MPRec1 and MPRec2 are consecutive, if the other P2L map record MPRec3 with physical address PAA being p+2, its logical address LAA being l+2, the P2L map records MPRec1, MPRec2 and MPRec3 are consecutive, and so on, there are N P2L map records with the values of physical addresses PAA increasing continuously from low to high by P, P +1, p+2, …, p+n-1, the values of physical addresses recorded in adjacent P2L map records differ by 1, and the values of logical addresses LAA also increasing continuously from low to high by L, L +1, l+2, …, l+n-1, i.e. the values of adjacent P2L map records differ by 1.

In a second aspect, a storage device is provided, comprising a flash memory, a processor and a computer program stored on the flash memory and executable on the processor, the processor implementing the steps in a P2L data management method of a storage device as described above when the computer program is executed.

In a third aspect, a computer readable storage medium is provided, on which a computer program is stored which, when executed by a processor, implements the steps of a P2L data management method of a storage device as described above.

Compared with the prior art, the P2L data management method and device for the storage device provided by the invention have the following beneficial effects:

1. a group of 2 adjacent P2L mapping entries are used for representing a plurality of continuous P2L mapping records, each P2L mapping entry only comprises a physical address and logic mapping data, the number of bytes occupied by the physical address and the logic mapping data is the same, namely, the data structure of the P2L mapping entry does not need to be changed, so that the data structure of the P2L mapping entry can be realized on the basis of improving the mapping record density of the P2L mapping table without re-writing codes.

2. For a flash memory device having partial map entries already written with data, since the data structure for representing consecutive pieces of P2L map records is the same as the partial map entries already written with data, no modification may be required for the partial P2L map entries in the already generated P2L map table, and for the case where P2L map records are consecutive in the non-generated P2L map entries, it may be unnecessary to format or delete the entire data of the storage device, but instead, a set of 2 adjacent P2L map entries for representing consecutive pieces of P2L map records may be directly written into the map entries corresponding to the P2L map table already created, and thermal update may be implemented to increase the map record density of the P2L map table.

3. Because special length fields are not required to be added to each P2L mapping entry, for the P2L mapping entry with the length of 1, the length fields are not required to be maintained during writing operation, the corresponding logical address is directly written into the mapping entry with the corresponding physical address, and the length fields are not required to be maintained additionally for the P2L mapping record with the length of 1, namely one P2L mapping entry corresponds to 1P 2L mapping record, so that the cost for maintaining the mapping entry with the length of 1 is reduced.

Drawings

FIG. 1 is a block diagram of a storage device according to the present invention;

fig. 2 is a schematic diagram of a P2L data management method of a storage device according to the present invention;

fig. 3 is a schematic diagram of a P2L data management method of a storage device according to the present invention;

fig. 4 is a prior art P2L map representation with flag data.

Detailed Description

Reference will now be made in detail to the present embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein the accompanying drawings are used to supplement the description of the written description so that one can intuitively and intuitively understand each technical feature and overall technical scheme of the present invention, but not to limit the scope of the present invention.

Before describing in detail the embodiments provided by the present invention, it is necessary to emphasize the inventive concepts of the present invention again in order for those skilled in the art to understand the technical contributions of the present invention compared to the prior art. In the process of researching how to improve the mapping record density of the P2L mapping table, the inventor finds that, through searching, patent document 2 also provides a scheme for improving the mapping record density of the mapping table, and the scheme is based on the same principle, namely fewer mapping entries represent more mapping entries, and the key is that a plurality of consecutive mapping records can be represented by the minimum address and the consecutive number, so that the purpose that fewer mapping entries represent more mapping entries is realized, and the mapping record density of the mapping table is improved. It has been found that the scheme of patent document 2 requires modification of the data structure of each mapping entry in the prior art, i.e. adding a length field to indicate the number of consecutive mapping records, which leads to the following problems:

1. While each original mapping entry only includes a pair of logical addresses and a corresponding physical address (i.e., a mapping record), in the solution in patent document 2, to newly increase a field in each mapping entry, the data structure of the mapping entry needs to be adjusted, and after each mapping entry needs to have a field added, the programming task of implementing the mapping table becomes more complex. For example, it is necessary to modify the code of an existing map entry data structure and write new code to implement a new data structure for the map entry.

2. Since in patent document 2, a length field needs to be added to each mapping entry, that is, unlike the original mapping entry data structure, in order to achieve the effect of improving the mapping record density in the cache mapping table, all contents of the mapping table in the flash memory must be updated completely, which means that, in a flash memory device having some mapping entries written with data, the effect of improving the mapping record density in the cache mapping table can only be achieved after the flash memory device is formatted, that is, thermal update cannot be achieved.

3. For a mapping entry with length of 1, the length field of the mapping entry needs to be maintained during writing operation, that is, the mapping entry is set to 1, which increases maintenance overhead.

The scheme of patent document 2 is applied to improving the mapping record density in the cache L2P mapping table, and the application scenario is different from the present invention, the present invention is applied to the P2L mapping table, the P2L mapping table needs to be used for garbage collection operation, and for convenience of garbage collection, the existing structure of the P2L mapping table needs to specially mark a flag bit corresponding to whether a physical address is valid or invalid, so as to facilitate subsequent garbage collection, and in garbage collection, it is not necessary to mark whether each logical address in the L2P is valid or invalid. It can be known that, because the P2L and L2P application scenarios are different, after merging multiple mapping records into one P2L mapping entry according to the principles in patent document 2, it is unable to identify whether each physical address is valid or invalid, which increases the difficulty in how to increase the mapping record density of the P2L mapping table.

The P2L data management method for a storage device according to the present invention will be described in detail with reference to the accompanying drawings and embodiments, to solve the above-mentioned problems and difficulties.

Referring to fig. 1, a frame diagram of a storage device according to this embodiment is provided. The device comprises a flash memory, a memory (i.e. DRAM), a processor (i.e. ARM CPU) and a computer program stored on the flash memory and capable of running on the processor, wherein the processor realizes each step in a P2L data management method of a storage device which can solve the problems when executing the computer program. The technical contribution of the invention lies in the method, and the specific framework of the storage device belongs to the prior art and is not repeated here.

The P2L data management method of the storage device provided by the invention comprises the following steps:

1. similar to patent document 2, the present invention also requires a condition for determining whether or not adjacent P2L mapping records on a plurality of physical addresses can be merged into a P2L mapping entry

In the embodiment of the invention, when writing data (it can be understood that the P2L mapping table is not affected when reading data), a plurality of P2L mapping records meeting the conditions can be combined into a group of adjacent 2P 2L mapping entries, and each group of generated adjacent 2P 2L mapping entries stores a plurality of continuous P2L mapping records; specifically, if one P2L map record MPRec1 with physical address PAA being P, its logical address LAA being L, if the other P2L map record MPRec2 with physical address PAA being p+1, its logical address LAA being l+1, the P2L map records MPRec1 and MPRec2 are consecutive, if the other P2L map record MPRec3 with physical address PAA being p+2, its logical address LAA being l+2, the P2L map records MPRec1, MPRec2 and MPRec3 are consecutive, and so on, there are N P2L map records with physical address PAA continuously increasing in value from low to high by P, P +1, p+2, …, p+n-1, the values of the physical addresses recorded in adjacent P2L map records differ by 1, and the values of the logical addresses LAA also increasing from low to high by L, L +1, l+2, …, N-1, the values of the adjacent P2L map records being consecutive P2L map records, the P2L map records being N2L map records.

For consecutive N P2L mapping records, 2P 2L mapping entries can be merged, which is defined as a set of adjacent 2P 2L mapping entries: for each set of 2 adjacent P2L map entries that are merged from multiple P2L map records: the physical addresses of the adjacent 2P 2L mapping entries in the same group are the same; the logic mapping data of the first P2L mapping entry in the same group is used for indicating the minimum logic address in a plurality of P2L mapping records of the group; the logical mapping data of the second P2L mapping entry in the same group is the number data of the plurality of P2L mapping records for indicating the combination.

Each P2L mapping entry only comprises a physical address and logic mapping data, wherein the number of bytes occupied by the physical address and the logic mapping data is the same; for a P2L mapping entry consisting of only 1P 2L mapping record, the logical mapping data is a logical address corresponding to a physical address for indicating the P2L mapping entry.

Compared with the prior art, the P2L data management method of the storage device provided by the invention has at least the following beneficial effects:

1. a group of 2 adjacent P2L mapping entries are used for representing a plurality of continuous P2L mapping records, each P2L mapping entry only comprises a physical address and logic mapping data, the number of bytes occupied by the physical address and the logic mapping data is the same, namely, the data structure of the P2L mapping entry does not need to be changed, so that the data structure of the P2L mapping entry can be realized on the basis of improving the mapping record density of the P2L mapping table without re-writing codes.

2. For a flash memory device having partial map entries already written with data, since the data structure for representing consecutive pieces of P2L map records is the same as the partial map entries already written with data, no modification may be required for the partial P2L map entries in the already generated P2L map table, and for the case where P2L map records are consecutive in the non-generated P2L map entries, it may be unnecessary to format or delete the entire data of the storage device, but instead, a set of 2 adjacent P2L map entries for representing consecutive pieces of P2L map records may be directly written into the map entries corresponding to the P2L map table already created, and thermal update may be implemented to increase the map record density of the P2L map table.

3. Because special length fields are not required to be added to each P2L mapping entry, for the P2L mapping entry with the length of 1, the length fields are not required to be maintained during writing operation, the corresponding logical address is directly written into the mapping entry with the corresponding physical address, and the length fields are not required to be maintained additionally for the P2L mapping record with the length of 1, namely one P2L mapping entry corresponds to 1P 2L mapping record, so that the cost for maintaining the mapping entry with the length of 1 is reduced.

2. When writing data, the data is divided according to the page unit, then the data is sequentially written into blocks with a plurality of continuous free pages in a Flash memory (NAND Flash) according to the order of logical addresses from low to high, each page of stored data corresponds to one P2L mapping record, and one to a plurality of P2L mapping entries can be generated by the continuous P2L mapping records.

When writing data, if the number of pages of the written data is N, the number of continuous free pages in a block with a plurality of continuous free pages in the flash memory is M, and N > M, the data needs to be stored across blocks, namely, the rest data pages need to be written into other blocks with a plurality of continuous free pages in sequence from low to high in logic address, until all the data pages are written into the memory.

When writing data, the data is also written into the block in units of pages, the writing sequence of the pages in the block can only be written from the lower address page to the higher address page in sequence and can not be written randomly, so that the data with low logical address is written into the page with low physical address, and an L2P mapping record from logical address to physical address is generated, and a corresponding P2L mapping record is correspondingly generated for operation in garbage collection. The data with the next lower logical address is written into the page with the next lower physical address to generate an L2P mapping record from the logical address to the physical address, and each corresponding L2P mapping record generates a corresponding P2L mapping record until the data of the request is completely written; if the free pages in the free blocks are all fully written in the writing process and part of page data still exist in the request and are not written into the NAND Flash, the data need to be written across the blocks, namely a new free block is allocated for writing the data in the writing request, and the data writing sequence is that the data with a low logic address are written into the pages with a low physical address, so that an L2P mapping record from the logic address to the physical address is generated, and a corresponding P2L mapping record is correspondingly generated; the next lower logical address data is written to the next lower physical address page to generate a logical address to physical address L2P map record, and a corresponding P2L map record is generated accordingly. And repeating the steps until all data in the write request are written into the NAND Flash, and generating a corresponding P2L mapping record.

The write request thus produces N P2L mapped records that are contiguous if no cross-block writes are produced at the time of writing. Therefore, the N mapping records can be combined into 2 mapping entries, namely a group of 2 adjacent P2L mapping entries, and the physical addresses of the 2 adjacent P2L mapping entries in the same group are the same; the logic mapping data of the first P2L mapping entry in the same group is used for indicating the minimum logic address in a plurality of P2L mapping records of the group; the logical mapping data of the second P2L mapping entry in the same group is the number data of the plurality of P2L mapping records for indicating the combination.

If the writing generates the writing of the cross-block, M mapping records corresponding to the data stored in the same block are continuous, so that the M mapping records can be combined into 2 mapping entries, the logic mapping data of the second P2L mapping entry in the same group is the quantity data used for indicating the combined multiple P2L mapping records, the top N bits of the quantity data are preset sign symbols C, and N is a natural number. The number of bits of the number data, except the top N bits, is used for indicating the number of the plurality of P2L mapping records combined and combined, and the number is M. If the data page is written, the data page is stored in a cross-block mode and distributed in S blocks, if the page number stored in the last block is not smaller than 2 pages, 2S pieces of P2L mapping entries are formed, and if the page number stored in the last block is only 1 page, 2S-1 pieces of P2L mapping entries are formed. The logical mapping data of the second P2L mapping entry of each set of 2P 2L mapping entries indicates the number of pages in the corresponding block in which data was written due to the current request.

Specifically, as shown in fig. 2, each P2L mapping entry is composed of 4 bytes, namely a 32-bit physical address (PAA) and a 32-bit logical address (LAA), and the known logical addresses 0x00001100-0x0000117F write continuous data, so that the L2P mapping table in the prior art occupies 0x 80L 2P mapping entries. If the 0x80 pages are all located on one block, as shown in the P2L mapping table in fig. 2, a group of 2 adjacent P2L mapping entries are identified, where the physical address of the first P2L mapping entry is 0x00000200, the physical address of the second P2L mapping entry is also 0x00000200, and the logical mapping data of the first P2L mapping entry is the smallest logical address in the P2L mapping records used to indicate the group where the first P2L mapping entry is located, that is, 0x00001100; the logical mapping data of the second P2L mapping entry is the number data of the plurality of P2L mapping records indicating the combination, that is, 0xFF000080, that is, N is 8, the top 8 bits are 0xFF, and the binary representation is 11111111, that is, the flag symbol is 11111111. The top N bits of the number data are preset flag symbols, that is, the flag symbol is C, and the number of the other bits of the number data except the top N bits is used to indicate the number of the P2L mapping records in the combination, that is, 0×80=128. It can be understood that, since the top N bits of the number data are preset flag symbols, the host excludes the logical address range corresponding to 0xFF000000-0xFFFFFFFF when writing data. The exclusion here refers to that the LBA field in the write command of the host excludes the logical address range corresponding to 0xFF000000-0xFFFFFFFF, specifically, when the host writes a piece of data to the flash memory device, the format of the write command sent to the flash memory device is Req (LAA: 0xfeffff, size: n1, DIR: W, S1 … Sn), where the LAA field is the starting logical address, in this example, 0xfeffff, the Size field is the Size of the piece of data, that is, the corresponding page number, in this example, n1, the DIR field is the command type, W represents writing data to the flash memory device, R represents reading data from the flash memory device, and finally, the fourth field is the transferred data, in this example, S1 … Sn. If the host reads a piece of data from the flash memory device, the read command is sent to the flash memory device in Req (LAA: 0xFEFFFFFF, size: n1, DIR: W) without a fourth field.

For the above reasons, since the top N bits of the number data are preset flag symbols, the host excludes the logical address range corresponding to 0xFF000000-0xFFFFFFFF when writing data, but since the logical address corresponding to 0xFF000000-0xFFFFFFFF is only the skipped range of the write command of the host file system, the use of the actual physical address in the flash memory is not affected, and the use range of the physical storage space in the flash memory is not reduced. It should be noted that, since the LAA field in the write command excludes the logical address range corresponding to 0xFF000000-0xFFFFFFFF, the logical address range corresponding to 0xFF000000-0xFFFFFFFF is not likely to occur in the logical mapping data of the first one of a set of 2 adjacent P2L mapping entries in the P2L mapping table. Therefore, when the logical address range corresponding to 0xFF000000-0xFFFFFFFF appears in the LAA field in the P2L table, the logical address corresponding to the PAA field in the P2L mapping entry can be determined, and the logical address is not the logical address corresponding to the PAA field in the P2L mapping entry, but is used for indicating the number of the combined multiple P2L mapping records, so that confusion is not caused. On the other hand, although the LAA field in the read/write command sent by the host does not have a logical address range corresponding to 0xFF000000-0xFFFFFFFF, the LAA field in the L2P table constructed by the flash memory device can still normally travel the logical address range corresponding to 0xFF000000-0xFFFFFFFF, so that the construction and use of the L2P table in the prior art are not affected.

Further, since the host excludes the logical address range corresponding to 0xFF000000-0xFFFFFFFF, the number of logical addresses that the host can use is less than the number of physical addresses in the flash memory, for example, 0xFF000000-0xffffff occupies a total of 16 to the power of 7 logical addresses, so that the number of logical addresses that the host can use is less than the number of physical addresses in the flash memory by the power of 16 (i.e., the power of 24 of 2), each logical address corresponds to 4K bytes (i.e., the power of 1 page, i.e., the power of 12 of 2), so that the host cannot directly access the flash memory device to the 36 bytes of 2, i.e., the power of 64GB. In other words, if the starting logical address of a certain file in the file system is within the logical address range corresponding to 0xFF000000-0xFFFFFFFF, e.g., 0xFF00000C, the file system will not be able to access the file. This may result in a file system that cannot effectively utilize the storage capacity of the flash memory when using existing file read-write control schemes for data access to the flash memory.

Based on this, in order to achieve the data structure of the P2L mapping entry without re-writing code on the basis of improving the mapping recording density of the P2L mapping table, and on the basis of achieving the effect of improving the mapping recording density of the P2L mapping table by performing thermal update on a flash memory device (i.e., a storage device) to which some mapping entries have been written, the embodiment further includes the following method:

Step A, defining a starting logical address when the highest N bits of the data are sign symbols and the other bits are 0;

step B, calculating the storage capacity of the flash memory device which cannot be directly accessed by the host computer based on the starting point logical address, and taking the storage capacity as a target storage capacity;

step C, the host selects a single file with the data volume not smaller than the target storage capacity from a file pool to be written into the flash memory device as a target file;

and D, generating a write command for writing the target file into the flash memory device, wherein the initial logical address in the write command is one bit less than the initial logical address.

The method is particularly suitable for being applied to a network disk scene, because a large amount of data is stored in the network disk, the existing P2L mapping table structure or L2P structure is inconvenient to change, so that the data structure of P2L mapping entries can be realized without re-writing codes on the basis of improving the mapping recording density of the P2L mapping table, and the utilization rate of the capacity of the flash memory can be improved on the basis of improving the mapping recording density of the P2L mapping table by realizing thermal updating on the basis of the flash memory device (namely a storage device) with partial mapping entries written with data. Generally, a blue-ray shadow file generally has several tens of GB or up to hundreds of GB, so that a range of storage capacities in which a host cannot directly access a flash memory device can be modified by adjusting a value of N, and the target storage capacity is smaller as N is larger. When there is no single file with a large enough data size, N needs to be enlarged, for example, when N is 12, the top 12 is adjusted to 0xFFF, and the top 12 bits of the number of data are 0xFFF, and the binary representation is 1111111111, that is, the logical address range corresponding to 0xFFF00000-0xFFFFFFFF is excluded, where 0xFFF00000 is defined as the starting logical address. Based on the starting logical address 0xFFF00000, it is known that the number of logical addresses that the host can use is less than the number of flash physical addresses by 5 th power of 16 (i.e., 20 th power of 2), and each logical address corresponds to 4 kbytes (i.e., 1 page, i.e., 12 th power of 2 bytes), so that the storage capacity that the host cannot directly access is 32 th power of 2, i.e., 4GB, i.e., the target storage capacity. For example, when the maximum file in the file pool to be written into the flash memory device is 4GB, the host sets N to 12, and the target file data amount is 4GB. Finally, the starting logical address is determined to be 0xFFEFFFFF, and a write command is generated to write the target file into the flash memory device, req (LAA: 0xFFFFFFFF, size:1048576, DIR: W, A1 … An).

Correspondingly, in the P2L mapping table, for each set of 2 adjacent P2L mapping entries formed by combining 1048576P 2L mapping records:

the physical addresses (PAAs) of the 2P 2L map entries that are adjacent in the same group are the same, in this example, all 0xC0000000;

the logical mapping data of the first P2L mapping entry in the same group is the smallest logical address (LAA) in the plurality of P2L mapping records used to indicate the group, in this example 0 xffeffff;

the logical mapping data of the second P2L mapping entry in the same group is the number data of the plurality of P2L mapping records used for indicating the combination and is represented as 0xFFFFFFFF in this example as 1048576.

Therefore, the initial logical address of the target file is not in the logical address range corresponding to 0xFFF00000-0xFFFFFFFF, and the storage capacity which cannot be directly accessed by the host is completely covered by the single file, so that the file stored in the logical address range corresponding to 0xFFF00000-0xFFFFFFFF can be accessed by the host, the storage space of the logical address range corresponding to 0xFFF00000-0xFFFFFFFF is not wasted, the access to a part of logical addresses is not influenced under the condition that the part of logical addresses are used as the sign marks, and the utilization rate of the host to the storage space of the flash memory device is further ensured.

3. In one embodiment, a process of calculating a logical address corresponding to the target physical address from the P2L mapping table is further provided, where the process specifically includes:

when the P2L mapping table is searched, and the target physical address can be directly searched from the physical addresses of the P2L mapping entries, the logical address corresponding to the physical address of the P2L mapping entry is used as the logical address corresponding to the target physical address.

As shown in fig. 2, the target physical address is 0x00000200, and two P2L mapping entries, i.e. 2P 2L mapping entries adjacent to the same group, are retrieved, wherein the logical mapping data of the first entry is 0x00001100, and the logical mapping data of the second entry is 0xFF000080. The logical mapping data of the first strip is determined to be a logical address when the highest N bits of the logical mapping data of the first strip are detected to be not the preset identification symbol C, and the logical mapping data of the second strip is determined to be a number of data when the highest N bits of the logical mapping data of the second strip are detected to be the preset identification symbol C. Then, 0x00001100 is set as the logical address corresponding to the target physical address 0x 00000200.

And searching the P2L mapping table, and comparing the target physical address with the physical address range represented by each mapping entry to judge whether the target physical address PAA falls in the physical address range represented by a certain group of 2 adjacent P2L mapping entries when the target physical address cannot be directly searched from the physical addresses of the P2L mapping entries.

For a group of 2 adjacent P2L mapping entries with the number N of a certain combined plurality of P2L mapping records, the physical address PAA1 stored in the first P2L mapping entry is LAA1, and when PAA > PAA1 and PAA < = paa1+n-1, the calculation method of the logical address LAA corresponding to the target physical address PAA indicates that the target physical address hits the group of 2 adjacent P2L mapping entries in the P2L mapping table is: laa=laa1+paa-PAA 1, and addressing of the logical address can be completed through calculation.

As in fig. 2, the target physical address paa=0x 00000202 cannot be directly retrieved from the physical addresses of the P2L mapping entries, and for a set of adjacent P2L mapping entries where the physical address of the first stripe is paa1=0x 00000200 and the physical address of the second stripe is 0x00000200 as well as the first stripe, paa1=0x00000200, laa=0x00001100, and n=0x80=128, i.e. laa=0x 00001102.

In one embodiment, in performing the garbage collection operation, the method further comprises:

example 1:

step S201, obtaining the block head physical address of a target block; the target block is a block which needs garbage recovery.

In this embodiment, physical addresses corresponding to each page are allocated to each block in the flash memory in advance, where the physical address of each page of one block is continuous, and the minimum physical address is the block head physical address of one block, and when writing data, the physical addresses of one block are allocated in sequence to store data, and only if all pages of one block are stored, the pages of the next block are allocated. Thus, when garbage collection is performed on a block, the block head address of the block can be found quickly.

Step S202, all P2L mapping entries which belong to the same target block as the block head physical address in the P2L mapping table are obtained.

Assuming that the number of pages of the target block is 0×80=128 pages and the block header physical address is 0× 00000200, as shown in fig. 3, for the continuous data stored on the block, it is known that all P2L mapping entries of the target block are a set of 2 adjacent P2L mapping entries, the first one is 0× 00000200, 0x00001100, and the second one is 0× 00000200, 0xFF000080.

In step S203, each physical address and its corresponding logical address included in each P2L mapping entry are calculated from all P2L mapping entries belonging to a target block with the block head physical address, so as to recover all P2L mapping records of the block, and serve as a target P2L mapping record set.

The target block totally relates to 128P 2L mapping records, the physical address is calculated from 0x00000200-0x0000027F according to the flow of calculating the logical address corresponding to the target physical address from the P2L mapping table: the logical address corresponding to the block head physical address 0x00000200 of the target block is 0x00001100, the target block secondary low physical address is 0x00000201, the target block secondary low logical address is 0x00001101, the target block highest physical address is 0x0000027F, and the target block highest logical address is 0x0000117F, so that the target P2L mapping record set is obtained.

Step S204, L2P mapping records corresponding to all logical addresses corresponding to the target P2L mapping record set are loaded from the L2P mapping table in the flash memory into the memory as the target L2P mapping record set.

As shown in FIG. 3, 128L2P mapping records in the L2P mapping table in the prior art require 128L2P mapping records, and the logical addresses are from 0x00001100 to 0x0000117F.

In step S205, the P2L mapping record and the L2P mapping record having the same logical address in both the target P2L mapping record set and the target L2P mapping record set are compared, and if both point to the same physical address, indicating that the page to which the physical address points is valid data, a move operation is generated.

As shown in fig. 3, the logical address 0x00001100 points to a physical address of 0x00000200 in the L2P mapping table and the P2L mapping table, indicating that the page pointed to by the physical address is valid data, and a move operation is generated.

In step S206, when the valid data in the target block has been moved to the new address, an erase operation is performed to complete garbage collection of the target block.

While logical address 0x00001103 points to physical address 0x00004012 in the L2P mapping table, the physical address pointed to in the P2L mapping table is calculated to be 0x00000203, indicating that the page pointed to by the physical address is invalid data, and an erase operation is performed.

Example 2:

step S301, obtaining a block head physical address of a target block; the target block is a block which needs garbage recovery.

In this embodiment, physical addresses corresponding to each page are allocated to each block in the flash memory in advance, where the physical address of each page of one block is continuous, and the minimum physical address is the block head physical address of one block, and when writing data, the physical addresses of one block are allocated in sequence to store data, and only if all pages of one block are stored, the pages of the next block are allocated. Thus, when garbage collection is performed on a block, the block head address of the block can be found quickly.

Step S302, obtain all P2L mapping entries in the P2L mapping table, which belong to a target block with the block header physical address.

Assuming that the number of pages of the target block is 0×80=128 pages and the block header physical address is 0× 00000200, as shown in fig. 3, for the continuous data stored on the block, it is known that all P2L mapping entries of the target block are a set of 2 adjacent P2L mapping entries, the first one is 0× 00000200, 0x00001100, and the second one is 0× 00000200, 0xFF000080.

In step S303, when it is detected that all P2L mapping entries belonging to the same target block only include 2P 2L mapping entries belonging to the same group, and the number of the plurality of P2L mapping records in the group is equal to the number of pages of the target block according to the logic mapping data indication of the second P2L mapping entry in the 2P 2L mapping entries adjacent to the group, L2P mapping records corresponding to all logic addresses included in all P2L mapping entries of the target block are loaded from the L2P mapping table in the flash memory into the memory as the target L2P mapping record set.

As shown in fig. 3, it can be seen that all P2L mapping entries of the target block are a group of 2 adjacent P2L mapping entries, the first entry is 0x00000200, 0x00001100, and the second entry is 0x00000200, 0xFF000080. And the logical mapping data of the second P2L mapping entry in the set of 2P 2L mapping entries indicates that the number of the plurality of P2L mapping records in which the set is combined is 128, which is equal to the number of pages of the target block.

The loading, from an L2P mapping table in the flash memory, L2P mapping records corresponding to all logical addresses contained in all P2L mapping entries of the target block into the memory, as a target L2P mapping record set, specifically includes:

the method comprises the steps of taking the lowest physical address of a first P2L mapping entry in a group of 2 adjacent P2L mapping entries as a starting physical address, taking the number of a plurality of P2L mapping records in which a logic mapping data instruction of a second P2L mapping entry of the group of 2 adjacent P2L mapping entries is combined minus 1 as an upper limit, starting from 0, adding the logic mapping data instruction with the starting physical address at intervals of 1, and calculating a plurality of target physical addresses. Then, all logical addresses included in the P2L mapping entry are calculated according to the respective target physical addresses, and the specific calculation may refer to a procedure of calculating the logical address corresponding to the target physical address from the P2L mapping table. For example, in fig. 3, the starting physical address is 0x00000200, the upper limit is 127, when 0 is added, the corresponding target physical address is 0x00000200, and the corresponding logical address 0x00001100 exists in the P2L mapping table. When 1 is added, the target physical address is 0x00000201, and the corresponding logical address 0x00001101 is calculated. And so on.

Then, L2P map records corresponding to all logical addresses included in all P2L map entries of the target block are loaded from the L2P map table of the flash memory as a target L2P map record set.

Step S304, sequentially adding 1 to the physical addresses contained in all the P2L mapping entries of the target block, respectively calculating the physical addresses contained in all the P2L mapping entries of the target block and the corresponding logical addresses thereof, so as to obtain a P2L mapping record corresponding to the current calculation and delete the P2L mapping record obtained by the previous calculation when each calculation is performed, and comparing the P2L mapping record with the L2P mapping record with the same logical address in the target L2P mapping record set when each calculation is performed, and if both points to the same physical address, indicating that the page pointed by the physical address is valid data, generating a moving operation.

As shown in fig. 3, the logical address 0x00001100 points to a physical address of 0x00000200 in the L2P mapping table and the P2L mapping table, indicating that the page pointed to by the physical address is valid data, and a move operation is generated.

In step S305, when the valid data in the target block has been moved to the new address, an erase operation is performed to complete garbage collection of the target block.

While logical address 0x00001103 points to physical address 0x00004012 in the L2P mapping table, the physical address pointed to in the P2L mapping table is calculated to be 0x00000203, indicating that the page pointed to by the physical address is invalid data, and an erase operation is performed.

In the above example, compared with the prior art that an identifier for identifying whether the current physical address is valid needs to be set in the P2L, the present embodiment of the present invention needs to maintain the identifier every time data is written, and the scheme provided by the present embodiment does not need to maintain the identifier, thereby reducing resource overhead. Compared with the P2L and L2P mapping table structures in the prior art, when garbage collection is performed, 128 mapping entries need to be loaded into the memory (i.e. DRAM) of the storage device, and space corresponding to 256 mapping entries need to be allocated in the memory, in this embodiment, only 128L 2P mapping entries and 2P 2L mapping entries need to be loaded into the memory, then each time a new P2L mapping entry is generated in the memory in a computing manner, and when a P2L mapping record corresponding to a current computation is obtained in each computing, the P2L mapping record obtained in the previous computing is deleted, so that less memory resources are occupied when garbage collection is performed. Meanwhile, since the P2L mapping table needs to be read from the flash memory during garbage collection, in the prior art, one mapping entry of the P2L mapping table corresponds to one mapping record, and a plurality of P2L mapping records are scattered in different pages, the multiple P2L mapping records may need to be read from the multiple pages during garbage collection of a block, and each time the flash memory is read, the read interference phenomenon is caused, compared with the read interference of a large range (i.e. more pages) caused during garbage collection in the prior art, in this embodiment, only fewer pages need to be read, and the read interference influence range is reduced.

In a second aspect, a storage device is provided, comprising a flash memory, a processor and a computer program stored on the flash memory and executable on the processor, the processor implementing the steps in a P2L data management method of a storage device as described above when the computer program is executed.

The inventive concept of this embodiment is the same as that of the method embodiment, and is not described here in detail.

In a third aspect, a computer readable storage medium is provided, on which a computer program is stored which, when executed by a processor, implements the steps of a P2L data management method of a storage device as described above.

The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.

Claims (10)

1. A method for P2L data management of a storage device, the method comprising:

when writing data, dividing the data according to page units, sequentially writing the data into blocks with a plurality of continuous free pages in a flash memory according to the sequence from low logical addresses to high logical addresses, and generating one to a plurality of P2L mapping entries according to one P2L mapping record corresponding to each stored page of data; if no cross-block write occurs during the write, the P2L mapping records are contiguous and can be consolidated into a set of 2 adjacent P2L mapping entries; if the cross-block writing is generated during writing, the P2L mapping records corresponding to the data stored in the same block are continuous, and all the corresponding P2L mapping records can be combined into a group of 2 adjacent P2L mapping entries; thus, if a cross-block store is generated and distributed across S blocks when writing a data page, 2S or 2S-1P 2L mapping entries are generated altogether, and a P2L mapping table is established based on the P2L mapping entries;

Each P2L mapping entry only comprises a physical address and logic mapping data, wherein the number of bytes occupied by the physical address and the logic mapping data is the same;

for a P2L mapping entry consisting of only 1P 2L mapping record, the logic mapping data is a logic address corresponding to a physical address for indicating the P2L mapping entry;

for each set of 2 adjacent P2L map entries that are merged from multiple P2L map records:

the physical addresses of the adjacent 2P 2L mapping entries in the same group are the same;

the logic mapping data of the first P2L mapping entry in the same group is used for indicating the minimum logic address in a plurality of P2L mapping records of the group;

the logical mapping data of the second P2L mapping entry in the same group is the number data of the plurality of P2L mapping records for indicating the combination.

2. The method for P2L data management of a storage device according to claim 1, wherein a top N bits of the number data are preset flag symbols, a number of bits of the number data other than the top N bits are used to indicate a number of P2L mapping records in which the combination is located, and N is a natural number.

3. The method for P2L data management of a storage device according to claim 2, further comprising:

When writing data, skipping the logic address range with the highest N bits in the logic address being the same as the preset sign.

4. The method for P2L data management of a storage device according to claim 2, further comprising a process of calculating a logical address corresponding to the target physical address from the P2L mapping table, wherein the process specifically comprises:

retrieving the P2L mapping table, wherein when the target physical address can be directly retrieved from the physical addresses of the P2L mapping entries, the logical address corresponding to the physical address of the P2L mapping entry is used as the logical address corresponding to the target physical address;

retrieving the P2L mapping table, and comparing the target physical address with the physical address range represented by each mapping entry to judge whether the target physical address PAA falls in the physical address range represented by a certain group of 2 adjacent P2L mapping entries under the condition that the target physical address cannot be directly retrieved from the physical addresses of the P2L mapping entries;

for a group of 2 adjacent P2L mapping entries with the number N of a certain combined plurality of P2L mapping records, the physical address PAA1 stored in the first P2L mapping entry is LAA1, and when PAA > PAA1 and PAA < = paa1+n-1, the calculation method of the logical address LAA corresponding to the target physical address PAA indicates that the target physical address hits the group of 2 adjacent P2L mapping entries in the P2L mapping table is: laa=laa1+paa-PAA 1, and addressing of the logical address can be completed through calculation.

5. The method for P2L data management of a storage device according to claim 4, wherein when performing garbage collection operations, the method further comprises:

acquiring a block head physical address of a target block; the target block is a block needing garbage recovery;

acquiring all P2L mapping entries which belong to the same target block as the block head physical address in a P2L mapping table;

calculating each physical address and the corresponding logical address contained in each P2L mapping entry from all P2L mapping entries belonging to a target block with the block head physical address so as to recover all P2L mapping records of the block and serve as a target P2L mapping record set;

loading L2P mapping records corresponding to all logical addresses corresponding to the target P2L mapping record set from an L2P mapping table in the flash memory into a memory to be used as the target L2P mapping record set;

comparing the P2L mapping record and the L2P mapping record with the same logical address in the target P2L mapping record set and the target L2P mapping record set, and generating a moving operation if the P2L mapping record and the L2P mapping record point to the same physical address, which indicates that the page pointed to by the physical address is valid data;

and after the valid data in the target block are all moved to the new address, executing an erasing operation to complete garbage collection of the target block.

6. The method for P2L data management of a storage device according to claim 5, wherein when performing garbage collection operations, the method further comprises:

acquiring a block head physical address of a target block; the target block is a block needing garbage recovery;

acquiring all P2L mapping entries which belong to the same target block as the block head physical address in a P2L mapping table;

when detecting that all P2L mapping entries belonging to the same target block only comprise 2 adjacent P2L mapping entries belonging to the same group, and indicating that the number of the combined P2L mapping records is equal to the number of pages of the target block according to logic mapping data of a second P2L mapping entry in the 2 adjacent P2L mapping entries of the group, loading L2P mapping records corresponding to all logic addresses contained in all P2L mapping entries of the target block from an L2P mapping table in a flash memory to a memory as a target L2P mapping record set;

sequentially adding 1 to physical addresses contained in all P2L mapping entries of a target block, respectively calculating physical addresses contained in all P2L mapping entries of the target block and corresponding logical addresses thereof, so as to obtain a P2L mapping record corresponding to the current calculation and delete the P2L mapping record obtained by the previous calculation when each calculation is performed, and comparing the P2L mapping record with L2P mapping records with the same logical addresses in a target L2P mapping record set when each calculation is performed, and generating a moving operation if the two mapping records point to the same physical addresses, wherein the page pointed by the physical address is valid data;

And after the valid data in the target block are all moved to the new address, executing an erasing operation to complete garbage collection of the target block.

7. The method of P2L data management for a storage device of claim 1, further comprising:

when writing data, if the number of pages of the written data is N, the number of continuous free pages in a block with a plurality of continuous free pages in a storage device is M, and when N is more than M, the data needs to be stored in a cross-block mode, namely the rest data pages are required to be written into other blocks with a plurality of continuous free pages in sequence from low to high according to logic addresses until all the data pages are written into the storage device;

if the data page is written into the data page, the block-crossing storage is generated, the logic mapping data of the second P2L mapping entry in each group of 2 adjacent P2L mapping entries indicates the number of the P2L mapping records in which the combination is located, namely the number of the data page stored in the corresponding block.

8. The method for P2L data management of a storage device according to claim 1, wherein:

each group of adjacent 2P 2L mapping entries stores a plurality of continuous P2L mapping records; if one P2L map record MPRec1 with physical address PAA being P, its logical address LAA being L, if the other P2L map record MPRec2 with physical address PAA being p+1, its logical address LAA being l+1, the P2L map records MPRec1 and MPRec2 are consecutive, if the other P2L map record MPRec3 with physical address PAA being p+2, its logical address LAA being l+2, the P2L map records MPRec1, MPRec2 and MPRec3 are consecutive, and so on, there are N P2L map records with the values of physical addresses PAA increasing continuously from low to high by P, P +1, p+2, …, p+n-1, the values of physical addresses recorded in adjacent P2L map records differ by 1, and the values of logical addresses LAA also increasing continuously from low to high by L, L +1, l+2, …, l+n-1, i.e. the values of adjacent P2L map records differ by 1.

9. A storage device comprising a flash memory, a processor and a computer program stored on the flash memory and executable on the processor, the processor implementing the steps of a P2L data management method of a storage device according to any one of claims 1 to 8 when the computer program is executed by the processor.

10. A computer readable storage medium, on which a computer program is stored, characterized in that the computer program, when being executed by a processor, implements the steps of a P2L data management method of a storage device according to any of claims 1 to 8.