CN107066393A - The method for improving map information density in address mapping table - Google Patents
The method for improving map information density in address mapping table Download PDFInfo
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- CN107066393A CN107066393A CN201710022698.0A CN201710022698A CN107066393A CN 107066393 A CN107066393 A CN 107066393A CN 201710022698 A CN201710022698 A CN 201710022698A CN 107066393 A CN107066393 A CN 107066393A
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
- G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
- G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
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- G—PHYSICS
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- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
- G06F12/1009—Address translation using page tables, e.g. page table structures
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/72—Details relating to flash memory management
- G06F2212/7201—Logical to physical mapping or translation of blocks or pages
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Abstract
The invention discloses a kind of method for improving map information density in address mapping table, the hit rate that mapping table is cached in the page mapping scheme based on caching part map information can be improved, improve the readwrite performance of flash translation layer (FTL), do not increasing in the caching mapping table in internal memory on the premise of list item quantity, will be all continuous in logical address and physical address, adjacent map record merges one map entry of generation, such map entry can represent multiple logical addresses to the mapping relations between physical address, being a rule map entry and be no longer that a rule can only represent a logical address to the map record of mapping relations between physical address in insertion caching mapping table, the map record quantity stored with this in increase caching mapping table on the premise of not increasing caching mapping table to the occupancy of internal memory, the hit rate of caching mapping table can be dramatically increased, improve the read-write efficiency of flash translation layer (FTL), it can be widely applied to the management of the NAND flash storages of various systems.
Description
Technical field
The present invention relates to map information density in technical field of data storage, more particularly to a kind of raising address mapping table
Method.
Background technology
NAND Flash be it is a kind of there is non-volatile semiconductor memory, will not because power-off and caused by loss be stored in
Data above is lost, because mechanical part is not present in the inside of NAND flash storages, therefore with low in energy consumption, heating
The advantage that traditional mechanical disk memory do not have such as small, lightweight, size is small, antidetonation is good, its random read-write performance is even more
Far above traditional mechanical disk memory.With the breakthrough of flash memory storage capacity bottleneck, under the optimization of performance and cost
Drop, NAND flash storages have changed into very important digital storage media.
NAND Flash are made up of many pieces (Block), and each block is made up of some pages (Page) again, and wherein page is reading
According to the least unit for writing data, block be erasing least unit.When write operation is carried out to NAND Flash, first have to
The block at this page of place is wiped, otherwise write operation can not be carried out to the page.Therefore flash memory has three kinds of basic operations：Read,
Write, wipe.
NAND Flash three kinds of operations have different performance, and preferably, write performance takes second place the performance of reading, wipes performance
It is worst.Read operation it is fastest, read a page and take around time of tens microseconds, write operation speed is slower than reading behaviour
Make, one page of write-in takes around the time of hundreds of microseconds, and erasing operation then takes very much, one block of erasing is about needed
Want several milliseconds of times.
The erasing times of NAND Flash block are all limited, once having exceeded its maximum erasing times, are stored in
Data above may become unreliable.
During the data stored in some page for updating NAND Flash, it is necessary to first using erasing operation by this page of place
Block is wiped, and erasing is the operation of Millisecond, and the write operation relative to Microsecond grade is an operation extremely taken, therefore such as
Fruit is same by the way of local update (In-Place Update), can seriously reduce the writing rate of flash memory.If in addition, certain
Data on block can cause the block to be rapidly reached its operating limit because constantly being wiped by continually local update.Therefore, exist
In actual use, when NAND Flash are updated the data using strange land update (Out-Place Update) by the way of, it is all more
New data will not be written in original page, but is re-write in the page (free page) being wiped free of to other.NAND
Flash storage resource is the allocation manager in the way of page number is physical address, as valid data are in NAND
The upper storage locations of Flash change, the mapping relations of logic to physics can not possibly by set up expression formula calculate obtain, it is necessary to
Addressing of the file system to data is provided by setting up mapping table.Therefore, introduce flash translation layer (FTL) and reflect (Flash
Translation Layer, FTL), by FTL realize Address Mapping to record logical address and data actual storage
Physical address between mapping relations turn into current main flow flash memory management scheme.
In order to realize that immediate addressing, mapping table are referred to as caching mapping table among being typically partly or entirely buffered in internal memory,
How can reduce caching mapping table the occupancy of internal memory can be allowed again request can by cache mapping table completion direct addressin be
The problem of flash translation layer (FTL) needs to solve.
According to the difference of address mapping granule, it can will set up caching mapping table method and be divided into four kinds：Page mapping (Page
Mapping), block mapping (Blocking Mapping), mixed-use developments (Hybrid Mapping), based on caching part mapping letter
The page mapping (Cached Page Mapping) of breath.
Page mapping is that address of cache is carried out in units of page, the mapping table based on page is preserved in internal memory, each logic
Page has a corresponding Physical Page, it is necessary to be kept in the mapping table with a map record, and a map record exists
A mapping item is taken in mapping table, the flexibility of page mapping method is high, but due to needing to set up address for each logical page (LPAGE)
Mapping item, causes mapping table committed memory big.
Block mapping is then that the address offset carried out in units of block in address of cache, logical block is kept with physical block bias internal
Unanimously.Than page map table, mapping table committed memory very little, but it has the disadvantage poor-performing, one when handling small data renewal
The renewal of small block data can cause the duplication to whole block content.
Comprehensive page mapping and the advantage and disadvantage that block maps produce mixed-use developments mechanism, and mixed-use developments are by the block on NAND Flash
Functionally it is divided into data block and log blocks, log blocks are less.When to be updated to the data in some data block, new number
According to log blocks can be write, when the quantity of all log blocks is less than certain value, it is necessary to which the data in log blocks and data block are entered
Row merges, and this operation can cause performance to be decreased obviously.
Page mapping scheme based on the caching part map information in internal memory is the improvement mapped page, this mapping mode
Using multiple pages of storage complete map tables on NAND Flash, this page is referred to as mapping table memory page, warp is cached in internal memory
Normal requested map record, cache size is fixed, that is, the quantity for caching the mapping item in mapping table is provided with the upper limit, can deposit
The map record quantity of storage is identical with the quantity of mapping item, it is ensured that caching mapping table EMS memory occupation will not be excessive.Work as read-write
Request is come, if corresponding map record does not hit caching mapping table not in caching, is then read from NAND Flash
Take map record, when caching mapping table in map record quantity when the maximum limit is reached, reflecting for access will be not used at most
Record is penetrated to swap out from caching, if the map record that is removed for it is dirty just record, i.e., the logic that the map record is stored to thing
The mapping relations of reason page have occurred that change in the buffer, then need in the mapping table that is written back in NAND Flash.Mapping
The reading of record and swapping out result in the additional read-write to NAND Flash.
In summary, page mapping is flexibly and performance is best, and mixed-use developments are poor, and block mapping performance is worst.And be based on
The page mapping scheme of caching part map information will not produce union operation, therefore its performance is higher than mixed-use developments, and page maps
The similar nature of mode.But it is due to that caching mapping table can only store limited map record, causes component requests not hit
Caching mapping table can not complete direct addressin and need to carry out map record exchange with the mapping table in NAND Flash, so as to produce
Having given birth to unsolicited cause to read on NAND Flash the additional read operation of mapping table and map record is written into NAND Flash
On additional write operation, map record write-in NAND Flash can be also produced because of the additional refuse recovery that free block is not enough and produces
Operation.These are additional to wipe and ultimately results in its performance and map low than page, and hit rate is lower, and performance is poorer.Therefore how not increase
Plus on the premise of EMS memory occupation, more mapping items are cached in caching mapping table, that is, improve caching mapping table storage density
It is the difficult point that the page mapping scheme based on caching part map information needs emphasis to solve to improve hit rate.
The content of the invention
It is an object of the invention to provide a kind of method for improving map information density in address mapping table, caching can be improved
Map record density in mapping table, reaches the purpose for the readwrite performance for improving FTL.
The purpose of the present invention is achieved through the following technical solutions：
A kind of method of map information density in raising address mapping table, including：
By page it is that unit is split by data when writing data, then by the order of logical address from low to high by number
According to having in write-in memory successively in the block of multiple continuous free pages, each page data after storage corresponds to a mapping note
Record, then arrive a plurality of map entry according to these map records generation one；
When reading data, read request address is split by page for unit, and the caching mapping in retrieval internal memory one by one
Table, if the logical address of certain one page does not hit the caching mapping table in internal memory, reading is used for storage mapping in memory
The mapping table memory page of table, obtains required target map record from mapping table memory page；While, also in the mapping table
The map record on searched targets map record periphery in memory page, by qualified periphery map record by merging generation one
Bar map entry, retrieving is as follows：Read mapping table memory page content, i.e. mapping table fragment, then using target map record as
The starting point mapping table fragment of both direction retrieval forwards, backwards, if finding that adjacent map record B reflects with target in some direction
The logical address values and physical address values for penetrating record all differ 1, then by starting point of adjacent map record B to same direction after
Continuous retrieval mapping table, until two adjacent map records are no longer continuous, although or continuous being already present on caching mapping
Untill table, or retrieve first in mapping table memory page or the last item map record；
Data will be write with reading during data, the caching mapping table that the map entry generated is inserted in the internal memory.
When writing data, if the number of pages of data is write for N, in the block in memory with multiple continuous free pages
Continuous free time number of pages is M, and N>During M, then need across block storage, that is, need remaining data page by logical address from low to high
Order data are write successively in the block that other have multiple continuous free pages, until all data pages are written into memory
In；
If generating S across block storage during write-in data page, S map entry, each map entry are generated altogether
In the data of map record that include be institute's data storage page in relevant block quantity.
The map entry stores several continuous map records；If a logical address LBA remembers for L mapping
MPRec1 is recorded, its physical address PBA is P, if an other logical address LBA is L+1 map record MPRec2, it is physically
Location PBA is P+1, then map record MPRec1 and MPRec2 are continuous, if an other logical address LBA maps for L+2
MPRec3 is recorded, its physical address PBA is P+2, then map record MPRec1, MPRec2 and MPRec3 is continuous, with such
Push away, there is a N bar map records, its logical address LBA value from low to high according to L, L+1, L+2 ..., L+N-1 continuously increase,
Neighbor mapping record in record logical address value difference 1, and its physical address PBA value be also be from low to high according to P,
P+1, P+2 ..., P+N-1 continuously increase, neighbor mapping record in record physical address value difference 1, such N bars reflect
It is continuous map record to penetrate record.
Map entry is in the continuous N bars map record, with the logic in minimum logical address that map record
Address and physical address and a length value N and a dirty flag bit composition；
In byte number wherein shared by the logical address and physical address of map entry, and corresponding map record logically
Location is identical with the byte number shared by physical address, using in addition with a byte come memory length value N and dirty flag bit, dirty mark
Whether the highest order of the will bit occupancy byte, be modified, such as identity map entry within the life cycle of caching mapping table
Fruit is changed, and is entered as 1, and otherwise value is 0；The length value of entry is stored in 0 to 7 of the byte.
The caching mapping table that map entry is inserted in the internal memory includes：
If the existing entry in map entry and caching mapping table is produced because having what is occured simultaneously and occur in logical address
Conflict, then need that correlation map entry is decomposed and reconfigured；
If the existing entry in map entry and caching mapping table is continuous, need to carry out correlation map entry
Merge again.
After map entry inserts the caching mapping table in the internal memory, if the read request hit mapping bar received
Mesh, then directly calculate corresponding physical address, and its step includes：
Retrieval caching mapping table, compares the logical address LBA in read request and the logical address represented by each map entry
Scope judges whether the LBA falls in the ranges of logical addresses represented by certain map record；
For the map entry that some length is N, wherein the logical address stored is LBA1, physical address is PBA1, when
LBA>=LBA1, and LBA<=LBA1+N-1, then it represents that the logical address included in request has been hit in caching mapping table
The computational methods of the corresponding physical address PBA of logical address LBA in map entry, read request are：PBA=PBA1+LBA-
LBA1, the addressing to physical address can be completed by calculating.
As seen from the above technical solution provided by the invention, corresponding map record is generated according to read-write operation and inserted
Enter to cache mapping table, map record density in caching mapping table can be improved on the premise of more memory sources are not take up, from
And increase map record quantity in caching mapping table, improve caching mapping table hit rate.
Brief description of the drawings
In order to illustrate the technical solution of the embodiments of the present invention more clearly, being used required in being described below to embodiment
Accompanying drawing be briefly described, it should be apparent that, drawings in the following description are only some embodiments of the present invention, for this
For the those of ordinary skill in field, on the premise of not paying creative work, other can also be obtained according to these accompanying drawings
Accompanying drawing.
Fig. 1 is a kind of flow for improving the method for map information density in address mapping table provided in an embodiment of the present invention
Figure；
Fig. 2 reflects when inserting the caching mapping table in internal memory for the map entry of generation provided in an embodiment of the present invention to correlation
Penetrate the schematic diagram that entry is decomposed and reconfigured；
Fig. 3 reflects when inserting the caching mapping table in internal memory for the map entry of generation provided in an embodiment of the present invention to correlation
Penetrate the schematic diagram that entry is merged；
Fig. 4 reflects when inserting the caching mapping table in internal memory for the map entry of generation provided in an embodiment of the present invention to correlation
Penetrate the schematic diagram that entry is merged.
Embodiment
With reference to the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete
Ground is described, it is clear that described embodiment is only a part of embodiment of the invention, rather than whole embodiments.Based on this
The embodiment of invention, the every other implementation that those of ordinary skill in the art are obtained under the premise of creative work is not made
Example, belongs to protection scope of the present invention.
The embodiment of the present invention provides a kind of method for improving map information density in address mapping table, as shown in figure 1, it is led
Including：
1st, judge whether map record adjacent in multiple logical addresses can be merged into the condition of map entry
In the embodiment of the present invention, when writing data with reading data, qualified multiple map records can be closed
And into map entry, several continuous map records are stored in the map entry of generation；Specifically, if a logic
Address LBA is L map record MPRec1, and its physical address PBA is P, if an other logical address LBA maps for L+1
MPRec2 is recorded, its physical address PBA is P+1, then map record MPRec1 and MPRec2 are continuous, if other one is patrolled
Volume address LBA is L+2 map record MPRec3, and its physical address PBA is P+2, then map record MPRec1, MPRec2 and
MPRec3 is continuous, by that analogy, has N bar map records, its logical address LBA value is according to L, L+1, L+ from low to high
2nd ..., L+N-1 continuously increases, the value difference 1 of the logical address recorded in neighbor mapping record, and its physical address PBA
Value be also from low to high according to P, P+1, P+2 ..., P+N-1 continuously increase, the physical address that records in neighbor mapping record
Value difference 1, such N bars map record is continuous map record, and such N bars map record can be merged into one and reflect
Penetrate entry.
For continuous N bars map record, map entry can be merged into：Every map entry is mapped by the continuous N bars
There are three parts such as minimum that map record of logical address, length value N and dirty flag bit to constitute in record；Wherein length
Value N and dirty flag bit are stored in same byte, the highest order of the dirty mark bit occupancy byte, for identifying the mapping bar
Whether mesh is modified within the life cycle of caching mapping table, and " 1 " is then entered as in the event of change, and otherwise value is " 0 ", bar
Purpose length value N is stored in 0 to 7 of the byte.
2nd, when writing data, data are split by page for unit, then will by the order of logical address from low to high
Data write in memory (NAND Flash) in the block with multiple continuous free pages successively, and each page data after storage is equal
One map record of correspondence, can arrive a plurality of map entry by these continuous map record generations one.
When writing data, if the number of pages of data is write for N, in the block in memory with multiple continuous free pages
Continuous free time number of pages is M, and N>During M, then need across block storage, that is, need remaining data page by logical address from low to high
Order data are write successively in the block that other have multiple continuous free pages, until all data pages are written into memory
In.
It will be understood by those skilled in the art that write data when, be equally using page as unit write-in block in, page in block
Write sequence can only be sequentially written in from low address page to high address page and be unable to random writing, therefore the low data quilt of logical address
The low page of physical address is write, a logical address is produced to the map record of physical address, the low data quilt of logical address time
The low page of physical address time is write, a logical address is produced to the map record of physical address, until the data quilt of this request
All write-in is completed；If the free page in ablation process in this free block is all fully written and this request still has partial page
Data, which are not written to NAND Flash, then needs across block write-in data, that is, distributing a new free block is used to write in write request
Data, likewise, the data that the order of data write-in is still low logic address write the page of low physical address, produce one
Logical address is to the map record of physical address, and logical address time low data are written into the low page of physical address time, produce one
Map record of the bar logical address to physical address.So repeatedly, until all data are written into NAND Flash in write request
In.
Therefore write request generates N bar map records, if not producing across block write-in during write-in, this N bar mapping note
Record is continuous.Therefore this N bars map record can be merged into 1 map entry, and entry length is N.
If generating across block write-in during write-in, the corresponding M bars map record of the data being stored in same piece is
Continuously, therefore this M bars map record can be merged into 1 map entry, entry length is M.If produced during write-in data page
S across block storage is given birth to, then the data for generating the map record included in S bar map entrys, each map entry altogether are
In relevant block because this request write data page quantity.
3rd, when reading data, read request address scope is split by page for unit, and it is slow in retrieval internal memory one by one
Mapping table is deposited, if the logical address of certain one page does not hit the caching mapping table in internal memory, the mapping in memory is read
Table, is referred to as mapping table memory page for preserving the Hash memory pages of mapping table.Required data are obtained by reading mapping table memory page
Logical address and physical address mapping relations, i.e. target map record；After the content of mapping table memory page is read, at this
The map record on searched targets map record periphery, map entry is merged into by the continuous map record in periphery in content, is examined
Rope process is as follows：Read out the content of mapping table memory page, i.e. mapping table fragment first, then, using target map record as rise
Both direction retrieves the mapping table fragment to point forwards, backwards, if finding that adjacent map record B remembers with mapping in some direction
The logical address values of record all differ 1 with physical address values, then continue to examine to same direction by starting point of adjacent map record B
Rope mapping table.Retrieving the condition stopped is：A) two adjacent map records no longer continuous (i.e. logical address values and physical address
No longer all it is difference 1 in value)；B) first map record in the mapping table fragment has been retrieved；C) retrieved
Last map record in the mapping table fragment；Although d) running into mapping note that is continuous but being already present on caching mapping table
Record.
4th, the caching mapping table that map entry of the data with reading to be generated during data is inserted in the internal memory will be write.
In the embodiment of the present invention, the caching mapping table for also inserting the map entry of generation in internal memory is asked with making full use of
The spatial locality and temporal locality asked, improve FTL read-write efficiency.Always according to tool during map entry insertion caching mapping table
Body situation uses the following two kinds Different treatments：
If one or more existing entries are produced because in logical address in the map entry being inserted into and caching mapping table
Spatially there is common factor, then need that correlation map entry is decomposed and reconfigured, two logical address space coincidence systems have
It is a variety of, it is necessary to be handled respectively according to different situations.Exemplary, it is that one kind therein is decomposed and reconfigured shown in Fig. 2
Method：Logic when map entry insertion caching mapping table of the logic first address for 1136 in the entry and caching mapping table
First address has common factor, it is necessary to be reconfigured for 1135 map entry on logical address space, and 3 are produced after combination newly
The entry stored on-site that map entry, wherein logic first address are 1135 is in caching mapping table, and other two entries are now located
In free state, if now having more than two empty list items in caching mapping table, bar can be mapped by two of free state
Mesh is inserted directly into caching mapping table.If caching the hollow list item of mapping table is less than two, needs to swap out first and do not visit at most
The map entry asked, then by the new entry insertion caching mapping table of free state.
If the existing entry in map entry and caching mapping table is continuous, need to carry out correlation map entry
Merge again.Exemplary, such as Fig. 3, can be with delaying when logic first address is the map entry insertion caching that 1132, length is 3
Deposit the entry that middle logic first address is 1135 to merge, merge and produce new map entry, new mappings entry logic first address
It is respectively 1132 and 517 with physics first address, map entry length is changed into 7.As shown in figure 4, logic first address is 1139, length
Can be that the map entry that 1135 length are 4 merges with the first address in caching, after merging when inserting caching for 3 map entry
Map entry still in-stiu encapsulation is in the buffer.
In the embodiment of the present invention, the method to calculate target map record is additionally provided by map entry：
If some map entry of request hit caching mapping table, can directly calculate corresponding physical address, its
Step includes：Retrieval caching mapping table, compares the logical address LBA in read request and the logical address represented by each map entry
Scope judges whether the LBA falls in the ranges of logical addresses represented by certain map record；For some length reflecting for N
Entry is penetrated, wherein the logical address stored is LBA1, physical address is PBA1, works as LBA>=LBA1, and LBA<=LBA1+N-1,
Then represent that the logical address included in request has hit the logical address in the map entry in caching mapping table, read request
The corresponding physical address PBA of LBA computational methods are：PBA=PBA1+LBA-LBA1, can be completed to physically by calculating
The addressing of location.
The such scheme of the embodiment of the present invention, can improve the hit rate of caching mapping table, improve FTL readwrite performance,
The present invention is not increasing in the caching mapping table in internal memory on the premise of list item quantity, and continuous map record is closed
And map entry is produced, so each map entry can represent multiple logical addresses to the mapping relations between physical address,
Cache being a rule map entry and being no longer that a rule can only represent a logic for each list item memory storage in mapping table
Address increases the map record number stored in caching mapping table with this to the map record of mapping relations between physical address
Amount, can dramatically increase the hit rate of caching mapping table, continuously be reflected in multiple logical addresses simultaneously as map entry can be expressed
Record is penetrated, can be improved the efficiency of FTL read-write effectively using the spatial locality of request, can be widely applied to various systems
NAND flash storages management.
Through the above description of the embodiments, those skilled in the art can be understood that above-described embodiment can
To be realized by software, the mode of necessary general hardware platform can also be added to realize by software.Understood based on such,
The technical scheme of above-described embodiment can be embodied in the form of software product, the software product can be stored in one it is non-easily
The property lost storage medium (can be CD-ROM, USB flash disk, mobile hard disk etc.) in, including some instructions are to cause a computer to set
Standby (can be personal computer, server, or network equipment etc.) performs the method described in each embodiment of the invention.
The foregoing is only a preferred embodiment of the present invention, but protection scope of the present invention be not limited thereto,
Any one skilled in the art is in the technical scope of present disclosure, the change or replacement that can be readily occurred in,
It should all be included within the scope of the present invention.Therefore, protection scope of the present invention should be with the protection model of claims
Enclose and be defined.
Claims (6)
1. a kind of method for improving map information density in address mapping table, it is characterised in that including：
Write data when, by data by page be unit split, then by the order of logical address from low to high by data according to
In secondary write-in memory in the block with multiple continuous free pages, each page data after storage corresponds to a map record,
A plurality of map entry is then arrived according to these map records generation one；
When reading data, read request address is split by page for unit, and the caching mapping table in retrieval internal memory one by one, such as
Really the logical address of certain one page does not hit the caching mapping table in internal memory, then reading is used for reflecting for memory map assignments in memory
Firing table memory page, obtains required target map record from mapping table memory page；While, also in the mapping table memory page
The map record on middle searched targets map record periphery, by qualified periphery map record by merging one mapping of generation
Entry, retrieving is as follows：Read mapping table memory page content, i.e. mapping table fragment, then by starting point of target map record to
Mapping table fragment is retrieved in former and later two directions, if finding adjacent map record B and target map record in some direction
Logical address values all differ 1 with physical address values, then continue to retrieve to same direction by starting point of adjacent map record B
Mapping table, until two adjacent map records are no longer continuous, although or it is continuous be already present on caching mapping table untill,
Or retrieve first in mapping table memory page or the last item map record；
Data will be write with reading during data, the caching mapping table that the map entry generated is inserted in the internal memory.
2. a kind of method for improving map information density in address mapping table according to claim 1, it is characterised in that
When writing data, if writing the number of pages of data for N, there is the continuous free page in the block of multiple continuous free pages in memory
Quantity is M, and N>During M, then across block storage is needed, that is, need remaining data page by logical address order from low to high by number
According to writing successively in the block that other have multiple continuous free pages, until all data pages are written into memory；
If generating S across block storage during write-in data page, generate in S map entry, each map entry and wrap altogether
The data of the map record contained are the quantity of institute's data storage page in relevant block.
3. a kind of method for improving map information density in address mapping table according to claim 1 or 2, its feature exists
In the map entry stores several continuous map records；If the map record that a logical address LBA is L
MPRec1, its physical address PBA are P, if an other logical address LBA is L+1 map record MPRec2, its physical address
PBA is P+1, then map record MPRec1 and MPRec2 are continuous, if an other logical address LBA, which is L+2, maps note
Record MPRec3, its physical address PBA be P+2, then map record MPRec1, MPRec2 and MPRec3 be it is continuous, by that analogy,
Have a N bar map records, its logical address LBA value from low to high according to L, L+1, L+2 ..., L+N-1 continuously increase, phase
The value difference 1 of the logical address recorded in adjacent map record, and it is according to P, P+ from low to high that its physical address PBA value, which is also,
1st, P+2 ..., P+N-1 continuously increase, the value difference 1 of the physical address recorded in neighbor mapping record, the mapping of such N bars
Record is continuous map record.
4. a kind of method for improving map information density in address mapping table according to claim 3, it is characterised in that reflect
Entry is penetrated in the continuous N bars map record, with the logical address and physics in minimum logical address that map record
Address and a length value N and a dirty flag bit composition；
Logical address in byte number wherein shared by the logical address and physical address of map entry, and corresponding map record and
Byte number shared by physical address is identical, using in addition with a byte come memory length value N and dirty flag bit, dirty flag bit
The highest order of the byte is taken, whether is modified within the life cycle of caching mapping table for identity map entry, if hair
Change is given birth to and has then been entered as 1, otherwise value is 0；The length value of entry is stored in 0 to 7 of the byte.
5. a kind of method for improving map information density in address mapping table according to claim 1, it is characterised in that will
The caching mapping table that map entry is inserted in the internal memory includes：
If the existing entry in map entry and caching mapping table is produced because there is the conflict occured simultaneously and occurred in logical address,
Then need that correlation map entry is decomposed and reconfigured；
If the existing entry in map entry and caching mapping table is continuous, need to carry out again correlation map entry
Merge.
6. a kind of method for improving map information density in address mapping table according to claim 1, it is characterised in that when
Map entry is inserted after the caching mapping table in the internal memory, if the read request hit map entry received, is directly counted
Corresponding physical address is calculated, its step includes：
Retrieval caching mapping table, compares the logical address LBA in read request and the ranges of logical addresses represented by each map entry
To judge whether the LBA falls in the ranges of logical addresses represented by certain map record；
For the map entry that some length is N, wherein the logical address stored is LBA1, physical address is PBA1, works as LBA>
=LBA1, and LBA<=LBA1+N-1, then it represents that the logical address included in request has hit the mapping in caching mapping table
The computational methods of the corresponding physical address PBA of logical address LBA in entry, read request are：PBA=PBA1+LBA-LBA1, leads to
The addressing to physical address can be completed by crossing calculating.
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