CN113590503A

CN113590503A - Garbage recovery method and garbage recovery system for non-volatile memory

Info

Publication number: CN113590503A
Application number: CN202110839169.6A
Authority: CN
Inventors: 赵啟鹏
Original assignee: Hefei Kangxinwei Storage Technology Co Ltd
Current assignee: Hefei Kangxinwei Storage Technology Co Ltd
Priority date: 2021-07-23
Filing date: 2021-07-23
Publication date: 2021-11-02
Anticipated expiration: 2041-07-23
Also published as: CN113590503B

Abstract

The invention provides a garbage recycling method and a garbage recycling system of a non-volatile memory, comprising the following steps: determining a source storage block and a target storage block; transferring the effective data in the source storage block to the target storage block, and acquiring an error physical address in the transfer process; obtaining a corresponding error logical address in a first mapping table according to the error physical address; obtaining a corresponding entry in a second mapping table according to the error logical address, and updating a physical address in the entry into a virtual value; when the host sends a read request to the nonvolatile memory, judging whether the read request hits the virtual value; if yes, sending an error signal to the host; if not, continuing to carry out the read request. The garbage collection method and the garbage collection system of the non-volatile memory provided by the invention can prolong the service life of the non-volatile memory.

Description

Garbage recovery method and garbage recovery system for non-volatile memory

Technical Field

The present invention relates to the field of storage technologies, and in particular, to a garbage collection method and a garbage collection system for a non-volatile memory.

Background

At present, most of the non-volatile memory memories use flash memory chips as storage media. A flash memory chip is a non-volatile memory whose basic memory cell is a floating gate transistor due to physical characteristics such as charge leakage and oxide layer aging. The data needs to be encoded before being written into the flash memory array, and the data needs to be decoded after being read out from the flash memory array. Due to the physical properties of flash memory itself, a data bit flipping phenomenon occurs when reading data from a flash memory array. When the bit number of the overturned bit is larger, the read data can make an error, and the main control can start the error correction module to correct the error. When the error correction module of the main control cannot successfully correct the error, the firmware is required to perform corresponding error processing. Since the host will report errors when reading data from the non-volatile memory, and garbage collection only operates inside the non-volatile memory, if the garbage collection reads errors and sends error status to the host, it will have a great influence on the service life of the non-volatile memory.

Disclosure of Invention

In view of the above-mentioned defects of the prior art, the present invention provides a garbage collection method and a garbage collection system for a non-volatile memory, by which the number of times of sending an error signal to a host when a garbage collection read error occurs can be reduced, and the service life of the non-volatile memory can be prolonged.

To achieve the above and other objects, the present invention provides a garbage collection method for a non-volatile memory, comprising:

determining a source storage block and a target storage block;

transferring the effective data in the source storage block to the target storage block, and acquiring an error physical address in the transfer process;

obtaining a corresponding error logical address in a first mapping table according to the error physical address;

obtaining a corresponding entry in a second mapping table according to the error logical address, and updating a physical address in the entry into a virtual value;

when the host sends a read request to the nonvolatile memory, judging whether the read request hits the virtual value;

if yes, sending an error signal to the host;

if not, continuing to carry out the read request.

Further, the second mapping table is a mapping table from a host logical address to a storage block physical address, and the first mapping table is a mapping table from a storage block physical address to a host logical address.

Further, the step of determining whether the read request hits the dummy value comprises:

acquiring a logic address in the read request;

obtaining corresponding entries in the second mapping table according to the logical addresses;

judging whether the physical address in the entry is a virtual value;

if so, the read request hits the virtual value;

if not, the read request does not hit the virtual value.

Further, when the host sends a write request to the non-volatile memory, and a logical address in the write request hits the wrong logical address, the corresponding entry is obtained in the second mapping table according to the logical address, and the virtual value in the entry is updated to a physical address corresponding to the logical address.

Further, the step of obtaining the wrong physical address in the transfer process comprises:

determining the valid data of the source memory block;

and performing a transfer operation, and defining the physical address of the memory block as the error physical address when the determined valid data is converted into the non-determined valid data in the transfer process.

Further, after all the valid data in the source storage block are transferred to the target storage block, the source storage block is erased.

Furthermore, the present invention further provides a garbage recycling system for a non-volatile memory, comprising:

the storage block determining module is used for determining a source storage block and a target storage block;

the error physical address counting module is used for acquiring an error physical address in the transfer process when the effective data in the source storage block is transferred to the target storage block;

a read error processing module, configured to obtain a corresponding error logical address in a first mapping table according to the error physical address; obtaining a corresponding entry in a second mapping table according to the error logical address, and updating a physical address in the entry into a virtual value;

the command judgment module is used for judging whether the read request hits the virtual value or not when the host sends the read request to the nonvolatile memory; if yes, sending an error signal to the host; if not, continuing to carry out the read request.

Further, the storage block determination module is configured to determine the source storage block from a plurality of storage blocks that are full of data, and determine the target storage block from a plurality of the storage blocks that are free.

Further, when the host sends a write request to the non-volatile memory, the command determining module is further configured to determine whether a logical address in the write request hits the erroneous logical address, and if so, obtain the corresponding entry in the second mapping table according to the logical address, and update the virtual value in the entry to the physical address corresponding to the logical address; if not, continuing to carry out the write request.

Further, when the host sends a read request to the nonvolatile memory, the command determining module obtains a logical address in the read request, and obtains a corresponding entry in the second mapping table according to the logical address, and when the physical address in the entry is a virtual value, the read request hits the virtual value.

In summary, the present invention provides a garbage collection method and a garbage collection system for a non-volatile memory, when performing garbage collection, first determining a source storage block and a target storage block, and then performing garbage collection operation, that is, transferring valid data in the source storage block to the target storage block, and obtaining an erroneous physical address occurring in the transfer process; then obtaining a corresponding error address in a first mapping table according to the error physical address, then obtaining a corresponding entry in a second mapping table according to the error logical address, updating the physical address in the entry into a virtual value, and judging whether the read request hits the virtual value when the host sends the read request to the nonvolatile memory; if yes, an error signal is sent to the host, and if not, the reading request is continued. The invention can reduce the read-out error condition of the non-volatile memory at the garbage recovery stage, namely, reduce the read-out error times or delay the error reporting of the non-volatile memory, thereby prolonging the service life of the non-volatile memory.

Drawings

FIG. 1: block diagram of a storage system in the present invention.

FIG. 2: the present invention is a system block diagram of a NAND-type flash memory.

FIG. 3: the invention discloses a system block diagram of a NAND memory chip.

FIG. 4: the invention relates to a block diagram of a memory cell array.

FIG. 5: the present invention is a composition diagram of a storage system.

FIG. 6: the structure of the system controller is shown schematically.

FIG. 7: the structure of the memory is shown schematically.

FIG. 8: the invention discloses a structural schematic diagram of a garbage recycling system of a non-volatile memory.

FIG. 9: the invention discloses a structural schematic diagram of a source storage block and a target storage block.

FIG. 10: the invention discloses a flow chart of a garbage collection method of a nonvolatile memory.

FIG. 11: the step S1 is shown in the present invention.

FIG. 12: the invention discloses a structure diagram of a first mapping table.

FIG. 13: the structure of the second mapping table is shown in the invention.

FIG. 14: the structure of the wrong physical address in the invention is shown schematically.

FIG. 15: the invention discloses a structural diagram of updating a virtual value in a write request into a latest physical address.

FIG. 16: the invention relates to a flow chart for judging whether a read request hits a virtual value.

FIG. 17: another flow chart of the garbage collection method of the non-volatile memory in the invention.

FIG. 18: the state of the k bit of the host logical address is shown in the invention.

FIG. 19: the structure of the storage system is shown schematically.

Detailed Description

The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.

It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.

The system described herein includes a novel architecture for controlling a mass storage module that includes flash memory chips. The entire system is shown in a highly schematic form in fig. 1. As with the other block diagrams herein, the elements shown in FIG. 1 are conceptual in nature, illustrating the nature of the interrelationship between these functional blocks and are not intended to represent an actual physical circuit level implementation.

As shown in fig. 1, the present embodiment proposes a memory system including a nonvolatile semiconductor memory device. The nonvolatile semiconductor memory device is a nonvolatile memory (non-transitory memory) that does not lose data even when power is turned off, and in this embodiment, the NAND flash memory 120 is illustrated as an example of the nonvolatile semiconductor memory device. In addition, as a memory system, a nonvolatile memory device (SSD) including a NAND flash memory is exemplified.

As shown in FIG. 1, the nonvolatile memory 100 is connected to a host device 170 (e.g., an information processing device) via an interface 171 and a power line 172. The host device 170 is configured by, for example, a personal computer, a CPU core, a server connected to a network, or the like. The host device 170 performs data access control on the nonvolatile memory 100, for example, by sending a write request, a read request, and an erase request to the nonvolatile memory 100, and performs data write, read, and erase on the nonvolatile memory 100.

As shown in fig. 1, the nonvolatile memory 100 includes an SSD controller (storage device control unit) 110, a NAND flash memory 120, an interface controller (interface unit) 130, and a power supply unit 140. The SSD controller 110, the interface controller 130, and the NAND-type flash memory 120 are connected to each other by a bus 150.

As shown in fig. 1, the power supply unit 140 is connected to the host device 170 via a power line 172, and receives external power supplied from the host device 170. The power supply unit 140 and the NAND-type flash memory 120 are connected by a power line 161, the power supply unit 140 and the SSD controller 110 are connected by a power line 162, and the power supply unit 140 and the interface controller 130 are connected by a power line 163. The power supply unit 140 boosts and lowers the voltage of the external power supply, generates various voltages, and supplies the voltages to the SSD controller 110, the NAND flash memory 120, and the interface controller 130.

As shown in fig. 1, the interface controller 130 is connected to the host device 170 via the interface 171. The interface controller 130 performs an interface process with the host device 170. As the interface 171, SATA (Serial Advanced Technology a ttachment: Serial Advanced Technology attachment), PCI Express (Peripheral Component Interconnect Express), SAS (Serial Attached SCSI), USB (Universal Serial Bus), or the like can be employed. In one embodiment, the interface 171 is described by using an example of SATA.

As shown in fig. 1, the NAND-type flash memory 120 nonvolatilely stores data. In the physical address space of the NAND-type flash memory 120, an FW area 121 for storing Firmware (FW), a management information area 122 for storing management information, a user area 123 for storing user data, and a filter log area 125 for storing various logs at the time of, for example, a test procedure are secured.

As shown in fig. 1, the SSD controller 110 controls various operations of the nonvolatile memory 100. The SSD controller 110 can realize its functions by a processor, various hardware circuits, and the like that execute firmware stored in the FW area 121 of the NAND-type flash memory 120, and executes data transfer control between the NAND-type flash memory 120 and the host device 170 for various commands such as a write request, a cache refresh request, and a read request from the host device 170, update and management of various management tables stored in the RAM111 and the NAND-type flash memory 120, and filtering processing. The SSD controller 110 receives power from the power supply line 172, reads out firmware from the FW area 121, and performs processing in accordance with the read firmware. The SSD controller 110 has a RAM111 as a buffer area and an operation area, and an ECC (Error Checking and Correcting) circuit 112.

As shown in fig. 1, the RAM111 is composed of a volatile RAM such as a DRAM (Dynamic Random Access Memory) or an SRAM (Static Random Access Memory), or a nonvolatile RAM such as an MRAM (Magnetoresistive Random Access Memory), a FeRAM (Ferroelectric Random Access Memory), a RAM (resistive Random Access Memory), or a PRAM (Phase-change Random Access Memory).

As shown in fig. 1, the ECC circuit 112 generates an error correction code for write data at the time of data writing, adds the error correction code to the write data, and transmits the write data to the NAND-type flash memory 120. In addition, the ECC circuit 112 performs error detection (error bit detection) and error correction on read data by using an error correction code included in the read data at the time of data reading. For ECC encoding and ECC decryption of the ECC circuit 112, for example, a Bose-Chaudhuri-Hocquenghem (BCH) code, a Reed-Solomon (RS) code, and a Low-Density Parity-check (LDPC) code are used. The circuit 112 may also be a Cyclic Redundancy Check (CRC) circuit 112 that uses a CRC code to detect errors.

As shown in fig. 2 to 3, fig. 2 is a system block diagram of the NAND-type flash memory 120, and fig. 3 is a system block diagram of the NAND memory chip 200, and the NAND-type flash memory 120 includes more than one NAND memory chip 200.

As shown in fig. 3, the memory cell array 202 is configured by arranging memory cells in a matrix form, in which data can be electrically rewritten. A plurality of bit lines, a plurality of word lines, and a common source line are arranged in the memory cell array 202. Memory cells are arranged in the intersection regions of bit lines and word lines.

As shown in fig. 3, a word line control circuit 205 as a row decoder is connected to a plurality of word lines, and selects and drives the word lines when data is read, written, and erased. The bit line control circuit 203 is connected to a plurality of bit lines, and controls voltages of the bit lines at the time of reading, writing, and erasing of data. The bit line control circuit 203 detects data on the bit line at the time of data reading, and applies a voltage corresponding to the write data to the bit line at the time of data writing. The column decoder 204 generates a column selection signal for selecting a bit line in accordance with an address, and transmits the column selection signal to the bit line control circuit 203.

As shown in fig. 3, read data read from the memory cell array 202 is output to the outside from the data input/output terminal 208 via the bit line control circuit 203 and the data input/output buffer 209. Further, write data inputted from the outside to the data input/output terminal 208 is inputted to the bit line control circuit 203 via the data input/output buffer 209.

As shown in fig. 3, the memory cell array 202, the bit line control circuit 203, the column decoder 204, the data input/output buffer 209, and the word line control circuit 205 are connected to the control circuit 206. The control circuit 206 generates control signals and control voltages for controlling the memory cell array 202, the bit line control circuit 203, the column decoder 204, the data input/output buffer 209, and the word line control circuit 205, based on a control signal input from the outside to the control signal input terminal 207. The NAND memory chip 200 is called a memory cell array control unit (NAND controller) 201 together with a portion other than the memory cell array 202.

As shown in fig. 4, fig. 4 is a block diagram showing the structure of the memory cell array 202. The memory cell array 202 has one or more planes (or partitions). The memory cell array 202 in fig. 4 includes, for example, 2 planes (plane 0 and plane 1). Each plane has a plurality of BLOCKs (BLOCK), each BLOCK (BLOCK) is composed of a plurality of memory cells, and data is erased in units of the BLOCK (BLOCK).

As shown in fig. 5, the present embodiment provides a block diagram of another storage system 30, the storage system 300 including at least one controller 310 and a plurality of memories 320. The controller 310 is connected to a host (not shown) through a Storage Area Network (SAN). The controller 310 may be a computing device such as a server, desktop computer, etc. An operating system and an application program are installed on the controller 310. The controller 310 may receive an input output (I/O) request from a host. The controller 310 may also store data carried in the I/O request (if any) and write the data to the memory 320. The memory 320 may be a non-volatile memory. The non-volatile memory is a memory using a flash memory (flash memory) chip as a medium, and is also called a Solid State Drive (SSD).

Fig. 5 is an exemplary illustration only, and in practical applications, the storage system may include two or more controllers, each of which has a similar physical structure and function as the controller 310, and the present embodiment does not limit the connection manner between the controllers and between any one of the controllers and the memory 320. As long as the respective controllers, and the respective controllers and the memory 320 can communicate with each other.

As shown in fig. 6, fig. 6 is a diagram illustrating an exemplary configuration of controller 310, and controller 310 includes an interface card 311, a processor 313, and an interface card 314. The interface card 311 is used to communicate with a host, and the controller 310 may receive an operation instruction of the host through the interface card 311. Processor 313 may be a Central Processing Unit (CPU). In an embodiment of the present invention, the processor 313 may be configured to receive an I/O request from a host and process the I/O request. The I/O request may be a write data request or a read data request, and the processor 313 may also send data in the write data request to the memory 320. Processor 313 may also be used to perform system garbage collection operations. Interface card 314 is used to communicate with memory 320, and controller 310 may send a write data request (including data and a lifecycle level of the data) through interface card 314 to memory 320 for storage.

As shown in fig. 6, in the present embodiment, the controller 310 may further include a memory 312. The memory 312 is used to temporarily store data received from the host or data read from the memory 320. When the controller 310 receives a plurality of write data requests transmitted by the host, data in the plurality of write data requests may be temporarily stored in the memory 312. When the capacity of the memory 312 reaches a certain threshold, the data stored by the memory 312 and the logical address allocated for the data are sent to the memory 320. The memory 320 stores the data. The memory 312 includes volatile memory, flash memory chips, or a combination thereof. Volatile memory is, for example, random-access memory (RAM). The flash memory chip may be a variety of machine-readable media that can store program codes, such as a floppy disk, a hard disk, a nonvolatile memory (SSD), and an optical disk. The memory 312 has a power-saving function, which means that when the system is powered off and powered on again, the data stored in the memory 312 will not be lost.

As shown in fig. 6, in the present embodiment, the controller 310 is responsible for identifying the life cycle of the data and dividing the data of different life cycles into several levels. In this embodiment, the data life cycle is related to the modification frequency of the data, and the shorter the data life cycle with the higher modification frequency, the longer the data life cycle with the lower modification frequency. Such as log writes that are large but are quickly deleted (the retention time in non-volatile memory storage may be only a few minutes), such data is divided into a first level of life cycle. Metadata, which is stored in the non-volatile memory for a slightly longer time than the journal, can be divided into a second level of life cycle. And hot data in the traffic data may be divided into a third level of lifecycle and cold data in the traffic data may be divided into a fourth level of lifecycle. Of course, the embodiment of the present invention does not limit the number of the lifecycle levels, and may only include two levels of lifecycle, or may include three or more levels of lifecycle. Specifically, the controller 310 may preset one or more lifecycle thresholds, and compare the lifecycle of the data to the lifecycle thresholds to determine the lifecycle level to which the data pertains. For example, a first life cycle threshold, a second life cycle threshold, and a third life cycle threshold are preset, wherein the second life cycle threshold is higher than the first life cycle threshold, and the third life cycle threshold is higher than the second life cycle threshold. The data belongs to a first level of lifecycle when its lifecycle is equal to or below a first lifecycle threshold, the data belongs to a second level of lifecycle when its lifecycle is between the first lifecycle threshold and a second lifecycle threshold, the data belongs to a third level of lifecycle when its lifecycle is between the second lifecycle threshold and a third lifecycle threshold, the data belongs to a fourth level of lifecycle when its lifecycle is above the third lifecycle threshold.

As shown in fig. 6, after identifying the lifecycle level of the data, the controller 310 transfers the identified lifecycle level to the memory 320 in the NVMe protocol in the form of a parameter, so that the memory 320 determines the lifecycle level according to the parameter of the lifecycle, and allocates flash memory blocks of different data storage modes for the data of different lifecycle levels.

As shown in fig. 6, it should be noted that the controller 310 belongs to a system controller, and the system controller is a separate device, different from the control chip in the non-volatile memory. The control chip of the non-volatile memory is referred to as a flash memory controller in this embodiment.

As shown in fig. 7, fig. 7 is a schematic structural diagram of the memory 320. The memory 320 includes a control unit 321 and a plurality of flash memory arrays 322. The control unit 321 is used for performing operations such as a write data request or a read data request sent by the controller 310.

As shown in fig. 7, the control unit 321 includes a Flash Translation Layer (FTL). The flash translation layer is used for storing the corresponding relation between the logical address and the actual address of the data. Therefore, the flash translation layer is used for converting the logical address in the write data request or the read data request sent by the system controller into the actual address of the data in the nonvolatile memory. The logical address of the data is assigned by the system controller, a subset of the logical address intervals of a segment. The logical address of the data includes a start logical address indicating a position of the segment where the data is located and a length representing a size of the data. The actual address of the data may be the physical address of the data in the non-volatile memory, or may be an address that is virtualized on the basis of the physical address and is only visible to the flash memory controller. The virtualized real address is not visible to the system controller.

As shown in fig. 7, memory 320 typically includes one or more flash memory arrays 322. Each flash array 322 includes a number of flash blocks. Memory 320 is read or written on a page (page) basis, but an erase operation can only be on a flash block basis, an erase operation meaning that all bits of the block are set to "1". Before erasing, the flash controller needs to copy the valid data in this flash block to the blank pages of another block. Valid data in a flash block refers to unmodified data stored in the block, which may be read. Invalid data in a flash block refers to data stored in the block that has been modified, and this part of the data cannot be read.

As shown in FIG. 7, each flash block contains multiple pages (pages). The memory 320 writes data in units of pages when executing a write data request. For example, the controller 310 sends a write data request to the control unit 321. The write data request includes a logical address of data. The control unit 321, after receiving the write data request, successively writes the data into one or more flash blocks in the order of time of reception. The continuous writing of one or more flash memory blocks means that the control unit 321 searches for a blank flash memory block, writes data into the blank flash memory block until the blank flash memory block is filled, and when the size of the data exceeds the capacity of the flash memory block, the control unit 321 searches for the next blank flash memory block again and continues writing. And the flash translation layer establishes and stores the corresponding relation between the logical address and the actual address of the page written with the data. When the controller 310 sends a read data request to the control unit 321, requesting to read the data, the logical address is included in the read data request. The control unit 321 reads the data according to the logical address and the corresponding relationship between the logical address and the actual address, and sends the data to the controller 310.

As shown in fig. 7, a memory cell (cell) is the minimum unit of operation of a page, and one memory cell corresponds to one floating gate transistor, which can store 1 bit (bit) or more bits of data, depending on the type of flash memory. Memory cells on a page share a word line. The memory cell includes a control gate and a floating gate, which is a cell that actually stores data. Data is stored in the memory cell in the form of an electrical charge (electric charge). How much charge is stored depends on the voltage applied to the control gate, which controls whether charge is pushed into or released from the floating gate. And the representation of the data is represented by whether the voltage of the stored charge exceeds a particular threshold. Writing data to the floating gate is accomplished by applying a voltage to the control gate such that sufficient charge is stored in the floating gate above a threshold value, indicating a 0. An erase operation on a flash memory is to discharge the floating gate so that the charge stored in the floating gate is below the threshold, indicating a 1.

As shown in fig. 8-9, the present embodiment further provides a garbage collection system 400 for a non-volatile memory, wherein the garbage collection system 400 may include a memory block determination module 401, an error physical address statistics module 402, a read error processing module 403, and a command determination module 404. Memory block determination module 401 may be used to determine source memory block 405 and target memory block 406. Memory block determination module 401 may determine source memory block 405 from a plurality of memory blocks storing data, that is, source memory block 405 includes valid data and invalid data, for example, source memory block 405 includes one valid data, and other data are all invalid data (filling area). The memory block determination module 401 may also determine a target memory block 406 from the plurality of memory blocks that are free. When the source storage block 405 and the target storage block 406 are determined, a garbage collection operation may be performed, that is, valid data in the source storage block 405 is transferred to the target storage block 406.

As shown in fig. 10, the present embodiment further provides a garbage collection method for a non-volatile memory, including:

s1: determining a source storage block and a target storage block;

s2: transferring the effective data in the source storage block to the target storage block, and acquiring an error physical address in the transfer process;

s3: obtaining a corresponding error logical address in a first mapping table according to the error physical address;

s4: obtaining a corresponding entry in a second mapping table according to the error logical address, and updating a physical address in the entry into a virtual value;

s5: is the host issue a new request to the non-volatile memory storage?

S6: if yes, determine that the host sent a read request?

S7: if yes, determine if the read request hits a dummy value?

S8: if yes, an error signal is sent to the host.

As shown in fig. 8 and 11, in steps S1-S2, after determining the source storage block 405 and the target storage block 406, the valid data in the source storage block 405 is transferred to the target storage block 406, and during the transfer, when a garbage collection read error occurs, an error physical address can be obtained by the error physical address statistics module 402, for example, as shown in fig. 11, the valid data in the source storage block 405 is "4", during the data transfer, the valid data in the target storage block 406 becomes "5", that is, during the data transfer, the data is in error, so the physical address of the source storage block 405 can be defined as the error physical address.

As shown in fig. 8 and fig. 12 to 14, after obtaining the erroneous physical address, the erroneous logical address may be obtained according to the first mapping table in steps S3 to S4. The first mapping table may be a memory block physical address to host logical address mapping table, and the first mapping table may include a plurality of entries (entries), each of which may be a combination of a memory block physical address and a host logical address. The size of the first mapping table may be 4KB/8KB/16KB/32 KB. The size of the entry may be 4 KB. Each entry stores a host logical address, and the storage block physical address is an index, so that the host logical address can be obtained after the storage block physical address is known. When the error physical address is obtained, the host logical address corresponding to the error physical address can be obtained, and the host logical address is defined as the error logical address. After obtaining the erroneous logical address, an entry (entry) corresponding to the erroneous logical address is then obtained according to the second mapping table. The second mapping table may be a host logical address to storage block physical address mapping table, and the combination of the host logical address and the storage block physical address may be an entry in the second mapping table. The size of the second mapping table may be 4KB/8KB/16KB/32 KB. The size of the entry may be 4 KB. The storage block physical address is stored in the second mapping table, and the host logical address is an index, so that after the host logical address is obtained, an entry corresponding to the host logical address can be found in the second mapping table, and the storage block physical address corresponding to the host logical address is obtained. As can be seen from fig. 14, the erroneous logical address corresponds to entry0 in the second mapping table, and thus the memory block physical address in this entry0 can be updated to a virtual value. The dummy value may act as a tag, and when a subsequent read request hits the dummy value, an error signal may be sent to the host.

As shown in FIG. 8, FIG. 10 and FIG. 15, in steps S5-S7, after a physical address in the second mapping table is updated to a virtual value, the command determination module 404 determines whether the host sends a new request to the non-volatile memory. If the host does not send a new request to the non-volatile memory, step S51 is performed to continue the garbage collection operation. When the host sends a new request to the non-volatile memory, step S6 is performed to further determine whether the request sent by the host is a read request, and if the request sent by the host is not a read request, step S61 is performed to perform a write request. If the request sent by the host is a read request, then step S7 is performed to determine whether the read request hits the virtual value, and if the read request does not hit the virtual value, step S71 is performed to continue the host read request. If the read request hits the virtual value, an error signal is sent to the host. In step S61, in the process of performing the write request, if the logical address in the write request hits in the wrong logical address, the corresponding entry is obtained according to the second mapping table, and the virtual value in the entry is updated to the physical address corresponding to the logical address, as can be seen from fig. 15, the wrong logical address corresponds to entry0 in the second mapping table, so the virtual value in entry0 is updated to the latest physical address. It should be noted that the command determining module 404 may also perform a command executing operation.

As shown in fig. 16, the step of determining whether the read request hits the virtual value in step S7 includes:

s711: acquiring a logic address in the read request;

s712: obtaining corresponding entries in the second mapping table according to the logical addresses;

s713: is the physical address in the entry determined to be a virtual value?

S714: if so, the read request hits the virtual value.

S715: if not, the read request does not hit the virtual value.

As shown in fig. 14 and fig. 16, in steps S712-S713, when the logical address corresponds to entry0 in the second mapping table, the physical address of the memory block in entry0 is a virtual value, and then the read request hits the virtual value, and when the logical address corresponds to entry 3 in the second mapping table, the physical address of the memory block in entry 3 is a normal value, then the read request misses the virtual value. When the read request hits the virtual value, an error signal is sent to the host, and when the read request does not hit the virtual value, garbage recycling read processing is continued. The method can delay the sending of the error signal to the host, thereby prolonging the service life of the nonvolatile memory.

As shown in fig. 17, the present embodiment further provides a garbage collection method for a non-volatile memory, including:

s100: determining a source storage block and a target storage block;

s101: transferring the effective data in the source storage block to the target storage block, and acquiring an error physical address in the transfer process;

s102: acquiring a host logical address corresponding to the error physical address in a first mapping table, and updating the state of the kth bit in the host logical address into an error mark state;

s103: updating the content of the first mapping table into a second mapping table;

s104: is the status of the kth bit in the host logical address in the first mapping table determined to be an error flag status?

S105: if yes, acquiring an entry corresponding to the host logical address in the second mapping table, and updating a storage block physical address in the entry to a virtual value;

s106: is it determined that the host sends a new request to the nonvolatile memory storage?

S107: if yes, determine that the host sent a read request?

S108: if yes, determine that the read request hits the dummy value?

S109: if yes, an error signal is sent to the host.

As shown in fig. 8 and fig. 17 to 18, in the present embodiment, steps S100 to S101 may refer to the description of steps S1 to S2 described above. In steps S102-S103, after the erroneous physical address is obtained, a corresponding entry may be obtained in the first mapping table according to the erroneous physical address, and since the entry is a combination of the physical address of the memory block and the host logical address, after the erroneous physical address is obtained, the host logical address corresponding to the erroneous physical address may be obtained in the first mapping table. As can be seen from fig. 18, the erroneous physical address is located in entry 0(entry0), for example, and the state of the k-th bit of the host logical address in entry0 is updated, for example, the state of the k-th bit is updated from "0" to "1", i.e., the state of the k-th bit is updated from the normal flag state to the error flag state. When the second mapping table is updated, the status of the error flag is subsequently updated into the second mapping table, i.e. the contents of the first mapping table can be updated into the second mapping table. In this embodiment, the value of k may be greater than or equal to 30, and k is a positive integer, such as 31 or 32. In the present embodiment, the k-th bit of the host logical address is set to be in the error flag state, and the value of k is relatively large, so that the present embodiment has good versatility and can be applied to a large-capacity nonvolatile memory.

As shown in fig. 8, fig. 14, fig. 15, and fig. 17 to fig. 18, in steps S104 to S105, when updating the second mapping table, it is also necessary to determine that the state of the kth bit in the host logical address in the first mapping table is an error flag state. If the state of the k bit is the error flag state, acquiring an entry of the host logical address corresponding to the second mapping table, and then updating the physical address of the storage block in the entry to a virtual value. For example, the state of the k-th bit of the host logical address in entry0 of the first mapping table is an error flag state, then entry0 corresponding to the host logical address may be obtained in the second mapping table, and the physical address of the memory block in entry0 is updated to a virtual value. If the state of the k bit is a normal flag state, acquiring the corresponding physical address of the storage block of the host logical address in the first mapping table, and then physically updating the storage block to the entry of the host logical address in the second mapping table, that is, replacing the original storage block address with the latest physical address of the storage block. It should be noted that steps S102 to S105 can be processed by the read error processing module 403 and the command judging module 404. When a garbage collection read error occurs in the garbage collection process, the frequency of garbage collection in a read-write memory array (Nand flash) when the read error is processed can be reduced on the premise of ensuring the normal operation of the nonvolatile memory, so that the efficiency of the nonvolatile memory for processing the garbage collection read error can be improved, and the performance of the nonvolatile memory can be improved.

As shown in fig. 10 and 17, in the present embodiment, steps S106 to S109 may refer to steps S5 to S8, and the present embodiment is not explained.

As shown in fig. 19, the present embodiment also provides a storage system 500, and the storage system 500 may include a host 510 and a data saving system 520 that communicates commands and/or data with the host 510 via an interface 511. Storage system 500 may be implemented as a Personal Computer (PC), workstation, data center, internet data center, storage area network, Network Attached Storage (NAS), or mobile computing device, although the inventive concepts are not limited to these examples. The mobile computing device may be implemented as a laptop computer, a cellular phone, a smart phone, a tablet PC, a Personal Digital Assistant (PDA), an Enterprise Digital Assistant (EDA), a digital still camera, a digital video camera, a Portable Multimedia Player (PMP), a personal navigation device or Portable Navigation Device (PND), a handheld game console, a Mobile Internet Device (MID), a wearable computer, an internet of things (IoT) device, an internet of things (IoE) device, a drone, or an electronic book, although the inventive concepts are not limited to these examples.

As shown in fig. 19, the interface 511 may be a Serial Advanced Technology Attachment (SATA) interface, a SATA express (SATA ae) interface, a SAS (serial attached Small Computer System Interface (SCSI)), a peripheral component interconnect express (PCIe) interface, a non-volatile memory express (NVMe) interface, an Advanced Host Controller Interface (AHCI), or a multimedia card (MMC) interface, but is not limited thereto. The interface 511 may transmit an electrical signal or an optical signal. Host 510 may control data processing operations (e.g., write operations or read operations) of data retention system 520 via interface 511. Host 510 may refer to a host controller.

As shown in fig. 19, data retention system 520 may be, but is not limited to, a flash-based memory device. The data saving system 520 may be implemented as SSD, embedded SSD (essd), universal flash memory (UFS), MMC, embedded MMC (emmc), or managed NAND, but the inventive concept is not limited to these examples. A flash-based memory device may include an array of memory cells. The memory cell array may include a plurality of memory cells. The memory cell array may include a two-dimensional memory cell array or a three-dimensional memory cell array. A three-dimensional memory cell array may be monolithically formed at one or more physical levels in a memory cell array having an active region disposed on or above a silicon substrate, and may include circuitry involved in the operation of the memory cells. The circuitry may be formed in, on, or over a silicon substrate. The term "monolithic" means that the layers of each level in the array are deposited directly on the layers of the lower levels in the array. A three-dimensional memory cell array can include vertical NAND strings oriented vertically such that at least one memory cell is placed on or over another memory cell. The at least one memory cell may include a charge trapping layer.

As shown in FIG. 19, a data retention system 520 may include a control unit 321 and a storage array 420, where the control unit 321 may control a host 510. Commands and/or data may be transferred or processed between control unit 321 and memory array 420. The garbage collection method of the data saving system 520 can refer to the above description.

The above description is only a preferred embodiment of the present application and a description of the applied technical principle, and it should be understood by those skilled in the art that the scope of the present invention related to the present application is not limited to the technical solution of the specific combination of the above technical features, and also covers other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the inventive concept, for example, the technical solutions formed by mutually replacing the above features with (but not limited to) technical features having similar functions disclosed in the present application.

Other technical features than those described in the specification are known to those skilled in the art, and are not described herein in detail in order to highlight the innovative features of the present invention.

Claims

1. A garbage collection method for a non-volatile memory is characterized by comprising the following steps:

determining a source storage block and a target storage block;

if yes, sending an error signal to the host;

if not, continuing to carry out the read request.

2. A method as claimed in claim 1, wherein the second mapping table is a mapping table from host logical address to memory block physical address, and the first mapping table is a mapping table from memory block physical address to host logical address.

3. A method as claimed in claim 1, wherein the step of determining whether the read request hits the dummy value comprises:

acquiring a logic address in the read request;

judging whether the physical address in the entry is a virtual value;

if so, the read request hits the virtual value;

if not, the read request does not hit the virtual value.

4. The method as claimed in claim 1, wherein when the host sends a write request to the nonvolatile memory and a logical address in the write request hits the erroneous logical address, the corresponding entry in the second mapping table is obtained according to the logical address, and the virtual value in the entry is updated to a physical address corresponding to the logical address.

5. A method as claimed in claim 1, wherein the step of obtaining the erroneous physical address during the transfer process comprises:

determining the valid data of the source memory block;

6. A method as claimed in claim 1, wherein when all the valid data in the source block is transferred to the target block, the source block is erased.

7. A garbage collection system for a non-volatile memory, comprising:

8. A garbage collection system for non-volatile memory as claimed in claim 7, wherein said memory block determination module is configured to determine said source memory block from a plurality of memory blocks which are full of data and said target memory block from a plurality of said memory blocks which are free.

9. The system of claim 7, wherein when the host sends a write request to the nonvolatile memory, the command determining module is further configured to determine whether a logical address in the write request hits the erroneous logical address, and if so, obtain the corresponding entry in the second mapping table according to the logical address, and update the virtual value in the entry to the physical address corresponding to the logical address; if not, continuing to carry out the write request.

10. The garbage collection system of claim 7, wherein when the host sends a read request to the nonvolatile memory, the command determination module obtains a logical address in the read request, and obtains a corresponding entry in the second mapping table according to the logical address, and when the physical address in the entry is a virtual value, the read request hits the virtual value.