CN117153831A - Flash memory chip and control method - Google Patents

Flash memory chip and control method Download PDF

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Publication number
CN117153831A
CN117153831A CN202311252293.8A CN202311252293A CN117153831A CN 117153831 A CN117153831 A CN 117153831A CN 202311252293 A CN202311252293 A CN 202311252293A CN 117153831 A CN117153831 A CN 117153831A
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Prior art keywords
command
flash memory
state machine
access command
chip
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Granted
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CN202311252293.8A
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CN117153831B (en
Inventor
刘长辉
蔡磊
陈强
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Hunan Rongchuang Microelectronic Co ltd
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Hunan Rongchuang Microelectronic Co ltd
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Priority to CN202311252293.8A priority Critical patent/CN117153831B/en
Priority claimed from CN202311252293.8A external-priority patent/CN117153831B/en
Publication of CN117153831A publication Critical patent/CN117153831A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B80/00—Assemblies of multiple devices comprising at least one memory device covered by this subclass

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Geometry (AREA)
  • Read Only Memory (AREA)

Abstract

The application is applicable to the technical field of chips and provides a flash memory chip and a control method. The flash memory chip includes: a plurality of flash memory bare chips are stacked, and an insulating medium layer is arranged between every two adjacent flash memory bare chips; the multiple flash memory bare chips are connected through pins with the same functions, have different bare chip identifiers, and operate in parallel. The application can enlarge the storage capacity of the flash memory chip under the condition of meeting the packaging area requirement of a single bare chip so as to meet the requirement.

Description

Flash memory chip and control method
Technical Field
The present application relates to the field of chip technologies, and in particular, to a flash memory chip and a control method thereof.
Background
With the rapid development of modern computer technology, the requirement of large capacity of Flash memory (Flash) chips is multiplied, the performance requirement is also improved, and the complexity of design is improved exponentially; the rapid increase of the cost of the flow chip, the extension of the cycle of the flow chip and the limitation of the packaging area of the single die make it impossible to expand the storage capacity of the flash memory chip by means of single-chip redesign.
Disclosure of Invention
The embodiment of the application provides a flash memory chip and a control method, which can solve the problem that the storage capacity of the flash memory chip is difficult to meet the requirement due to the limitation of the packaging area of a single bare chip.
In a first aspect, an embodiment of the present application provides a flash memory chip, including:
the device comprises a plurality of stacked flash memory bare chips, wherein an insulating medium layer is arranged between every two adjacent flash memory bare chips in the plurality of flash memory bare chips;
the pins with the same functions in all pins of the multiple flash memory bare chips are connected, the multiple flash memory bare chips have different bare chip identifiers, and state machines of the multiple flash memory bare chips run in parallel.
In a second aspect, an embodiment of the present application provides a control method of a flash memory chip, where the control method includes:
the state machine receives an access command;
the state machine identifies the access command;
if the identification result indicates that the access command is a concurrent command, the state machine executes concurrent operation according to the concurrent command;
if the identification result indicates that the access command is an independent space access command, the state machine responds to the independent space access command according to a command identifier carried by the independent space access command.
Optionally, the state machine identifies the access command, including:
the state machine identifies the command identifier carried by the access command;
if the command identification is the same as the command code of the preset concurrent command, determining that the access command is the concurrent command; otherwise, determining the access command as an independent space access command.
Optionally, the state machine performs the concurrent operation according to the concurrent command, including:
the state machine generates an effective chip select signal according to the concurrent command and executes the concurrent command according to the effective chip select signal.
Optionally, the state machine responds to the independent space access command according to a command identifier carried by the independent space access command, including:
the state machine compares the corresponding bare chip identifier with the command identifier carried by the independent space access command;
if the bare chip identification is the same as the command identification carried by the independent space access command, the state machine generates an effective chip selection signal according to the independent space access command and executes the independent space access command according to the effective chip selection signal;
if the bare chip identification is different from the command identification carried by the independent space access command, the state machine performs invalid execution according to the independent space access command.
The scheme of the application has the following beneficial effects:
in the embodiment of the application, the plurality of flash memory bare chips are stacked and packaged, pins with the same functions are connected together, each flash memory bare chip is provided with the independent different bare chip identifiers, and the state machines of the flash memory bare chips run in parallel, so that the flash memory chip formed by stacking and packaging the plurality of flash memory bare chips can be expanded under the condition of meeting the single bare chip packaging area requirement, and the storage capacity of the flash memory chip can meet the requirement.
Other advantageous effects of the present application will be described in detail in the detailed description section which follows.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments or the description of the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a flash memory chip according to an embodiment of the present application;
FIG. 2 is a top view of a flash memory chip according to an embodiment of the present application;
FIG. 3 is a flowchart illustrating a control method according to an embodiment of the present application;
FIG. 4 is a flow chart of concurrent command access provided by an embodiment of the present application;
FIG. 5 is a flow chart illustrating the access of independent space access commands according to one embodiment of the present application;
fig. 6 is a flowchart of a second control method according to an embodiment of the application.
Detailed Description
In the following description, for purposes of explanation and not limitation, specific details are set forth such as the particular system architecture, techniques, etc., in order to provide a thorough understanding of the embodiments of the present application. It will be apparent, however, to one skilled in the art that the present application may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present application with unnecessary detail.
It should be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It should also be understood that the term "and/or" as used in the present specification and the appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes such combinations.
As used in the present description and the appended claims, the term "if" may be interpreted as "when..once" or "in response to a determination" or "in response to detection" depending on the context. Similarly, the phrase "if a determination" or "if a [ described condition or event ] is detected" may be interpreted in the context of meaning "upon determination" or "in response to determination" or "upon detection of a [ described condition or event ]" or "in response to detection of a [ described condition or event ]".
Furthermore, the terms "first," "second," "third," and the like in the description of the present specification and in the appended claims, are used for distinguishing between descriptions and not necessarily for indicating or implying a relative importance.
Reference in the specification to "one embodiment" or "some embodiments" or the like means that a particular feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the application. Thus, appearances of the phrases "in one embodiment," "in some embodiments," "in other embodiments," and the like in the specification are not necessarily all referring to the same embodiment, but mean "one or more but not all embodiments" unless expressly specified otherwise. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless expressly specified otherwise.
Aiming at the problem that the storage capacity of a flash memory chip is difficult to meet the requirement due to the limitation of the packaging area of a single bare chip, the embodiment of the application provides the flash memory chip, the flash memory chip is formed by stacking and packaging a plurality of flash memory bare chips, pins with the same functions are connected together, each flash memory bare chip is provided with a bare chip identifier which is independent and different, and the state machines of the flash memory bare chips run in parallel, so that the storage capacity of the flash memory chip formed by stacking and packaging the plurality of flash memory bare chips can be expanded under the condition of meeting the requirement of the packaging area of the single bare chip, and the storage capacity of the flash memory chip can meet the requirement.
The flash memory chip provided by the application is exemplified below.
As shown in fig. 1, the flash memory chip provided by the present application includes: and an insulating medium layer is arranged between every two adjacent flash memory bare chips in the plurality of flash memory bare chips. The pins with the same functions in all pins of the multiple flash memory bare chips are connected, the multiple flash memory bare chips have different bare chip identifiers, and state machines of the multiple flash memory bare chips run in parallel.
For example, in fig. 1, a flash memory die 0, a flash memory die 1, a flash memory die 2 and a flash memory die 3 stacked in sequence represent a flash memory die, an insulating medium layer is disposed between every two adjacent flash memory dies, two sides of the stacked multiple flash memory dies are pins of the flash memory chip formed by connecting pins with the same function in all pins, different die identifiers are configured on address pins of each flash memory die, that is, a die identifier configured on an address pin of the flash memory die 0 is 0, a die identifier configured on an address pin of the flash memory die 1 is 1, a die identifier configured on an address pin of the flash memory die 2 is 2, and a die identifier configured on an address pin of the flash memory die 3 is 3.
As shown in fig. 2, the uppermost layer of the flash memory chip is a flash memory bare chip 3, and two sides of the flash memory chip are pins of the flash memory chip formed by connecting pins with the same function in all pins.
It should be noted that, an insulating medium layer is disposed between every two adjacent flash memory dies to prevent the flash memory dies from directly contacting each other, resulting in a short circuit. The insulating dielectric layer may be an insulating dielectric layer composed of a conventional insulating medium such as silicon dioxide, for example. The capacity of the flash memory chip is the superposition of a plurality of flash memory bare chips, and the capacity of an exemplary single flash memory bare chip is 256 bytes, the flash memory chip is formed by superposing N flash memory bare chips, the capacity of the flash memory chip is 256 multiplied by N bytes, after a state machine receives a storage command and executes the storage command, if the capacity of the flash memory bare chip corresponding to the state machine is not free, the next received storage command can be appointed to be executed by other state machines in the flash memory chip.
It is worth mentioning that the capacity of the flash memory chip is expanded through the capacity superposition of the plurality of stacked flash memory bare chips, so that the flash memory chip can be expanded under the condition of meeting the single bare chip packaging area requirement, the capacity expansion cost of the flash memory chip is reduced, and the marketing period of various storage capacity products is greatly shortened.
Next, an exemplary description is given of a control method of the flash memory chip provided by the present application.
The control method can be applied to any state machine of the flash memory chip, as shown in fig. 3, and the control method of the flash memory chip includes the following steps:
in step 31, the state machine receives an access command.
For example, the access command may be sent by a system or a host device accessing the flash memory chip, where the access command may be a command such as single word programming, write cache programming, sector erasing, chip erasing, single word reading, page reading, etc., and the device sends any access command to a state machine, and the state machine receives the access command and performs the next step of processing.
It should be noted that the access commands are divided into two types: all state machines in the flash memory chip are required to generate effective chip selection signals simultaneously, and access commands to be executed are concurrent commands, such as chip erasing commands; the state machine which only needs to meet the preset conditions generates an effective chip select signal and executes the access command, and the access command which is not executed in an invalid way by the state machine which meets the preset conditions is an independent space access command, such as a single word programming command and a write cache programming command.
When the state machine executes the command according to the access command, the effect corresponding to the access command cannot be generated or the result corresponding to the access command cannot be obtained after the command is executed because no effective chip select signal is generated.
In step 32, the state machine identifies the access command.
Specifically, the state machine can recognize the command identifier carried by the access command to recognize the access command.
If the command identifier is the same as the command code of the preset concurrent command, determining that the access command is the concurrent command; otherwise, determining the access command as an independent space access command.
Specifically, the preset command codes for concurrent commands are command codes which are used for representing the types of the commands and are convenient for the state machine to recognize the commands, wherein the command codes are defined for various commands in advance in the state machine.
For example, the command code of the concurrency command preset in the state machine is 01, and if the command identifier carried by the access command is also 01, the access command is determined to be the concurrency command; if the command identification carried by the access command is 10 and is different from the preset command code of the concurrent command, the access command is determined to be an independent space access command.
It should be noted that, the access command is identified, so that the state machine can perform corresponding subsequent operations according to the category of the access command.
If the identification result indicates that the access command is a concurrent command, the state machine executes the concurrent operation according to the concurrent command, step 33.
Specifically, the state machine generates an active chip select signal according to the concurrent command, and executes the concurrent command according to the active chip select signal. For example, if the concurrent instruction indicates chip erasure, all state machines of the flash memory chip perform chip erasure.
It should be noted that the active chip select signal is an internal switch control signal of the flash memory die.
The above steps are exemplified in conjunction with a specific example.
As shown in fig. 4, the access flow of the concurrent command is that the state machine maintains an initial state, after receiving the command of the instruction 1 (i.e., the concurrent command), the state machine executes the flow of the instruction 1, i.e., the state machine performs preparation such as initialization according to the instruction 1, and then executes the operation of the instruction 1 (i.e., the concurrent operation), i.e., the state machine generates a valid chip select signal according to the instruction 1, executes the instruction 1 according to the valid chip select signal, then determines whether the operation of the instruction 1 is finished, if the operation of the instruction 1 is finished, the state machine returns to the initial state, and if the operation of the instruction 1 is not finished, the state machine returns to the step of executing the operation of the instruction 1.
It should be noted that, the concurrent operation of the state machine on the concurrent command can implement the execution of the concurrent command by the flash memory chip.
If the identification result indicates that the access command is an independent space access command, the state machine responds to the independent space access command according to the command identifier carried by the independent space access command, step 34.
In some embodiments of the present application, the specific process of the state machine responding to the independent space access command according to the command identifier carried by the independent space access command is as follows:
the state machine compares the corresponding bare chip identifier with the command identifier carried by the independent space access command;
if the bare chip identification is the same as the command identification carried by the independent space access command, the state machine generates an effective chip selection signal according to the independent space access command and executes the independent space access command according to the effective chip selection signal;
if the bare chip identification is different from the command identification carried by the independent space access command, the state machine performs invalid execution according to the independent space access command.
In some embodiments of the present application, the state machine may compare the corresponding die identifier with the upper two bits of the command identifier carried by the independent space access command, so as to complete the comparison of the die identifier and the command identifier carried by the independent space access command.
The upper two bits of the command identifier carried by the independent space access command are 10, and if the die identifier corresponding to the state machine is also 10, the state machine generates an effective chip selection signal according to the independent space access command and executes the independent space access command according to the effective chip selection signal; if the die identifier corresponding to the state machine is 01 and is different from the upper two bits of the command identifier carried by the independent space access command, the state machine does not generate an effective chip selection signal and performs invalid execution according to the independent space access command. It can be understood that the high order bit number of the command identifier compared with the above can be adjusted according to practical situations, for example, when the die identifier corresponding to the state machine is 100, the high order three bits of the command identifier are compared with the die identifier.
The above steps are exemplified in conjunction with a specific example.
As shown in fig. 5, the access flow of the independent space access command is that the state machine maintains an initial state, after receiving the command of the command 2 (i.e. the independent space access command), it is determined whether the command identifier carried by the command of the command 2 matches with the die identifier, if not, the state machine does not generate the valid chip option of the command 2, if matching, the state machine generates the valid chip option of the command 2, then the state machine executes the flow of the command 2, i.e. the state machine performs preparation work such as initialization according to the command 2, and then performs execution of the command 2, i.e. the state machine executes the command 2 according to the valid chip option signal, or performs invalid execution according to the command 2, then the state machine determines whether the command 2 is ended, if the command 2 is ended, the state machine returns to the initial state, and if the command 2 is not ended, the state machine returns to the step executed by the command 2.
It should be noted that, the state machine performs ineffective execution according to the independent space access command, so as to keep synchronous with the state machine that performs the independent space access command according to the effective chip selection signal inside the flash memory chip, and the response of the state machine to the independent space access command can implement the execution of the independent space access command by the flash memory chip.
The control method of the above-described flash memory chip is exemplarily described below with reference to a specific example.
As shown in fig. 6, the flow of the control method of the flash memory chip is that the state machine keeps an initial state, after receiving the access command, the state machine judges whether the access command is a concurrent command, if yes, the state machine judges that the access command is a concurrent command, then the state machine executes the concurrent flow, then executes the concurrent operation, then judges whether the concurrent operation is finished, if so, the state machine returns to the initial state, and if not, the state machine returns to the step of executing the concurrent operation; if the access command is not the concurrent command, judging the independent space access command, judging whether a command identifier carried by the independent space access command is matched with the bare chip identifier, if so, generating a valid chip selection signal by the state machine, if not, generating no valid chip selection signal by the state machine, executing an independent space access flow by the state machine, executing the independent space access command, judging whether executing the independent space access command is finished, if so, returning to an initial state by the state machine, and if not, returning to the step of executing the independent space access command by the state machine.
It is worth mentioning that providing a control method for the flash memory chip can realize effective control of the flash memory chip.
In the foregoing embodiments, the descriptions of the embodiments are emphasized, and in part, not described or illustrated in any particular embodiment, reference is made to the related descriptions of other embodiments.
While the foregoing is directed to the preferred embodiments of the present application, it will be appreciated by those skilled in the art that various modifications and adaptations can be made without departing from the principles of the present application, and such modifications and adaptations are intended to be comprehended within the scope of the present application.

Claims (5)

1. A flash memory chip, comprising:
a plurality of stacked flash memory bare chips, wherein an insulating medium layer is arranged between every two adjacent flash memory bare chips in the plurality of flash memory bare chips;
the pins with the same functions in all pins of the multiple flash memory bare chips are connected, the multiple flash memory bare chips have different bare chip identifications, and state machines of the multiple flash memory bare chips run in parallel.
2. A control method of a flash memory chip, applied to any one of the state machines of the flash memory chip of claim 1, the control method comprising:
the state machine receives an access command;
the state machine identifies the access command;
if the identification result indicates that the access command is a concurrent command, the state machine executes concurrent operation according to the concurrent command;
and if the identification result indicates that the access command is an independent space access command, the state machine responds to the independent space access command according to a command identifier carried by the independent space access command.
3. The control method according to claim 2, wherein the state machine identifying the access command comprises:
the state machine identifies the command identifier carried by the access command;
if the command identifier is the same as a preset command code of the concurrent command, determining that the access command is the concurrent command; otherwise, determining the access command as an independent space access command.
4. The control method according to claim 2, wherein the state machine performs a concurrent operation according to the concurrent command, comprising:
and the state machine generates an effective chip select signal according to the concurrent command and executes the concurrent command according to the effective chip select signal.
5. The control method according to claim 2, wherein the state machine responding to the independent space access command according to a command identifier carried by the independent space access command, comprises:
the state machine compares the corresponding bare chip identifier with the command identifier carried by the independent space access command;
if the bare chip identifier is the same as the command identifier carried by the independent space access command, the state machine generates an effective chip selection signal according to the independent space access command and executes the independent space access command according to the effective chip selection signal;
and if the bare chip identifier is different from the command identifier carried by the independent space access command, the state machine performs invalid execution according to the independent space access command.
CN202311252293.8A 2023-09-26 Flash memory chip and control method Active CN117153831B (en)

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Application Number Priority Date Filing Date Title
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CN114843252A (en) * 2022-05-05 2022-08-02 中国电子科技集团公司第五十八研究所 Large-capacity three-dimensional stacked Nand Flash chip
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