CN106030544B - Method for detecting memory of computer equipment and computer equipment - Google Patents
Method for detecting memory of computer equipment and computer equipment Download PDFInfo
- Publication number
- CN106030544B CN106030544B CN201480065448.XA CN201480065448A CN106030544B CN 106030544 B CN106030544 B CN 106030544B CN 201480065448 A CN201480065448 A CN 201480065448A CN 106030544 B CN106030544 B CN 106030544B
- Authority
- CN
- China
- Prior art keywords
- memory
- detection unit
- cpu
- detection
- memory detection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- G06K5/00—Methods or arrangements for verifying the correctness of markings on a record carrier; Column detection devices
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Quality & Reliability (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
The memory detection method and the computer equipment provided by the embodiment of the invention are used for solving the problem that the normal working timeliness of the computer equipment is influenced due to overlong memory detection time in the prior art. According to the memory detection method and the computer device provided by the embodiment of the invention, the at least two memory modules are simultaneously detected by the at least one memory detection unit, so that the purpose of detecting the memory modules in parallel is realized, the at least two memory modules can be detected at the same time, the time for detecting the memory modules is shortened, and the detection efficiency is improved.
Description
Technical Field
The present invention relates to the field of information technology, and in particular, to a method for detecting a memory of a computer device and a computer device.
Background
At present, the larger the capacity of a random access memory (hereinafter referred to as a memory, namely a RAM) used by computer equipment is, the longer the detection process becomes to ensure the complete function of the memory when a system is started, and the longer the detection process becomes because the capacity is larger and larger. The conventional method at present does not carry out memory detection when starting; however, in a system with critical services, it will take a lot of time to ensure the reliability of the system and check it. For example, the test time for one memory module is T, if the computer device has N memory modules, the total test time is N × T, and the memory self-test time is too long, which affects the timeliness of the system from power-on to normal operation.
Disclosure of Invention
The embodiment of the invention provides a method for detecting a memory of computer equipment and the computer equipment, which aim to solve the problem of overlong memory detection time in the prior art.
In a first aspect, an embodiment of the present invention provides a method for detecting a memory of a computer device, including:
at least one memory detection unit receives a memory detection instruction sent by a Central Processing Unit (CPU) of the computer equipment, and performs memory detection on at least two of at least two memory modules of the computer equipment at the same time; the at least one memory detection unit is connected with the CPU and the at least two memory modules of the computer equipment, so that the CPU is communicated with the at least two memory modules through the at least one memory detection unit;
and the at least one memory detection unit acquires a request according to the detection result sent by the CPU and sends the detection results of the at least two memory modules to the CPU.
With reference to the first aspect, in a first possible implementation manner of the first aspect, the memory detection unit is located in each memory module, or the memory detection unit is located between the CPU and at least two memory modules.
With reference to the first aspect or the first possible implementation manner of the first aspect, in a second possible implementation manner of the first aspect, the method further includes:
when the memory detection unit is communicated with the CPU, the memory detection unit cuts off the connection with the at least two memory modules; or when the memory detection unit detects the memory module, the memory detection unit cuts off the connection with the CPU.
With reference to the first possible implementation manner of the first aspect, in a third possible implementation manner of the first aspect, when the memory detection unit is located in each memory module, each memory module includes one memory detection unit, and the memory detection unit is connected to all RAM chips in each memory module; or the like, or, alternatively,
each RAM Chip of the memory module comprises one memory detection unit.
With reference to the first aspect and the first to third possible implementation manners of the first aspect, in a fourth possible implementation manner of the first aspect, before the at least one memory detection unit receives a memory detection instruction sent by a CPU of the computer device, the method further includes:
and modifying the basic input and output BIOS program to enable the CPU to send an indication of memory detection to the at least one memory detection unit according to the program in the BIOS.
In a second method, an embodiment of the present invention further provides a method for detecting a memory of a computer device, including:
a Central Processing Unit (CPU) of computer equipment sends a memory detection instruction to at least one memory detection unit, wherein the memory detection instruction is used for instructing the at least one memory detection unit to start detection of a memory module, and the CPU is communicated with at least two memory modules through the at least one memory detection unit;
the CPU obtains the detection result of the memory module from the at least one memory detection unit, wherein the detection result is the detection result of the at least one memory detection unit after performing memory detection on at least two of the at least two memory modules simultaneously.
With reference to the second aspect, in a first possible implementation manner of the second aspect, before the CPU of the computer device sends the memory detection instruction to the at least one memory detection unit, the method further includes:
and the CPU acquires an instruction from a basic input/output BIOS program and sends an instruction of memory detection to the at least one memory detection unit.
With reference to the second aspect and the first possible implementation manner of the second aspect, in a second possible implementation manner of the second aspect, the acquiring, by the CPU, the detection result of the memory module from the at least one memory detection unit includes:
and the CPU acquires the detection result of the memory module from the memory detection unit in a polling mode, or the CPU receives the detection result of the memory module reported by the memory detection unit in an interruption mode.
In a third aspect, an embodiment of the present invention further provides a computer device, including a central processing unit CPU and at least two memory modules, where the computer device further includes at least one memory detection unit; wherein the content of the first and second substances,
the CPU is used for sending a memory detection instruction to the at least one memory detection unit;
the at least one memory detection unit is used for receiving a memory detection instruction sent by the CPU, simultaneously performing memory detection on at least two of the at least two memory modules according to the received memory detection instruction, and sending a detection result to the CPU or sending the detection result to the CPU in an interruption mode according to the detection result instruction obtained by the CPU.
With reference to the third aspect, in a first possible implementation manner of the third aspect, the CPU communicates with the at least two memory modules through the at least one memory detection unit.
With reference to the third aspect and the first possible implementation manner of the third aspect, in a second possible implementation manner of the third aspect, the memory detection unit includes:
the detection control unit is used for receiving the memory detection instruction sent by the CPU and simultaneously carrying out memory detection on at least two of the at least two memory modules according to the received memory detection instruction;
and the detection result storage unit is used for storing the detection results of the detection control unit after the detection of the at least two memory modules, and sending the detection results to the CPU or sending the detection results to the CPU in an interruption mode according to the detection result acquisition instruction of the CPU.
With reference to the third aspect and the first to second possible implementation manners of the third aspect, in a third possible implementation manner of the third aspect, the memory detection unit further includes a switch, where the switch is configured to implement connection switching between the memory detection unit and the CPU and between the memory detection unit and the memory module, cut off connection between the memory detection unit and the memory module when the memory detection unit communicates with the CPU, and cut off connection between the memory detection unit and the CPU when the memory detection unit communicates with the memory module.
With reference to the third aspect and the first to third possible implementation manners of the third aspect, in a fourth possible implementation manner of the third aspect, the at least one memory detection unit is located in the memory module to be detected, or the at least one memory detection unit is located between the CPU and the memory module to be detected.
With reference to the fourth possible implementation manner of the third aspect, in a fifth possible implementation manner of the third aspect, when the memory detection unit is located in each memory module, each memory module includes one memory detection unit, and the memory detection unit is connected to all the RAM chips in each memory module; or the like, or, alternatively,
each RAM Chip of the memory module comprises one memory detection unit.
According to the memory detection method and the computer device provided by the embodiment of the invention, the at least two memory modules are simultaneously detected by the at least one memory detection unit, so that the purpose of detecting the memory modules in parallel is realized, the at least two memory modules can be detected at the same time, the time for detecting the memory modules is shortened, and the detection efficiency is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 is a schematic flow chart illustrating a method for detecting a memory of a computer device according to an embodiment of the present invention;
FIG. 2 is a schematic flow chart illustrating another method for detecting a memory of a computer device according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a first specific implementation of a memory detection method for a computer device according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of a second specific implementation of a method for detecting a memory of a computer device according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of a third specific implementation of a method for detecting a memory of a computer device according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of an internal structure of a memory detection unit according to an embodiment of the present invention;
FIG. 7 is a diagram illustrating an exemplary configuration of a computing device 700;
FIG. 8 is a diagram illustrating a second implementation manner of a computer device 700 according to an embodiment of the present invention;
FIG. 9 is a schematic structural diagram of a third implementation manner of a computer device 700 according to an embodiment of the present invention;
fig. 10 is a schematic structural diagram illustrating a first implementation manner of a memory detection unit 703 of a computer device 700 according to an embodiment of the present invention;
fig. 11 is a schematic structural diagram illustrating a second implementation manner of a memory detection unit 703 of a computer device 700 according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all, embodiments of the present invention. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, shall fall within the scope of protection of the present invention.
Referring to fig. 1, fig. 1 is a schematic flow chart of a method for detecting a memory of a computer device according to an embodiment of the present invention, including:
step 101: at least one memory detection unit receives a memory detection instruction sent by a CPU of the computer equipment and simultaneously performs memory detection on at least two memory modules of the computer equipment; the at least one memory detection unit is connected with the CPU and the at least two memory modules of the computer equipment, so that the CPU is communicated with the at least two memory modules through the at least one memory detection unit;
the memory module may be a memory bank, or a RAM Chip in a memory bank.
In a specific implementation, one memory detection unit may be connected to at least two memory modules, and the one memory detection unit detects the at least two memory modules in parallel; or one memory detection unit is connected with one memory module, the other memory detection unit is connected with the other memory module, and the two memory detection units simultaneously detect the memory modules connected with each other in parallel; or one memory detection unit is connected with one memory module, the other memory detection unit is connected with two or more other memory modules, and the two memory detection units simultaneously detect the memory modules connected with each other in parallel. As long as the parallel detection of the memory modules at the same time can be realized, the embodiments of the present invention are included in the protection scope, and no examples are given.
Step 102: and the at least one memory detection unit acquires a request according to the detection result sent by the CPU and sends the detection results of the at least two memory modules to the CPU.
In a specific implementation, the memory detection unit may receive a polling request of the CPU and send a detection result to the CPU; the memory detection unit can report the detection result to the CPU through other modes such as interruption and the like.
According to the method, the at least two memory modules are simultaneously detected by the at least one memory detection unit, so that the purpose of parallel detection of the memory modules is achieved, the at least two memory modules can be detected at the same time, the time for detecting the memory modules is shortened, and the detection efficiency is improved.
As an optional implementation manner, in the embodiment of the present invention, before step 101, the method further includes: and modifying the basic input and output BIOS program to enable the CPU to send an indication of memory detection to the at least one memory detection unit according to the program in the BIOS. In a specific implementation, a program may be added to the BIOS, and the CPU in the computer device reads the added program from the BIOS and sends an instruction of memory detection to the at least one memory detection unit.
Correspondingly, after the computer device is started and the initialization of the memory is completed, the CPU in the computer device may send an instruction of memory detection to the at least one memory detection unit.
In the embodiment of the present invention, the detection of the memory module by the at least one memory detection unit may be implemented as follows: each memory detection unit writes first data into a memory module connected with the memory detection unit, reads second data from a space for storing the first data, compares the first data with the second data, and judges whether the memory has a fault according to a comparison result.
The specific judgment method may be: and if the first data is the same as the second data, the memory module is determined to be normal, and if the first data is inconsistent with the second data, the memory module is determined to be abnormal or failed.
As an optional implementation manner, any one of the memory detection units may perform data writing and reading on one memory module for multiple times, and determine whether the memory module is abnormal or failed after performing judgment for multiple times.
Optionally, the at least one memory detection unit is located in the memory module to be detected, or the at least one memory detection unit is located between the CPU and the memory to be detected. In a specific implementation, the at least one memory detection unit is located in the memory module to be detected, and may be located in one memory bank and connected to each RAM Chip respectively, or one memory detection unit is disposed in each RAM Chip of one memory bank. The specific implementation mode that the at least one memory detection unit is positioned between the CPU and the memory to be detected can be realized by arranging the at least one memory detection unit on a channel between a memory bank and the CPU; for example, the memory detection unit may be a chip disposed on a motherboard of a computer device, and is used to implement the functions of the memory detection unit.
Optionally, when each memory detection unit communicates with the CPU, the memory detection unit cuts off the connection with the memory module; or when each memory detection unit detects the memory module, the connection with the CPU is cut off. That is, the memory detection unit is connected with only the CPU or only the memory module at the same time, so that the memory detection unit does not receive the command of the CPU and does not conflict when detecting the memory module.
Referring to fig. 2, fig. 2 is a schematic flow chart of another method for detecting a memory of a computer device according to an embodiment of the present invention, including:
step 201: a Central Processing Unit (CPU) of computer equipment sends a memory detection instruction to at least one memory detection unit, wherein the memory detection instruction is used for instructing the at least one memory detection unit to start detection of a memory module, and the CPU is communicated with at least two memory modules through the at least one memory detection unit;
the memory module may be a memory bank, or a RAM Chip in a memory bank.
Step 202: the CPU obtains the detection result of the memory module from the at least one memory detection unit, wherein the detection result is the detection result of the at least one memory detection unit after performing memory detection on at least two of the at least two memory modules simultaneously.
In specific implementation, the CPU may poll each memory detection unit, and the CPU may poll the detection result of each memory module repeatedly until the detection results of all memories are obtained; the memory detection unit can report the detection result to the CPU through other modes such as interruption and the like.
According to the method, the CPU of the computer device simultaneously detects the at least two memory modules through the at least one memory detection unit, the purpose of detecting the memory modules in parallel is achieved, the at least two memory modules can be detected at the same time, the time for detecting the memory modules is shortened, and the detection efficiency is improved.
As an optional implementation manner, in the embodiment of the present invention, before step 101, the method further includes:
and modifying the basic input and output BIOS program to enable the CPU to send an indication of memory detection to the at least one memory detection unit according to the program in the BIOS. In a specific implementation, a program may be added to the BIOS, and the CPU in the computer device reads the added program from the BIOS and sends an instruction of memory detection to the at least one memory detection unit.
Correspondingly, after the computer device is started and completes initialization of the memory, the CPU in the computer device may send an instruction of memory detection to the at least one memory detection unit. The detection of the memory module by the at least one memory detection unit can be realized by the following modes: each memory detection unit writes first data into a memory module connected with the memory detection unit, reads second data from a space for storing the first data, compares the first data with the second data, and judges whether the memory has a fault according to a comparison result.
The specific judgment method may be: and if the first data is the same as the second data, the memory module is determined to be normal, and if the first data is inconsistent with the second data, the memory module is determined to be abnormal or failed.
As an optional implementation manner, any one of the memory detection units may perform data writing and reading on one memory module for multiple times, and determine whether the memory module is abnormal or failed after performing judgment for multiple times.
Referring to fig. 3, fig. 3 is a schematic diagram of a first specific implementation structure of a memory detection method for a computer device according to an embodiment of the present invention, in fig. 3, a memory detection unit is located in a memory bank, each memory bank includes one memory detection unit, and a CPU is connected to each memory bank through the memory detection unit in each memory bank. The memory detection units in the plurality of memory banks can simultaneously detect the memory banks and send the detection results to the central processing unit. For example, the memory detection unit in the memory 1 and the memory detection unit in the memory 2 can detect the memories simultaneously, so that the parallel detection of the memories is realized, and the purposes of saving the memory detection time and improving the memory detection efficiency are achieved.
Referring to fig. 4, fig. 4 is a schematic diagram of a second specific implementation structure of a memory detection method of a computer device according to an embodiment of the present invention, in fig. 4, a memory detection unit is located outside a memory bank, and a CPU is connected to each memory bank through the memory detection unit. The memory detection units in the plurality of memory banks can simultaneously detect the memory banks and send the detection results to the central processing unit. For example, the memories 1 to 1 are simultaneously detected by the memory detection unit 1, so that the parallel detection of the memories is realized, and the purposes of saving the memory detection time and improving the memory detection efficiency are achieved. Further, the memory detection unit 2 can detect other memories at the same time, so that more memories can be detected in parallel, and the purposes of saving more memory detection time and improving the memory detection efficiency are achieved.
Referring to fig. 5, fig. 5 is a schematic diagram of a third specific implementation structure of the memory detection method of the computer device according to the embodiment of the present invention, in fig. 4, a memory detection unit is located in each RAM Chip of a memory bank, and a CPU is connected to the RAM Chip of each memory bank through the memory detection unit in each RAM Chip of each memory bank. The memory detection units in the plurality of memory banks can simultaneously detect the memory banks and send the detection results to the central processing unit. For example, the memory detection unit in each RAM Chip in the memory 1 simultaneously detects the respective corresponding RAM Chip in the memory 1, thereby realizing the parallel detection of the memories, and achieving the purposes of saving the memory detection time and improving the memory detection efficiency. Further, the memory detection unit in each RAM Chip in the memory 2 detects the respective corresponding RAM Chip in the memory 2 at the same time, so that more memories can be detected in parallel, and the purposes of saving more memory detection time and improving the memory detection efficiency are achieved. In addition, the RAM Chip is internally provided with the memory detection unit, so that the self-detection speed can be further improved, and the design complexity of the memory detection unit is reduced.
The memory detection unit in fig. 3, fig. 4 or fig. 5 may be an integrated chip, and its internal structure is shown in fig. 6:
the memory detection unit takes over the memory bus of the CPU accessing the memory, and the CPU can read and write the register of the memory detection unit by accessing a specific physical address. For example, the memory space (memory space) under the switch in the memory detection unit is 0x00000000-0x01000000, and an address space (e.g. 0x01000000-0x10000010) out of this range is selected as a register, and the CPU accesses the memory detection unit by accessing the address space of the register. The switcher in the memory detection unit realizes switching of the memory to the CPU access or the detection engine access of the memory detection unit, and when the CPU sends a detection instruction to the memory detection unit, the switcher cuts off the connection between the retrieval engine and the memory; when the detection engine starts the detection of the memory module, the switch cuts off the connection with the CPU. Wherein, the conversion of the switcher is realized by a controller which can write in a register; the detection trigger command of the memory detection unit and the querier for querying the detection state are stored in this register.
When the computer equipment is started and the initialization of the memory is completed, the central processing unit CPU sends an instruction for starting the memory detection to the memory detection unit through the register, and at the moment, the switch in the memory detection unit cuts off the connection between the detection engine and the memory. When the register completes the memory detection instruction issued by the CPU and starts the detection of the memory, the switch cuts off the connection between the register and the switch, namely cuts off the connection between the memory detection unit and the CPU, the search engine detects the memory space with the address of 0x00000000-0x01000000, and can judge whether the memory space to be detected is normal or not, whether a fault exists or not by writing data and reading data for many times and judging whether the read data is consistent with the written data or not. When the detection engine finishes detecting the memory, the detection result is stored in the register. When the CPU obtains the detection result from the register in a polling mode, reading the stored detection result from the register; or the register sends the detection result to the CPU in an interrupt mode.
Referring to fig. 7, fig. 7 is a schematic structural diagram of a computer device 700 according to an embodiment of the present invention, where the computer device 700 includes a central processing unit CPU701, at least two memory modules 702, and at least one memory detection unit 703; the CPU701 is connected to the at least one memory module 702 through at least one memory detection unit 703;
the CPU701 is configured to send a memory detection instruction to the at least one memory detection unit 703;
the at least one memory detection unit 703 is configured to receive a memory detection instruction sent by the CPU701, perform memory detection on at least two of the at least two memory modules 702 simultaneously according to the received memory detection instruction, and send a detection result to the CPU701 according to a detection result acquisition instruction of the CPU701 or send the detection result to the CPU701 in an interrupt manner.
According to the computer device, the at least two memory modules 702 are simultaneously detected by the at least one memory detection unit 703, so that the purpose of parallel detection of the memory modules is achieved, the at least two memory modules can be detected at the same time, the time for detecting the memory modules is shortened, and the detection efficiency is improved.
The memory module 702 may be a memory bank, or a RAM Chip in a memory bank. The CPU701 sends an instruction to acquire a detection result to the memory detection unit 703 in a polling manner.
In a specific implementation, one memory detection unit 703 may be connected to at least two memory modules 702, and the memory detection unit 703 detects at least two memory modules 702 in parallel at the same time, as shown in fig. 7. As shown in fig. 8, one memory detection unit 703 may be connected to one memory module 702, another memory detection unit 703 is connected to another memory module 702, and the two memory detection units 703 simultaneously detect the respective connected memory modules 702 in parallel. Alternatively, one memory detection unit 703 may be connected to one memory module 702, another memory detection unit 703 may be connected to two or more other memory modules 702, and the two memory detection units simultaneously detect the respective connected memory modules in parallel, as shown in fig. 9. As long as the parallel detection of the memory modules at the same time can be realized, the embodiments of the present invention are included in the protection scope, and no examples are given.
It should be noted that, in the above-mentioned drawings of fig. 7 to 9, for the sake of simplifying and clearly showing the drawings, a plurality of memory detection units 703 and memory modules 702 are not shown, that is, only one memory detection module 703 is shown for "at least one memory detection module 703", only two memory modules 702 are shown for "at least two memory modules 702", and the like. For more than two memory sensing modules 703 or more than three memory modules 702, etc., all of which are within the scope of the embodiments of the present invention, one memory sensing unit 703 or two memory modules 702 in fig. 7-9 should not be construed as limiting the embodiments of the present invention.
In a specific implementation, as shown in fig. 10, any one memory sensing unit 703 of the at least one memory sensing unit 703 includes:
a detection control unit 7031, configured to receive a memory detection instruction sent by the CPU701, and perform memory detection on at least two of the at least two memory modules 702 simultaneously according to the received memory detection instruction;
a detection result storage unit 7032, configured to store a detection result obtained by the detection control unit 7031 after detecting the at least two memory modules 702, and send the detection result to the CPU701 according to the detection result obtained by the CPU701, or send the detection result to the CPU701 in an interrupt manner.
In a specific implementation, the detection of the memory module 702 by the detection control unit 7031 may be implemented as follows: the detection control unit 7031 writes first data into a memory module connected thereto, reads second data from a space in which the first data is stored, compares the first data with the second data, and determines whether the memory has a fault according to a result of the comparison. The specific judgment method may be: and if the first data is the same as the second data, the memory module is determined to be normal, and if the first data is inconsistent with the second data, the memory module is determined to be abnormal or failed.
As an optional implementation manner, as shown in fig. 11, the memory detection unit 703 further includes a switch 7033, configured to implement connection switching between the memory detection unit and the CPU701 and the memory module 702, and cut off connection between the memory detection unit 703 and the memory module 702 when the memory detection unit 703 communicates with the CPU701, and cut off connection between the memory detection unit 703 and the CPU701 when the memory detection unit 703 communicates with the memory module 702. So that the memory detection unit 703 is connected only to the CPU701 or only to the memory module 702 at the same time. In this way, the memory detection unit 703 does not receive the command of the CPU701 when detecting the memory module 702, and thus a collision does not occur.
Optionally, the at least one memory detection unit 703 may be located in the memory module 702 to be detected, or the at least one memory detection unit 703 is located between the CPU701 and the memory module 702 to be detected. In a specific implementation, the at least one memory detection unit 703 is located in the memory module to be detected, where the at least one memory detection unit 703 is located in one memory bank and is respectively connected to each RAM Chip, or one memory detection unit is disposed in each RAMChip of one memory bank. The specific implementation manner that the at least one memory detection unit 703 is located between the CPU701 and the memory 702 to be detected can be implemented by providing at least one memory detection unit 703 on a channel between the memory module 702 and the CPU 701; for example, the memory detection unit 703 may be a chip disposed on a motherboard of a computer device.
The computer device 700 according to the embodiment of the present invention may be implemented by referring to the implementation manners in the embodiments shown in fig. 1 to fig. 6, and details are not described again.
Those of ordinary skill in the art will appreciate that the elements and algorithm steps of the examples described in connection with the embodiments disclosed herein may be embodied in electronic hardware, computer software, or combinations of both, and that the components and steps of the examples have been described in a functional general in the foregoing description for the purpose of illustrating clearly the interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
It is clear to those skilled in the art that, for convenience and brevity of description, the specific working processes of the above-described systems, apparatuses and units may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.
In the several embodiments provided in the present application, it should be understood that the disclosed system, apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units is only one logical division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may also be an electric, mechanical or other form of connection.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment of the present invention.
In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.
The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention essentially or partially contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product stored in a storage medium and including instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.
While the invention has been described with reference to specific embodiments, the invention is not limited thereto, and various equivalent modifications and substitutions can be easily made by those skilled in the art within the technical scope of the invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (11)
1. A method for memory detection in a computer device, comprising:
at least one memory detection unit receives a memory detection instruction sent by a Central Processing Unit (CPU) of the computer equipment, and performs memory detection on at least two of at least two memory modules of the computer equipment at the same time; the memory detection instruction is sent by the CPU to the at least one memory detection unit according to an instruction in a basic input output BIOS program, and the at least one memory detection unit is connected with the CPU and at least two memory modules of the computer equipment, so that the CPU communicates with the at least two memory modules through the at least one memory detection unit;
and the at least one memory detection unit acquires a request according to the detection result sent by the CPU and sends the detection results of the at least two memory modules to the CPU.
2. The method of claim 1, wherein:
the memory detection unit is located in each memory module, or the memory detection unit is located between the CPU and at least two memory modules.
3. The method according to claim 1 or 2, characterized in that the method further comprises:
when the memory detection unit is communicated with the CPU, the memory detection unit cuts off the connection with the at least two memory modules; or when the memory detection unit detects the memory module, the memory detection unit cuts off the connection with the CPU.
4. The method of claim 2, wherein:
when the memory detection unit is positioned in each memory module, each memory module comprises one memory detection unit, and the memory detection unit is connected with all RAM chips in each memory module; or the like, or, alternatively,
each RAM Chip of the memory module comprises one memory detection unit.
5. A method for memory detection in a computer device, comprising:
a Central Processing Unit (CPU) of computer equipment acquires an instruction from a basic input/output system (BIOS) program and sends an instruction of memory detection to at least one memory detection unit, wherein the memory detection instruction is used for instructing the at least one memory detection unit to start the detection of a memory module, and the CPU is communicated with at least two memory modules through the at least one memory detection unit;
the CPU obtains the detection result of the memory module from the at least one memory detection unit, wherein the detection result is the detection result of the at least one memory detection unit after performing memory detection on at least two of the at least two memory modules simultaneously.
6. The method of claim 5, wherein the CPU obtaining the memory module test results from the at least one memory test unit comprises:
and the CPU acquires the detection result of the memory module from the memory detection unit in a polling mode, or the CPU receives the detection result of the memory module reported by the memory detection unit in an interruption mode.
7. A computer device comprises a Central Processing Unit (CPU) and at least two memory modules, and is characterized by further comprising at least one memory detection unit; wherein the content of the first and second substances,
the CPU is used for acquiring instructions from a basic input output BIOS program and sending memory detection instructions to the at least one memory detection unit; the CPU is communicated with the at least two memory modules through the at least one memory detection unit;
the at least one memory detection unit is used for receiving a memory detection instruction sent by the CPU, simultaneously performing memory detection on at least two of the at least two memory modules according to the received memory detection instruction, and sending a detection result to the CPU or sending the detection result to the CPU in an interruption mode according to the detection result instruction obtained by the CPU.
8. The computer device of claim 7, wherein the memory detection unit comprises:
the detection control unit is used for receiving the memory detection instruction sent by the CPU and simultaneously carrying out memory detection on at least two of the at least two memory modules according to the received memory detection instruction;
and the detection result storage unit is used for storing the detection results of the detection control unit after the detection of the at least two memory modules, and sending the detection results to the CPU or sending the detection results to the CPU in an interruption mode according to the detection result acquisition instruction of the CPU.
9. The computer device according to any one of claims 7 to 8, wherein the memory detection unit further comprises a switch, and the switch is configured to switch connection between the memory detection unit and the CPU and the memory module, and disconnect the memory detection unit from the memory module when the memory detection unit communicates with the CPU, and disconnect the memory detection unit from the CPU when the memory detection unit communicates with the memory module.
10. The computer device according to any of claims 7 to 8, wherein the at least one memory detection unit is located in the memory module to be detected, or the at least one memory detection unit is located between the CPU and the memory module to be detected.
11. The computer device according to claim 10, wherein when the memory detection unit is located in each memory module, each memory module includes one memory detection unit, and the memory detection unit is connected to all the RAM chips in each memory module; or the like, or, alternatively,
each RAM Chip of the memory module comprises one memory detection unit.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/CN2014/094823 WO2016101177A1 (en) | 2014-12-24 | 2014-12-24 | Random access memory detection method of computer device and computer device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106030544A CN106030544A (en) | 2016-10-12 |
| CN106030544B true CN106030544B (en) | 2020-01-21 |
Family
ID=56148913
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201480065448.XA Active CN106030544B (en) | 2014-12-24 | 2014-12-24 | Method for detecting memory of computer equipment and computer equipment |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN106030544B (en) |
| WO (1) | WO2016101177A1 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108021482A (en) * | 2017-12-28 | 2018-05-11 | 杭州迪普科技股份有限公司 | The method and device of memory is detected under a kind of Boot Loader |
| CN110618905B (en) * | 2019-08-06 | 2023-05-09 | 晶晨半导体（深圳）有限公司 | Method for detecting abnormal DDR memory in DDR memory module |
| CN114780323A (en) * | 2022-06-17 | 2022-07-22 | 新华三信息技术有限公司 | Fault detection method, device and equipment for memory in server |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1991782A (en) * | 2005-12-30 | 2007-07-04 | 英业达股份有限公司 | RAM module mounting condition detecting method and system |
| CN102708031A (en) * | 2012-05-15 | 2012-10-03 | 浪潮电子信息产业股份有限公司 | Hardware implementation method for rapidly positioning fault memory |
| CN102799506A (en) * | 2012-06-29 | 2012-11-28 | 浪潮电子信息产业股份有限公司 | Method for positioning fault memory |
| CN103065687A (en) * | 2012-12-28 | 2013-04-24 | 山东华芯半导体有限公司 | A method of parallel detection for RAM production defects in an integrated circuit |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3655176B2 (en) * | 2000-02-22 | 2005-06-02 | 松下電器産業株式会社 | Memory pause device and memory pause method |
| US7805644B2 (en) * | 2007-12-29 | 2010-09-28 | Texas Instruments Incorporated | Multiple pBIST controllers |
| CN102237115A (en) * | 2011-08-03 | 2011-11-09 | 深圳芯邦科技股份有限公司 | Test method and corresponding test system |
| JP6070374B2 (en) * | 2013-03-29 | 2017-02-01 | 富士通株式会社 | Information processing apparatus, memory test program, and memory test method |
-
2014
- 2014-12-24 CN CN201480065448.XA patent/CN106030544B/en active Active
- 2014-12-24 WO PCT/CN2014/094823 patent/WO2016101177A1/en active Application Filing
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1991782A (en) * | 2005-12-30 | 2007-07-04 | 英业达股份有限公司 | RAM module mounting condition detecting method and system |
| CN102708031A (en) * | 2012-05-15 | 2012-10-03 | 浪潮电子信息产业股份有限公司 | Hardware implementation method for rapidly positioning fault memory |
| CN102799506A (en) * | 2012-06-29 | 2012-11-28 | 浪潮电子信息产业股份有限公司 | Method for positioning fault memory |
| CN103065687A (en) * | 2012-12-28 | 2013-04-24 | 山东华芯半导体有限公司 | A method of parallel detection for RAM production defects in an integrated circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2016101177A1 (en) | 2016-06-30 |
| CN106030544A (en) | 2016-10-12 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101477480B (en) | Memory control method, apparatus and memory read-write system | |
| CN106294222A (en) | A kind of method and device determining PCIE device and slot corresponding relation | |
| US8205038B2 (en) | Flash memory accessing apparatus and accessing method thereof | |
| EP2960777B1 (en) | Data protection method, apparatus and device | |
| CN103077102A (en) | Computer starting detection system | |
| CN106030544B (en) | Method for detecting memory of computer equipment and computer equipment | |
| CN106155826B (en) | For the method and system of mistake to be detected and handled in bus structures | |
| CN107070747A (en) | A kind of method of the automatic test network interface card network connection stability under network card binding pattern | |
| US20140164845A1 (en) | Host computer and method for testing sas expanders | |
| CN113992578B (en) | Method, device, equipment and storage medium for switching servers of cloud desktop terminal | |
| US9417942B1 (en) | Event-based in-band host registration | |
| CN105573872A (en) | Hardware maintenance method and device of data storage system | |
| CN112133357B (en) | eMMC test method and device | |
| CN112866061A (en) | NCSI (network control information system) testing method, device, equipment and medium of onboard network port | |
| US8977892B2 (en) | Disk control apparatus, method of detecting failure of disk apparatus, and recording medium for disk diagnosis program | |
| CN104484260A (en) | Simulation monitoring circuit based on GJB289 bus interface SoC (system on a chip) | |
| US8783576B2 (en) | Memory card having multiple interfaces and reset control method thereof | |
| CN101533372B (en) | Data accessing system | |
| CN102841836B (en) | Testing method and programmable processor | |
| CN101751283A (en) | Virtual machine monitor, virtual machine system and client operation system state acquiring method | |
| CN103793283A (en) | Terminal fault handling method and terminal fault handling device | |
| CN106610878A (en) | Fault debugging method for dual-controller system | |
| CN101533373B (en) | Data accessing system | |
| EP3557422A1 (en) | Method for accessing code sram, and electronic device | |
| CN113330411B (en) | Storage controller and data relocation monitoring method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |