CN104809075A

CN104809075A - Solid recording device and method for accessing in real time and parallel processing

Info

Publication number: CN104809075A
Application number: CN201510188733.7A
Authority: CN
Inventors: 孟劲松; 高斌; 刘群英; 任文伟; 田贵云
Original assignee: University of Electronic Science and Technology of China
Current assignee: University of Electronic Science and Technology of China
Priority date: 2015-04-20
Filing date: 2015-04-20
Publication date: 2015-07-29
Anticipated expiration: 2035-04-20
Also published as: CN104809075B

Abstract

The invention discloses a solid recording device and a solid recording method for accessing in real time and parallel processing. The solid recording device for accessing in real time and parallel processing comprises a solid recording system control card for accessing and parallel processing, a plurality of solid storage cards for accessing and parallel processing, and a single board computer, wherein the system control card is connected with acquisition and playback peripheral equipment through specific peripheral equipment communication interfaces, and is connected with one or more than one solid storage card which is provided with four groups of independent flash arrays and a controller thereof through multi-channel high-speed access communication interfaces; a reading data link and a writing data link which are independent of each other are established between the acquisition and playback peripheral equipment and any two groups of flash arrays on the solid storage card; the flash array controller performs multistage assembly line read/write operation; the solid recording method for accessing and parallel processing comprises the following steps: performing recording and playback operation on all hard wire parallel processing; accelerating the conversion from LBA (Logic Block Address) to PBA (Physical Block Address) by adopting equalization write and address quadratic mapping strategies; therefore, the aim of performing data recording and playback simultaneously at a high speed is achieved by the solid recording device and the solid recording method for accessing in real time and parallel processing.

Description

A kind of solid state record device and method accessing real-time parallel process

Technical field

The present invention relates to field of data storage, particularly relate to solid state recording instrument field, particularly a kind of solid state record device and method accessing real-time parallel process.

Background technology

Existing data storage technology, comprising: open disk sort memory technology, closed registering instrument memory technology.

Open disk sort memory technology, its typical products is as solid-state disk, DAS/SAN/NAS disk array etc., be usually used in the file system data storage of computing machine, server, the single single card microcomputer communication interface of general employing is as PCIe, SAT/SAS, FC, LAN etc., the parallel access of many storage mediums is adopted to have the feature of high burst rate, expansion more easily realizes, but can not meet the demand of continuous high speed real time access; And due to storage array be single critical resource topological structure, record cannot carry out with read operation simultaneously, thus does not support the parallel processing that accesses.As on 08 13rd, 2014 Granted publications, notification number is CN101178933B, name is called " a kind of flash memory array device ".

Closed registering instrument memory technology, except single card microcomputer communication interface, one or more external dedicated communication interfaces are generally provided, peripheral hardware carries out the access of data by the peripheral hardware special communication interface of registering instrument, linear address writes continuously or reads, do not need file system support, there is the feature of continuous real time high-speed access, but memory array structure is still single critical resource topological structure, thus the parallel processing accessed is not supported yet, and due to its closure, the extended capability of speed and capacity is limited.As on 01 30th, 2008 Granted publications, notification number is CN10365599C, name is called " flash array storage method and device thereof for real-time data record in digital signal processor ", and 2008 06 month the 30th volume the 6th phase " modern radar " deliver, name is called " extendible VXS bus solid state record equipment ".

The sampling of RF low pass or the RF bandpass sampling radio such as radar, software radio, radio technique reconnaissance, data sampling rate can reach hundreds of MS/s or more than GS/s, data throughput is very high, these high-speed radio electricity products, in exploitation, evaluation stage, need to provide excitation in real time, continuously, at a high speed and test data storage system usually; Some electronic products, as high definition/high speed image collects and records equipment, perform non-linear playback while requiring to gather.These kind of situation all needs a kind of solid state storage technologies supporting to access real-time parallel process.

Consider above situation, radio products, in exploitation, assessment, and performs the electronic product of non-linear playback while requiring data acquisition, desirably support the process of access real-time parallel, speed and capacity can the solid state record device of flexible configuration and expansion.

Summary of the invention

The object of the invention is to the deficiency overcoming existing memory technology, a kind of solid state record device and method accessing real-time parallel process is provided, support the process of access real-time parallel, and the speed and capacity of flexible expansion solid state record device.

A kind of solid state record device accessing real-time parallel process of the present invention, it is characterized in that, comprising: access parallel processing Solid Recording System control card (hereinafter referred to as system control card), multiple access parallel processing solid-state memory card (hereinafter referred to as solid-state memory card), a single card microcomputer;

System control card is connected with collection, playback peripheral hardware by the peripheral hardware private communication interface of front panel or backboard, is connected with multiple solid-state memory card by multi-channel high-speed access communication interface; By system control card, in collection, between playback peripheral hardware and solid-state memory card, set up reading and writing two independent data links, and reading and writing operation parallel processing;

Single card microcomputer is connected with system control card, solid-state memory card by management interface controller, and detects it, configures and monitoring management.

Wherein, described system control card, adopts full hard-wired design, comprises peripheral hardware private communication interface, multi-channel high-speed access communication interface, access parallel processing control device, high-speed cache, and config memory;

Described peripheral hardware private communication interface comprises collection peripheral communication interface and playback peripheral communication interface, is connected respectively with collection, playback peripheral hardware, for the storage and reproduce of information source data, and concrete employing 2 kinds of forms:

(1) front panel peripheral hardware private communication interface, is adopted peripheral communication agreement, is connected by optical cable or cable with external collection/playback peripheral hardware;

(2) backboard peripheral hardware private communication interface, is connected with built-in collection, playback peripheral communication controller electrical resistance by backboard;

Described multi-channel high-speed access communication interface adopts multichannel full-duplex high-speed serial communication interface, is connected, adopts 2 kinds of forms with multiple solid-state memory card:

(1) front panel multi-channel high-speed access communication interface, adopts SFP+/Mini SAS multi-channel high-speed serial communication interface FMC module, then by optical cable or cable, is connected with multiple solid-state memory card;

(2) backboard multi-channel high-speed access communication interface, is adopted multi-channel high-speed serial communication interface, then is connected with multiple solid-state memory card electrical resistance by backboard;

Described access parallel processing control device, comprise collection/playback peripheral communication controller, multi-channel high-speed access communication controller, management interface controller, address manager, data management system, Configuration Control Unit, be connected with peripheral hardware private communication interface, zero access communication interface, high-speed cache, config memory etc., for accessing the system management of the address of solid state record device, data link and Frame;

Wherein, described address manager, comprise write operation LA/LBA (Logic Block Address, logical block addresses) maker, write operation LBA register, read offset register, read logical address LA (LogicAddress, logical address) register, solid-state memory card capability register group, RAID mode register, address process controller; Generate for write operation LBA, read that logical address calculates, the read pointer initialization of high-speed cache and generate control, the address search of plate level, the shunting of data and aggregation scheme control etc.;

Wherein, described data management system, comprises data frames and shunting, data aggregate, image data impact damper, cache controller, reads the parallel processing of data aggregate for the frame formatting of peripheral data and shunting, solid-state memory card;

Described high-speed cache, adopt QDR SRAM storage medium, the capacity of storage medium is more than or equal to N number of logical blocks size respectively, and for the data that buffer memory collection peripheral hardware or solid-state memory card are sent, wherein N is more than or equal to 2;

Described config memory, adopt nonvolatile memory, for recording peripheral hardware private communication interface channel number and the systematic parameter such as speed, solid-state memory card quantity and capacity, RAID mode, up-to-date write operation LBA, high speed access channel number, zero access speed, when powering on, these systematic parameters are loaded into above-mentioned corresponding register from config memory.

Described solid-state memory card, adopt full hard-wired design, comprise zero access communication interface, communication and read-while writing processing controller, block mapping table is deposited, logical blocks mapping table, four independently flash array, four independently flash array controllers, and config memory;

Described zero access communication interface, adopt full-duplex high-speed serial communication interface, be connected with system control card, the transmitting-receiving for Frame is transmitted, and adopts following 2 kinds of forms:

(1) front panel zero access communication interface, is adopted SFP+, Mini SAS high-speed serial communication interface FMC module, is connected by optical cable or Mini SAS cable with system control card;

(2) backboard zero access communication interface, is adopted high-speed serial communication interface, is connected by backboard with system control card electrical resistance;

Described communication and read-while writing processing controller, comprise address memory controller, read-while writing processing controller, zero access communication controler, management interface controller, and local bus control, be connected with zero access communication interface, block mapping table, logical blocks mapping table, four independent flash array control units, for data communication, address, data link, Frame, flash memory access, single card microcomputer configuration and the real-time parallel process monitored; Wherein, read-while writing processing controller comprises read-while writing processing state machine, data frames and scheduler, write buffer, read buffer, and four-way is write number of times Parasites Fauna, writes LBA_1, write PBA, the current LBA_1 of reading, the current PBA of reading, read the registers such as LAB_1 next time; Address memory controller, for the Read-write Catrol of logical blocks mapping table, block mapping table, is connected with read-while writing processing controller simultaneously, solid-state memory card and veneer function is managed block mapping table and logical blocks mapping table;

Described logical blocks mapping table, adopt nonvolatile memory and SRAM, during for performing write operation, the once mapping LBA_1 of the logical block addresses LBA of fast recording flash array, according to LBA to its immediate addressing; The most significant digit of LBA_1 is as the zone bit made a mistake during flash memory programming, and " 1 " is mistake; Wherein, nonvolatile memory is used for power down and preserves, and is loaded into SRAM, with fast access after powering on;

Described piece of mapping table, adopts SRAM, for storing all pieces of solid-state memory card remap, using and once mapping LBA_1 and form block address BA (Block Address), to its immediate addressing; Management software on single card microcomputer creates after block remaps list completing solid-state memory card, creates or upgrade block mapping table via management interface controller; When performing data access operation, read-while writing processing controller carries out read operation to it;

Described four independently flash arrays, form four independent dynamic critical resources, and at least there are two idle critical resources at any time, often organize the corresponding independent flash array control unit of flash array, thus form four independent access passages, at any time, 2 passages are had at least to be in idle condition;

Described four independently flash array controllers, adopt alternately die (wafer), multi-plane, cacheprogram pattern to flash array perform multi-stage pipeline ECC, read/programme, the operation such as status register reading;

Described config memory, for recording the system configuration parameters such as zero access communication interface speed, read/write buffer memory capacity, the layout parameter of flash array, the structural parameters of flash chip.

Described flash array, adopts M × N wafer array layout, and wherein, N is determined by access bandwidth and I/O bit wide, and M is determined by the real-time continuous of four-way flash array read/write operation; Flash array controller adopts alternately die (wafer), multi-plane, cache program pattern to implement the read/write operation of M level production line to the flash array be attached thereto, when performing the programming operation of afterbody streamline write operation to M × N wafer array of certain passage, the programming of first order streamline write operation completed be in idle condition can be continued on for perform read/write operation, although the programming of the N number of wafer in the second level may also carried out.

Wherein, described M level production line read/write operation, accesses the page array of M × aN at every turn, and this M × aN page array is a block, in block, the numbering of each page is identical, block address LBA={ logical block index, logical page (LPAGE) index, logical channel index }, block size is M × aN × P, wherein, P is page size, and unit is byte; The PBA={ physical channel index that LBA is corresponding, M × aN physical block index, Physical Page index }, wherein, M, N are the layout parameter of M × N wafer array, and a is the number of plane in each wafer.

Further, the present invention can also utilize described multiple solid state record devices can form an access real-time parallel process Solid Recording System, main system control card is installed in computing machine, by the multichannel access communication interface of front panel, be connected with the peripheral hardware private communication interface of slave system control card in each solid state record device, there is the RAID 0 of Unit Level, RAID 1, RAID 10 mode of operation, realize the expansion of memory rate and capacity.

Further, the present invention also provides a kind of method utilizing solid state record device to carry out accessing real-time parallel process, it is characterized in that, comprises the following steps:

(1), systematic parameter load, initialization of register

After powering on, management software on single card microcomputer obtains configuration parameter from the config memory of system control card, solid-state memory card, be configured to the corresponding registers of system control card, the LA/LBA maker of initialization system control card, the four-way of solid-state memory card write number of times Parasites Fauna, if need to perform bad block to detect to wipe with block and process, perform step (2), if do not needed, perform step (4);

(2), solid-state memory card carries out bad block check processing

2.1), management software carries out bad block detection to each solid-state memory card, obtains the bad block list of each solid-state memory card, generates bad block listing file, if do not need to perform erase operation, perform step 2.3), if need to perform erase operation, perform step 2.2);

2.2), management software performs erase operation to needing the block of each wafer in the solid-state memory card of erasing, if the erase operation failure of certain block, bad block mark is set up in the spare area of the first page of this block, need if all the erase operation of the solid-state memory card performing erase operation to complete, return and perform step 2.1);

2.3), according to the bad block listing file of solid-state memory card, obtain the active block number in each plane of each wafer, if the active block number in single wafer is less than minimum nominal active block number (Valid Block Number, NVB), then need to change flash memory, operation terminates; If not, determine the active block number of solid-state memory card, calculate the capacity of solid-state memory card, and the solid-state memory card capability register group of writing system control card, perform step (3);

(3) solid-state storage fixture block mapping table, is created

3.1) block, with plane once remaps: adopt inverted order mapping policy, the bad block of each plane in each for the flash array of each passage wafer is remapped to the good block of physics of same plane, obtain block mapping table of all wafers in solid-state memory card, save as block map file;

3.2), the block Quadratic Map of logic-oriented block addressing: according to block mapping table, each logical blocks is mapped to the physical blocks comprising all physical block numbers in block, forms block mapping table, save as file;

(4), loading blocks mapping table: management software is by the block mapping table of management interface by block mapping table write solid-state memory card;

(5), the access parallel processing of collection and playback

5.1), set up the plate level link of data distribution/polymerization: the Solid Recording System that multiple solid state record device is built, close the LA/LBA maker from system control card, the shunting solid-state memory card number of RAID0 is determined according to the multiple proportion gathering playback rate and storage card read-write speed, basis is the need of redundancy backup again, setting RAID 0, shunting/the aggregated links of RAID 1 or RAID 10, if single record operation, single card microcomputer enabled systems control card, the data receiving channel of solid-state memory card, perform step 5.2), if single playback operation, perform step 5.6), if perform playback operation at the synchronization performing logger task, then parallel execution of steps 5.2) and 5.6),

5.2), image data receives and frame formatting: system control card receives the data gathering peripheral hardware and send over, and often receives the data of a block, performs LBA=LBA+1, according to RAID mode, solid-state memory card capacity, determines target solid-state memory card; System control card forms write operation Frame, by zero access communications interface transmission to target solid-state memory card;

5.3), solid-state memory card is when receiving the write command frame that system control card sends over, and carries out second level address mapping to writing LBA:

5.3.1) write LBA and be mapped as LBA_1: solid-state memory card is isolated and is write LBA from write command frame, obtains a mapping address LBA_1 of LBA, is recorded to logical blocks mapping table, will be labeled as and write busy, and perform step 5.3.2 by write access);

5.3.2) LBA_1 is mapped as PBA: carry out secondary addressing according to LBA mapping address LBA_1 to block mapping table, obtains the index of all physical blocks in a logical blocks, obtains physical block address PBA, carry out step 5.4);

5.4), storage card receives the write data frame that system control card sends over, user data is put into buffer zone, successively physical block address PBA and user data are sent to the flash array controller of this passage, M level production line write operation is performed to M × N wafer array, after programming instruction is sent to last column wafer, no matter whether its programming completes, be idle by this path marking, perform step 5.5), simultaneously, flash array controller monitoring programming state, if made a mistake during programming, confirm the block made a mistake, with interrupt mode advice note trigger, upgrade bad block listing file, the most significant digit of LBA_1 is made bad block mark by read-while writing processing controller,

5.5), system control card checks whether the up-to-date LBA of writing has reached the power system capacity of pen recorder, if reached, terminates recording processing; If do not reached, reexamine and whether receive stopping recording instruction, if do not receive stopping recording instruction, perform step 5.2), if receive stopping recording instruction, the up-to-date LBA of writing is updated to config memory, terminates recording processing;

5.6), single card microcomputer pre-sets and reads offset address, or system is in the process performing write operation, single card microcomputer arranges at random and reads logical address LA, read its length, to the remainder of LA divided by LBA be read come the read pointer of initialization speed buffering, when meeting reading conditions, starting read operation, performing step 5.7);

5.7), check whether the offset address of read operation is less than or equal to the size of 2 logical blocks:

5.7.1) if the offset address of read operation is less than or equal to the size of 2 logical blocks, system control card is according to high-speed cache read pointer, the data read in high-speed cache send to playback peripheral hardware, often read the data of a logical blocks, check whether to reach to read length or receive stopping and reading instruction, if not, continue to read the data in delaying at a high speed and deposit into row playback, if so, playback process is terminated;

5.7.2) if the offset address of read operation is greater than the size of 2 logical blocks, LBA, reading length are packaged as and read command frame by system control card, check whether write command frame or write data frame send, if, wait for that it completes, if not, then send and read command frame and Frame to target solid-state memory card, execution step 5.8);

5.8), solid-state memory card monitoring reception reads command frame, and therefrom isolate and read LBA, LBA register is read in initialization, performs step 5.9);

5.9) the Quadratic Map operation of reading LBA to PBA, is performed:

5.9.1), use and read LBA addressing is carried out to logical blocks mapping table, obtain and once map LBA_1, will be labeled as by read channel and read to hurry, perform step 5.9.2);

5.9.2), to LBA_1 carry out Quadratic Map, obtain all physical block numbers in a logical blocks, obtain PBA, concurrently, carry out step 5.10), 5.11);

5.10), make LBA+1, obtain the once mapping LBA_1 of LBA+1, determine pre-read channel accordingly, and be labeled as and read to hurry next time;

5.11), whether idlely check by read channel, write busy if be in by read channel, wait for, if idle by read channel, PBA is sent to by the flash array controller of read channel, multi-stage pipeline read operation is performed to the flash array of this passage; Response frame and read data frame are read in formation, send to system control card by the zero access interface of solid-state memory card; After the read operation of last column wafer is completed, be idle by this path marking, perform step 5.12);

5.12), solid-state memory card checks whether to reach and reads length or receive stopping play-back command, and if so, solid-state memory card empties the relevant register of read operation, terminate read operation, if not, LBA+1 pushes and reads LBA register by solid-state memory card, performs step 5.9);

5.13) what, system control card monitoring reception solid-state memory card sended over reads response frame and read data frame, if RAID 1 or RAID 10 pattern, what check that 2 solid-state memory card of mirror image each other send simultaneously reads the block quality that response frame indicates, select correct solid-state memory card data, stored in high-speed cache; System control card reads the data in high-speed cache, and sends the data to playback peripheral hardware, performs step 5.14);

5.14), system control card checks whether the stopping play-back command receiving single card microcomputer and send over, if do not receive stopping playback command, perform step 5.13), if receive stopping play-back command, then send to solid-state memory card and stop play-back command, playback process terminates; ;

End process;

Wherein, described hyperchannel equilibrium is written as:

When performing the write operation in units of logical blocks, if do not have read operation to occur, then solid-state memory card has four passages to be in idle condition, if there is read operation to occur simultaneously, have 2 passages to be in respectively and to read to hurry, read busy condition next time, then solid-state memory card has two passages to be in idle condition, a passage writing least number of times is selected from idle channel, when writing number of times and being identical, the passage that selector channel sequence number is minimum, as the passage of current execution write operation, this makes write operation around four channel rotation, the situation of the same passage of continuous write can not occur, equally, the situation of double reading same channels also can not occur, read operation and write operation is made to avoid competition to critical resource, write strategy towards hyperchannel equilibrium, the LBA of solid state record device is defined as LBA={LB, LP, LCH}, wherein, LB, LP, LCH, be respectively logical block index, logical page (LPAGE) index, logical channel index, the low level of LBA is logical channel index, embodies hyperchannel equilibrium and writes,

Wherein, the described LBA that writes is mapped as once being mapped as of LBA_1:

Be LBA_1={PCH, LB, PP} by a mapping definition, wherein, PCH, LB, PP, be respectively physical channel index, logical block index, Physical Page index, { LB, PP} are defined as this passage and write times N _wR, write strategy according to hyperchannel equilibrium, when idle channel write number of times identical time, the passage that selector channel sequence number is minimum, what make this passage writes times N _wR+ 1, obtain LBA_1={ physical channel index, passage writes number of times }=PCH, LB ', and PP ' }, by it stored in logical blocks map store;

Wherein, described LBA_1 is mapped as PBA:

For step 5.3.2), 5.9.2), obtain in solid-state memory card and once map LBA_1={PCH, LB, after PP}, use { PCH, LB, Row, Col} conduct interviews to block map store, obtain the M × N wafer array each physical block index PB corresponding to logical block index LB of flash array in passage PCH, final acquisition physical block address PBA={PCH, PB (M × aN), PP}, wherein, Row≤M, Col≤N is respectively line index and the column index of wafer in block, and a is the plane number in each wafer.

The object of the present invention is achieved like this:

One access real-time parallel process solid state record device and method of the present invention; Access real-time parallel process solid state record device comprises the unit such as access parallel processing Solid Recording System control card, multiple access parallel processing solid-state memory card, single card microcomputer; System control card is connected with collection, playback peripheral hardware by peripheral hardware private communication interface, be connected with the more than one solid-state memory card having four groups of independent flash arrays and controller thereof by multi-channel high-speed access communication interface, set up reading and writing two independent data links between any 2 groups of flash arrays in collection, playback peripheral hardware and solid-state memory card, flash array controller performs multi-stage pipeline read/write operation; Access parallel processing solid state record method, record, playback operation is fully hard line parallel processing, adopt equilibrium to write and address Quadratic Map strategy, accelerate the conversion of LBA to PBA; This access real-time parallel process solid state record apparatus and method reach the object that data record and review carries out at a high speed simultaneously.

Accompanying drawing explanation

Fig. 1 is that the one of access real-time parallel process solid state record device of the present invention specifically implements structural representation;

Fig. 2 (A) is a kind of embodiment of access parallel processing system (PPS) control card structure of the present invention;

Fig. 2 (B) is a kind of concrete structure embodiment of Fig. 2 of the present invention (A) described address manager;

Fig. 2 (C) is a kind of specific embodiment of Fig. 2 of the present invention (A) described command frame form;

Fig. 2 (D) is a kind of specific embodiment of Fig. 2 of the present invention (A) described data frame format;

Fig. 2 (E) is that the one of the plate DBMS link configuration of Fig. 2 of the present invention (A) described RAID 10 pattern specifically implements schematic diagram;

Fig. 3 (A) is that the one of access parallel processing solid-state memory card of the present invention specifically implements structural representation;

Fig. 3 (B) is that Fig. 3 of the present invention (A) described read-while writing processing controller one specifically implements structural representation;

Fig. 4 (A) is that schematic diagram implemented by the topological structure of Fig. 3 of the present invention (A) described flash array;

Fig. 4 (B) is a kind of specific embodiment of the flash array streamline write operation described in Fig. 4 of the present invention (A);

Fig. 5 (A) is a kind of specific embodiment that same plane block of the present invention maps;

Fig. 5 (B) is a kind of specific embodiment of the block Quadratic Map of logic-oriented block of the present invention;

Fig. 5 (C) is the concrete storage mode embodiment of one of of the present invention piece of mapping table;

Fig. 6 (A) is the concrete mechanism embodiment of one that strategy is write in hyperchannel of the present invention equilibrium;

Fig. 6 (B) is a kind of specific embodiment of logical blocks write operation Quadratic Map mechanism of the present invention;

Fig. 6 (C) is a kind of specific embodiment of logical blocks read operation Quadratic Map mechanism of the present invention;

Fig. 7 is a kind of embodiment that the present invention accesses the speed and capacity expansion of real-time parallel process solid state record device;

Fig. 8 is that the bad block of access parallel processing solid-state memory card of the present invention detects and create block mapping table process flow diagram.；

Fig. 9 is the access parallel processing process flow diagram of access parallel processing solid state record device of the present invention;

Embodiment

Below in conjunction with accompanying drawing, the specific embodiment of the present invention is described, so that those skilled in the art understands the present invention better.Requiring particular attention is that, in the following description, when perhaps the detailed description of known function and design can desalinate main contents of the present invention, these are described in and will be left in the basket here.

Fig. 1 is that the one that the present invention accesses real-time parallel process solid state record device specifically implements structural representation.

In the present embodiment, as shown in Figure 1, access real-time parallel process solid state record device 10, be made up of access parallel processing Solid Recording System control card (abbreviation system control card), multiple access parallel processing solid-state memory card (abbreviation solid-state memory card), single card microcomputer etc., be installed in a cabinet, as CPCI/CPCIe/VPX/ATCA, in the present embodiment, adopt CPCIe cabinet; System control card is connected with collection, playback peripheral hardware by the optical cable of the peripheral hardware private communication interface of front panel or cable 103,104, single card microcomputer is connected with system control card, solid-state memory card by the PCIe bus 101 of backboard, and system control card is connected with multiple solid-state memory card by SFP+, Mini SAS cable of the multi-channel high-speed access communication interface of front panel or optical cable 105.System control card, according to the setting of RAID 0, RAID 1 or RAID 10, in collection, sets up reading and writing two independent data links between playback peripheral hardware and solid-state memory card, and reading and writing operation parallel processing; Single card microcomputer is connected with system control card, solid-state memory card by management interface controller, and it is detected, configure and monitoring management, wherein, management interface controller can adopt PCI/PCIe or RapidIO interface controller, in the present embodiment, PCIe controller is adopted.

Other computing machine, also by the LAN interface of single card microcomputer, writes data or reading data via management interface controller directly to storage card.

Fig. 2 (A) is a kind of embodiment of access parallel processing system (PPS) control card structure of the present invention.

System control card 20 comprises the unit such as collection peripheral communication interface FMC, playback peripheral communication interface FMC, multi-channel high-speed access communication interface FMC, access parallel processing control device 201, high-speed cache, system configuration memory 202; Access parallel processing control device, adopt FPGA, full hard-wired design, comprises and gathers peripheral communication controller, multi-channel high-speed access communication controller, management interface controller, address manager, data management system 2010, cache controller, system configuration controller etc.; Wherein, data management system comprises the unit such as data frames and stream manager, data aggregate manager, image data impact damper, cache controller; Management interface controller is PCIe controller, is connected with single card microcomputer.The external interface of collection/playback peripheral communication interface FMC meets the electrical specification of collection/playback peripheral hardware, internally adopts the high-speed serial communication based on SerDes, is connected with access parallel processing control device 201; Multi-channel high-speed access communication interface FMC externally adopts SFP+/Mini SAS cable or optical cable, internally adopts the high-speed serial communication based on SerDes, is connected with multi-channel high-speed access communication controller; High-speed cache, adopt QDR SRAM, at the present embodiment, adopt CY7C1165KV18-550BZC, system configuration memory 202 adopts serial ferroelectric memory FM25CL64B-G, for recording the systematic parameter such as peripheral hardware private communication interface channel number and speed, solid-state memory card quantity and capacity, RAID mode, up-to-date write operation LBA, high speed access channel number and speed, when powering on, management software reads these systematic parameters from system configuration memory, be configured to corresponding register, according to up-to-date write operation LBA initialization LA/LBA maker;

If gathering playback rate is 2 of the read-write speed of storage card ⁿdoubly, wherein N is nonnegative integer, and Data Segmentation is become 2 with stream manager by data frames ⁿindividual, form 2 ⁿindividual Frame, is diverted to 2 ⁿindividual solid-state memory card, determines the configuration of RAID 0 accordingly, if N=0, is then normal mode; Basis is the need of data redundancy backup again, determine RAID 1 or RAID 10 pattern, if RAID 1 pattern, then by data distribution to 2 solid-state memory card, if RAID 10 pattern, then to need same number, according to the solid-state memory card mailing to one group 2 mirror images each other simultaneously, to set up RAID 1 pattern, again according to the configuration of RAID 0, by 2 ⁿindividual RAID 1 is combined into RAID 0 pattern, thus sets up RAID 10 pattern; Set up plate DBMS link accordingly.

When starting to record, system control card receives the data gathering peripheral hardware, by collection peripheral communication controller, data are sent to the image data impact damper of data management system 2010, data are sent to data frames and stream manager by data buffer, the LA/LBA maker of address manager counts reception data, by the size of LA divided by a logical blocks, its business is added as writing LBA with initialization LBA, form write command frame, and then Frame is sent, until LBA change, then resend write command frame.In the process performing record, if receive the memory capacity stopping recording instruction or reach pen recorder, recording processing terminates, and the up-to-date LBA of writing is updated to config memory.

During read operation, single card microcomputer is arranged reading logical address or reading offset register by PCIe, address manager draws LA, if read offset address when being more than or equal to 2 logical blocks, address manager then will read the size of LA divided by logical blocks, and its business, as reading LBA, is formed and reads command frame, according to RAID mode, command frame will be read and send to 2 ⁿa group/solid-state memory card, solid-state memory card performs data read operation and sends the data to system control card, system control card carries out the converging operation of data, and reads high-speed cache with reading the remainder initialization read pointer of LA divided by logical blocks size, and reading data are sent to playback peripheral hardware.

Fig. 2 (B) is a kind of concrete structure embodiment of Fig. 2 of the present invention (A) described address manager.Address manager, comprise write operation LA/LBA maker, write operation LBA register, read offset register, read logical address register, 256 solid-state memory card capability register groups, RAID mode register, address process controllers etc., for the address administration of reading and writing parallel processing operations.Before record, RAID mode is sent to the data frames of data management system and stream manager and cohesively managed device by management software, sets up plate level shunt/aggregated links; During record, LA/LBA maker generates LBA, send to data frames and stream manager, for generating write command frame, during playback, address manager is by the read pointer of LA divided by the remainder initialise cache of LBA, 2 logical blocks whether are greater than relative to write address according to reading address, carry out the MUX of control data manager, if be less than or equal to 2 logical blocks, the then direct buffer memory image data of high-speed cache, if be greater than 2 logical blocks, then will read LBA and send to data frames and stream manager to generate to read command frame.

Fig. 2 (C) is a kind of specific embodiment of Fig. 2 of the present invention (A) described command frame form.Comprise SF (Start of Frame, frame starts), read/write instruction, LBA etc.Wherein SF uses the Comma character (certain K character) of RocketIO, and it starts except marker frames, also plays the effect that transmitting synchronous controls.Fig. 2 (D) is a kind of specific embodiment of Fig. 2 of the present invention (A) described data frame format.Comprise SF, user data/instruction response etc., wherein, same Fig. 2 of use (B) of SF; The size of Frame is determined by the reliability of high-speed serial communication, and the present embodiment gets 2048 bytes, before first Frame of a transmission logical blocks, first sends write command frame.

Fig. 2 (E) is that the one of the plate DBMS link configuration of Fig. 2 of the present invention (A) described RAID 10 pattern specifically implements schematic diagram.When peripheral data speed is 4 times of storage card, first by storage card 240 and 241, storage card 242 and 243, storage card 244 and 245, storage card 246 and 247, forms RAID 1 pattern of mirror image each other between two, be combined to form RAID 0 pattern by these four groups again, finally form RAID 10 pattern.

Fig. 3 (A) is that the one of access parallel processing solid-state memory card of the present invention specifically implements structural representation.

In the present embodiment, as shown in Fig. 3 (A), the present invention accesses parallel processing solid-state memory card 30 and comprises the formations such as communication and read-while writing processing controller 301, four-way flash array controller 302, logical blocks mapping table, block mapping table, config memory, front panel communication interface 305, backplane communication interface 303, PCIe interface, four-way flash array.

As shown in Fig. 3 (A), communication and read-while writing processing controller 301, with the full hard-wired design of a slice FPGA, comprise the unit such as address memory controller, read-while writing processing controller, zero access communication controler 3011/3012, PCIe controller 3013, local bus control 3014; Be connected with system control card by front panel/backboard zero access communication interface 305,303, front panel adopts zero access communication FMC form, external employing SFP+/Mini SAS cable or optical cable, internal employing is based on the high-speed serial communication of SerDes, be connected with zero access communication controler 3011, backboard adopts zero access communication controler 3012, is connected with system control card electrical resistance; Address memory controller is deposited with block mapping table, logical blocks mapping table is connected, and is also connected with single card microcomputer by PCIe controller; Local bus control 3014 is connected with four-way flash array controller 302 by local bus 307,308, wherein, local bus 307 adopts the binary channels full-duplex high-speed serial communication based on SerDes, and local bus 308 is for the state-detection of read-write operation;

As shown in Fig. 3 (A), four-way flash array controller 302, with 2 full hard-wired design of FPGA, comprises local bus control's 3021, four independent flash array control units, each flash array controller is connected with one group of flash array, forms four independently read/write access passages.

Fig. 3 (B) is that the read-while writing processing controller one described in Fig. 3 of the present invention (A) specifically implements structural representation.Comprise read-while writing processing state machine, write buffer, read buffer, data frames and scheduler, and four-way is write number of times Parasites Fauna, writes LBA_1, is write PBA, the current LBA_1 of reading, the current PBA of reading, read the registers such as LAB_1 next time.Read-while writing processing state machine monitors read write command frame and command frame, therefrom isolates and writes LBA or read LBA.If write LBA, detect the read-write busy condition of four-way, strategy is write according to hyperchannel equilibrium, write access is determined from idle channel, will by write access be labeled as write busy, create write LBA_1, send to address memory controller, acquisition writes PBA stored in writing PBA register, and data frames and scheduler form write command frame and Frame is sent to the flash array controller of respective channel by high speed serialization local bus; If read LBA, LBA is sent to address memory controller, obtain and read LBA_1 and read PBA, stored in the current LBA_1 of reading with currently read PBA register, will be labeled as by read channel and read to hurry; To LBA+1 be read simultaneously, and obtain and read LBA_1 next time, will be labeled as and read to hurry next time by read channel next time; Data frames and scheduler are formed reads command frame is sent to respective channel flash array controller by high speed serialization local bus, and read data are put into read buffer;

As the topological structure enforcement schematic diagram that Fig. 4 (A) is the flash array as described in Fig. 3 of the present invention.

In the present embodiment, as shown in Fig. 4 (A), flash array has four groups, often organize the die array layout that flash array presses M × N, the I/O bit wide of each die is k, bound by N number of die, its figure place is the increase of kN, bit wide, be equivalent to data distribution, be conducive to the raising of access rate, the increase of pipeline series, be conducive to the continuity and the real-time that improve read-write operation, by the I/O cascade often arranged, M level production line write access M × aN page, this M × aN page is a logical blocks, and wherein a is the number of the plane in a logical block LUN.

Cascade number M is determined by the pipeline series demand replacing die, multi-plane, cache program read-write mode: when performing the programming operation of afterbody streamline write operation to M × N wafer array, the programming of first order streamline write operation completed be in idle condition can be continued on for perform read/write operation, although the programming of the N number of wafer in the second level may also carried out.

In the present embodiment, flash chip adopts MT29F256G08AUCABH3-10IT, there are 4 target its inside, each target has 2 wafer (die, LUN), each die has 2 plane, and each plane has 2048 blocks, each piece has 128 pages, and the page size of each plane is the data segment of 8K byte and the spare area of 448 bytes.At I/O tissue, one single chip can form the die array of 8 I/O of 4 × 2, adopts 4 chips, laterally binds 64 die, forming the die array of 4 × 8, is one group with 4 chips, by upper and lower for M group cascade, form the die array of 4M × 8, wherein, M be more than or equal to 1 integer.

Fig. 4 (B) is a kind of specific embodiment of the flash array streamline write operation described in Fig. 4 of the present invention (A).Solid-state memory card has four passages, and each passage comprises M 64 I/O binding type die ₀, die ₁... die _m, for any 2 passages J, L of performing write operation continuously, wherein, J, L are the integer of 1 ~ 4, and J is not equal to L, M binding type die cascade according to the order of sequence, and each passage forms M × 8 array.In the present embodiment, adopt the M level production line read/write operation of alternately die (LUN), multi-plane, cache program pattern, M × 8 array can be formed M level flowing water write operation 40,41,42 ..., 47.Every level production line write operation comprises the operational phases such as plane 0 instruction/address/data input operation 401, plane 1 instruction/address/data input operation 402, programming 403, state reading 404.The programming operation elapsed time of flash memory is far longer than other stage, again can not programme during programming operation and can not read, read operation then only has command/address/data, 2 stages such as state-detection, relatively easy realization is read fast, for the process of satisfied access real-time parallel, first flash array need ensure continuous write operation, the 1st die complete command/address/data phase send programming instruction enter programming phases time, need not wait for that the programming of this die completes, continue access second die, by that analogy, when in the end a level production line transmission programming instruction enters programming phases, 1st die write operation should complete and enter idle condition, can be used for read/write operation next time.After passage J afterbody streamline sends programming instruction, be labeled as idle channel, wait until read operation, for write operation, strategy is write based on hyperchannel equilibrium, peripheral data is switched to idle channel L, starts new streamline write operation, so can write storage card continuously in real time.

The determination of pipeline series, in this example, as shown in Fig. 4 (B), to each die, adopts 200MHzDDR data I/O and multi-plane write operation, and mainly consuming time is the I/O transmission of 2 plane, and the consuming time of command/address/data phase is t _c, programming consuming time is t _p, the consuming time of state-detection is t _s, the consuming time of complete write operation is: t _wR=2*t _c+ t _p+ t _s, according to uninterrupted write operation principle, then streamline write operation should meet:

M*2*t _c+t _s＞t _WR,M＞t _p/(2*t _c)+1

In the present embodiment, t _pbe 560us to the maximum, t _cbe about 50us, then should there is M > 6.6, it is 8 that M rounds, i.e. 8 level production line write operations, when performing the programming operation of afterbody streamline write operation to the flash array of certain passage, the programming of first order streamline write operation has completed and has been in idle condition, although the programming of the N number of die in the second level remains unfulfilled, but this passage can be continued on for performing read/write operation, therefore, outside would not occur waiting for phenomenon to the read-write operation of flash array;

In the present embodiment, often organize flash array and comprise 2 × 4 flash chips, be made into SO-DIMM (SmallOutline Dual In-line Memory Module) module, convenient for maintaining is changed, often open storage card and have four passages, each passage has 1 SO-DIMM module, now, the continuous real-time storage speed of individual storage card can reach more than 1.2GBps, memory capacity is 1TB, owing to there is bad block in each die, for avoiding the access to bad block, if press the method for logical block index=physical block index, as long as then there is a physics bad block in logical blocks, whole logical blocks all can only be abandoned need not, for the present embodiment, 4096 blocks are had in a die, NVB=4016, then the probability of each piece of as well block is p=0.98, and for the p of logical blocks probability as well ₁₂₈=0.98 ¹²⁸=0.075, the utilization factor of effective storage capacity is too low, and for addressing this problem, the present embodiment adopts block secondary to remap strategy.

Fig. 5 (A) is a kind of specific embodiment that same plane block of the present invention maps.Management software passes through via PCIe bus, by block address BA={CH [1:0], Row [2:0], Col [2:0], B [10:0], PL} carries out bad block detection and erase operation to wafer each on each storage card, set up the bad block list of storage card, form bad block listing file, wherein, CH [1:0], Row [2:0], Col [2:0], B [10:0], PL are respectively passage index, wafer line index, wafer column index, block index, plane index.As shown in Fig. 5 (A), in the present embodiment, each die has 2 plane, each plane has 2048 blocks, the good block of bad block in same plane is replaced, specific strategy is: adopt inverted order mapping policy, the bad block of each plane in each for the flash array of each passage wafer is remapped to the good block of physics of same plane, according to the bad block listing file of solid-state memory card, block in each plane of each wafer is retrieved, if good block, then its physical block number is its mapping block number, if first bad block, then be mapped to the good block of physics that the numbering of same plane is maximum, if second bad block, then be mapped to the good block of physics that the numbering of same plane is second largest, by that analogy, block mapping table of whole wafer in final acquisition solid-state memory card.In the present embodiment, as shown in Fig. 5 (A), plane0 has three bad blocks, plane1 has 2 bad blocks, and after the mapping of LBA to PBA, the active block of plane0 is 4088, the active block of plane1 is 4091, under multi-plane pattern, active block should get the minimum value of the active block number of plane 0 and plane 1, is 4088.Set up block mapping table of die array and the maximum effective value of block of shown in Fig. 4 (A) 8 × 8 successively, save as block map file.

Fig. 5 (B) is a kind of specific embodiment of the block Quadratic Map of logic-oriented block of the present invention.Each piece of a block mapping table is in disperse state, be unfavorable for that logical blocks is changed to physical blocks, therefore block Quadratic Map strategy is adopted, be specially: according to block mapping table, logic-oriented block, is mapped to the physical blocks comprising M × aN block by each logical blocks, form block Quadratic Map table, in the present embodiment, each passage of storage card has 2 ²²=2048 logical blocks, each logical blocks comprises the good block of M × aN=8 × 16 physics, each logical blocks is mapped to the block array of physical blocks 8 × 16, forms the list of block Quadratic Map.

Fig. 5 (C) is the concrete storage mode embodiment of one of of the present invention piece of mapping table.In the present embodiment, often open solid-state memory card and add up to 256 die, 512K block, each piece number can represent with 12, adopt 36 NoBL SRAM, then each storage unit can store the block number of plane 0 and plane 1 simultaneously, in the present embodiment, block map store adopts the CY7C1354C of 256K × 36, utilize LBA_1={PCH [1:0], LB [10:0], PP [6:0] } a high position reconstitute block address BA={PCH [1:0], LB [10:0], Row [2:0], Col [2:0] } addressing is carried out to it, wherein Row and Col is line number and the row number of 8 × 8 wafer arrays, the physical block number of 2 plane can be write at every turn, block Quadratic Map table is write CY7C1354C via PCIe bus by address memory controller by management software.Carrying out recording, playback operation time, by address memory controller, read operation is carried out to CY7C1354C by read-while writing processing controller.For the NoBL SRAM of 200MHz, the time obtaining PB [11:0] (1 × 16) of a logical blocks the first row physical address is about 40ns, for continuous acquisition or the playback of 12Gbps, only cushion the data of about 125 bytes, ensure that the real-time of read/write operation.

Fig. 6 (A) is the concrete mechanism embodiment of one that strategy is write in hyperchannel of the present invention equilibrium.

In the present embodiment, the LBA of solid-state storage device is defined as LBA={LB [10:0], LP [6:0], LCH [1:0] }, the read-while writing processing controller of storage card is according to write command frame first, isolate and write LBA, write time number register with { LB [10:0], LP [6:0] } initialization four-way, its content is { LB [10:0], PP [6:0] }, { LB [10:0], PP [6:0] } is also logical block number in passage, wherein, LCH is logical channel index, and LB is logical block index, and LP is logical page (LPAGE) index, if do not have read operation to occur, four passages are then had to be in idle condition, if there is read operation to occur simultaneously, read operation has read operation hurry and read to hurry next time, take two passages, two passages are then had to be in idle condition, a passage writing least number of times is selected from idle channel, when writing number of times and being identical, the passage that selector channel sequence number is minimum, what make respective channel writes number of times+1, obtain LB ' [10:0], PP ' [6:0] }, if selected physical channel number is PCH, PCH is used to remove to replace the LCH of LBA, arrange the mapping address LBA_1={PCH [1:0] obtaining LBA, LB ' [10:0], PP ' [6:0] }, be recorded to logical blocks mapping table.

Fig. 6 (B) is a kind of specific embodiment of logical blocks write operation Quadratic Map mechanism of the present invention.In the present embodiment, a logical blocks of each streamline read-write operation access, comprises 8 × 16=128 Physical Page, every page is adhered to separately different blocks, if the PBA of each logical blocks of complete documentation, data volume is huge, in the present embodiment, adopt logical blocks Quadratic Map mechanism, be specially:

During write operation, LBA will be write and be mapped as LBA_1.Mechanism is write according to hyperchannel equilibrium, as shown in Fig. 6 (A), obtain LBA_1, in the present embodiment, the logical blocks of each storage card adds up to 4 × 2048 × 128=1M logical blocks, LBA_1 takies three bytes, storage medium adopts QDR SRAM+NOR Flash, NOR Flash is used to be convenient to non-volatilely to preserve at plate, use QDR SRAM to be the parallel processing being convenient to reading and writing operation, in the present embodiment, NOR Flash selects the N25Q032A13ESEA0F of 32Mb, QDR SRAM selects CY7C1165KV18-550BZC, uses LBA to carry out addressing;

LBA_1 is mapped as PBA: according to the once mapping LBA_1={PCH [1:0] obtained, LB [10:0], PP [6:0] }, use { PCH [1:0], LB [10:0], Row [2:0], Col [2:0] } block map store is conducted interviews, obtain 8 × 16 physical block index PB corresponding to logical block index LB of flash array in passage PCH, final acquisition physical block address PBA={PCH [1:0], PB [11:0] (8 × 16), PP [6:0] }, send to the flash array controller of passage PCH [1:0], wherein, Row [2:0], Col [2:0] is respectively line index and the column index of wafer in block.

Fig. 6 (C) is a kind of specific embodiment of logical blocks read operation Quadratic Map mechanism of the present invention.When performing read operation, storage card is isolated and is read LBA from read command frame, first a map operation of LBA to LBA_1 is performed, use LBA={LB [10:0], LP [6:0], LCH [1:0] } addressing is carried out to logical blocks mapping table, obtain and once map LBA_1={PCH [1:0], LB ' [10:0], PP [6:0] }.

Fig. 7 is a kind of embodiment of the speed and capacity expansion of access real-time parallel process solid state record device of the present invention.When the off-capacity of the solid state record device shown in Fig. 1 needs to expand, computing machine 70 by the cable of SFP+, Mini SAS interface of system control card 701 front panel or optical cable 72 access solid state record device 71 ... 78 system control card 711 ... the collection Peripheral Interface of 781, close pen recorder 71 ... the LA/LBA generator of the system control card of 78.Computing machine 70 in register system and each pen recorder 71 ... 78 LAN/Ethernet740 ... 748 is interconnected by switch, system control card 701 is according to the setting of logging mode RAID 0, RAID 1 or RAID 10, set up the Unit Level data link of data distribution/polymerization, realize the memory rate of access real-time parallel process Solid Recording System and the expansion of memory capacity, wherein system control card 701 is called main system control card, all the other are called slave system control card, and slave system control card can be expanded again.

Fig. 8 is that the bad block of solid-state memory card detects and create block mapping table process flow diagram.

In the present embodiment, as shown in Figure 8, the step 2.1 of the corresponding content of the present invention in step ST211 ~ 212), the step 2.2 of the corresponding content of the present invention in step ST22 ~ 23), 2.3), the step 3.1 of the corresponding content of the present invention of step ST31), the step 3.2 of the corresponding content of the present invention in step ST321 ~ 322).

It should be noted that, in the present embodiment, as Fig. 5 (A), 5 (B), shown in 5 (C), logical block is 2048, number of pages is 128, port number is 4, thus have LBA={LB [10:0], LP [6:0], LCH [1:0] }, total logical blocks number=4 × 2048 × 128=1048576, physical block number=M × aN=8 × 16 of a logical blocks, physical block address PBA={PCH [1:0], PB [11:0] (8 × 16), PP [6:0] }, actual size M × aN × P=8 × 16 × the 128=1MB of a block, wherein, M, N is the row of M × N wafer array, train value, a is the number of plane in each wafer, P is the size of each Physical Page in wafer,

When performing the operations such as the detection of bad block, erasing, block address BA={PCH [1:0], Row [1:0], Col [1:0], B [10:0], PL}}; Nominal active block number NVB=4016, when detecting that the active block number of certain chip block is less than NVB, needs to change this flash chip;

When performing step ST31, the block with plane once remaps, and adopt inverted order mapping policy, step and method are as shown in Fig. 5 (A); When performing step ST321, the Quadratic Map of logic-oriented block addressing, method is as shown in Fig. 5 (B); When performing step ST322, single card microcomputer is by PCIe bus by block Quadratic Map list write-in block map store, and its store method is as shown in Fig. 5 (C).

Fig. 9 is the access parallel processing process flow diagram of access parallel processing solid state record device of the present invention.

In the present embodiment, as shown in Figure 9, the step (4) of the corresponding content of the present invention of step ST40, the step 5.1 of the corresponding content of the present invention of step ST51), the step 5.2 of the corresponding content of the present invention in step ST521 ~ 522), the step 5.3 of the corresponding content of the present invention in step ST531 ~ 532), the step 5.4 of the corresponding content of the present invention of step ST54 ~ ST56), 5.5), 5.6), the step 5.7 of the corresponding content of the present invention in step ST571 ~ 572), the step 5.8 of the corresponding content of the present invention of step ST58), the step 5.9 of the corresponding content of the present invention in step ST591 ~ 592), the step 5.10 of the corresponding content of the present invention of step ST5100), the step 5.11 of the corresponding content of the present invention of step ST5111 ~ ST5113), the step 5.12 of the corresponding content of the present invention of step ST5120), the step 5.13 of the corresponding content of the present invention of step ST5131 ~ ST5132), the step 5.14 of the corresponding content of the present invention of step ST5140).

It should be noted that, in the present embodiment, LBA={LB [10:0], LP [6:0], LCH [1:0] }, PBA={PCH [1:0], PB [11:0] (8 × 16), PP [6:0] }, for Solid Recording System described in Fig. 7, except main system control card 701, need closedown fall system control card 711 ... the LA/LBA maker of 781.When performing step ST531 ~ 532, adopt the balanced write-in policy of four-way, its concrete grammar is as shown in Fig. 6 (A), carry out second level address mapping to writing LBA, its concrete grammar as shown in Fig. 6 (B), secondary addressing block address BA={PCH used [1:0], LB [10:0], Row [2:0], Col [2:0] }, its selected cell comprises in same die the index of 2 blocks adhering to different plane separately; When performing step ST591 ~ 592, carry out second level address mapping to writing LBA, its concrete grammar is as shown in Fig. 6 (C).

Although be described the illustrative embodiment of the present invention above; so that those skilled in the art understand the present invention; but should be clear; the invention is not restricted to the scope of embodiment; to those skilled in the art; as long as various change to limit and in the spirit and scope of the present invention determined, these changes are apparent, and all innovation and creation utilizing the present invention to conceive are all at the row of protection in appended claim.

Claims

1. one kind accesses the solid state record device of real-time parallel process, it is characterized in that, comprising: access parallel processing Solid Recording System control card (hereinafter referred to as system control card), multiple access parallel processing solid-state memory card (hereinafter referred to as solid-state memory card), a single card microcomputer;

2. the solid state record device of access real-time parallel according to claim 1 process, it is characterized in that, described system control card, adopt full hard-wired design, comprise peripheral hardware private communication interface, multi-channel high-speed access communication interface, access parallel processing control device, high-speed cache, and config memory;

Wherein, described address manager, comprise write operation LA/LBA (Logic Block Address, logical block addresses) maker, write operation LBA register, read offset register, read logical address LA (Logic Address, logical address) register, solid-state memory card capability register group, RAID mode register, address process controller; Generate for write operation LBA, read that logical address calculates, the read pointer initialization of high-speed cache and generate control, the address search of plate level, the shunting of data and aggregation scheme control etc.;

Wherein, described data management system, comprises data frames and shunting, data aggregate, image data impact damper, cache controller, and the format of frame lattice and shunting, solid-state memory card for peripheral data read the parallel processing of data aggregate;

3. the solid state record device of access real-time parallel according to claim 1 process, it is characterized in that, described solid-state memory card, adopt full hard-wired design, comprise zero access communication interface, communication and read-while writing processing controller, block map store, logical blocks map store, four independently flash array, four independently flash array controllers, and config memory;

Described communication and read-while writing processing controller, comprise address memory controller, read-while writing processing controller, zero access communication controler, PCIe controller, and local bus control, be connected with zero access communication interface, block map store, logical blocks map store, four independent flash array control units, for data communication, address, data link, Frame, flash memory access, single card microcomputer configuration and the real-time parallel process monitored; Wherein, read-while writing processing controller comprises read-while writing processing state machine, data frames and scheduler, write buffer, read buffer, and four-way is write number of times, writes LBA_1, write PBA, the current LBA_1 of reading, the current PBA of reading, read the registers such as LAB_1 next time; Address memory controller, for the Read-write Catrol of logical blocks map store, block map store, is connected with read-while writing processing controller simultaneously, solid-state memory card and veneer function is managed block mapping table and logical blocks mapping table;

Described four independent flash array control units, adopt alternately die (wafer), multi-plane, cache program pattern to flash array perform multi-stage pipeline ECC, read/programme, the operation such as status register reading;

4. the solid state record device of access real-time parallel according to claim 2 process, is characterized in that, described flash array, adopt M × N wafer array layout, wherein, N is determined by access bandwidth and I/O bit wide, and M is determined by the real-time continuous of four-way flash array read/write operation; Flash array controller adopts alternately die (wafer), multi-plane, cache program pattern to implement the read/write operation of M level production line to the flash array be attached thereto, when M × N wafer array of certain passage being performed to afterbody streamline write operation

During programming operation, the programming of first order streamline write operation completed be in idle condition can be continued on for perform read/write operation, although the programming of the N number of wafer in the second level may also carried out.

5. access real-time parallel process solid state record device according to claim 4, is characterized in that, described M level production line read/write operation, the page array of each access M × aN, this M × aN page array is a block, and in block, the numbering of each page is identical, block address LBA={ logical block index, logical page (LPAGE) index, logical channel index }, block size is M × aN × P, wherein, P is page size, and unit is byte; The PBA={ physical channel index that LBA is corresponding, M × aN physical block index, Physical Page index }, wherein, M, N are the layout parameter of M × N wafer array, and a is the number of plane in each wafer.

6. the solid state record device of the access real-time parallel process according to Claims 2 or 3, it is characterized in that, described management interface controller adopts PCI/PCIe or RapidIO interface, for single card microcomputer connected system control card and solid-state memory card, and system control card and solid-state memory card are managed.

7. one kind utilizes the access real-time parallel process Solid Recording System of multiple solid state record device composition according to claim 1, it is characterized in that, main system control card is installed in computing machine, by the multichannel access communication interface of front panel, be connected with the peripheral hardware private communication interface of slave system control card in each solid state record device, there is the RAID 0 of Unit Level, RAID 1, RAID 10 mode of operation, realize the expansion of memory rate and capacity.

8. utilize the solid state record device described in claim 1 to carry out accessing a method for real-time parallel process, it is characterized in that, comprise the following steps:

(1), systematic parameter load, initialization of register

(2), solid-state memory card carries out bad block check processing

(3) solid-state storage fixture block mapping table, is created

3.2), the block secondary of logic-oriented block addressing maps: according to block mapping table, each logical blocks is mapped to the physical blocks comprising all physical block numbers in block, forms block mapping table, save as file;

(5), the access parallel processing of collection and playback

5.3.2) LBA_1 is mapped as PBA: carry out an addressing according to LBA mapping address LBA_1 to block mapping table, obtains the index of all physical blocks in a logical blocks, obtains physical block address PBA, carry out step 5.4);

5.7.2) if the offset address of read operation is in the size of 2 logical blocks, LBA, reading length are packaged as and read command frame by system control card, check whether write command frame or write data frame send, if, wait for that it completes, if not, then send and read command frame and Frame to target solid-state memory card, execution step 5.8);

5.9) the Quadratic Map operation of reading LBA to PBA, is performed:

5.14), system control card checks whether the stopping play-back command receiving single card microcomputer and send over, if do not receive stopping playback command, perform step 5.13), if receive stopping play-back command, then send to solid-state memory card and stop play-back command, playback process terminates;

End process;

Wherein, described hyperchannel equilibrium is written as:

Wherein, described LBA_1 is mapped as PBA: