CN116795765B

CN116795765B - Data alignment method and device for high-speed data transmission

Info

Publication number: CN116795765B
Application number: CN202311094335.XA
Authority: CN
Inventors: 王亚宁
Original assignee: Xinyaohui Technology Co ltd
Current assignee: Xinyaohui Technology Co ltd
Priority date: 2023-08-29
Filing date: 2023-08-29
Publication date: 2023-12-08
Anticipated expiration: 2043-08-29
Also published as: CN116795765A

Abstract

The application provides a data alignment method and device for high-speed data transmission. The method comprises the following steps: detecting the distribution of the same control character used for data alignment between front and rear beats of parallel port data in a parallel port data signal by a detection circuit, determining the data misalignment degree of the parallel port data signal based on the distribution so as to generate a detection signal, wherein the parallel port data signal is multi-beat parallel port data obtained by sampling a differential serial signal according to a parallel port clock signal, and the parallel port clock signal is obtained by dividing the frequency of the serial port clock signal by a clock frequency dividing circuit; the clock adjusting circuit generates a clock adjusting signal according to the detection signal, sends the clock adjusting signal to the clock frequency dividing circuit, and changes the phase of the parallel port clock signal output by the clock frequency dividing circuit by using the clock adjusting signal, so that the data misalignment degree of the parallel port data signal measured by the detection circuit later is reduced. This saves resources and reduces latency.

Description

Data alignment method and device for high-speed data transmission

Technical Field

The present application relates to the field of computer technologies, and in particular, to a data alignment method and apparatus for high-speed data transmission.

Background

In high-speed digital transmission application, differential serial signals are generally adopted for high-speed data transmission, a receiving end recovers serial signals through a clock data recovery circuit to obtain serial port clocks, the serial port clocks are divided to obtain parallel port clocks, and the parallel port clocks are used for recovering data from the serial signals to obtain parallel port data. Subsequent circuits perform data alignment, requiring the identification of special codewords, e.g., version 6.0 of the high-speed serial computer expansion bus standard (Peripheral Component Interconnect Express, PCIe) defines a specific coding scheme and special codewords. In the prior art, the parallel port data are spliced, then special code words required by addressing are arranged in the spliced data, and the positions of the code words in the spliced data are random, so that the delay loss is also random, and the maximum possible delay loss is increased along with the increase of the bit width of the parallel port data. Along with the increasing data transmission rate, the width of parallel port data bits is also increased, the negative effect caused by delay loss generated in the data alignment link is also more and more obvious, and the stability of data transmission is not maintained because of the randomness of the delay loss.

Therefore, the application provides a data alignment method and a data alignment device for high-speed data transmission, which are used for solving the technical problems existing in the prior art.

Disclosure of Invention

In a first aspect, the present application provides a data alignment method for high speed data transmission. The data alignment method is applied to a data alignment device, and the data alignment device comprises a detection circuit and a clock adjustment circuit, wherein the clock adjustment circuit is connected with the detection circuit and the clock frequency division circuit. The data alignment method comprises the following steps: detecting the distribution of the same control character used for data alignment between front and rear beats of parallel port data in a parallel port data signal by the detection circuit, and determining the data misalignment degree of the parallel port data signal based on the distribution so as to generate a detection signal, wherein the parallel port data signal is multi-beat parallel port data obtained by sampling a differential serial signal according to a parallel port clock signal, the parallel port clock signal is obtained by dividing the frequency of a serial port clock signal by the clock frequency dividing circuit, and the serial port clock signal is recovered from the differential serial signal; and generating a clock adjustment signal according to the detection signal by the clock adjustment circuit, sending the clock adjustment signal to the clock frequency division circuit, and changing the phase of the parallel port clock signal output by the clock frequency division circuit by using the clock adjustment signal, so that the data misalignment degree of the parallel port data signal measured by the detection circuit later is reduced.

According to the first aspect of the application, a feedback loop design from measuring the data misalignment degree of the parallel port data signals to generating detection signals, generating clock adjustment signals according to the detection signals and then changing the phase of the parallel port clock signals output by the clock frequency dividing circuit by using the clock adjustment signals is constructed by using the detection circuit and the clock adjustment circuit, so that the data alignment design purpose is finally realized by reducing the data misalignment degree of the parallel port data signals measured by the detection circuit later; the method integrates the related execution details of the data alignment link into the improvement of the frequency division operation of obtaining the parallel port clock signal by frequency division of the serial port clock signal and the sampling operation of obtaining the parallel port data signal by sampling the differential serial signal according to the parallel port clock signal, does not need to carry out additional buffering and processing on the parallel port data signal, and can send the parallel port data signal output by the serial-to-parallel circuit after the data alignment is completed to the elastic buffering for subsequent processing together with the parallel port clock signal, thereby not needing to carry out additional buffering and processing on the parallel port data signal, saving resources and being beneficial to reducing processing delay.

In a possible implementation manner of the first aspect of the present application, the same control character includes a plurality of bits in succession, and the distribution is a number of bits in which the plurality of bits are distributed between the two-beat parallel port data.

In a possible implementation manner of the first aspect of the present application, the degree of data misalignment of the parallel port data signal is the number of bits of the parallel port data of the next beat of the parallel port data of the front and rear two beats of the parallel port data distributed by the same control character.

In a possible implementation manner of the first aspect of the present application, the degree of data misalignment of the parallel port data signals indicates a unit time interval difference of a front side or a rear side of the same control character with respect to a boundary of the front and rear two beats of parallel port data.

In a possible implementation manner of the first aspect of the present application, the boundary of the multi-beat parallel port data is determined based on a sampling clock edge of the parallel port clock signal, and the clock adjustment circuit changes a phase of the parallel port clock signal by using the clock adjustment signal so as to reduce a phase difference of a front side of a control character in the parallel port data signal measured later by the detection circuit relative to the sampling clock edge.

In a possible implementation manner of the first aspect of the present application, the sampling clock edge is a rising clock edge.

In a possible implementation manner of the first aspect of the present application, the differential serial signal is used for high-speed data transmission from a transmitting end to a receiving end, the data alignment device is disposed at the receiving end, and the same control character is inserted into the differential serial signal at the transmitting end for data alignment at the receiving end.

In a possible implementation manner of the first aspect of the present application, a codec scheme for high-speed data transmission between the transmitting end and the receiving end defines a plurality of special codewords, the same control word being any one of the plurality of special codewords, and the plurality of special codewords being inserted into the differential serial signal at the transmitting end at fixed intervals or at non-fixed intervals.

In a possible implementation manner of the first aspect of the present application, the clock adjustment signal is used to change the phase of the parallel port clock signal output by the clock frequency division circuit, so that the number of bits of the next parallel port data in the two front and rear parallel port data in the parallel port data signal, which is measured by the detection circuit later, is zero.

In a possible implementation manner of the first aspect of the present application, the clock adjustment circuit changes, with the clock adjustment signal, a phase of the parallel port clock signal output by the clock frequency division circuit so that a unit time interval difference of a front side or a rear side of the same control character measured later by the detection circuit with respect to a boundary of the front and rear two beats of parallel port data is zero.

In a possible implementation manner of the first aspect of the present application, the clock adjustment signal is used to change the phase of the parallel port clock signal output by the clock frequency division circuit so that the front side of the control character in the parallel port data signal measured later by the detection circuit is aligned with the sampling clock edge.

In a possible implementation manner of the first aspect of the present application, the clock adjustment circuit includes a clock gating circuit, the clock gating circuit outputs an enable clock signal to the clock frequency division circuit, the clock frequency division circuit is configured to divide the serial clock signal by a bit width of the parallel port data signal when the enable clock signal indicates to be on, the clock gating circuit is configured to generate the clock adjustment signal according to the detection signal, and the clock adjustment signal causes the enable clock signal to indicate to be off in a first clock cycle so that the parallel port clock signal output by the clock frequency division circuit is delayed by the first clock cycle.

In a possible implementation manner of the first aspect of the present application, the enable clock signal is turned on when being set high, and the enable clock signal is turned off when being pulled low, and the clock gating circuit is configured to pull down the enable clock signal in the first clock cycle according to the detection signal, so that the parallel port clock signal output by the clock dividing circuit is delayed by the first clock cycle and in turn the parallel port data signal obtained by sampling the differential serial signal according to the delayed parallel port clock signal is delayed by a first beat number associated with the first clock cycle.

In a possible implementation manner of the first aspect of the present application, the data alignment method further includes: and the detection circuit and the clock adjustment circuit enter a low-power consumption state in response to the clock adjustment circuit reducing the data misalignment degree of the parallel port data signal measured by the detection circuit to zero.

In a second aspect, embodiments of the present application further provide a computer device, the computer device including a memory, a processor, and a computer program stored on the memory and executable on the processor, the processor implementing a method according to any one of the implementations of any one of the above aspects when the computer program is executed.

In a third aspect, embodiments of the present application also provide a computer-readable storage medium storing computer instructions that, when run on a computer device, cause the computer device to perform a method according to any one of the implementations of any one of the above aspects.

In a fourth aspect, embodiments of the present application also provide a computer program product comprising instructions stored on a computer-readable storage medium, which when run on a computer device, cause the computer device to perform a method according to any one of the implementations of any one of the above aspects.

In a fifth aspect, the embodiment of the present application further provides a data alignment device for high-speed data transmission. The data alignment apparatus includes: a detection circuit for: detecting the distribution of the same control character used for data alignment between two front and rear beats of parallel port data in a parallel port data signal, and determining the data misalignment degree of the parallel port data signal based on the distribution so as to generate a detection signal, wherein the parallel port data signal is multi-beat parallel port data obtained by sampling a differential serial signal according to a parallel port clock signal, the parallel port clock signal is obtained by dividing a serial port clock signal through a clock frequency dividing circuit, and the serial port clock signal is recovered from the differential serial signal; the clock adjusting circuit is connected with the detecting circuit and the clock frequency dividing circuit and is used for: generating a clock adjustment signal according to the detection signal, sending the clock adjustment signal to the clock frequency division circuit, and changing the phase of the parallel port clock signal output by the clock frequency division circuit by utilizing the clock adjustment signal, so that the data misalignment degree of the parallel port data signal measured by the detection circuit later is reduced.

In a possible implementation manner of the fifth aspect of the present application, the data alignment device belongs to a receiving end system, and the receiving end system includes: the differential receiving circuit is used for receiving the differential serial signal, the clock data recovery circuit is used for recovering the serial port clock signal from the differential serial signal, the clock frequency division circuit is used for dividing the serial port clock signal to obtain the parallel port clock signal, and the serial-to-parallel circuit is used for sampling the differential serial signal according to the parallel port clock signal to obtain the parallel port data signal.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a flow chart of a data alignment method for high-speed data transmission according to an embodiment of the present application;

fig. 2 is a schematic diagram of a data alignment device for high-speed data transmission according to an embodiment of the present application;

Fig. 3 is a schematic diagram of a receiving end system including the data alignment device shown in fig. 2 according to an embodiment of the present application;

FIG. 4 is a schematic diagram of an implementation of the data alignment apparatus shown in FIG. 2 according to an embodiment of the present application;

FIG. 5 is a schematic diagram of a parallel port clock signal before and after phase adjustment according to an embodiment of the present application;

fig. 6 is a schematic structural diagram of a computing device according to an embodiment of the present application.

Detailed Description

Embodiments of the present application will be described in further detail below with reference to the accompanying drawings.

It should be understood that in the description of the application, "at least one" means one or more than one, and "a plurality" means two or more than two. In addition, the words "first," "second," and the like, unless otherwise indicated, are used solely for the purposes of description and are not to be construed as indicating or implying a relative importance or order.

Fig. 1 is a flow chart of a data alignment method for high-speed data transmission according to an embodiment of the present application. The data alignment method is applied to a data alignment device, and the data alignment device comprises a detection circuit and a clock adjustment circuit, wherein the clock adjustment circuit is connected with the detection circuit and the clock frequency division circuit. As shown in fig. 1, the data alignment method includes the following steps.

Step S110: and detecting the distribution of the same control character used for data alignment between front and rear beats of parallel port data in the parallel port data signals through the detection circuit, and determining the data misalignment degree of the parallel port data signals based on the distribution so as to generate detection signals, wherein the parallel port data signals are multiple beats of parallel port data obtained by sampling differential serial signals according to parallel port clock signals, the parallel port clock signals are obtained by frequency division of serial port clock signals through the clock frequency division circuit, and the serial port clock signals are recovered from the differential serial signals.

Step S120: and generating a clock adjustment signal according to the detection signal by the clock adjustment circuit, sending the clock adjustment signal to the clock frequency division circuit, and changing the phase of the parallel port clock signal output by the clock frequency division circuit by using the clock adjustment signal, so that the data misalignment degree of the parallel port data signal measured by the detection circuit later is reduced.

In related applications of high-speed digital transmission, such as a serial de-Serializer (SERDES) system, differential serial signals are generally used for high-speed data transmission, and a receiving end recovers a serial clock from the serial signals through a clock data recovery (Clock and Data Recovery, CDR) circuit, and divides the serial clock to obtain a parallel clock. The parallel port clock is used for recovering the data signal from the serial signal, thus obtaining the parallel port data signal, and converting the serial signal into the parallel signal, namely the parallel port signal, and synchronizing the parallel port clock signal and the parallel port data signal. Next, the parallel data signal is data aligned with the parallel clock signal. The parallel port data signals are spliced to obtain spliced data (concaterate), and then the spliced data are sampled according to the periodical change of the parallel port clock signals, such as rising edges and falling edges, and special code words are identified from sampling results. The special codeword is added to the differential serial signal at the transmitting end for data alignment at the receiving end. For example, the data transmission specification and protocol of the universal serial bus (Universal Serial Bus, USB) defines an 8B/10B codec scheme, encoding 12 special characters into 12 control characters. These control characters are used for data alignment, for example, by aligning data to words, for clock correction, block synchronization, etc. Because the spliced data obtained by splicing the parallel port data has certain randomness, the specific position of the special code word (control character) for data alignment in the spliced data is also random. Furthermore, the addition of special codewords or control characters at the transmitting end may or may not be fixed to the interval of the differential serial signal, which further makes it difficult to predict the specific location of the special codewords (control characters) for data alignment. The delay of the data alignment stage in addressing the special code words required in the spliced data is therefore difficult to predict, and the maximum possible delay loss increases with the increase of the bit width of the parallel port data. Along with the increasing data transmission rate, the width of parallel port data bits is also increased, the negative effect caused by delay loss generated in the data alignment link is also more and more obvious, and the stability of data transmission is not maintained because of the randomness of the delay loss. For example, assuming that a certain control character occupies a total of 8 bits, a portion of the parallel data signal of the previous beat and a portion of the parallel data signal of the next beat, this is due to misalignment between the spliced data and the parallel clock signal. For data alignment, all the complete special code words need to be found, which causes delay loss of at least one beat of parallel port data length. The delay loss calculation is in units of Unit Intervals (UIs). If the parallel port data bit width is N bits (N is a positive integer greater than 1), N UIs are corresponding. The current beat of parallel port data comprises 7 bits of special code words of 8 bits, and the rest special code words of 1 bit are in the subsequent beat of parallel port data, so that the delay loss is N-1, namely 7 UI. The delay is more pronounced when the parallel port data bit width is larger, for example, when the parallel port data bit width is 40 bits, corresponding to 40 UIs, which means that the delay penalty may be 40 minus 1 for 39 UIs. High-speed data transmission applications, such as the scenario where the SERDES system uses high-speed differential serial signals for data transmission, must undergo data alignment to determine the special code words specified by the communication protocol coding scheme and to implement beat-to-beat transmission between parallel port data and parallel port clocks, which necessarily results in delay loss. In addition, generally, after the data alignment link, beat-to-beat transmission is realized between the parallel port data signal and the parallel port clock signal, and the parallel port data signal is sent to the subsequent elastic buffer. The elastic buffer is used for absorbing frequency difference and phase difference between local clocks of the sending end and the receiving end respectively. Thus delay loss in the data alignment link affects overall system efficiency and processing delay.

In the data alignment method for high-speed data transmission shown in fig. 1, in step S110, a distribution of the same control character for data alignment between two consecutive beats of parallel port data in a parallel port data signal is detected by the detection circuit, and a degree of data misalignment of the parallel port data signal is measured based on the distribution to generate a detection signal. The detection circuit is used for detecting the parallel port data signal output by the serial-to-parallel circuit and the parallel port clock signal output by the clock frequency division circuit, so as to determine the distribution of the same control character used for data alignment between two beats of parallel port data in the parallel port data signal, such as the UI difference value of the boundary between the output and the expected code word. In step S120, a clock adjustment signal is generated according to the detection signal by the clock adjustment circuit, the clock adjustment signal is sent to the clock frequency division circuit, and the phase of the parallel port clock signal output by the clock frequency division circuit is changed by using the clock adjustment signal, so as to reduce the degree of data misalignment of the parallel port data signal measured by the detection circuit. Thus, the data alignment method for high-speed data transmission shown in fig. 1 constructs a feedback loop design from measuring the data misalignment degree of the parallel port data signals to generating detection signals, generating clock adjustment signals according to the detection signals, and then changing the phase of the parallel port clock signals output by the clock frequency division circuit by using the clock adjustment signals, and realizes the design purpose of reducing the data misalignment degree of the parallel port data signals measured by the detection circuits later so as to finally realize data alignment. In one possible implementation, the clock adjustment circuit may include, for example, a clock gating circuit that pulls the enable clock signal down by the number of beats corresponding to the UI difference value, which means that the clock divider circuit is turned off for the clock period corresponding to the number of beats. In these clock cycles when the clock dividing circuit is turned off, the signal to be divided, i.e. the serial clock signal, is not divided by the calculation, which means that the divided signal output by the clock dividing circuit, i.e. the parallel clock signal, is delayed by the corresponding clock cycle. Therefore, the first UI difference detected by the detecting circuit is used for pulling down a first beat number corresponding to the first UI difference of the enabling clock signal by the clock gating circuit, then causing the clock frequency dividing circuit to close a first number of clock cycles corresponding to the first beat number, and finally causing the parallel port clock signal to be delayed by the first number of clock cycles. Thus, a feedback loop is formed, and the larger UI difference value can lead to the parallel port clock signal to be delayed for more clock cycles, so that the UI difference value can be quickly converged. By means of the feedback loop design, the UI difference value detected by the detection circuit is reduced, namely the data misalignment degree of the parallel port data signals detected by the detection circuit is reduced, and finally the UI difference value is zero, which means that data alignment is completed, and the data alignment can be directly sent to the elastic buffer. It should be understood that the clock adjustment circuit may use a clock gating circuit to construct the feedback loop, or may use other circuits, hardware, devices, etc. to construct the feedback loop, so long as the characteristics that the higher the data misalignment of the parallel port data signal measured by the detection circuit, the higher the feedback and the faster the convergence can be achieved. For example, by measuring a UI difference or other value reflecting the degree of misalignment of the data of the parallel port data signals and converting the measured value into a detection signal; the clock adjustment circuit may include a device such as a counter, an inverter, etc. for generating a data adjustment signal based on the degree of data misalignment of the parallel port data signal reflected by the detection signal, for the purpose of rapid convergence.

It should be understood that the data alignment method for high-speed data transmission shown in fig. 1 uses the clock adjustment signal to change the phase of the parallel port clock signal output by the clock frequency dividing circuit, so as to reduce the degree of data misalignment of the parallel port data signal measured by the detecting circuit. The distribution of the same control character for data alignment between two front and rear beats of parallel port data in the parallel port data signal is changed by changing the phase of the parallel port clock signal, wherein the parallel port data signal is multiple beats of parallel port data obtained by sampling a differential serial signal according to the parallel port clock signal. That is, the data alignment method for high-speed data transmission shown in fig. 1 achieves the data alignment purpose by adjusting the phase of the parallel port clock signal, which has smaller delay and simpler circuit implementation details than the method of adjusting the parallel port data signal to achieve the data alignment purpose. If the data misalignment of the parallel port data signal is reduced by adjusting the parallel port data signal, it means that the front edge or the back edge of the parallel port data signal is adjusted with reference to a certain reference clock pulse, for example, the front edge or the back edge of the data is aligned with the front edge or the back edge of the clock pulse or the data is moved to the center of the clock pulse edge, which necessarily introduces an additional circuit structure to buffer and process the parallel port data signal, thereby causing a larger delay. In contrast, in the data alignment method for high-speed data transmission shown in fig. 1 provided by the embodiment of the present application, the data misalignment degree of the parallel port data signal is reduced by adjusting the phase of the parallel port clock signal, on one hand, the parallel port data signal output by the serial parallel circuit and the parallel port clock signal output by the clock frequency dividing circuit are detected by the detection circuit, so as to determine the data misalignment degree of the parallel port data signal (based on the distribution of the same control character for data alignment between two beats of parallel port data in the parallel port data signal), and on the other hand, the clock adjustment signal is sent to the clock frequency dividing circuit by the clock adjustment circuit (the parallel port clock signal is obtained by frequency dividing the serial port clock signal by the clock frequency dividing circuit), so that the frequency dividing operation of the clock frequency dividing circuit is affected by the clock adjustment signal, and the phase of the parallel port clock signal output by the clock frequency dividing circuit is changed. The data alignment method for high-speed data transmission shown in fig. 1 does not need to perform additional buffering and processing on parallel port data signals, so that resources are saved and processing delay is reduced. Because the serial-parallel circuit or similar module is used for sampling the differential serial signal according to the parallel clock signal to obtain the parallel data signal, namely multi-beat parallel data, the clock adjustment circuit utilizes the clock adjustment signal to influence the frequency division operation of the clock frequency division circuit so as to change the phase of the parallel clock signal output by the clock frequency division circuit, and the serial-parallel circuit is influenced to sample the parallel data signal obtained according to the parallel clock signal with the changed phase. Therefore, the data alignment method for high-speed data transmission shown in fig. 1 reduces the data misalignment degree of the parallel port data signal by adjusting the phase of the parallel port clock signal, and needs to influence the operation of the serial-to-parallel circuit and the clock frequency dividing circuit. Therefore, an additional data alignment module is not required to be provided after the serial-parallel circuit for data buffering and alignment processing, but an elastic buffer can be directly connected after the serial-parallel circuit, and the parallel port data signal output by the serial-parallel circuit after the data alignment is completed can be sent to the elastic buffer together with the parallel port clock signal for subsequent processing because the parallel port data signal already meets the data alignment requirement.

In summary, the data alignment method for high-speed data transmission shown in fig. 1 utilizes a detection circuit and a clock adjustment circuit to construct a feedback loop design from determining the data misalignment degree of the parallel port data signal to generating a detection signal, generating a clock adjustment signal according to the detection signal, and then changing the phase of the parallel port clock signal output by the clock frequency division circuit by using the clock adjustment signal, thereby realizing the design purpose of reducing the data misalignment degree of the parallel port data signal measured by the detection circuit at a later time so as to finally realize data alignment; the related execution details of the data alignment link are integrated into the improvement of the frequency division operation of obtaining the parallel port clock signal by frequency division of the serial port clock signal and the sampling operation of obtaining the parallel port data signal by sampling the differential serial signal according to the parallel port clock signal, the parallel port data signal does not need to be additionally cached and processed, and the parallel port data signal output by the serial-to-parallel circuit after the data alignment is completed can be sent to the elastic cache together with the parallel port clock signal for subsequent processing, so that the parallel port data signal does not need to be additionally cached and processed, resources are saved, and the processing delay is reduced; and further, since the data misalignment degree of the parallel port data signal is reduced by adjusting the phase of the parallel port clock signal (compared with the adjustment of the parallel port data signal to achieve the data alignment purpose) and the rapid convergence is achieved based on the feedback loop design, various modes of inserting control characters or special code words at the transmitting end, such as equidistant insertion or unequal interval insertion, can be flexibly dealt with, various coding and decoding schemes of the data transmission protocol can be flexibly dealt with, and rapid response can be rapidly made to various emergency situations (such as network communication conditions, data flow changes and the like) in practical application. In some examples, a UI difference, such as a UI difference that outputs a boundary with a desired codeword, may be employed as a quantization index for the determined degree of data misalignment of the parallel port data signal. The UI difference is detected from the parallel data signal output from the serial-parallel circuit, for example, by monitoring the distribution of the same control character between every two adjacent beats of parallel data in the parallel data signal in real time or at intervals. And then the UI difference value is used for controlling the clock gating circuit, so that the parallel port clock signal is delayed, the distribution of the same control character measured later between two adjacent beats of parallel port data is changed, and the same control character is not distributed in the next beat of parallel port data, namely 0 bit. Because the parallel port clock signal is regulated based on the detection result of the parallel port data signal, the data alignment is realized, the parallel port clock signal can be suitable for any insertion mode of control characters, can also be suitable for the situation of insertion at higher or lower frequency, and is simple to realize and low in delay.

Fig. 2 is a schematic diagram of a data alignment device for high-speed data transmission according to an embodiment of the present application. The data alignment apparatus includes: detection circuit 210 for: detecting the distribution of the same control character used for data alignment between two beats of parallel port data in a parallel port data signal 202, and determining the data misalignment degree of the parallel port data signal 202 based on the distribution so as to generate a detection signal 204, wherein the parallel port data signal 202 is multi-beat parallel port data obtained by sampling a differential serial signal according to a parallel port clock signal, the parallel port clock signal is obtained by dividing a serial port clock signal by a clock frequency dividing circuit, and the serial port clock signal is recovered from the differential serial signal; a clock adjustment circuit 220 connected to the detection circuit 210 and the clock dividing circuit, the clock adjustment circuit 220 being configured to: generating a clock adjustment signal 206 according to the detection signal 204, sending the clock adjustment signal 206 to the clock frequency division circuit, and changing the phase of the parallel port clock signal output by the clock frequency division circuit by using the clock adjustment signal 206, so as to reduce the data misalignment degree of the parallel port data signal 202 measured by the detection circuit later.

The data alignment device for high-speed data transmission shown in fig. 2 is constructed by using a detection circuit 210 and a clock adjustment circuit 220 from the measurement of the data misalignment degree of the parallel port data signal 202 to the generation of a detection signal 204, to the generation of a clock adjustment signal 206 according to the detection signal 204, and to the design of a feedback loop for changing the phase of the parallel port clock signal 201 output by the clock frequency division circuit by using the clock adjustment signal 206, so that the design purpose of reducing the data misalignment degree of the parallel port data signal 202 measured by the detection circuit 210 later is realized, and finally realizing the data alignment is realized; the related execution details of the data alignment link are integrated into the improvement of the frequency division operation of obtaining the parallel port clock signal 201 by frequency division of the serial port clock signal and the sampling operation of obtaining the parallel port data signal 202 by sampling the differential serial signal according to the parallel port clock signal 201, the parallel port data signal 202 does not need to be additionally cached and processed, and the parallel port data signal 202 output by the serial-to-parallel circuit after the data alignment is completed can be sent to the elastic cache for subsequent processing together with the parallel port clock signal 201, so that the parallel port data signal 202 does not need to be additionally cached and processed, resources are saved, and the processing delay is also reduced; further, since the phase of the parallel port clock signal 201 is adjusted to reduce the data misalignment degree of the parallel port data signal 202 (compared with the adjustment of the parallel port data signal 202 to achieve the data alignment purpose) and the feedback loop design is used to achieve fast convergence, the method can flexibly cope with various ways of inserting control characters or special codewords at the transmitting end, such as equidistant insertion or unequal interval insertion, and the like, can flexibly cope with the coding and decoding schemes of various data transmission protocols, and can also quickly respond to various emergencies (such as network communication conditions, data flow changes, and the like) in practical application.

Fig. 3 is a schematic diagram of a receiving end system including the data alignment device shown in fig. 2 according to an embodiment of the present application. As shown in fig. 3, the data alignment device shown in fig. 2 belongs to a receiving end system. The receiving end system comprises: the differential receiving circuit 240 is configured to receive the differential serial signal, the clock data recovery circuit 242 is configured to recover the serial clock signal 208 from the differential serial signal, the clock frequency dividing circuit 230 is configured to divide the serial clock signal 208 to obtain the parallel clock signal 201, and the serial-parallel circuit 244 is configured to sample the differential serial signal according to the parallel clock signal 201 to obtain the parallel data signal 202. It can be seen that the serial-parallel circuit 244 of the receiving end system shown in fig. 3 is configured to sample the differential serial signal according to the parallel clock signal 201 to obtain the parallel data signal 202, and the clock frequency dividing circuit 230 is configured to divide the serial clock signal 208 to obtain the parallel clock signal 201; the clock adjustment circuit 220 generates the clock adjustment signal 206 according to the detection signal 204, sends the clock adjustment signal 206 to the clock divider circuit, and changes the phase of the parallel clock signal 201 output by the clock divider circuit using the clock adjustment signal 206. In this way, the detection circuit 210 and the clock adjustment circuit 220 together form a feedback loop, and from the detection circuit 210 measuring the data misalignment degree of the parallel port data signal 202 (the detection circuit 210 detects the parallel port data signal 202 output by the serial-parallel circuit 244 and the parallel port clock signal 201 output by the clock frequency division circuit 230 to measure the data misalignment degree of the parallel port data signal 202), the detection signal 204 is generated, then the clock adjustment signal 206 is generated according to the detection signal 204, and then the phase of the parallel port clock signal 201 output by the clock frequency division circuit 230 is changed by using the clock adjustment signal 206, so that the parallel port data signal 202 obtained by sampling the serial-parallel circuit 244 according to the parallel port clock signal 201 with the phase changed is affected. Thus, the details of the execution of the data alignment procedure are equivalent to being integrated into the improvement of the frequency dividing operation of the clock divider circuit 230 and the sampling operation of the serial-to-parallel circuit 244. Thus, an additional data alignment module is not required to be provided after the serial-parallel circuit 244 for data buffering and alignment, but an elastic buffer can be directly connected after the serial-parallel circuit 244, because the parallel port data signal 202 output by the serial-parallel circuit 244 after the data alignment is completed already meets the requirement of the data alignment, and can be sent to the elastic buffer together with the parallel port clock signal 201 for subsequent processing.

Fig. 4 is a schematic diagram of an implementation manner of the data alignment device shown in fig. 2 according to an embodiment of the present application. The clock adjustment circuit 220 of the data alignment device shown in fig. 2 may be the clock gating circuit 250 shown in fig. 4. The clock gating circuit 250 controls the enable clock signal 209 output to the clock divider circuit according to the detection signal 204, so as to achieve the design purpose of the clock adjustment signal 206 shown in fig. 2. For example, clock gating circuit 250 pulls enable clock signal 209 low by the number of beats corresponding to the UI difference, which means that the clock divider circuit is turned off for the clock cycle corresponding to the number of beats. In these clock cycles when the clock dividing circuit is turned off, the signal to be divided, i.e. the serial clock signal, is not divided by the calculation, which means that the divided signal output by the clock dividing circuit, i.e. the parallel clock signal, is delayed by the corresponding clock cycle. Accordingly, the first UI difference detected by the detection circuit 210 is used for pulling down the first beat number of the enable clock signal 209 corresponding to the first UI difference by the clock gating circuit 250, and then causes the clock dividing circuit to turn off the first number of clock cycles corresponding to the first beat number, and finally causes the parallel port clock signal to be delayed by the first number of clock cycles. Thus, a feedback loop is formed, and the larger UI difference value can lead to the parallel port clock signal to be delayed for more clock cycles, so that the UI difference value can be quickly converged. With such a feedback loop design, the UI difference value detected by the detection circuit 210 is reduced, that is, the degree of data misalignment of the parallel port data signal detected by the detection circuit 210 is reduced, and finally, the UI difference value is zero, which means that the data alignment is completed, and the UI difference value can be directly sent to the elastic buffer. It should be understood that fig. 4 illustrates an embodiment of the data alignment apparatus shown in fig. 2, where the clock adjustment circuit 220 of the data alignment apparatus shown in fig. 2 may use the clock gating circuit 250 shown in fig. 4 to construct a feedback loop, and may use other circuits, hardware, devices, etc. to construct a feedback loop, so long as the characteristics that the higher the degree of data misalignment of the parallel port data signal measured by the detection circuit 210, the faster the data misalignment will be, can be achieved. For example, by measuring a UI difference or other value reflecting the degree of misalignment of the data of the parallel port data signals and converting the measured value into a detection signal; the clock adjustment circuit may include a device such as a counter, an inverter, etc. for generating a data adjustment signal based on the degree of data misalignment of the parallel port data signal reflected by the detection signal, for the purpose of rapid convergence.

Fig. 5 is a schematic diagram of a parallel port clock signal before and after phase adjustment according to an embodiment of the present application. As shown in fig. 5, comparing the pre-adjustment parallel port clock signal 510 with the pre-adjustment parallel port data signal 512, it can be seen that the control word a for data alignment is provided with 16 bits, wherein the 1 st bit to 12 th bit 502 of the control word a is located in the previous beat of data, and the 13 th bit to 16 th bit 504 of the control word a is located in the subsequent beat of data. As described above, the distribution of the control character a between the two beats of data, that is, the positions of each of the 1 st to 12 th bits 502 of the control character a and the 13 th to 16 th bits 504 of the control character a, is random because the specific position of the special codeword (control character) for data alignment in the spliced data is also random, and the addition of the special codeword at the transmitting end or the interval of the control character to the differential serial signal is also difficult to predict. While the pre-adjustment case shown in fig. 5 illustrates the case where there is a data misalignment between the pre-adjustment parallel port clock signal 510 and the pre-adjustment parallel port data signal 512, at least with respect to the case where there is a data misalignment of the control character a, the complete control character a needs to be addressed and confirmed in the data alignment link, resulting in a delay loss, and the greater the possible delay loss with a greater parallel port data bit width. With the development of high-speed data transmission, the width of parallel data bits is larger and larger, so that greater data throughput efficiency and data transmission rate can be brought, and therefore, the delay loss possibly caused by addressing complete control characters in a data alignment link is also larger. Therefore, the data alignment method for high-speed data transmission shown in fig. 1 and the data alignment device for high-speed data transmission shown in fig. 2 integrate the execution details of the data alignment link into the improvement of the frequency division operation of the serial port clock signal to obtain the parallel port clock signal and the sampling operation of the parallel port data signal obtained by sampling the differential serial signal according to the parallel port clock signal, without additional buffering and processing of the parallel port data signal, the parallel port data signal output by the serial-parallel circuit after the data alignment is completed can be sent to the elastic buffer together with the parallel port clock signal for subsequent processing, so that additional buffering and processing of the parallel port data signal are not needed, resources are saved, and the processing delay is also reduced. As shown in fig. 5, the degree of data misalignment between the adjusted parallel port clock signal 520 and the adjusted parallel port data signal 522 has been reduced to a minimum, wherein the 1 st bit to 16 th bit 506 of the control character a is located in the previous beat of data, thus completing the addressing of the complete control character a, i.e. achieving the data alignment requirement. The data alignment method for high-speed data transmission shown in fig. 1 and the data alignment device for high-speed data transmission shown in fig. 2 can flexibly cope with various modes of inserting control characters or special codewords at a transmitting end, such as equidistant insertion or unequal interval insertion, and can flexibly cope with coding and decoding schemes of various data transmission protocols, and can also quickly respond to various emergency situations (such as network communication conditions, data stream changes and the like) in practical application.

With reference to fig. 1 to fig. 5, various implementation manners, embodiments, examples and other examples of a data alignment method and apparatus for high-speed data transmission according to an embodiment of the present application are further described below.

The control character, also called a special codeword, is added to the differential serial signal at the transmitting end for data alignment at the receiving end. For example, the data transmission specification and protocol of the universal serial bus (Universal Serial Bus, USB) defines an 8B/10B codec scheme, encoding 12 special characters into 12 control characters. These control characters are used for data alignment, for example, by aligning data to words, for clock correction, block synchronization, etc. Because the spliced data obtained by splicing the parallel port data has certain randomness, the specific position of the special code word (control character) for data alignment in the spliced data is also random. Furthermore, the addition of special codewords or control characters at the transmitting end may or may not be fixed to the interval of the differential serial signal, which further makes it difficult to predict the specific location of the special codewords (control characters) for data alignment. The detection circuit is used for detecting the parallel port data signals output by the serial-to-parallel conversion circuit and the parallel port clock signals output by the clock frequency division circuit, so that the distribution of the same control character used for data alignment between front and back beats of parallel port data in the parallel port data signals is determined, and the degree of data misalignment of the parallel port data signals is measured based on the distribution, so that detection signals are generated. In one possible implementation, the same control character includes a plurality of bits in succession, and the distribution is a number of bits in which the plurality of bits are distributed between the two-beat parallel port data. For example, let the same control character have 8 bits, 7 bits in the previous beat of parallel port data, and the remaining 1 bit in the next beat of parallel port data. The data misalignment degree of the parallel port data signal can be measured numerically through the bit number of the plurality of bits distributed between the front and rear two beats of parallel port data. In one possible implementation, the degree of data misalignment of the parallel port data signal is the number of bits of the parallel port data of the next one of the two front and rear two parallel port data distributed by the same control character. Thus, by measuring the number of bits of the parallel port data of the next one of the two front and rear parallel port data, the degree of data misalignment of the parallel port data signal can be measured numerically. For example, let the same control character have 8 bits, 7 bits in the previous beat of parallel port data, and the remaining 1 bit in the next beat of parallel port data. By determining the number of bits, e.g. 1 bit, of the parallel port data of the same control character distributed in the subsequent beat, the degree of data misalignment of the parallel port data signal can be conveniently determined. In some embodiments, the clock adjustment circuit is configured to change the phase of the parallel port clock signal output by the clock frequency division circuit by using the clock adjustment signal, so that the number of bits of the parallel port data of the next two beats of parallel port data in the front and back two beats of parallel port data measured by the detection circuit is zero. Therefore, the related execution details of the data alignment link are integrated into the frequency division operation of frequency division of the serial port clock signal to obtain the parallel port clock signal and the improvement of sampling operation of sampling the differential serial signal according to the parallel port clock signal to obtain the parallel port data signal, so that the data alignment is realized, the parallel port data signal does not need to be additionally cached and processed, resources are saved, and the processing delay is reduced.

In the data alignment link, the delay loss calculation may be performed in units of Unit Intervals (UI). In one possible implementation, the degree of data misalignment of the parallel port data signals indicates a unit time interval difference of a front side or a rear side of the same control character with respect to a boundary of the front and rear two beats of parallel port data. The boundary of the front and back two-beat parallel port data is the boundary between the front beat parallel port data and the back beat parallel port data. The parallel port data signal is multi-beat parallel port data obtained by sampling the differential serial signal by the serial-to-parallel circuit according to the parallel port clock signal, so that the boundary of the front and rear two beats of parallel port data is determined by the sampling operation of the serial-to-parallel circuit. Therefore, the difference of the unit time interval of the front side or the rear side of the same control character relative to the boundary of the front and rear two beats of parallel port data can be used as a numerical index for measuring the data misalignment degree of the parallel port data signal. In some embodiments, the clock adjustment circuit changes the phase of the parallel port clock signal output by the clock frequency division circuit by using the clock adjustment signal so that the unit time interval difference of the front side or the rear side of the same control character measured by the detection circuit later relative to the boundary of the front and rear two beats of parallel port data is zero. Therefore, the related execution details of the data alignment link are integrated into the frequency division operation of frequency division of the serial port clock signal to obtain the parallel port clock signal and the improvement of sampling operation of sampling the differential serial signal according to the parallel port clock signal to obtain the parallel port data signal, so that the data alignment is realized, the parallel port data signal does not need to be additionally cached and processed, resources are saved, and the processing delay is reduced.

The data alignment method and device for high-speed data transmission provided by the embodiment of the application change the phase of the parallel port clock signal output by the clock frequency division circuit by utilizing the clock adjustment signal, thereby reducing the data misalignment degree of the parallel port data signal measured by the detection circuit. The distribution of the same control character for data alignment between two front and rear beats of parallel port data in the parallel port data signal is changed by changing the phase of the parallel port clock signal, wherein the parallel port data signal is multiple beats of parallel port data obtained by sampling a differential serial signal according to the parallel port clock signal. In one possible implementation, the boundary of the multi-beat parallel port data is determined based on a sampling clock edge of the parallel port clock signal, and the clock adjustment circuit changes the phase of the parallel port clock signal by using the clock adjustment signal so as to reduce a phase difference of a front side of a control character in the parallel port data signal, which is measured later by the detection circuit, relative to the sampling clock edge. Wherein when the front side of the control character is aligned with the sampling clock edge, it means that each sampling, i.e. each new beat of parallel port data starts from the front side of the control character, so that the previous beat of parallel port data contains the complete control character. When the back side of the control character is aligned with the sampling clock edge, it also means that the same beat of parallel port data contains the complete control character. In some embodiments, the clock adjustment circuit is configured to change the phase of the parallel port clock signal output by the clock frequency dividing circuit by using the clock adjustment signal so that the front side of a control character in the parallel port data signal measured later by the detection circuit is aligned with the sampling clock edge. Therefore, the related execution details of the data alignment link are integrated into the frequency division operation of frequency division of the serial port clock signal to obtain the parallel port clock signal and the improvement of sampling operation of sampling the differential serial signal according to the parallel port clock signal to obtain the parallel port data signal, so that the data alignment is realized, the parallel port data signal does not need to be additionally cached and processed, resources are saved, and the processing delay is reduced. In some embodiments, the sampling clock edge is a rising clock edge. In other embodiments, the sampling clock edge is a falling clock edge.

In one possible implementation, the differential serial signal is used for high-speed data transmission from a transmitting end to a receiving end, the data alignment device is disposed at the receiving end, and the same control character is inserted into the differential serial signal at the transmitting end for data alignment at the receiving end. In some embodiments, a codec scheme for high-speed data transmission between the transmitting end and the receiving end defines a plurality of special codewords, the same control word being any one of the plurality of special codewords, the plurality of special codewords each being inserted into the differential serial signal at the transmitting end at a fixed or non-fixed interval. The parallel port clock signal is adjusted to reduce the data misalignment degree of the parallel port data signal (compared with the parallel port clock signal is adjusted to realize the data alignment), and the feedback loop design is used for realizing rapid convergence, so that various modes of inserting control characters or special code words at a transmitting end, such as equidistant insertion or unequal interval insertion, can be flexibly dealt with, various coding and decoding schemes of data transmission protocols can be flexibly dealt with, and rapid response can be rapidly carried out on various emergency situations (such as network communication conditions, data flow changes and the like) in practical application.

In one possible implementation, the clock adjustment circuit includes a clock gating circuit that outputs an enable clock signal to the clock dividing circuit, the clock dividing circuit is configured to divide the serial clock signal by a bit width of the parallel data signal when the enable clock signal indicates on, and the clock gating circuit is configured to generate the clock adjustment signal according to the detection signal, the clock adjustment signal causes the enable clock signal to indicate off at a first clock cycle such that the parallel clock signal output by the clock dividing circuit is delayed by the first clock cycle. In some embodiments, the enable clock signal is asserted high and the enable clock signal is asserted low and the enable clock signal is asserted off, the clock gating circuit being configured to pull down the enable clock signal in the first clock cycle in response to the detection signal such that the parallel port clock signal output by the clock divider circuit is delayed by the first clock cycle and such that the parallel port data signal resulting from sampling the differential serial signal in accordance with the delayed parallel port clock signal is delayed by a first beat number associated with the first clock cycle. In some examples, a UI difference, such as a UI difference that outputs a boundary with a desired codeword, may be employed as a quantization index for the determined degree of data misalignment of the parallel port data signal. The UI difference is detected from the parallel data signal output from the serial-parallel circuit, for example, by monitoring the distribution of the same control character between every two adjacent beats of parallel data in the parallel data signal in real time or at intervals. And then the UI difference value is used for controlling the clock gating circuit, so that the parallel port clock signal is delayed, the distribution of the same control character measured later between two adjacent beats of parallel port data is changed, and the same control character is not distributed in the next beat of parallel port data, namely 0 bit. The first UI difference value detected by the detection circuit is used for pulling down a first beat number corresponding to the first UI difference value of the enabling clock signal by the clock gating circuit, then the clock frequency dividing circuit is caused to close a first number of clock cycles corresponding to the first beat number, and finally the parallel port clock signal is caused to be delayed by the first number of clock cycles. Thus, a feedback loop is formed, and the larger UI difference value can lead to the parallel port clock signal to be delayed for more clock cycles, so that the UI difference value can be quickly converged. By means of the feedback loop design, the UI difference value detected by the detection circuit is reduced, namely the data misalignment degree of the parallel port data signals detected by the detection circuit is reduced, and finally the UI difference value is zero, which means that data alignment is completed, and the data alignment can be directly sent to the elastic buffer.

In one possible implementation, the data alignment method further includes: and the detection circuit and the clock adjustment circuit enter a low-power consumption state in response to the clock adjustment circuit reducing the data misalignment degree of the parallel port data signal measured by the detection circuit to zero. As described above, the related execution details of the data alignment link are integrated into the improvement of the frequency division operation of obtaining the parallel port clock signal by frequency division of the serial port clock signal and the sampling operation of obtaining the parallel port data signal by sampling the differential serial signal according to the parallel port clock signal, so that additional buffering and processing of the parallel port data signal are not required, the parallel port data signal output by the serial-to-parallel circuit after the data alignment is completed can be sent to the elastic buffer memory together with the parallel port clock signal for subsequent processing, and therefore, additional buffering and processing of the parallel port data signal are not required, resources are saved, and processing delay is reduced. In addition, as shown in fig. 3, the feedback loop constructed by the detection circuit 210 and the clock adjustment circuit 220 has an effect on the frequency division operation of the clock frequency division circuit 230 and the sampling operation of the serial-parallel circuit 244 based on the detection of the misalignment of data by the detection circuit 210, so that when the misalignment of the data of the parallel port data signal measured by the detection circuit 210 is zero, the feedback loop does not affect the frequency division operation of the clock frequency division circuit 230 and the sampling operation of the serial-parallel circuit 244, which means that the detection circuit and the clock adjustment circuit can enter a low power consumption state, thereby reducing the overall power consumption of the system. Moreover, since there is no need to provide an additional data alignment module after the serial-parallel circuit for data buffering and alignment processing, the detection circuit and the clock adjustment circuit in the low power consumption state do not cause additional delay, which helps to reduce the overall processing delay. And, once the detection circuit determines that the data misalignment degree of the parallel port data signal is not zero, a feedback loop may be started, for example, the detection circuit and the clock adjustment circuit are not in low power consumption Zhang Tai any more, so as to reduce the data misalignment degree of the parallel port data signal, which is subsequently determined by the detection circuit. Therefore, the data alignment method and apparatus for high-speed data transmission provided in the embodiments of the present application, for example, the data alignment method for high-speed data transmission shown in fig. 1 and the data alignment apparatus for high-speed data transmission shown in fig. 2, not only realize that when the data misalignment degree of the parallel port data signal is not zero, the relevant execution details of the data alignment link are integrated into the frequency division operation of dividing the serial port clock signal to obtain the parallel port clock signal, but also the improvement of the sampling operation of sampling the differential serial signal according to the parallel port clock signal to obtain the parallel port data signal, thereby realizing the data alignment; and when the data misalignment degree of the parallel port data signal is zero, the detection circuit and the clock adjustment circuit are enabled to enter a low-power-consumption state, so that the overall power consumption of the system is reduced.

Fig. 6 is a schematic structural diagram of a computing device provided by an embodiment of the present application, where the computing device 600 includes: one or more processors 610, a communication interface 620, and a memory 630. The processor 610, communication interface 620, and memory 630 are connected to each other by a bus 640. Optionally, the computing device 600 may further include an input/output interface 650, where the input/output interface 650 is connected to an input/output device for receiving parameters set by a user, etc. The computing device 600 can be used to implement some or all of the functionality of the device embodiments or system embodiments described above in embodiments of the present application; the processor 610 can also be used to implement some or all of the operational steps of the method embodiments described above in connection with the embodiments of the present application. For example, specific implementations of the computing device 600 performing various operations may refer to specific details in the above-described embodiments, such as the processor 610 being configured to perform some or all of the steps of the above-described method embodiments or some or all of the operations of the above-described method embodiments. For another example, in an embodiment of the present application, the computing device 600 may be used to implement some or all of the functionality of one or more components of the apparatus embodiments described above, and the communication interface 620 may be used in particular for communication functions and the like necessary to implement the functionality of those apparatuses, components, and the processor 610 may be used in particular for processing functions and the like necessary to implement the functionality of those apparatuses, components.

It should be appreciated that the computing device 600 of fig. 6 may include one or more processors 610, and that the multiple processors 610 may cooperatively provide processing power in a parallelized connection, a serialized connection, a serial-parallel connection, or any connection, or the multiple processors 610 may constitute a processor sequence or processor array, or the multiple processors 610 may be separated into primary and secondary processors, or the multiple processors 610 may have different architectures such as employing heterogeneous computing architectures. In addition, the computing device 600 shown in FIG. 6, the associated structural and functional descriptions are exemplary and not limiting. In some example embodiments, computing device 600 may include more or fewer components than shown in fig. 6, or combine certain components, or split certain components, or have a different arrangement of components.

The processor 610 may be implemented in various manners, for example, the processor 610 may include one or more of a central processing unit (central processing unit, CPU), a graphics processor (graphic processing unit, GPU), a neural network processor (neural-network processing unit, NPU), a tensor processor (tensor processing unit, TPU), or a data processor (data processing unit, DPU), and the embodiments of the present application are not limited in particular. Processor 610 may also be a single-core processor or a multi-core processor. The processor 610 may be formed by a combination of a CPU and a hardware chip. The hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (programmable logic device, PLD), or a combination thereof. The PLD may be a complex programmable logic device (complex programmable logic device, CPLD), a field-programmable gate array (field-programmable gate array, FPGA), general-purpose array logic (generic array logic, GAL), or any combination thereof. The processor 610 may also be implemented solely with logic devices incorporating processing logic, such as an FPGA or digital signal processor (digital signal processor, DSP) or the like. The communication interface 620 may be a wired interface, which may be an ethernet interface, a local area network (local interconnect network, LIN), etc., or a wireless interface, which may be a cellular network interface or use a wireless lan interface, etc., for communicating with other modules or devices.

The memory 630 may be a nonvolatile memory such as a read-only memory (ROM), a Programmable ROM (PROM), an Erasable PROM (EPROM), an electrically Erasable EPROM (EEPROM), or a flash memory. The memory 630 may also be volatile memory, which can be random access memory (random access memory, RAM) used as external cache. By way of example, and not limitation, many forms of RAM are available, such as Static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous DRAM (SLDRAM), and direct memory bus RAM (DR RAM). The memory 630 may also be used to store program code and data such that the processor 610 invokes the program code stored in the memory 630 to perform some or all of the operational steps of the method embodiments described above, or to perform corresponding functions of the apparatus embodiments described above. Moreover, computing device 600 may contain more or fewer components than shown in FIG. 6, or may have a different configuration of components.

Bus 640 may be a peripheral component interconnect express (peripheral component interconnect express, PCIe) bus, or an extended industry standard architecture (extended industry standard architecture, EISA) bus, a unified bus (Ubus or UB), a computer quick link (compute express link, CXL), a cache coherent interconnect protocol (cache coherent interconnect for accelerators, CCIX), or the like. Bus 640 may be divided into an address bus, a data bus, a control bus, and the like. Bus 640 may include a power bus, a control bus, a status signal bus, and the like in addition to a data bus. But is shown with only one bold line in fig. 6 for clarity of illustration, but does not represent only one bus or one type of bus.

The method and the device provided by the embodiment of the application are based on the same inventive concept, and because the principle of solving the problem by the method and the device is similar, the embodiment, the implementation, the example or the implementation of the method and the device can be mutually referred, and the repetition is not repeated. Embodiments of the present application also provide a system comprising a plurality of computing devices, each of which may be structured as described above. The functions or operations that may be implemented by the system may refer to specific implementation steps in the above method embodiments and/or specific functions described in the above apparatus embodiments, which are not described herein.

Embodiments of the present application also provide a computer-readable storage medium having stored therein computer instructions which, when executed on a computer device (e.g., one or more processors), implement the method steps of the method embodiments described above. The specific implementation of the processor of the computer readable storage medium in executing the above method steps may refer to specific operations described in the above method embodiments and/or specific functions described in the above apparatus embodiments, which are not described herein again.

It will be appreciated by those skilled in the art that embodiments of the present application may be provided as a method, system, or computer program product. The application can take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Embodiments of the application may be implemented, in whole or in part, in software, hardware, firmware, or any other combination. When implemented in software, the above-described embodiments may be implemented in whole or in part in the form of a computer program product. The present application may take the form of a computer program product embodied on one or more computer-usable storage media having computer-usable program code embodied therein. The computer program product includes one or more computer instructions. When loaded or executed on a computer, produces a flow or function in accordance with embodiments of the present application, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a computer network, or other programmable apparatus. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by a wired (e.g., coaxial cable, fiber optic, digital subscriber line), or wireless (e.g., infrared, wireless, microwave, etc.). Computer readable storage media can be any available media that can be accessed by a computer or data storage devices, such as servers, data centers, etc. that contain one or more collections of available media. Usable media may be magnetic media (e.g., floppy disks, hard disks, tape), optical media, or semiconductor media. The semiconductor medium may be a solid state disk, or may be a random access memory, flash memory, read only memory, erasable programmable read only memory, electrically erasable programmable read only memory, register, or any other form of suitable storage medium.

The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the application. Each flow and/or block of the flowchart and/or block diagrams, and combinations of flows and/or blocks in the flowchart and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks. These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks. These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

In the foregoing embodiments, the descriptions of the embodiments are emphasized, and for parts of one embodiment that are not described in detail, reference may be made to the related descriptions of other embodiments. It will be apparent to those skilled in the art that various modifications and variations can be made to the embodiments of the present application without departing from the spirit or scope of the embodiments of the application. The steps in the method of the embodiment of the application can be sequentially adjusted, combined or deleted according to actual needs; the modules in the system of the embodiment of the application can be divided, combined or deleted according to actual needs. The present application is also intended to include such modifications and alterations if they come within the scope of the claims and the equivalents thereof.

Claims

1. A data alignment method for high-speed data transmission, the data alignment method being applied to a data alignment apparatus including a detection circuit and a clock adjustment circuit connected to the detection circuit and a clock division circuit, the data alignment method comprising:

detecting the distribution of the same control character used for data alignment between front and rear beats of parallel port data in a parallel port data signal by the detection circuit, and determining the data misalignment degree of the parallel port data signal based on the distribution so as to generate a detection signal, wherein the parallel port data signal is multi-beat parallel port data obtained by sampling a differential serial signal according to a parallel port clock signal, the parallel port clock signal is obtained by dividing the frequency of a serial port clock signal by the clock frequency dividing circuit, and the serial port clock signal is recovered from the differential serial signal;

Generating a clock adjustment signal according to the detection signal by the clock adjustment circuit, sending the clock adjustment signal to the clock frequency division circuit, and changing the phase of the parallel port clock signal output by the clock frequency division circuit by using the clock adjustment signal, thereby reducing the data misalignment degree of the parallel port data signal measured by the detection circuit,

the clock adjustment circuit comprises a clock gating circuit which outputs an enable clock signal to the clock frequency division circuit, the clock frequency division circuit is used for dividing the serial port clock signal according to the bit width of the parallel port data signal when the enable clock signal indicates to be started, the clock gating circuit is used for generating the clock adjustment signal according to the detection signal, the clock adjustment signal enables the enable clock signal to indicate to be closed in a first clock period so that the parallel port clock signal output by the clock frequency division circuit is delayed by the first clock period,

the clock gating circuit is configured to cause the parallel data signal, which is derived from sampling the differential serial signal according to the delayed parallel clock signal, to be delayed by a first beat number associated with the first clock cycle.

2. The data alignment method of claim 1, wherein the same control character comprises a continuous plurality of bits, the distribution being a number of bits of the plurality of bits distributed between the front and rear two beats of parallel port data.

3. The data alignment method according to claim 1, wherein the degree of data misalignment of the parallel port data signal is the number of bits of the parallel port data of the next one of the front and rear two-beat parallel port data distributed with the same control character.

4. The data alignment method of claim 1, wherein the degree of data misalignment of the parallel port data signals indicates a unit time interval difference of a front side or a rear side of the same control character with respect to a boundary of the front and rear two beats of parallel port data.

5. The data alignment method of claim 1, wherein the boundary of the multi-beat parallel port data is determined based on a sampling clock edge of the parallel port clock signal, the clock adjustment circuit changing a phase of the parallel port clock signal using the clock adjustment signal to reduce a phase difference of a front side of a control character in the parallel port data signal with respect to the sampling clock edge measured later by the detection circuit.

6. The data alignment method of claim 5, wherein the sampling clock edge is a rising clock edge.

7. The data alignment method according to claim 1, wherein the differential serial signal is used for high-speed data transmission from a transmitting end to a receiving end, the data alignment device being disposed at the receiving end, the same control character being inserted into the differential serial signal at the transmitting end for data alignment at the receiving end.

8. The data alignment method of claim 7, wherein a codec scheme for high-speed data transmission between the transmitting end and the receiving end defines a plurality of special codewords, the same control word being any one of the plurality of special codewords, the plurality of special codewords each being inserted into the differential serial signal at the transmitting end at a fixed or non-fixed interval.

9. The data alignment method according to claim 3, wherein the clock adjustment circuit changes the phase of the parallel port clock signal outputted by the clock frequency dividing circuit by using the clock adjustment signal so that the number of bits of the next parallel port data in the preceding and following two-beat parallel port data measured by the detection circuit is zero.

10. The data alignment method according to claim 4, wherein the phase of the parallel port clock signal outputted from the clock frequency dividing circuit is changed by the clock adjusting circuit by the clock adjusting signal so that a unit time interval difference of a front side or a rear side of the same control character measured later by the detecting circuit with respect to a boundary of the front and rear two beats of parallel port data is zero.

11. The data alignment method according to claim 5, wherein the phase of the parallel port clock signal outputted from the clock dividing circuit is changed by the clock adjusting circuit using the clock adjusting signal so that a front side of a control character in the parallel port data signal measured later by the detecting circuit is aligned with the sampling clock edge.

12. The data alignment method of claim 1, wherein the enable clock signal is asserted high to indicate on and the enable clock signal is pulled low to indicate off, the clock gating circuit being configured to pull down the enable clock signal at the first clock cycle based on the detection signal such that the parallel clock signal output by the clock divider circuit is delayed by the first clock cycle.

13. The data alignment method of claim 1, further comprising:

and the detection circuit and the clock adjustment circuit enter a low-power consumption state in response to the clock adjustment circuit reducing the data misalignment degree of the parallel port data signal measured by the detection circuit to zero.

14. A computer device, characterized in that it comprises a memory, a processor and a computer program stored on the memory and executable on the processor, which processor implements the method according to any of claims 1 to 13 when executing the computer program.

15. A computer readable storage medium storing computer instructions which, when run on a computer device, cause the computer device to perform the method of any one of claims 1 to 13.

16. A data alignment apparatus for high speed data transmission, the data alignment apparatus comprising:

a detection circuit for: detecting the distribution of the same control character used for data alignment between two front and rear beats of parallel port data in a parallel port data signal, and determining the data misalignment degree of the parallel port data signal based on the distribution so as to generate a detection signal, wherein the parallel port data signal is multi-beat parallel port data obtained by sampling a differential serial signal according to a parallel port clock signal, the parallel port clock signal is obtained by dividing a serial port clock signal through a clock frequency dividing circuit, and the serial port clock signal is recovered from the differential serial signal;

The clock adjusting circuit is connected with the detecting circuit and the clock frequency dividing circuit and is used for: generating a clock adjustment signal according to the detection signal, sending the clock adjustment signal to the clock frequency division circuit, and changing the phase of the parallel port clock signal output by the clock frequency division circuit by using the clock adjustment signal, thereby reducing the data misalignment degree of the parallel port data signal measured by the detection circuit,

17. The data alignment device of claim 16, wherein the data alignment device belongs to a receiving end system, the receiving end system comprising: the differential receiving circuit is used for receiving the differential serial signal, the clock data recovery circuit is used for recovering the serial port clock signal from the differential serial signal, the clock frequency division circuit is used for dividing the serial port clock signal to obtain the parallel port clock signal, and the serial-to-parallel circuit is used for sampling the differential serial signal according to the parallel port clock signal to obtain the parallel port data signal.