CN117056269B

CN117056269B - Data alignment method for parallel interface connection, computer equipment and medium

Info

Publication number: CN117056269B
Application number: CN202311310024.2A
Authority: CN
Inventors: 汪津
Original assignee: Xinyaohui Technology Co ltd
Current assignee: Xinyaohui Technology Co ltd
Priority date: 2023-10-11
Filing date: 2023-10-11
Publication date: 2024-02-09
Anticipated expiration: 2043-10-11
Also published as: CN117056269A

Abstract

The application relates to the technical field of computers and provides a data alignment method, computer equipment and a medium for parallel interface connection. The method comprises the following steps: receiving a plurality of parallel port data signals and a data selection signal, wherein each parallel port data signal comprises a plurality of first signals corresponding to a plurality of first lines; generating a corresponding plurality of second differential signal pairs based on the data selection signal; for each first signal, sampling the first signal according to first three sampling clock edges of a second differential signal pair corresponding to a first line corresponding to the first signal to obtain first three sampling results, selecting a first beat sampling clock edge based on the sampling results, adjusting the second differential signal pair based on the first beat sampling clock edge to obtain an adjusted differential signal pair, and sampling the first signal by using the first beat sampling clock edge and the adjusted second differential signal pair to realize data alignment. Thus, high transmission performance, high channel rate, and high resource utilization are achieved.

Description

Data alignment method for parallel interface connection, computer equipment and medium

Technical Field

The present invention relates to the field of computer technologies, and in particular, to a data alignment method, a computer device, and a medium for parallel interface connection.

Background

In an application scenario using a high-speed parallel interface connection, for example, a high-performance memory based on a double data rate synchronous dynamic random access memory (Double Data Rate Synchronous Dynamic Random Access Memory, DDR SRAM), and further, for example, a standard communication interface specification based on DDR SRAM, such as a double data rate synchronous dynamic random access memory physical layer interface (DDR PHY Interface, DFI) protocol, multiple bits of parallel data are transmitted through a single channel, which is affected by factors such as delay and clock offset, and challenges are faced in improving transmission performance and channel rate.

For this reason, the present application provides a data alignment method, a computer device, and a medium for parallel interface connection, which are used to solve the technical problems in the prior art.

Disclosure of Invention

In a first aspect, the present application provides a data alignment method for parallel interface connection. The data alignment method comprises the following steps: receiving a plurality of parallel port data signals and a data selection signal through a receiving end, wherein each of the plurality of parallel port data signals comprises a plurality of first signals, the first signals are in one-to-one correspondence with a plurality of first lines between the receiving end and a transmitting end, each of the first signals is transmitted through a first line corresponding to the first signal in the first lines, the data selection signal is transmitted through a second line between the receiving end and the transmitting end, the plurality of parallel port data signals are transmitted based on the triggering of the upper edge and the lower edge of a reference clock signal, and the data selection signal is a first differential signal pair generated based on the reference clock signal; generating, by the receiving end, a plurality of second differential signal pairs corresponding to the plurality of first lines one to one based on the data selection signal; for each first signal in the plurality of first signals, sampling the first signal according to first three sampling clock edges of a second differential signal pair corresponding to a first line corresponding to the first signal in the plurality of second differential signal pairs to obtain first three sampling results respectively, then selecting a first beat sampling clock edge from the first three sampling clock edges based on the first three sampling results, adjusting the second differential signal pair based on the first beat sampling clock edge to obtain an adjusted differential signal pair, and sampling the first signal by using the first beat sampling clock edge and the adjusted second differential signal pair to realize data alignment between the multi-beat parallel port data signal and the data selection signal.

According to the first aspect of the application, the data alignment between the multi-beat parallel port data signal and the data selection signal is realized so as to read data correctly, meanwhile, the high transmission performance and the high channel rate are also considered, the limited delay adjustment capability is equivalently enlarged and the resource utilization rate is improved through the optimization design of the sampling operation and the adjustment operation, and further, the requirements of various application scenes, various frequency points and various communication protocols are met, and the delay adjustment capability of the differential signal can be provided to be high enough so as to realize the data alignment under different system frequencies.

In a possible implementation manner of the first aspect of the present application, the multi-beat parallel port data signal is sent based on a trigger of upper and lower edges of the reference clock signal, so that a same clock period of the reference clock signal includes two transmission periods, and the data selection signal is used for distinguishing the two transmission periods included in the same clock period of the reference clock signal.

In a possible implementation manner of the first aspect of the present application, the receiving end is a physical interface layer of a double data rate synchronous dynamic random access memory, the sending end is a double data rate synchronous dynamic random access memory device side, and the double data rate synchronous dynamic random access memory device side sends the multi-beat parallel port data signal and the data selection signal in response to a read command.

In a possible implementation manner of the first aspect of the present application, the side of the double data rate synchronous dynamic random access memory device includes a plurality of double data rate synchronous dynamic random access memory devices, and any double data rate synchronous dynamic random access memory device in the plurality of double data rate synchronous dynamic random access memory devices is used for sending the multi-beat parallel port data signal and the data selection signal and supports a data bit width corresponding to the number of the plurality of first signals.

In a possible implementation manner of the first aspect of the present application, the multi-beat parallel port data signals are all 8 bits, the plurality of first signals are all 1 bit, and the number of the plurality of first signals is 8.

In a possible implementation manner of the first aspect of the present application, the delay of the second line is greater than the delay of any first line of the plurality of first lines, and the delay between any two first lines of the plurality of first lines is not greater than a first threshold, where the first threshold is determined based on a communication interface specification between the receiving end and the transmitting end.

In a possible implementation manner of the first aspect of the present application, the first three sampling clock edges in the second differential signal pair are a first sampling clock edge, a second sampling clock edge and a third sampling clock edge, wherein the second sampling clock edge follows the first sampling clock edge and the third sampling clock edge follows the second sampling clock edge, the first sampling clock edge and the third sampling clock edge are located on the same differential signal of the second differential signal pair, and the second sampling clock edge is located on the other differential signal of the second differential signal pair with respect to the same differential signal.

In a possible implementation manner of the first aspect of the present application, the first sampling clock edge, the second sampling clock edge, and the third sampling clock edge are rising clock edges or falling clock edges.

In a possible implementation manner of the first aspect of the present application, the first three sampling results include a first sampling result, a second sampling result and a third sampling result, where the first sampling result is obtained by sampling the first signal based on the first sampling clock edge, the second sampling result is obtained by sampling the first signal based on the second sampling clock edge, and the third sampling result is obtained by sampling the first signal based on the third sampling clock edge.

In a possible implementation manner of the first aspect of the present application, when the first sampling result and the second sampling result are both null and the third sampling result is not null, the first sampling clock edge is the third sampling clock edge, and adjusting the second differential signal pair based on the third sampling clock edge to obtain the adjusted differential signal pair includes: the first sampling clock edge is used for scanning the front edge of the second beat data of the first signal, then the third sampling clock edge is used for scanning the rear edge of the first beat data of the first signal so as to obtain a first scanning result, the center position of the first beat data of the first signal is calculated based on the first scanning result, and the second differential signal pair is adjusted so that the third sampling clock edge is aligned with the center position of the first beat data of the first signal.

In a possible implementation manner of the first aspect of the present application, when the first sampling result is null and the second sampling result is not null, the first sampling clock edge is the second sampling clock edge, and adjusting the second differential signal pair based on the second sampling clock edge to obtain the adjusted differential signal pair includes: the second sampling clock edge is used for scanning the front edge of the first beat data of the first signal and then the third sampling clock edge is used for scanning the rear edge of the first beat data of the first signal so as to obtain a second scanning result, the center position of the first beat data of the first signal is calculated based on the second scanning result, and the second differential signal pair is adjusted so that the second sampling clock edge is aligned with the center position of the first beat data of the first signal.

In a possible implementation manner of the first aspect of the present application, when the first sampling result is not null, the first beat sampling clock edge is the first sampling clock edge, and adjusting the second differential signal pair based on the first sampling clock edge to obtain the adjusted differential signal pair includes: the first sampling clock edge is used for scanning the front edge of the first beat data of the first signal, then the second sampling clock edge is used for scanning the rear edge of the first beat data of the first signal so as to obtain a third scanning result, the center position of the first beat data of the first signal is calculated based on the third scanning result, and the second differential signal pair is adjusted so that the first sampling clock edge is aligned with the center position of the first beat data of the first signal.

In a possible implementation manner of the first aspect of the present application, the plurality of second differential signal pairs are in one-to-one correspondence with a plurality of delay chains, where adjusting the second differential signal pairs based on the first beat sampling clock edge results in the adjusted differential signal pairs, including: and based on the first beat sampling clock edge, delaying the second differential signal pair through a delay chain corresponding to the second differential signal pair in the plurality of delay chains to obtain the adjusted differential signal pair, wherein the maximum delay range of the delay chain does not exceed half period of the first differential signal pair.

In a possible implementation manner of the first aspect of the present application, adjusting the second differential signal pair based on the first beat sampling clock edge to obtain the adjusted differential signal pair further includes: the first signal is selectively scanned using the first three sampling clock edges based on the first beat sampling clock edges and the scan range does not exceed the maximum delay range of the delay chain.

In a second aspect, embodiments of the present application further provide a computer device, where the computer device includes a memory, a processor, and a computer program stored on the memory and executable on the processor, where the processor implements a method according to any implementation manner of any one of the foregoing aspects when the computer program is executed.

In a third aspect, embodiments of the present application also provide a computer-readable storage medium storing computer instructions that, when run on a computer device, cause the computer device to perform a method according to any one of the implementations of any one of the above aspects.

In a fourth aspect, embodiments of the present application also provide a computer program product comprising instructions stored on a computer-readable storage medium, which when run on a computer device, cause the computer device to perform a method according to any one of the implementations of any one of the above aspects.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic diagram of a double data rate synchronous dynamic random access memory application scenario;

Fig. 2 is a flow chart of a data alignment method for parallel interface connection according to an embodiment of the present application;

FIG. 3 is a schematic diagram of a sampling result and an adjusted differential signal pair according to an embodiment of the present disclosure;

FIG. 4 is a schematic diagram of another sampling result and an adjusted differential signal pair according to an embodiment of the present disclosure;

FIG. 5 is a schematic diagram of another sampling result and an adjusted differential signal pair according to an embodiment of the present application;

fig. 6 is a schematic structural diagram of a computing device according to an embodiment of the present application.

Detailed Description

Embodiments of the present application will be described in further detail below with reference to the accompanying drawings.

It should be understood that in the description of this application, "at least one" means one or more than one, and "a plurality" means two or more than two. In addition, the words "first," "second," and the like, unless otherwise indicated, are used solely for the purposes of description and are not to be construed as indicating or implying a relative importance or order.

FIG. 1 is a schematic diagram of a double data rate synchronous dynamic random access memory application scenario. As shown in fig. 1, in the double data rate synchronous dynamic random access memory application scenario, the double data rate synchronous dynamic random access memory physical interface layer 110 and the double data rate synchronous dynamic random access memory device side 120 are connected through a parallel interface. Wherein the double data rate synchronous dynamic random access memory physical interface layer 110 is the physical interface layer of double data rate synchronous dynamic random access memory (Double Data Rate Synchronous Dynamic Random Access Memory, DDR SRAM). Data read between the double data rate synchronous dynamic random access memory physical interface layer 110 and the double data rate synchronous dynamic random access memory device side 120 generally begins with the double data rate synchronous dynamic random access memory device side 120 receiving a read command 130. The double data rate synchronous dynamic random access memory device side 120 then returns the parallel data signal 132 and the data select signal 134 to the double data rate synchronous dynamic random access memory physical interface layer 110 via different lines, respectively. The parallel port data signal 132 is a plurality of beats of data signals, the data selection signal 134 and the parallel port data signal 132 are generated simultaneously, and the data transmission is performed twice on the rising edge and the falling edge of the external clock in the double data rate synchronous dynamic random access memory device side 120 under the action of the data selection signal 134, so that the data transmission twice as wide as the chip bit width is realized, namely, the double data rate is realized. At the receiving end, i.e., the double data rate synchronous dynamic random access memory physical interface layer 110, the received data select signal 134 is utilized to sample the parallel port data signal 132, thereby distinguishing between two transmission cycles within the same clock cycle at the sending end, i.e., the parallel port data signal 132 from the double data rate synchronous dynamic random access memory device side 120. Taking fig. 1 as an example, in an application scenario where a high-speed parallel interface connection is adopted, for example, a high-performance memory based on DDR SRAM, and further, for example, a standard communication interface specification based on DDR SRAM, such as a double data rate synchronous dynamic random access memory physical layer interface (DDR PHY Interface, DFI) protocol, multiple bits of parallel data are transmitted through a single channel, which is affected by factors such as delay and clock offset, and challenges are faced in improving transmission performance and channel rate. Although the parallel data signal 132 and the data select signal 134 are generated internally on the double data rate synchronous dynamic random access memory device side 120, clock skew, i.e., delay differences between multiple sub-clock signals generated by the same clock, may be generated. Factors that may cause clock skew may be skew between the outputs of the clock driver, may include routing errors, etc. And, the double data rate synchronous dynamic random access memory device side 120 responds to the read command 130 to return the parallel port data signal 132 and the data selection signal 134 to the double data rate synchronous dynamic random access memory physical interface layer 110 through different lines, respectively. Generally, the hardware delay of the data select signal 134 is large or the lines used to transmit the data select signal 134 may cause a large delay. Therefore, at the receiving end, i.e. the physical interface layer 110 of the double data rate synchronous dynamic random access memory, due to the delay difference and clock offset, it is difficult to correctly sample the parallel data signal 132 through the data selection signal 134, which may result in data loss, and thus, it is not beneficial to correctly execute the read command 130 and to improve the overall processing efficiency. In addition, the double data rate synchronous dynamic random access memory physical interface layer 110 and the double data rate synchronous dynamic random access memory device side 120 are connected through a parallel interface, and the parallel interface data signal 132 includes a plurality of signals, for example, corresponding to 8 data signals, and delay differences between each of the 8 data signals and the data selection signal 134 may not be consistent. In order to ensure that the parallel data signal 132 can be read correctly with the data select signal 134, it is necessary to cope with the delay differences of the data signals under the parallel data signal 132. In addition, the plurality of data signals under the parallel port data signal 132 are generally transmitted through different lines, and if the parallel port data signal 132 includes 8 data signals, the 8 data signals pass through 8 lines, that is, each data signal corresponds to one data signal line. Therefore, there may be different hardware delays between the data signal lines corresponding to the data signals under the parallel port data signal 132. For this reason, in the application scenario of the double data rate synchronous dynamic random access memory, and similar application scenarios that employ high-speed parallel interface connection, such as high-performance memory based on DDR SRAM and DFI protocol, challenges in correctly sampling data signals at the receiving end due to clock offset, hardware delay difference, and the like need to be addressed. The following describes in detail, with reference to specific embodiments of the present application, how to address these challenges, a data alignment method, a computer device, and a medium for parallel interface connection provided in the embodiments of the present application.

Fig. 2 is a flow chart of a data alignment method for parallel interface connection according to an embodiment of the present application. As shown in fig. 2, the data alignment method includes the following steps.

Step S210: and receiving a plurality of parallel port data signals and a data selection signal through a receiving end, wherein each of the plurality of parallel port data signals comprises a plurality of first signals, the first signals are in one-to-one correspondence with a plurality of first lines between the receiving end and a transmitting end, each of the first signals is transmitted through a first line corresponding to the first signal in the first lines, the data selection signal is transmitted through a second line between the receiving end and the transmitting end, the plurality of parallel port data signals are transmitted based on the upper edge and the lower edge of a reference clock signal, and the data selection signal is a first differential signal pair generated based on the reference clock signal.

Step S220: and generating a plurality of second differential signal pairs corresponding to the first lines one by one based on the data selection signals through the receiving end.

Step S230: for each first signal in the plurality of first signals, sampling the first signal according to first three sampling clock edges of a second differential signal pair corresponding to a first line corresponding to the first signal in the plurality of second differential signal pairs to obtain first three sampling results respectively, then selecting a first beat sampling clock edge from the first three sampling clock edges based on the first three sampling results, adjusting the second differential signal pair based on the first beat sampling clock edge to obtain an adjusted differential signal pair, and sampling the first signal by using the first beat sampling clock edge and the adjusted second differential signal pair to realize data alignment between the multi-beat parallel port data signal and the data selection signal.

Referring to fig. 2, in step S210, a multi-beat parallel port data signal and a data selection signal are received by a receiving end. Each beat of parallel port data signal in the multi-beat parallel port data signals comprises a plurality of first signals, the first signals are in one-to-one correspondence with a plurality of first lines between the receiving end and the transmitting end, each first signal in the plurality of first signals is transmitted through a first line corresponding to the first signal in the plurality of first lines, the data selection signal is transmitted through a second line between the receiving end and the transmitting end, the multi-beat parallel port data signals are transmitted based on the upper edge trigger and the lower edge trigger of a reference clock signal, and the data selection signal is a first differential signal pair generated based on the reference clock signal. In the application scenario of parallel interface connection, for example, a double data rate synchronous dynamic random access memory (Double Data Rate Synchronous Dynamic Random Access Memory, DDR SRAM), a high performance memory based on DDR SRAM, and an interconnection device using a double data rate synchronous dynamic random access memory physical layer interface (DDR PHY Interface, DFI) protocol as a standard communication specification, etc., in order to implement double data rate, data transmission is triggered based on the upper and lower edges of a reference clock signal, for example, data transmission is performed in two times on the rising edge and the falling edge of the reference clock signal, that is, there are two transmission periods in one clock period, so that data transmission twice as wide as a chip bit width can be implemented, thereby fully utilizing the bandwidth resources of parallel interface connection. In some examples, the transmitting end corresponds to a side of a double data rate synchronous dynamic random access memory device, such as one or more double data rate synchronous dynamic random access memory devices, and the receiving end corresponds to a physical interface layer or a motherboard card of the double data rate synchronous dynamic random access memory device. In some examples, with DDR SRAM of DDR 4 or DDR 5 related standards, the training firmware of the physical interface layer sends a read command to the device side, which then returns the data to be read to the physical interface layer. The receiving end receives the multi-beat parallel port data signal and the data selection signal. Wherein the multi-beat parallel port data signal represents data to be read and is a multi-beat data signal. The data selection signal is generated at a transmitting end together with a multi-beat parallel port data signal, the multi-beat parallel port data signal is transmitted based on the triggering of the upper edge and the lower edge of a reference clock signal, and the data selection signal is a first differential signal pair generated based on the reference clock signal. The multi-beat parallel port data signal is transmitted over the same channel and the data select signal associated therewith is used to sample the signal received by the receiving end over that channel to read the data correctly. That is, since the data selection signal is a first differential signal pair generated based on the reference clock signal, the data selection signal may be used to sample the multi-beat parallel port data signal transmitted based on the up-down edge trigger of the reference clock signal, so that in the case where the multi-beat parallel port data signal is transmitted in such a manner that there are two transmission periods within the same clock period (for example, data transmission is performed in two times on the rising edge and the falling edge of the external clock under the action of the data selection signal within the transmitting end such as the double data rate synchronous dynamic random access memory device side), two transmission periods within the same clock period are separated at the receiving end so as to achieve correct data reading. In addition, each of the multi-beat parallel port data signals includes a plurality of first signals, the plurality of first signals are in one-to-one correspondence with a plurality of first lines between the receiving end and the transmitting end, each of the plurality of first signals is transmitted through a first line corresponding to the first signal among the plurality of first lines, and the data selection signal is transmitted through a second line between the receiving end and the transmitting end. Here, the plurality of first lines are used for transmitting a plurality of first signals under the multi-beat parallel port data signal, and the second lines are used for transmitting the data selection signal. There may be a delay difference, such as a hardware delay, between the plurality of first lines, such as a hardware delay, between each of the plurality of first lines and the second line, and a delay difference, such as a hardware delay, between each of the plurality of first lines and the second line, may not be uniform. Therefore, there may be a delay difference between the plurality of first signals transmitted through the plurality of first lines, respectively, and there may also be a delay difference between each of the plurality of first signals and the data selection signal. In addition, the clock skew affects, that is, there may be a delay difference between a plurality of sub-clock signals generated by the same clock due to the clock driver output skew, the trace error, and the like, and thus there may be a delay difference between the data selection signal transmitted from the transmitting end to the receiving end and the multi-beat parallel port data signal due to the clock skew affects. In order to correctly read data at the receiving end, it is necessary to implement data alignment between the multi-beat parallel port data signal and the data selection signal, that is, to overcome misalignment between the data selection signal and each of the plurality of first signals included in each of the multi-beat parallel port data signals due to factors such as hardware delay and clock skew.

With continued reference to fig. 2, in step S220, a plurality of second differential signal pairs corresponding to the plurality of first lines one-to-one are generated by the receiving end based on the data selection signal. As mentioned above, the plurality of first lines are used for transmitting the plurality of first signals under the multi-beat parallel port data signal, and the second lines are used for transmitting the data selection signal. There may be a delay difference, such as a hardware delay, between the plurality of first lines, such as a hardware delay, between each of the plurality of first lines and the second line, and a delay difference, such as a hardware delay, between each of the plurality of first lines and the second line, may not be uniform. When the effects caused by hardware delay and clock skew exceed a certain level, data loss may result, for example, the first beat of valid data is difficult to be effectively collected by the data selection signal. And, while realizing the alignment of data between the multi-beat parallel port data signal and the data selection signal so as to correctly read data, the performance in terms of transmission performance and channel rate needs to be considered. If the first signals are aligned and then aligned with the data selection signals, the alignment operation is performed twice, which results in low transmission performance and is not beneficial to improving the channel rate. The data selection signal is a first differential signal pair generated based on the reference clock signal, and in step S220, a plurality of second differential signal pairs corresponding to the plurality of first lines one to one are generated based on the data selection signal. That is, by the receiving end, a plurality of second differential signal pairs corresponding to the plurality of first lines one to one are generated based on the first differential signal pairs. In some examples, the receiving end is a physical interface layer of the double data rate synchronous dynamic random access memory, the first differential signal pair may be divided into a plurality of differential signal pairs by hardware and analog circuits inside the physical interface layer, and the specific structure, device and circuit may adopt any suitable implementation manner, which is not limited herein.

With continued reference to fig. 2, in step S230, for each first signal of the plurality of first signals, first three sampling results are obtained by sampling the first signal according to first three sampling clock edges of a second differential signal pair corresponding to a first line corresponding to the first signal of the plurality of second differential signal pairs, then, based on the first three sampling results, a first beat sampling clock edge is selected from the first three sampling clock edges, and based on the first beat sampling clock edge, the second differential signal pair is adjusted to obtain an adjusted differential signal pair, and the first signal is sampled by using the first beat sampling clock edge and the adjusted second differential signal pair, so as to realize data alignment between the multi-beat parallel port data signal and the data selection signal. In this way, the first signal is sampled by the first three sampling clock edges to obtain first three sampling results respectively, then the first sampling clock edge is selected from the first three sampling clock edges based on the first three sampling results, and then the second differential signal pair is adjusted based on the first sampling clock edge to obtain an adjusted differential signal pair, so that only one alignment operation or one adjustment operation is needed, and the transmission performance and the channel rate are improved. Further, for each first signal of the plurality of first signals, sampling is performed according to a second differential signal pair corresponding to a first line corresponding to the first signal of the plurality of second differential signal pairs to obtain first three sampling results, so that subsequent adjustment and alignment are realized for each first signal through the corresponding second differential signal pair. In this way, there is no need to take into account any delay differences, such as hardware delays, that may exist between the plurality of first lines, nor clock offsets between the plurality of first signals, which saves the overhead of deskew training. Compared to the method of aligning the first signals and then aligning the second signals with the data selection signal, the data alignment method shown in fig. 2 generates the second differential signal pairs corresponding to the first lines one by one based on the first differential signal pairs, and then performs an alignment operation, that is, adjusts the second differential signal pairs based on the first sampling clock edge to obtain adjusted differential signal pairs, thereby achieving data alignment between the multi-beat parallel port data signal and the data selection signal so as to correctly read data while also achieving high transmission performance and high channel rate.

With continued reference to fig. 2, it is mentioned that, by the receiving end, a plurality of second differential signal pairs corresponding to the plurality of first lines one to one are generated based on the data selection signal, that is, the first differential signal pair, and then, for each of the plurality of first signals, a subsequent sampling operation and an adjustment operation are performed according to the second differential signal pair corresponding to the first line corresponding to the first signal. This eliminates the need to take into account possible delay differences and clock skew between the first lines, thereby saving resources for deskew training and additional resources required for the two alignment operations. Since the respective second differential signal pairs are to be provided for each first signal separately in order to perform the subsequent sampling operation and adjustment operation, this means that the larger the number of the plurality of first signals under the multi-beat parallel port data signal, the larger the number of second differential signal pairs that need to be provided, and the greater the number of sampling operations and adjustment operations that need to be performed as well. The adjustment operation means that the differential signal pair is delayed, thereby achieving alignment. In a hardware implementation, the delay processing of the electrical signal may be accomplished by analog circuit hardware such as a plurality of inverters. The number of inverters determines the adjustment capability, i.e. the maximum adjustment range over which the signal can be delayed. However, analog circuit hardware, such as an inverter, for delay processing of an electrical signal may occupy resources, resulting in a larger circuit area and higher power consumption. Also, since a corresponding second differential signal pair needs to be provided separately for each first signal in order to perform the subsequent sampling operation and adjustment operation, this means that analog circuit hardware such as an inverter needs to be provided separately for each first signal to make adjustment, which means that the number of the plurality of first signals under the multi-beat parallel port data signal affects the occupation of resources, the increase of circuit area, and the increase of power consumption as a whole. On the one hand, for the purpose of improving the resource utilization efficiency, the resource occupation of the analog circuit hardware should be reduced as much as possible, for example, the number of inverters is reduced as much as possible, which inevitably results in limitation of the adjustment capability of delay processing on the signal. On the other hand, in order to achieve the data alignment between the multi-beat parallel port data signal and the data selection signal after the signal is adjusted, there must be enough adjustment capability to overcome the effects of delay differences and clock offsets, and system frequency and product requirements need to be considered. For example, a product characteristic aspect may dictate that the offset between the multi-beat parallel port data signal and the data select signal be between plus or minus 100 picoseconds, meaning that the maximum offset estimate is around 200 picoseconds. Here, the delay adjustment capability for the differential signal is limited by the system frequency, and is generally set to half a clock period corresponding to the system frequency. When the system frequency is high, such as 4800 mhz, the half clock period corresponding to the system frequency is about 208 picoseconds, so that the data alignment requirement in the extreme case of offset between the multi-beat parallel port data signal and the data select signal can be substantially satisfied. Depending on the application scenario and the user's needs, there may be multiple frequency points, multiple communication protocol requirements, which may result in a change in system frequency, or a need to adapt to multiple different system frequencies. When the system frequency is greater than 4800 megahertz, the allowable offset limit of the system will be less than half a clock period; when the system frequency is less than 4800 mhz, the allowable offset limit of the system will be greater than half a clock cycle. Thus, as the system frequency changes, the delay adjustment capability for the differential signal also changes, and the comparison with respect to the allowable offset limit of the system may also change. In order to meet the requirements of various application scenarios, various frequency points and various communication protocols, it is necessary to provide delay adjustment capability for differential signals high enough to achieve data alignment at different system frequencies, and at the same time, the problems of resource occupation, increase in circuit area and increase in power consumption caused by analog circuit hardware need to be considered. The data alignment method for parallel interfacing shown in fig. 2 uses limited analog circuit hardware to provide limited delay adjustment capability for differential signals and around limited delay adjustment capability for differential signals, which is equivalent to expanding the limited delay adjustment capability through an optimized design of sampling operations and adjustment operations. Specifically, for each first signal in the plurality of first signals, sampling the first signal according to first three sampling clock edges of a second differential signal pair corresponding to a first line corresponding to the first signal in the plurality of second differential signal pairs to obtain first three sampling results respectively. Such a sampling operation means that sampling with the first three sampling clock edges of the differential signal pair can result in a greater probability of acquiring the correct data signal over a greater range than sampling with a single sampling clock edge, which equivalently expands the delay adjustment capability. Next, since the first three sampling clock edges are used for sampling, there is a possibility that the sampling result is empty, and a valid sampling clock edge needs to be selected based on the first three sampling results, that is, a first beat sampling clock edge is selected from the first three sampling clock edges based on the first three sampling results. And then adjusting the second differential signal pair based on the first beat sampling clock edge to obtain an adjusted differential signal pair, so that the delay adjustment capability is expanded, and the delay adjustment capability is expanded to be three times of a half clock period, namely a range of 1.5 clock periods under the condition of half clock period, thereby being beneficial to improving the resource utilization rate. Further, as mentioned above, the multi-beat parallel port data signal is transmitted based on the triggering of the upper and lower edges of the reference clock signal, and the data selection signal is a first differential signal pair generated based on the reference clock signal. The data selection signal may be used to sample the multi-beat parallel port data signal that is sent based on the up and down edge triggers of the reference clock signal, so that in the case where the multi-beat parallel port data signal is sent with two transmission periods in the same clock period (for example, data transmission is performed in two times on the rising edge and the falling edge of the external clock under the action of the data selection signal inside the sending end such as the side of the double data rate synchronous dynamic random access memory device), the two transmission periods in the same clock period are separated in the receiving end so as to achieve correct data reading. Therefore, the characteristic that the multi-beat parallel port data is transmitted based on the up-down edge trigger of the reference clock signal means that there are two transmission periods within the same clock period, in other words, one half clock period corresponds to one transmission period. In this way, the optimal design of sampling operation and adjustment operation by using the first three sampling clock edges can be combined, in the case that the delay adjustment capability is half a clock period (for example, the delay adjustment capability for the differential signal is set to be half a clock period corresponding to the system frequency), the effective sampling clock edges can be better selected based on the first three sampling results, and various possible data misalignment situations can be better covered, so that the data alignment can be realized under different system frequencies.

In summary, the data alignment method for parallel interface connection shown in fig. 2 achieves data alignment between the multi-beat parallel port data signal and the data selection signal so as to correctly read data, and simultaneously combines high transmission performance and high channel rate, and by optimizing design of sampling operation and adjustment operation, limited delay adjustment capability is equivalently enlarged, resource utilization rate is improved, and further, requirements of various application scenes, various frequency points and various communication protocols are met, and delay adjustment capability of differential signals can be provided sufficiently high so as to achieve data alignment under different system frequencies.

It should be appreciated that the data alignment method for parallel interfacing shown in fig. 2 may be used to achieve data alignment between the multi-beat parallel port data signal and the data selection signal. Here, the multi-beat parallel port data signal corresponds to a communication channel, and the data selection signal is a set of differential signal pairs for sampling the parallel port data signal transmitted through the communication channel. In this way, the multi-beat parallel port data signal that is transmitted based on the up and down edge trigger of the reference clock signal is sampled by the data selection signal, so that in the case where the multi-beat parallel port data signal is transmitted in such a manner that there are two transmission periods in the same clock period (for example, data transmission is performed in two times on the rising edge and the falling edge of the external clock under the action of the data selection signal inside the transmitting end such as the double data rate synchronous dynamic random access memory device side), the two transmission periods in the same clock period are separated in the receiving end so as to achieve correct data reading. In one possible implementation, the transmitting end may transmit data to the receiving end through a plurality of communication channels, for example, depending on the bit width supported by the system, the transmitting end may transmit a plurality of sets of multi-beat parallel port data signals, each set of multi-beat parallel port data signals referring to the multi-beat data signals shown in fig. 2, and each set of multi-beat parallel port data signals further has a corresponding data selection signal, i.e., a differential signal pair, for sampling independently of each other. For the case where there are a plurality of communication channels and a plurality of groups of multi-beat parallel port data signals, reference may be made to the data alignment method for parallel interface connection shown in fig. 2, and for each group of multi-beat parallel port data signals and corresponding data selection signals, data alignment between the group of multi-beat parallel port data signals and the data selection signals is achieved.

In one possible implementation, the multi-beat parallel port data signal is sent based on the up and down edge triggers of the reference clock signal such that the same clock cycle of the reference clock signal includes two transmission cycles, and the data selection signal is used to distinguish between the two transmission cycles included in the same clock cycle of the reference clock signal. In this way, the data selection signal may be used to sample the multi-beat parallel port data signal that is sent based on the up and down edge triggers of the reference clock signal, so that in the case where the multi-beat parallel port data signal is sent in a manner that there are two transmission periods in the same clock period (for example, data transmission is performed in two times on the rising edge and the falling edge of the external clock under the action of the data selection signal inside the sending end such as the side of the double data rate synchronous dynamic random access memory device), two transmission periods in the same clock period are separated in the receiving end so as to achieve correct data reading.

In one possible implementation, the receiving end is a physical interface layer of a double data rate synchronous dynamic random access memory, and the transmitting end is a double data rate synchronous dynamic random access memory device side, and the double data rate synchronous dynamic random access memory device side transmits the multi-beat parallel port data signal and the data selection signal in response to a read command. In some embodiments, the double data rate synchronous dynamic random access memory device side includes a plurality of double data rate synchronous dynamic random access memory devices, any of the plurality of double data rate synchronous dynamic random access memory devices being configured to transmit the multi-beat parallel port data signal and the data select signal and supporting a data bit width corresponding to a number of the plurality of first signals. In some embodiments, the multi-beat parallel port data signals are each 8 bits, the first plurality of signals are each 1 bit, and the number of first plurality of signals is 8. Therefore, in the application scenario related to the double data rate synchronous dynamic random access memory, the parallel port data transmission by adopting the high-speed parallel interface connection is realized, and the parallel port data transmission has high transmission performance and high channel rate.

In one possible implementation, the delay of the second line is greater than the delay of any of the plurality of first lines, and the delay between any two of the plurality of first lines is not greater than a first threshold, the first threshold being determined based on a communication interface specification between the receiving end and the transmitting end. In this way, the communication interface specification can be flexibly adapted, and delay differences between lines can be effectively dealt with.

Compared with the data alignment method shown in fig. 2, the first three sampling clock edges are adopted for sampling compared with the sampling by a single sampling clock edge, so that the first three sampling results are obtained, the correct data signals can be acquired with a larger probability in a larger range, and the delay adjustment capability is equivalently enlarged. There may be a case where the first three sampling results are empty, and a valid sampling clock edge needs to be selected based on the first three sampling results, that is, a first beat sampling clock edge is selected from the first three sampling clock edges based on the first three sampling results. And then adjusting the second differential signal pair based on the first beat sampling clock edge to obtain an adjusted differential signal pair. In addition, the optimal design of sampling operation and adjustment operation by utilizing the first three sampling clock edges can be combined, and in the case that the delay adjustment capability is half a clock period (for example, the delay adjustment capability of differential signals is set to be half a clock period corresponding to the system frequency), the effective sampling clock edges can be better selected based on the first three sampling results, and various possible data misalignment situations can be better covered, so that the data alignment can be realized under different system frequencies. This is described in further detail below in conjunction with fig. 3, 4 and 5.

Fig. 3 is a schematic diagram of a sampling result and an adjusted differential signal pair according to an embodiment of the present application. In one possible implementation, the first three sampling clock edges of the second differential signal pair are a first sampling clock edge, a second sampling clock edge, and a third sampling clock edge, wherein the second sampling clock edge follows the first sampling clock edge and the third sampling clock edge follows the second sampling clock edge, the first sampling clock edge and the third sampling clock edge being located at the same differential signal of the second differential signal pair, the second sampling clock edge being located at another differential signal of the second differential signal pair relative to the same differential signal. In some embodiments, the first three sampling results include a first sampling result, a second sampling result, and a third sampling result, wherein the first sampling result is obtained by sampling the first signal based on the first sampling clock edge, the second sampling result is obtained by sampling the first signal based on the second sampling clock edge, and the third sampling result is obtained by sampling the first signal based on the third sampling clock edge. In some embodiments, the first, second, and third sampling clock edges are each rising or falling clock edges. Taking the rising clock edge as an example in fig. 3, it should be understood that the falling clock edge may also be used as the sampling clock edge, and the relevant details are adjusted, which will not be described herein. As shown in fig. 3, the upper half of fig. 3 shows a second differential signal pair a before adjustment, which is composed of a first differential signal 310 of the second differential signal pair a before adjustment and a first differential signal 312 of the second differential signal pair a before adjustment, as compared with the first signal a 302, it can be seen that: the first sampling clock edge 320 of the second differential signal pair a before adjustment corresponds to the first sampling clock edge, the second sampling clock edge 322 of the second differential signal pair a before adjustment corresponds to the second sampling clock edge, the third sampling clock edge 324 of the second differential signal pair a before adjustment corresponds to the third sampling clock edge, and the first signal a 302 is sampled using the first three sampling clock edges to obtain the first three sampling results. The lower part of fig. 3 shows an adjusted second differential signal pair a consisting of a first differential signal 330 of the adjusted second differential signal pair a and a first differential signal 332 of the adjusted second differential signal pair a, and compared to the first signal a 302, it can be seen that the first sampling clock edge 340 of the adjusted second differential signal pair a, the second sampling clock edge 342 of the adjusted second differential signal pair a, and the third sampling clock edge 344 of the adjusted second differential signal pair a are each positioned relative to the first signal a 302. The sampling results and adjusted differential signal pairs shown in fig. 3 are exemplary: when the first sampling result and the second sampling result are both null and the third sampling result is not null, the first sampling clock edge is the third sampling clock edge, wherein adjusting the second differential signal pair based on the third sampling clock edge to obtain the adjusted differential signal pair includes: the first sampling clock edge is used for scanning the front edge of the second beat data of the first signal, then the third sampling clock edge is used for scanning the rear edge of the first beat data of the first signal so as to obtain a first scanning result, the center position of the first beat data of the first signal is calculated based on the first scanning result, and the second differential signal pair is adjusted so that the third sampling clock edge is aligned with the center position of the first beat data of the first signal. As shown in fig. 3, by comparing the second differential signal pair a before adjustment with the first signal a 302, it can be seen that the sampling results corresponding to the first sampling clock edge 320 of the second differential signal pair a before adjustment and the second sampling clock edge 322 of the second differential signal pair a before adjustment are both null, that is, no valid data is collected. Thus, the first beat sample clock edge is the third sample clock edge. The second differential signal pair is adjusted based on the third sampling clock edge to obtain the adjusted differential signal pair a, and it can be seen that the third sampling clock edge 344 of the adjusted second differential signal pair a aligns with the center position of the first beat data D0 of the first signal a 302. The first beat of data for the first signal a 302 is D0, the second beat of data is D1, and so on, followed by D2, D3, D4, D5, D6, D7, D8. And the edge scanning algorithm performed around the first sampling clock edge also embodies the optimal design for sampling operation and adjustment operation by using the first three sampling clock edges, so that the corresponding edge can be scanned by only limited edge scanning capability, and further, the basis is provided for subsequent calculation.

Fig. 4 is a schematic diagram of another sampling result and an adjusted differential signal pair according to an embodiment of the present application. In one possible implementation, the first three sampling clock edges of the second differential signal pair are a first sampling clock edge, a second sampling clock edge, and a third sampling clock edge, wherein the second sampling clock edge follows the first sampling clock edge and the third sampling clock edge follows the second sampling clock edge, the first sampling clock edge and the third sampling clock edge being located at the same differential signal of the second differential signal pair, the second sampling clock edge being located at another differential signal of the second differential signal pair relative to the same differential signal. In some embodiments, the first three sampling results include a first sampling result, a second sampling result, and a third sampling result, wherein the first sampling result is obtained by sampling the first signal based on the first sampling clock edge, the second sampling result is obtained by sampling the first signal based on the second sampling clock edge, and the third sampling result is obtained by sampling the first signal based on the third sampling clock edge. In some embodiments, the first, second, and third sampling clock edges are each rising or falling clock edges. Taking the rising clock edge as an example in fig. 4, it should be understood that the falling clock edge may also be used as the sampling clock edge, and the relevant details are adjusted, which will not be described herein. As shown in fig. 4, the upper half of fig. 4 shows a pre-adjustment second differential signal pair B composed of a first differential signal 410 of the pre-adjustment second differential signal pair B and a first differential signal 412 of the pre-adjustment second differential signal pair B, and it can be seen that, compared with the first signal B402: the first sampling clock edge 420 of the second differential signal pair B before adjustment corresponds to the first sampling clock edge, the second sampling clock edge 422 of the second differential signal pair B before adjustment corresponds to the second sampling clock edge, the third sampling clock edge 424 of the second differential signal pair B before adjustment corresponds to the third sampling clock edge, and the first signal B402 is sampled using the first three sampling clock edges to obtain the first three sampling results. The lower part of fig. 4 shows an adjusted second differential signal pair B consisting of a first differential signal 430 of the adjusted second differential signal pair B and a first differential signal 432 of the adjusted second differential signal pair B, and compared to the first signal B402, it can be seen that the first sampling clock edge 440 of the adjusted second differential signal pair B, the second sampling clock edge 442 of the adjusted second differential signal pair B, and the third sampling clock edge 444 of the adjusted second differential signal pair B are each positioned relative to the first signal B402. The sampling results and adjusted differential signal pairs shown in fig. 4 are exemplary: when the first sampling result is null and the second sampling result is not null, the first sampling clock edge is the second sampling clock edge, wherein adjusting the second differential signal pair based on the second sampling clock edge to obtain the adjusted differential signal pair includes: the second sampling clock edge is used for scanning the front edge of the first beat data of the first signal and then the third sampling clock edge is used for scanning the rear edge of the first beat data of the first signal so as to obtain a second scanning result, the center position of the first beat data of the first signal is calculated based on the second scanning result, and the second differential signal pair is adjusted so that the second sampling clock edge is aligned with the center position of the first beat data of the first signal. As shown in fig. 4, by comparing the second differential signal pair B before adjustment with the first signal B402, it can be seen that the first sampling clock edge 420 of the second differential signal pair B before adjustment is empty and the sampling result corresponding to the second sampling clock edge 422 of the second differential signal pair B before adjustment is not empty. Thus, the first beat sample clock edge is the second sample clock edge. The second differential signal pair is adjusted based on the second sampling clock edge to obtain the adjusted differential signal pair B, and it can be seen that the second sampling clock edge 442 of the adjusted second differential signal pair B aligns with the center position of the first beat data D0 of the first signal B402. The first beat of data for the first signal B402 is D0, the second beat of data is D1, and so on, followed by D2, D3, D4, D5, D6, D7, D8. And the edge scanning algorithm performed around the first sampling clock edge also embodies the optimal design for sampling operation and adjustment operation by using the first three sampling clock edges, so that the corresponding edge can be scanned by only limited edge scanning capability, and further, the basis is provided for subsequent calculation.

FIG. 5 is a schematic diagram of another sampling result and an adjusted differential signal pair according to an embodiment of the present application; in one possible implementation, the first three sampling clock edges of the second differential signal pair are a first sampling clock edge, a second sampling clock edge, and a third sampling clock edge, wherein the second sampling clock edge follows the first sampling clock edge and the third sampling clock edge follows the second sampling clock edge, the first sampling clock edge and the third sampling clock edge being located at the same differential signal of the second differential signal pair, the second sampling clock edge being located at another differential signal of the second differential signal pair relative to the same differential signal. In some embodiments, the first three sampling results include a first sampling result, a second sampling result, and a third sampling result, wherein the first sampling result is obtained by sampling the first signal based on the first sampling clock edge, the second sampling result is obtained by sampling the first signal based on the second sampling clock edge, and the third sampling result is obtained by sampling the first signal based on the third sampling clock edge. In some embodiments, the first, second, and third sampling clock edges are each rising or falling clock edges. Taking the rising clock edge as an example in fig. 5, it should be understood that the falling clock edge may also be used as the sampling clock edge, and the relevant details are adjusted, which will not be described herein. As shown in fig. 5, the upper half of fig. 5 shows a second differential signal pair C before adjustment, which is composed of a first differential signal 510 of the second differential signal pair C before adjustment and a first differential signal 512 of the second differential signal pair C before adjustment, and it can be seen that, compared with the first signal C502: the first sampling clock edge 520 of the second differential signal pair C before adjustment corresponds to the first sampling clock edge, the second sampling clock edge 522 of the second differential signal pair C before adjustment corresponds to the second sampling clock edge, the third sampling clock edge 524 of the second differential signal pair C before adjustment corresponds to the third sampling clock edge, and the first signal C502 is sampled using the first three sampling clock edges to obtain the first three sampling results. The lower part of fig. 5 shows an adjusted second differential signal pair C consisting of a first differential signal 530 of the adjusted second differential signal pair C and a first differential signal 532 of the adjusted second differential signal pair C, and compared to the first signal C502, the relative positions of each of the first sampling clock edge 540 of the adjusted second differential signal pair C, the second sampling clock edge 542 of the adjusted second differential signal pair C, and the third sampling clock edge 544 of the adjusted second differential signal pair C with respect to the first signal C502 can be seen. The sampling results and adjusted differential signal pairs shown in fig. 5 are exemplary: when the first sampling result is not null, the first beat sampling clock edge is the first sampling clock edge, wherein adjusting the second differential signal pair based on the first sampling clock edge to obtain the adjusted differential signal pair includes: the first sampling clock edge is used for scanning the front edge of the first beat data of the first signal, then the second sampling clock edge is used for scanning the rear edge of the first beat data of the first signal so as to obtain a third scanning result, the center position of the first beat data of the first signal is calculated based on the third scanning result, and the second differential signal pair is adjusted so that the first sampling clock edge is aligned with the center position of the first beat data of the first signal. As shown in fig. 5, by comparing the second differential signal pair C before adjustment with the first signal C502, it can be seen that the first sampling clock edge 520 of the second differential signal pair C before adjustment is not null. Thus, the first beat sample clock edge is the first sample clock edge. The second differential signal pair is adjusted based on the first sampling clock edge to obtain the adjusted differential signal pair C, and it can be seen that the first sampling clock edge 540 of the adjusted second differential signal pair C is aligned with the center position of the first beat data D0 of the first signal C502. The first beat of data for the first signal C502 is D0, the second beat of data is D1, and so on, followed by D2, D3, D4, D5, D6, D7, D8. And the edge scanning algorithm performed around the first sampling clock edge also embodies the optimal design for sampling operation and adjustment operation by using the first three sampling clock edges, so that the corresponding edge can be scanned by only limited edge scanning capability, and further, the basis is provided for subsequent calculation.

Referring to fig. 3-5, fig. 3-5 exemplarily illustrate that a valid sampling clock edge is selected based on the first three sampling results, i.e., a first beat sampling clock edge is selected from the first three sampling clock edges based on the first three sampling results. And then adjusting the second differential signal pair based on the first beat sampling clock edge to obtain an adjusted differential signal pair. In this way, the optimal design of sampling operation and adjustment operation by using the first three sampling clock edges can be combined, in the case that the delay adjustment capability is half a clock period (for example, the delay adjustment capability for the differential signal is set to be half a clock period corresponding to the system frequency), the effective sampling clock edges can be better selected based on the first three sampling results, and various possible data misalignment situations can be better covered, so that the data alignment can be realized under different system frequencies. And after the second differential signal pair is adjusted based on the first beat sampling clock edge to obtain an adjusted differential signal pair, the first beat sampling clock edge is used as an effective sampling clock edge to the center position of the first beat data of the first signal, so that the sampling to a metastable state can be avoided, and errors caused by missing sampling and wrong sampling can be avoided.

With continued reference to fig. 2, in one possible implementation, the plurality of second differential signal pairs are in one-to-one correspondence with a plurality of delay chains, where adjusting the second differential signal pairs based on the first beat sampling clock edge results in the adjusted differential signal pairs, including: and based on the first beat sampling clock edge, delaying the second differential signal pair through a delay chain corresponding to the second differential signal pair in the plurality of delay chains to obtain the adjusted differential signal pair, wherein the maximum delay range of the delay chain does not exceed half period of the first differential signal pair. In some embodiments, adjusting the second differential signal pair based on the first beat sampling clock edge results in the adjusted differential signal pair, further comprising: the first signal is selectively scanned using the first three sampling clock edges based on the first beat sampling clock edges and the scan range does not exceed the maximum delay range of the delay chain. For the purpose of improving the resource utilization efficiency, the resource occupation of the analog circuit hardware should be reduced as much as possible, for example, the number of inverters is reduced as much as possible, which inevitably results in limitation of the adjustment capability of delay processing on signals. In order to achieve data alignment between the multi-beat parallel port data signal and the data select signal after the signal is adjusted, there must be sufficient adjustment capability to overcome the effects of delay differences and clock skew, and system frequency and product requirements must be considered. In this way, in the case of limited delay adjustment capability, that is, the maximum delay range of the delay chain does not exceed half the period of the first differential signal pair, the first sampling clock edge is selected from the first three sampling clock edges based on the first three sampling results, and then the second differential signal pair is adjusted based on the first sampling clock edge, so that the delay adjustment capability is equivalently enlarged, and in the case of half the delay adjustment capability, the delay adjustment capability is equivalently enlarged to three times the half clock period, that is, 1.5 clock periods, thereby contributing to improving the resource utilization rate and realizing the data alignment under different system frequencies.

Fig. 6 is a schematic structural diagram of a computing device provided in an embodiment of the present application, where the computing device 600 includes: one or more processors 610, a communication interface 620, and a memory 630. The processor 610, communication interface 620, and memory 630 are connected to each other by a bus 640. Optionally, the computing device 600 may further include an input/output interface 650, where the input/output interface 650 is connected to an input/output device for receiving parameters set by a user, etc. The computing device 600 can be used to implement some or all of the functionality of the device embodiments or system embodiments described above in the embodiments of the present application; the processor 610 can also be used to implement some or all of the operational steps of the method embodiments described above in the embodiments of the present application. For example, specific implementations of the computing device 600 performing various operations may refer to specific details in the above-described embodiments, such as the processor 610 being configured to perform some or all of the steps of the above-described method embodiments or some or all of the operations of the above-described method embodiments. For another example, in the embodiment of the present application, the computing device 600 may be used to implement some or all of the functions of one or more components in the apparatus embodiments described above, and the communication interface 620 may be used in particular for communication functions and the like necessary for implementing the functions of these apparatuses, components, and the processor 610 may be used in particular for processing functions and the like necessary for implementing the functions of these apparatuses, components.

It should be appreciated that the computing device 600 of fig. 6 may include one or more processors 610, and that the multiple processors 610 may cooperatively provide processing power in a parallelized connection, a serialized connection, a serial-parallel connection, or any connection, or the multiple processors 610 may constitute a processor sequence or processor array, or the multiple processors 610 may be separated into primary and secondary processors, or the multiple processors 610 may have different architectures such as employing heterogeneous computing architectures. In addition, the computing device 600 shown in FIG. 6, the associated structural and functional descriptions are exemplary and not limiting. In some example embodiments, computing device 600 may include more or fewer components than shown in fig. 6, or combine certain components, or split certain components, or have a different arrangement of components.

The processor 610 may be implemented in various manners, for example, the processor 610 may include one or more of a central processing unit (central processing unit, CPU), a graphics processor (graphic processing unit, GPU), a neural network processor (neural-network processing unit, NPU), a tensor processor (tensor processing unit, TPU), or a data processor (data processing unit, DPU), which are not limited in particular. Processor 610 may also be a single-core processor or a multi-core processor. The processor 610 may be formed by a combination of a CPU and a hardware chip. The hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (programmable logic device, PLD), or a combination thereof. The PLD may be a complex programmable logic device (complex programmable logic device, CPLD), a field-programmable gate array (field-programmable gate array, FPGA), general-purpose array logic (generic array logic, GAL), or any combination thereof. The processor 610 may also be implemented solely with logic devices incorporating processing logic, such as an FPGA or digital signal processor (digital signal processor, DSP) or the like. The communication interface 620 may be a wired interface, which may be an ethernet interface, a local area network (local interconnect network, LIN), etc., or a wireless interface, which may be a cellular network interface or use a wireless lan interface, etc., for communicating with other modules or devices.

The memory 630 may be a nonvolatile memory such as a read-only memory (ROM), a Programmable ROM (PROM), an Erasable PROM (EPROM), an electrically Erasable EPROM (EEPROM), or a flash memory. The memory 630 may also be volatile memory, which can be random access memory (random access memory, RAM) used as external cache. By way of example, and not limitation, many forms of RAM are available, such as Static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous DRAM (SLDRAM), and direct memory bus RAM (DR RAM). The memory 630 may also be used to store program code and data such that the processor 610 invokes the program code stored in the memory 630 to perform some or all of the operational steps of the method embodiments described above, or to perform corresponding functions of the apparatus embodiments described above. Moreover, computing device 600 may contain more or fewer components than shown in FIG. 6, or may have a different configuration of components.

Bus 640 may be a peripheral component interconnect express (peripheral component interconnect express, PCIe) bus, or an extended industry standard architecture (extended industry standard architecture, EISA) bus, a unified bus (Ubus or UB), a computer quick link (compute express link, CXL), a cache coherent interconnect protocol (cache coherent interconnect for accelerators, CCIX), or the like. Bus 640 may be divided into an address bus, a data bus, a control bus, and the like. Bus 640 may include a power bus, a control bus, a status signal bus, and the like in addition to a data bus. But is shown with only one bold line in fig. 6 for clarity of illustration, but does not represent only one bus or one type of bus.

The method and the device provided in the embodiments of the present application are based on the same inventive concept, and because the principles of solving the problems by the method and the device are similar, the embodiments, implementations, examples or implementation of the method and the device may refer to each other, and the repetition is not repeated. Embodiments of the present application also provide a system that includes a plurality of computing devices, each of which may be structured as described above. The functions or operations that may be implemented by the system may refer to specific implementation steps in the above method embodiments and/or specific functions described in the above apparatus embodiments, which are not described herein.

Embodiments of the present application also provide a computer-readable storage medium having stored therein computer instructions which, when executed on a computer device (e.g., one or more processors), may implement the method steps in the above-described method embodiments. The specific implementation of the processor of the computer readable storage medium in executing the above method steps may refer to specific operations described in the above method embodiments and/or specific functions described in the above apparatus embodiments, which are not described herein again.

It will be appreciated by those skilled in the art that embodiments of the present application may be provided as a method, system, or computer program product. The present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Embodiments of the present application may be implemented in whole or in part by software, hardware, firmware, or any other combination. When implemented in software, the above-described embodiments may be implemented in whole or in part in the form of a computer program product. The present application may take the form of a computer program product embodied on one or more computer-usable storage media having computer-usable program code embodied therein. The computer program product includes one or more computer instructions. When loaded or executed on a computer, produces a flow or function in accordance with embodiments of the present application, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a computer network, or other programmable apparatus. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by a wired (e.g., coaxial cable, fiber optic, digital subscriber line), or wireless (e.g., infrared, wireless, microwave, etc.). Computer readable storage media can be any available media that can be accessed by a computer or data storage devices, such as servers, data centers, etc. that contain one or more collections of available media. Usable media may be magnetic media (e.g., floppy disks, hard disks, tape), optical media, or semiconductor media. The semiconductor medium may be a solid state disk, or may be a random access memory, flash memory, read only memory, erasable programmable read only memory, electrically erasable programmable read only memory, register, or any other form of suitable storage medium.

The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. Each flow and/or block of the flowchart and/or block diagrams, and combinations of flows and/or blocks in the flowchart and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks. These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks. These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

In the foregoing embodiments, the descriptions of the embodiments are emphasized, and for parts of one embodiment that are not described in detail, reference may be made to the related descriptions of other embodiments. It will be apparent to those skilled in the art that various modifications and variations can be made to the embodiments of the present application without departing from the spirit and scope of the embodiments of the present application. The steps in the method of the embodiment of the application can be sequentially adjusted, combined or deleted according to actual needs; the modules in the system of the embodiment of the application can be divided, combined or deleted according to actual needs. Such modifications and variations of the embodiments of the present application are intended to be included herein, if they fall within the scope of the claims and their equivalents.

Claims

1. A data alignment method for parallel interface connection, the data alignment method comprising:

receiving a plurality of parallel port data signals and a data selection signal through a receiving end, wherein each of the plurality of parallel port data signals comprises a plurality of first signals, the first signals are in one-to-one correspondence with a plurality of first lines between the receiving end and a transmitting end, each of the first signals is transmitted through a first line corresponding to the first signal in the first lines, the data selection signal is transmitted through a second line between the receiving end and the transmitting end, the plurality of parallel port data signals are transmitted based on the triggering of the upper edge and the lower edge of a reference clock signal, and the data selection signal is a first differential signal pair generated based on the reference clock signal;

Generating, by the receiving end, a plurality of second differential signal pairs corresponding to the plurality of first lines one to one based on the data selection signal;

for each first signal of the plurality of first signals, sampling the first signal according to first three sampling clock edges of a second differential signal pair corresponding to a first line corresponding to the first signal of the plurality of second differential signal pairs to obtain first three sampling results respectively, then selecting a first beat sampling clock edge from the first three sampling clock edges based on the first three sampling results, adjusting the second differential signal pair based on the first beat sampling clock edge to obtain an adjusted second differential signal pair, sampling the first signal using the first beat sampling clock edge and the adjusted second differential signal pair to realize data alignment between the multi-beat parallel port data signal and the data selection signal,

the first three sampling clock edges in the second differential signal pair are a first sampling clock edge, a second sampling clock edge and a third sampling clock edge,

the first three sampling results include a first sampling result, a second sampling result, and a third sampling result, wherein the first sampling result is obtained by sampling the first signal based on the first sampling clock edge, the second sampling result is obtained by sampling the first signal based on the second sampling clock edge, the third sampling result is obtained by sampling the first signal based on the third sampling clock edge,

Selecting the first beat sampling clock edge from the first three sampling clock edges based on the first three sampling results, including:

when both the first sampling result and the second sampling result are empty and the third sampling result is not empty, the first beat sampling clock edge is the third sampling clock edge,

when the first sampling result is empty and the second sampling result is not empty, the first beat sampling clock edge is the second sampling clock edge,

when the first sampling result is not null, the first beat sampling clock edge is the first sampling clock edge.

2. The data alignment method of claim 1, wherein the multi-beat parallel port data signal is transmitted based on a trigger of upper and lower edges of the reference clock signal such that a same clock cycle of the reference clock signal includes two transmission cycles, the data selection signal being used to distinguish between the two transmission cycles included in the same clock cycle of the reference clock signal.

3. The data alignment method of claim 1, wherein the receiving side is a double data rate synchronous dynamic random access memory physical interface layer, the transmitting side is a double data rate synchronous dynamic random access memory device side, and the double data rate synchronous dynamic random access memory device side transmits the multi-beat parallel port data signal and the data selection signal in response to a read command.

4. The data alignment method of claim 3, wherein the double data rate synchronous dynamic random access memory device side comprises a plurality of double data rate synchronous dynamic random access memory devices, any double data rate synchronous dynamic random access memory device of the plurality of double data rate synchronous dynamic random access memory devices being configured to transmit the multi-beat parallel port data signal and the data selection signal and supporting a data bit width corresponding to a number of the plurality of first signals.

5. The data alignment method of claim 4, wherein the multi-beat parallel port data signals are each 8 bits, the first plurality of signals are each 1 bit, and the number of first plurality of signals is 8.

6. The data alignment method of claim 1, wherein the delay of the second line is greater than the delay of any of the plurality of first lines, the delay between any two of the plurality of first lines being no greater than a first threshold, the first threshold being determined based on a communication interface specification between the receiving end and the transmitting end.

7. The data alignment method of claim 1, wherein the second sampling clock edge follows the first sampling clock edge and the third sampling clock edge follows the second sampling clock edge, the first and third sampling clock edges being located at a same differential signal of the second differential signal pair, the second sampling clock edge being located at another differential signal of the second differential signal pair relative to the same differential signal.

8. The data alignment method of claim 7, wherein the first, second, and third sampling clock edges are each rising or falling clock edges.

9. The data alignment method of claim 7, wherein the first beat sampling clock edge is the third sampling clock edge, wherein adjusting the second differential signal pair based on the third sampling clock edge to obtain the adjusted second differential signal pair comprises: the first sampling clock edge is used for scanning the front edge of the second beat data of the first signal, then the third sampling clock edge is used for scanning the rear edge of the first beat data of the first signal so as to obtain a first scanning result, the center position of the first beat data of the first signal is calculated based on the first scanning result, and the second differential signal pair is adjusted so that the third sampling clock edge is aligned with the center position of the first beat data of the first signal.

10. The data alignment method of claim 7, wherein the first beat sampling clock edge is the second sampling clock edge, wherein adjusting the second differential signal pair based on the second sampling clock edge to obtain the adjusted second differential signal pair comprises: the second sampling clock edge is used for scanning the front edge of the first beat data of the first signal and then the third sampling clock edge is used for scanning the rear edge of the first beat data of the first signal so as to obtain a second scanning result, the center position of the first beat data of the first signal is calculated based on the second scanning result, and the second differential signal pair is adjusted so that the second sampling clock edge is aligned with the center position of the first beat data of the first signal.

11. The data alignment method of claim 7, wherein the first beat sampling clock edge is the first sampling clock edge, wherein adjusting the second differential signal pair based on the first sampling clock edge to obtain the adjusted second differential signal pair comprises: the first sampling clock edge is used for scanning the front edge of the first beat data of the first signal, then the second sampling clock edge is used for scanning the rear edge of the first beat data of the first signal so as to obtain a third scanning result, the center position of the first beat data of the first signal is calculated based on the third scanning result, and the second differential signal pair is adjusted so that the first sampling clock edge is aligned with the center position of the first beat data of the first signal.

12. The data alignment method of claim 1, wherein the plurality of second differential signal pairs are in one-to-one correspondence with a plurality of delay chains, wherein adjusting the second differential signal pairs based on the first beat sampling clock edge results in the adjusted second differential signal pairs, comprising: and based on the first beat sampling clock edge, delaying the second differential signal pair through a delay chain corresponding to the second differential signal pair in the plurality of delay chains to obtain the adjusted second differential signal pair, wherein the maximum delay range of the delay chain does not exceed half period of the first differential signal pair.

13. The data alignment method of claim 12, wherein adjusting the second differential signal pair based on the first beat sampling clock edge results in the adjusted second differential signal pair, further comprising: the first signal is selectively scanned using the first three sampling clock edges based on the first beat sampling clock edges and the scan range does not exceed the maximum delay range of the delay chain.

14. A computer device, characterized in that it comprises a memory, a processor and a computer program stored on the memory and executable on the processor, which processor implements the method according to any of claims 1 to 13 when executing the computer program.

15. A computer readable storage medium storing computer instructions which, when run on a computer device, cause the computer device to perform the method of any one of claims 1 to 13.