CN210518362U - Single-wire communication circuit and communication system - Google Patents
Single-wire communication circuit and communication system Download PDFInfo
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- CN210518362U CN210518362U CN201921875563.XU CN201921875563U CN210518362U CN 210518362 U CN210518362 U CN 210518362U CN 201921875563 U CN201921875563 U CN 201921875563U CN 210518362 U CN210518362 U CN 210518362U
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Abstract
The utility model discloses a single-wire communication circuit, including analytic clock generation unit and data analysis unit, analytic clock generation unit output single-wire communication signal analysis clock to data analysis unit, analytic clock generation unit includes first time delay module for receive outside electric wire communication signal, based on the single-wire communication signal output first time delay signal of input; the control signal generation module is used for generating a new pulse signal as an oscillation source control signal based on the received single-wire communication signal and the first delay signal; and the clock generation module is used for receiving the oscillation source control signal and outputting a control signal as a single-wire communication signal analysis clock based on the oscillation source control signal. The single-wire communication circuit can simplify the circuit structure and reduce the cost on the basis of ensuring the communication speed and the quality. A single-wire communication system is also disclosed.
Description
Technical Field
The invention belongs to the field of communication, and particularly relates to a single-wire communication circuit and a communication system.
Background
With the continuous development of technology, communication becomes an indispensable function between different devices or modules. The main communication means currently existing are wired communication and wireless communication. In fact, the wireless communication physical layer can evolve into single-wire communication, and finally, signals can also be converted into wired communication through the wireless transmitting and receiving module. The traditional wired communication modes mainly include serial communication and parallel communication. The serial communication has two communication modes of serial asynchronous communication and serial synchronous communication, wherein a transmitting end and a receiving end of the serial asynchronous communication need to be connected with a transmission line and a ground wire.
Single-wire communication is one type of serial asynchronous communication, the protocol of which is defined between a master device and a slave device, both sharing a single-wire connection to transfer data to each other in a simultaneous bidirectional manner (full duplex). In most cases, in the direction of data transmission from a transmitting data device (master or slave) to a receiving data device (slave or master), the transmitting data device modulates the duty cycle of a periodic signal in accordance with the signal to be transmitted (logic level 0 or logic level 1), and the receiving data device recovers the data transmitted by the transmitting device by measuring the duty cycle.
Taking fig. 1 as an example, in order to satisfy the stability of signal measurement, a clock signal with a frequency at least 8 times higher than that of a single-wire signal and 2 registers are required inside a circuit of a data receiving device, wherein the clock signal is used for synchronizing the single-wire signal and ensuring timing stability, and the 2 registers are used for measuring a duty cycle of the signal.
Single wire protocol communications are typically used in circuits that have requirements for circuit area and power consumption, and designers often desire to be able to achieve higher communication rates with less area and circuit power consumption. The single-wire signal analysis circuit is used as a part of a single-wire protocol system, and increasing the analysis rate of the signal generally means increasing the area of the analysis circuit and increasing the power consumption. Therefore, a new circuit structure is required to solve this problem.
The invention patent application with application publication number CN108494433A discloses a single-wire communication method and a circuit implementation thereof, and particularly the single-wire communication circuit comprises a signal processing circuit, the signal processing circuit is used for receiving and processing an external pulse signal CLK1, outputting corresponding DATA bits DATA, and generating a DATA bit-by-DATA bit synchronizing signal CLK2 as a synchronizing trigger signal of a subsequent circuit, wherein each DATA bit DATA determination requires a CLK1 signal with at least 1 pulse number, each synchronizing signal CLK2 is generated by the first pulse in a pulse signal CLK1, and the time from input of the pulse signal CLK1 to generation of the synchronizing signal CLK2 is greater than the total time from occurrence of the pulse in the input of the pulse signal CLK1 to the end of the pulse; the synchronization signal CLK2 should occur before the second set of pulse signals. The single-line communication single-path occupied area and the circuit power consumption can only meet the requirements of some communication devices.
SUMMERY OF THE UTILITY MODEL
The utility model aims at providing a single line communication circuit, this single line communication circuit can be on the basis of guaranteeing communication rate and quality, has simplified circuit structure, reduce cost.
A second object of the utility model is to provide a single line communication system, it includes single line communication circuit utilizes single line communication single pass carries out the data analysis among the single line communication signal, and this single line communication system has guaranteed communication rate and quality on the basis of simplifying circuit result and reduce cost.
In order to achieve the above-mentioned main objective, the utility model provides a pair of single-wire communication circuit, including analytic clock generation unit and data analysis unit, analytic clock generation unit output single-wire communication signal analysis clock extremely data analysis unit, data analysis unit is according to transmission data and output are analyzed out from the single-wire communication signal of input to single-wire communication signal analysis clock, analytic clock generation unit includes first time delay module, control signal generation module and clock generation module;
the first time delay module is used for receiving an external wire communication signal and outputting a first time delay signal based on an input single-wire communication signal;
the control signal generation module is used for generating a new pulse signal as an oscillation source control signal based on the received single-wire communication signal and the first delay signal;
the clock generation module is used for receiving the oscillation source control signal and outputting a signal serving as a single-wire communication signal analysis clock based on the oscillation source control signal.
Preferably, the single-wire communication circuit further includes a filtering processing unit, where the filtering processing unit is configured to receive an external single-wire communication signal, and output a filtered single-wire communication signal to the data analysis unit or the analysis clock generation unit based on the received single-wire communication signal.
Another preferred scheme is that the filtering processing unit comprises a second delay module and a second logic operation module;
the second time delay module is used for receiving an external single-wire communication signal and outputting a second time delay signal based on the single-wire communication signal;
the second logic operation module outputs the filtered single-wire communication signal to the data analysis unit or the analysis clock generation unit based on the received single-wire communication signal and the second delay signal.
Preferably, the clock generation module comprises an analog oscillation source with a control port, and the analog oscillation source generates an oscillation pulse signal.
The preferred solution is that the clock generation module comprises a digital frequency division circuit with a control port.
The data analysis unit preferably includes a data register, and the data register has inputs of the single-wire communication signal analysis clock and the single-wire communication signal and outputs of the data register as registered transmission data.
The specific scheme is that the first delay module comprises a first delay circuit formed by connecting an even number of inverters in series.
The specific scheme is that the second delay module comprises a second delay circuit formed by connecting an even number of inverters in series.
In order to realize the above-mentioned second purpose, the utility model provides a single line communication system, including data sending terminal and data receiving terminal, the data sending terminal sends single line communication signal, the data receiving terminal includes foretell single line communication circuit, single line communication circuit is used for receiving single line communication signal, and based on single line communication signal output is followed the transmission data who analyzes out among the single line signal.
Drawings
Fig. 1 is a schematic structural diagram of a common data parsing circuit in a data receiving apparatus;
FIG. 2 is a schematic diagram of the structure of embodiment 1 of the single-wire communication circuit of the present invention;
FIG. 3 is a schematic diagram of a single-wire embodiment 2 of the present invention;
FIG. 4 is a schematic diagram of the single-wire embodiment 3 of the present invention;
FIG. 5 is a waveform schematic diagram of embodiment 3 of the single-wire communication circuit of the present invention;
FIG. 6 is a schematic block diagram of a single-wire communication system embodiment of the present invention;
FIG. 7 is a schematic diagram of an embodiment of a digital divide-by-two circuit according to the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more clearly understood, the following detailed description of the present embodiment is made with reference to the accompanying drawings and the embodiments. It should be understood that the detailed description and specific examples, while indicating the scope of the invention, are intended for purposes of illustration only and are not intended to limit the scope of the invention.
Single wire communication circuit embodiments
As shown in fig. 2, the single-wire communication circuit according to the embodiment includes an analysis clock generation unit 201 and a data analysis unit 202, where the analysis clock generation unit 201 controls the analog oscillation pulse signal according to an external single-wire communication signal to generate a single-wire communication signal analysis clock, and outputs the single-wire communication signal analysis clock to the data analysis unit 202, and the data analysis unit 202 analyzes transmission data from the input single-wire communication signal according to the single-wire communication signal analysis clock and outputs the transmission data.
In the embodiment, the level of transmitting the 1 st bit effective data in the external single-wire communication signal is opposite to the phase of the level of the idle state of the single-wire communication signal.
Specifically, the resolution clock generation unit 201 includes a first delay module 2011, a control signal generation module 2012 and a clock generation module 2013. The first delay module 2011 is configured to receive an external wire communication signal, output a first delay signal based on an input single-wire communication signal, perform first delay on the input single-wire communication signal, and output the first delay signal; the control signal generating module 2012 is configured to generate a new pulse signal as an oscillation source control signal based on the received single-wire communication signal and the first delay signal, that is, perform a first logic operation on the input single-wire communication signal and the first delay signal, and generate the new pulse signal as the oscillation source control signal; the clock generation module 2013 is configured to receive an oscillation source control signal, and output a signal based on the oscillation source control signal as a single-wire communication signal analysis clock, that is, under the control of the oscillation source control signal, the output signal is used as the single-wire communication signal analysis clock. The single-wire communication signal analysis clock may be used as a synchronous clock of the data analysis unit and/or a synchronous clock of other subsequent circuits.
The first delay module 2011 is mainly configured to delay an external single-line pulse signal to generate a delay signal, so that the first delay module 2011 may employ a first delay circuit formed by connecting an even number of inverters in series, for example, the first delay module 2011 may be a first delay circuit formed by 4 CMOS inverters, and a delay time of the delay circuit is determined by a delay of each inverter and a signal line transmission delay. The time delay circuit occupies small circuit area, and has low power consumption and low cost.
The control signal generating module 2012 generates a pulse signal according to the input first delay signal and the externally input single-wire communication signal, and in order to save computation consumption, the control signal generating module 2012 computes the first delay signal and the single-wire communication signal by a single logic operation to generate a reset or set level pulse to generate the oscillation source control signal. In the embodiment, the reset or set generation process is that the external single-wire signal generates a falling edge, and after the logic of the first delay module and the control signal generation module, a reset or set level pulse is generated and is given to the oscillation source for a high level or a low level lasting for t3 time, so that the oscillation source is in a reset or set state.
The clock generation module 2013 mainly uses the control action of the oscillation source control signal to generate a new signal to be a single-wire communication signal analysis clock. The oscillation source control signal can play a reset role or a set role, a reset or set action is triggered by a high level or a low level, when the oscillation source control signal plays the reset role, the low level is controlled and output, and when the oscillation source control signal plays the set role, the high level is controlled and output so as to control the state of the generated single-wire communication signal analysis clock.
The clock generation module 2013 may include an analog oscillator source with a control port. The analog oscillation source can generate an analog oscillation pulse signal spontaneously, and the analog oscillation source is also provided with a control port, so that the analog oscillation pulse signal generated by the analog oscillation source is reset or set again in each data transmission period under the control action of the oscillation source control signal output by the control signal generation module 2012, and a formed signal is output as a single-wire communication signal analysis clock. The type of the analog oscillation source is not limited as long as the analog oscillation source can spontaneously generate the analog oscillation pulse signal and has a control port. For example, the analog oscillator source may be an OSC IP.
The clock generation module 2013 may also include a digital divider circuit having a control port. Because the digital frequency dividing circuit also has a control port, the original clock input at the input end of the digital frequency dividing circuit is reset or set again in each data transmission period under the control action of the oscillation source control signal output by the control signal generation module 2012, and a signal is formed and output as the single-wire communication signal analysis clock. The specific circuit structure of the digital frequency divider circuit is not limited as long as it has a control port. For example, in the digital divide-by-two circuit shown in fig. 7, CLKIn is the input original clock, Reset is the asynchronous low level Reset signal, i.e. the oscillation source control signal output by the control signal generation module 2012, and CLKOut is the divide-by-two clock of CLKIn, i.e. the single-wire communication signal analysis clock. When Reset is a Reset level state (low level), the CLKOut output level is a Reset level; with Reset in the non-Reset state (high), the output level of CLKOut transitions with the rising edge of CLKIn.
The control port of the analog oscillation source and the digital frequency division circuit is a communication port capable of receiving an oscillation source control signal, and the reset or setting of the oscillation pulse signal is realized according to the high level or the low level of the oscillation source control signal.
The single-wire communication circuit skillfully obtains an oscillation source control signal from an external single-wire communication signal through a delay module and a logic operation module, and then the oscillation source control signal is used for controlling an analog oscillation pulse signal to generate a single-wire communication signal analysis clock, so that the external single-wire communication signal and a local analysis clock are skillfully connected, the data analysis unit 202 can omit a counter when carrying out transmission data registration based on the single-wire communication signal analysis clock, and transmission data 0 or 1 can be acquired from the single-wire communication signal through an effective edge in the single-wire communication signal analysis clock which is periodically reset. On the basis of ensuring the communication speed and quality, the circuit structure is simplified, and the cost is reduced.
When the single-wire communication signal has noise, in order to avoid the noise from affecting the accuracy of data analysis, as shown in fig. 3, a filtering processing unit 301 is further added in the single-wire communication circuit, the filtering processing unit 301 is configured to receive an external single-wire communication signal, output a filtered single-wire communication signal to the data analysis unit based on the received single-wire communication signal, and remove the noise that may affect the result of data registration by filtering the single-wire communication signal, so as to improve the accuracy of data analysis.
Specifically, the filter processing unit 301 includes a second delay module 3011 and a second logical operation module 3012; the second delay module 3011 is configured to receive an external single-wire communication signal, output a second delay signal based on the single-wire communication signal, that is, perform a second delay on the single-wire communication signal, and output the second delay signal; the second logic operation module 3012 is configured to output the filtered single-wire communication signal to the data analysis unit 202 or the analysis clock generation unit 201 through the received single-wire communication signal and the second delay signal, that is, perform a second logic operation on the single-wire communication signal and the second delay signal to implement filtering on the single-wire communication signal, and input the filtered single-wire communication signal to the data analysis unit 202 or the analysis clock generation unit 201.
In general, the delay times of the first delay module 2011 and the second delay module 3011 are not equal. The structure of the second delay module 3011 may be the same as that of the first delay module 2011, in order to reduce the circuit area and power consumption of the second delay module and reduce the cost, the second delay module 3011 may be selected as a second delay circuit formed by connecting an even number of inverters in series, the delay time of the delay circuit is determined by the delay of each inverter and the signal line transmission delay, the number of inverters in the second delay circuit is greater than that of the inverters in the first delay circuit, for example, the second delay module 3011 may be a second delay circuit composed of 6 CMOS inverters.
In order to simplify the circuit structure and reduce the cost, the noise in the single-wire communication signal is filtered out by performing a logic operation on the second delayed signal and the single-wire communication signal, wherein the second logic operation is performed to filter out the noise in the single-wire communication signal, and the first logic operation is performed to generate a new pulse signal as a control signal of the oscillation source, so that the first logic operation is different from the second logic operation.
As shown in fig. 3, when the filtered single-wire communication signal is input to the data analyzing unit 202, the single-wire communication signal analyzing clock signal is from the original single-wire communication signal, that is, the input data of the analyzing clock generating unit is the original single-wire communication signal, the generation of the single-wire communication signal analyzing clock is controlled according to the original single-wire communication signal, and the unit data analyzing unit 202 analyzes the transmission data from the filtered single-wire communication signal according to the single-wire communication signal analyzing clock.
As shown in fig. 4, when the filtered single-wire communication signal is input to the analysis clock generation module 201, that is, the input single-wire communication signal is filtered to remove noise to obtain the filtered single-wire communication signal, at this time, the analysis clock generation module 201 generates a single-wire communication signal analysis clock according to the input filtered single-wire communication signal, and the data analysis unit 202 analyzes transmission data from the filtered single-wire communication signal according to a single-wire transmission signal analysis clock generated based on the filtered single-wire communication signal.
As shown in fig. 4, the data parsing unit 202 further includes a data register 2021. The data register 2021 receives the single-wire communication signal analysis clock and the single-wire communication signal, registers transmission data from the single-wire communication signal according to an effective edge of the single-wire communication signal analysis clock in each period, and outputs the registered transmission data in parallel from the data register 2021 after a data transmission is completed.
The embodiment also provides a single-wire communication format matched with the single-wire communication circuit, namely, in a single-wire communication signal, high and low levels or low and high levels with the time t1 and t2 form a transmission period of 1bit data; in the single-wire communication signal analysis clock, high and low levels or low and high levels with the time of t5 and t6 form a clock period; time t3 is a first delay time; the times t1, t2, t3, t5, and t6 satisfy (t1+ t2) < (t3+2 × t5+ t6) at the same time.
When the single-wire communication circuit limits the single-wire communication signal period to be t1+ t2 and the clock period of the single-wire communication signal analysis clock to be t5+ t6, and when the first delay time is t3, in order to ensure the accuracy of registering transmission data, the single-wire communication signal period and the clock period are limited to meet (t1+ t2) < (t3+2 × t5+ t6), so that when data are transmitted, 1-bit data only correspond to an internal effective period, namely only one effective clock edge exists in the transmission period of the 1-bit data, the logic design can be simplified, and the accuracy of transmission data acquisition can be ensured.
Fig. 5 shows a waveform schematic diagram of the single-wire communication circuit shown in fig. 3. The default level of the external single-wire communication signal is high level, t1+ t2 is the transmission period of the external single-wire communication signal, the first delay time is t3, the second delay time is t4, t4 > t3, t5+ t6 is the clock period of the single-wire communication signal analysis clock, and (t1+ t2) < (t3+2 × t5+ t 6).
The single-wire communication signal and the first delay signal are subjected to exclusive nor operation to obtain an oscillation source control signal, a rising edge in each period of the oscillation source control signal is a reset edge, the analog oscillation pulse starts to reset at a time corresponding to the reset edge, a new pulse period starts, and the single-wire communication signal analysis clock shown in fig. 5 is formed.
The second delay signal and the single-wire communication signal are subjected to a combinational logic operation to implement filtering of the single-wire communication signal, forming a filtered single-wire communication signal as shown in fig. 5.
When the single-wire communication signal parsed by the data parsing unit 202 is the original single-wire communication signal, t1> (t3+ t5) and t2< (t3+ t5) are defined. t1> (t3+ t5) ensures that the time corresponding to the effective edge (corresponding to the rising edge in fig. 5) in each clock cycle in the single-wire communication signal analysis clock is within the duration of the low level of the data 0, that is, the effective edge in each clock cycle is ensured to adopt the low level of the single-wire communication signal, so that the analysis and the registration of the data 0 contained in the single-wire communication signal are realized. t2< (t3+ t5) ensures that the time corresponding to the effective edge (corresponding to the rising edge in fig. 5) in each clock cycle in the single-wire communication signal analysis clock is within the duration of the high level of the data 1, that is, the effective edge in each clock cycle can adopt the high level of the single-wire communication signal, thus realizing the analysis and registration of the data 1 contained in the single-wire communication signal.
When the single-wire communication signal analyzed by the data analysis unit 202 is a filtered single-wire communication signal, t1> (t3+ t5), t4< (t3+ t5), and t2< (t3+ t5) are defined. t1> (t3+ t5) and t4< (t3+ t5) can ensure that the active edge in each clock cycle can take the low level of the single-wire communication signal, thus realizing the analytic registration of the data 0 contained in the single-wire communication signal. t2< (t3+ t5) ensures that the active edge in each clock cycle can assume the high level of the single-wire communication signal, thus achieving the resolved registration of data 1 contained in the single-wire communication signal.
As can be seen from the analysis of fig. 5, before point a, the external single-wire communication signal line is idle; at the moment of point a, the single-wire communication signal wire starts to bear effective data, and at the moment, the internal analog oscillation source resets, and a clock level default value of 0 is output.
And at the moment b, releasing the reset terminal of the analog oscillation source, starting the normal work of the analog oscillation source, and waiting for the time t 5.
At time c, the single-wire communication signal analysis clock generates the first rising edge, the data register registers the filtered single-wire communication signal (at this time, 0) at the time of the clock rising edge, and the output DATAOUT becomes 0.
At the time point d, the 1 st bit data transmission is completed, and the transmission of the 2 nd bit data is started.
Time e is like time c, and time f is like time d.
At time g, the 3 rd bit data transmission is completed, and no data is being transmitted, the single-wire communication signal is always maintained at the default level.
The single-wire communication method further includes an analysis clock generation step of generating an analysis clock of the single-wire communication signal according to an external single-wire communication signal, and a data analysis step of analyzing the transmission data from the input single-wire communication signal according to the single-wire communication signal analysis clock generated by the analysis clock generation step and outputting the transmission data. Specifically, as shown in fig. 6, the single-wire communication method includes the steps of:
s601, carrying out first time delay processing on an input single-wire communication signal to generate a first time delay signal;
s602, performing a first logic operation on the input single-wire communication signal and the first delay signal to generate a new pulse signal as an oscillation source control signal;
s603, controlling the analog oscillation pulse signal by using the oscillation source control signal, and using the generated signal as a single-wire communication signal analysis clock;
and S604, analyzing the transmission data from the input single-wire communication signal according to the single-wire communication signal analysis clock and outputting the transmission data.
The single-wire communication method is based on an external single-wire communication signal, an internal single-wire communication signal analysis clock is generated through simple logic operation, the single-wire communication signal analysis clock is used for analyzing transmission data carried in the single-wire communication signal, and the accuracy of analyzing the transmission data is improved.
In order to avoid that noise affects the accuracy of the analyzed data, in addition, the single-wire communication method provided in the embodiment includes a filtering processing step of filtering the input single-wire communication signal in addition to the analysis clock generating step and the data analyzing step, and the filtered single-wire communication signal is provided to the data analyzing step for data analysis. Specifically, as shown in fig. 7, the single-wire communication method includes the steps of:
s701, carrying out first time delay processing on an input single-wire communication signal to generate a first time delay signal;
s702, carrying out first logic operation on the input single-wire communication signal and the first delay signal to generate a new pulse signal as an oscillation source control signal;
s703, controlling the analog oscillation pulse signal by using the oscillation source control signal, and using the generated signal as a single-wire communication signal analysis clock;
s704, filtering the input single-wire communication signal to obtain a filtered single-wire communication signal;
s705, parsing the transmission data from the input single-wire communication signal according to the single-wire communication signal parsing clock, and outputting the transmission data.
The single-wire communication method is based on an external single-wire communication signal, an internal single-wire communication signal analysis clock is generated through simple logic operation, the single-wire communication signal analysis clock is used for analyzing transmission data carried in the single-wire communication signal, accuracy of analyzing the transmission data is improved, in addition, interference of noise signals is filtered before the single-wire communication signal is analyzed, and accuracy of explaining the transmission data is further improved.
In another embodiment, the noise in the original single-wire communication signal is filtered by a logic operation of the delayed signal and the original single-wire communication signal, and specifically, the single-wire communication method includes the following steps:
s801, carrying out first time delay processing on an input single-wire communication signal to generate a first time delay signal;
s802, carrying out first logic operation on the input single-wire communication signal and the first delay signal to generate a new pulse signal as an oscillation source control signal;
s803, controlling the analog oscillation pulse signal by using the oscillation source control signal, and using the generated signal as a single-wire communication signal analysis clock;
s804, carrying out second time delay processing on the input single-wire communication signal to generate a second time delay signal;
s805, performing a second logic operation different from the first logic operation on the input single-wire communication signal and the second delay signal to filter the single-wire communication signal, and obtaining a filtered single-wire communication signal;
and S806, analyzing the transmission data from the input single-wire communication signal according to the single-wire communication signal analysis clock and outputting the transmission data.
The single-wire communication method improves the accuracy of analyzing the transmission data, reduces the calculation overhead and saves the cost.
In the above single-wire communication method, the first logic operation is to generate a new pulse signal as a reset signal of the oscillation source, and the second logic operation is to filter out noise in the single-wire communication signal, so that the first logic operation is different from the second logic operation.
In the single-wire communication method, the analog oscillation pulse signal may be generated by an analog oscillation source having a control port. Or the analog oscillating pulse signal can be generated by a digital frequency dividing circuit with a control port.
Because the analog oscillation source or the digital frequency division circuit is provided with the control port, the analog oscillation pulse signal generated by the analog oscillation source or the input analog oscillation pulse signal is reset or set again in each period under the control action of the oscillation source control signal, and the formed signal is used as a single-wire communication signal analysis clock and is output. The kind of analog oscillation source and the specific circuit structure of the digital frequency dividing circuit are not limited as long as the control port is provided.
The single-wire communication method also limits the high-low level or the low-high level with the time t1 and t2 in the single-wire communication signal to form a transmission period of 1bit data; in the single-wire communication signal analysis clock, a clock period is formed by high and low levels or low and high levels with the time of t5 and t 6; time t3 is a first delay time; the times t1, t2, t3, t5, and t6 satisfy (t1+ t2) < (t3+2 × t5+ t6) at the same time. Therefore, when data are ensured to be sent, the 1-bit data only correspond to one internal effective period, namely, only one effective clock edge exists in the transmission period of the 1-bit data, so that the logic design can be simplified, and the accuracy of transmission data acquisition can be ensured.
Single wire communication system embodiments
As shown in fig. 6, the single-wire communication system 900 provided in the embodiment includes a data transmitting end 901 and a data receiving end 902, where the data transmitting end 901 transmits a single-wire communication signal carrying transmission data, and the data receiving end includes a single-wire communication circuit 9021, and the single-wire communication circuit 9021 is configured to receive the single-wire communication signal and output the transmission data parsed from the single-wire signal based on the single-wire communication signal. That is, after the single-wire communication signal is transmitted to the data receiving terminal 902, the data receiving terminal 902 analyzes the transmission data from the single-wire communication signal by the single-wire communication circuit 9021 and outputs the transmission data.
The single-wire communication circuit 9021 has the same structure as the single-wire communication circuits shown in fig. 2 to 5, and the process of analyzing transmission data from the single-wire communication signal is the same, which is not described herein again.
The single-wire communication system utilizes the single-wire communication single path to analyze data in the single-wire communication signal, and ensures the communication speed and quality on the basis of simplifying a circuit result and reducing cost.
The above-mentioned embodiments are intended to illustrate the technical solutions and advantages of the present invention in detail, and it should be understood that the above-mentioned embodiments are only the most preferred embodiments of the present invention, and are not intended to limit the present invention, and any modifications, additions, and equivalents made within the scope of the principles of the present invention should be included in the scope of the present invention.
Claims (9)
1. A single-wire communication circuit comprises an analysis clock generating unit and a data analysis unit, wherein the analysis clock generating unit outputs a single-wire communication signal analysis clock to the data analysis unit, and the data analysis unit analyzes transmission data from an input single-wire communication signal according to the single-wire communication signal analysis clock and outputs the transmission data;
the first time delay module is used for receiving an external wire communication signal and outputting a first time delay signal based on an input single-wire communication signal;
the control signal generation module is used for generating a new pulse signal as an oscillation source control signal based on the received single-wire communication signal and the first delay signal;
the clock generation module is used for receiving the oscillation source control signal and outputting a signal serving as a single-wire communication signal analysis clock based on the oscillation source control signal.
2. The single-wire communication circuit according to claim 1, further comprising a filter processing unit configured to receive an external single-wire communication signal, and output a filtered single-wire communication signal to the data resolution unit or the resolution clock generation unit based on the received single-wire communication signal.
3. The single-wire communication circuit as claimed in claim 2, wherein said filtering processing unit includes a second delay block and a second logical operation block;
the second time delay module is used for receiving an external single-wire communication signal and outputting a second time delay signal based on the single-wire communication signal;
the second logic operation module outputs the filtered single-wire communication signal to the data analysis unit or the analysis clock generation unit based on the received single-wire communication signal and the second delay signal.
4. The single-wire communication circuit as claimed in claim 2, wherein the clock generation module includes an analog oscillation source having a control port, the analog oscillation source generating an oscillation pulse signal.
5. The single-wire communication circuit of claim 2, wherein the clock generation module includes a digital frequency divider circuit having a control port.
6. A single-wire communication circuit according to any one of claims 1 to 5, wherein the data resolution unit includes a data register, inputs of which are the single-wire communication signal resolution clock and the single-wire communication signal, and an output of which is registered transmission data.
7. A single-wire communication circuit as claimed in any one of claims 1 to 5, wherein the first delay module comprises a first delay circuit formed by an even number of inverters connected in series.
8. The single-wire communication circuit of claim 3, wherein the second delay block includes a second delay circuit formed of an even number of inverters connected in series.
9. A single-wire communication system comprises a data transmitting end and a data receiving end, wherein the data transmitting end transmits a single-wire communication signal, and the single-wire communication system is characterized in that the data receiving end comprises the single-wire communication circuit according to any one of claims 1 to 8, and the single-wire communication circuit is used for receiving the single-wire communication signal and outputting transmission data analyzed from the single-wire communication signal based on the single-wire communication signal.
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