CN115459774A - Method for improving sampling rate of analog-digital converter - Google Patents
Method for improving sampling rate of analog-digital converter Download PDFInfo
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- CN115459774A CN115459774A CN202211156634.7A CN202211156634A CN115459774A CN 115459774 A CN115459774 A CN 115459774A CN 202211156634 A CN202211156634 A CN 202211156634A CN 115459774 A CN115459774 A CN 115459774A
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- H—ELECTRICITY
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- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/1205—Multiplexed conversion systems
- H03M1/121—Interleaved, i.e. using multiple converters or converter parts for one channel
- H03M1/1215—Interleaved, i.e. using multiple converters or converter parts for one channel using time-division multiplexing
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- H—ELECTRICITY
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- H03H17/02—Frequency selective networks
- H03H17/06—Non-recursive filters
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
- H03M1/1245—Details of sampling arrangements or methods
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- H—ELECTRICITY
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- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
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Abstract
The invention relates to the technical field of electronic circuits, in particular to a method for improving the sampling rate of an analog-digital converter, which converts an analog input signal into an oscillation frequency signal through a voltage-controlled oscillation circuit; the multi-phase clock sampling circuit preprocesses the oscillation frequency signal to obtain sampling data; the multi-channel signal error correction and reconstruction circuit corrects and reconstructs the sampled data in real time to obtain reconstructed data; the method saves the number, area and power consumption of digital-to-analog converters, the sampling circuits are all arranged in one digital-to-analog converter, the physical layout is close to each other, the parameter offset of each analog-to-digital converter is reduced, the analog-to-digital conversion precision is improved, the total equivalent sampling frequency is improved by improving the number of the sampling circuits and adopting the corresponding digital filtering and signal combination circuits, and therefore the total oversampling multiple and the analog-to-digital conversion precision are improved.
Description
Technical Field
The invention relates to the technical field of electronic circuits, in particular to a method for improving the sampling rate of an analog-digital converter.
Background
An analog-to-digital converter, as an important signal processing electronic device, is used to convert a continuously changing analog signal into a discrete digital signal, and a conventional analog-to-digital converter compares an analog input voltage with a reference voltage in a voltage comparison manner, thereby implementing digital quantization, so that the performance of the conventional analog-to-digital converter is limited by the precision of the comparator.
In recent years, a multichannel time-interleaved analog-to-digital converter is proposed to improve the sampling rate of the analog-to-digital converter, a plurality of analog-to-digital converters are connected in parallel, and the alternating clock and time division multiplexing modes are used for working in turn, so that the sampling signals of the low-speed analog-to-digital converters on each channel are combined into the sampling signals of the high-speed analog-to-digital converter, theoretically, when the analog-to-digital converter parameters of each channel are completely consistent, the equivalent sampling rate of the multichannel time-interleaved analog-to-digital converter structure is in direct proportion to the number of the channels of the parallel analog-to-digital converter.
In practice, however, the analog-to-digital converters of different channels are difficult to be truly and completely consistent in circuit implementation, which may cause spurs in the output spectrum, and seriously affect the dynamic characteristic index of the multi-channel time-interleaved analog-to-digital converter, thereby affecting the sampling rate of the converter.
Disclosure of Invention
The invention aims to provide a method for improving the sampling rate of an analog-to-digital converter, and aims to solve the problem that the sampling rate of the converter is influenced because the existing multichannel time-interleaved analog-to-digital converter is difficult to be truly and completely consistent.
In order to achieve the above object, the present invention provides a method for increasing the sampling rate of an analog-to-digital converter, comprising the following steps:
converting the analog input signal into an oscillation frequency signal through a voltage-controlled oscillation circuit;
the multiphase clock sampling circuit preprocesses the oscillation frequency signal to obtain sampling data;
the multi-channel signal error correction and reconstruction circuit corrects and reconstructs the sampled data in real time to obtain reconstructed data;
and combining the reconstructed data by a digital filtering and signal combining circuit to obtain an equivalent sampling signal.
The specific way of converting the analog input signal into the oscillation frequency signal by the voltage-controlled oscillation circuit is as follows:
an external analog input signal is input into the voltage-controlled oscillating circuit;
the voltage-controlled oscillation circuit is used for performing analog-to-digital conversion on the external analog input signal into an oscillation frequency signal.
The multiphase clock sampling circuit preprocesses the oscillation frequency signal to obtain a specific mode of sampling data:
the multi-phase clock sampling circuit collects the oscillation frequency signals to obtain multi-channel data;
and carrying out filtering processing on the multi-channel data to obtain sampling data.
The digital filtering and signal combining circuit carries out filtering pretreatment on the reconstructed data to obtain processed data;
and combining the processing data to generate an output signal to obtain an equivalent sampling signal.
Wherein the filtering pretreatment is multiphase FIR downsampling filtering operation.
The invention relates to a method for improving the sampling rate of an analog-digital converter, which converts an analog input signal into an oscillation frequency signal through a voltage-controlled oscillation circuit; the multiphase clock sampling circuit preprocesses the oscillation frequency signal to obtain sampling data; the multi-channel signal error correction and reconstruction circuit corrects errors and reconstructs the sampled data in real time to obtain reconstructed data; the digital filtering and signal combination circuit combines the reconstructed data to obtain equivalent sampling signals, the method saves the number, the area and the power consumption of the digital-to-analog converters, and the sampling circuits are all arranged in one digital-to-analog converter, and the physical layouts of the sampling circuits are close to each other, so that the parameter offset of each analog-to-digital converter can be greatly reduced, and the analog-to-digital conversion precision is improved. By increasing the number of sampling paths and adopting the corresponding digital filtering and signal combination circuit, the total equivalent sampling frequency is increased on the premise of not increasing the frequency of a single-path sampling clock, so that the total oversampling multiple is increased, the analog-to-digital conversion precision is improved, and the problems that the sampling rate of the converter is influenced because the existing multi-channel time-interleaved analog-to-digital converter is difficult to achieve real complete consistency are solved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic block diagram of an M-channel high-speed analog-to-digital converter based on a VCO quantizer according to an embodiment of the present invention.
Fig. 2 is a clock timing diagram generated by the M-phase clock generator according to the embodiment of the present invention.
Fig. 3 is a flowchart of the operation of the analog-to-digital converter provided in the embodiment of the present invention.
Fig. 4 is a schematic diagram of VCO quantizer noise shaping for the analog-to-digital converter provided in the embodiment of the present invention.
Fig. 5 is a schematic diagram of the dynamic performance index of the analog-to-digital converter provided in the embodiment of the present invention (M =1, without decimation filter).
Fig. 6 is a schematic diagram of the dynamic performance index of the analog-to-digital converter provided in the embodiment of the present invention (M =1, with a decimation filter).
Fig. 7 is a schematic diagram of the dynamic performance index of the analog-to-digital converter provided in the embodiment of the present invention (M =4, without decimation filter).
Fig. 8 is a schematic diagram of the dynamic performance index of the analog-to-digital converter provided in the embodiment of the present invention (M =4, with a decimation filter).
Fig. 9 is a schematic diagram of the dynamic performance index of the analog-to-digital converter provided in the embodiment of the present invention (M =16, without decimation filter).
Fig. 10 is a schematic diagram of the dynamic performance index of the analog-to-digital converter provided in the embodiment of the present invention (M =16, with a decimation filter).
Fig. 11 is a flowchart of a method for increasing the sampling rate of an analog-to-digital converter according to the present invention.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the accompanying drawings are illustrative and intended to explain the present invention and should not be construed as limiting the present invention.
Referring to fig. 1 to 11, the present invention provides a method for increasing a sampling rate of an analog-to-digital converter, comprising the following steps:
s1, converting an analog input signal into an oscillation frequency signal through a voltage-controlled oscillation circuit;
specifically, the error caused by quantization can be reduced, the sampling circuit can perform accurate sampling conveniently, the noise shaping function is provided, the signal to noise ratio is improved, the VCO oscillation center frequency can be dynamically configured and adjusted, the analog input signal voltage range matching is facilitated, the signal linearity is improved, and the power consumption matching of the digital-to-analog converter and an application scene is controlled.
The specific mode is as follows:
s11, inputting an external analog input signal into the voltage-controlled oscillation circuit;
and S12, converting the external analog input signal into an oscillation frequency signal by the voltage-controlled oscillation circuit.
Specifically, a voltage-controlled oscillator (VCO) implements an external analog input voltage signal x a (t) converting into a frequency signal f a (t) output to a multi-phase clock sampling circuit (converting the voltage signal to frequency by using a standard VCO)The signal, and thus the frequency, is quantized, reducing the impact of the above matching problem, thereby achieving the effect of reducing quantization error).
S2, preprocessing the oscillation frequency signal by a multiphase clock sampling circuit to obtain sampling data;
specifically, the multiphase clock sampling circuit includes M sampling circuits, and under the control of different phase sampling clocks, sampling of the output signal of the voltage-controlled oscillation circuit is completed (the sampling quantization process of the frequency signal is realized by counting by a counter, and the larger the count value of the frequency signal in the same sampling period time is, the higher the frequency is), so as to obtain M sampling signals y of different phase sampling clocks 0 (t),...,y M-1 (t) of (d). The invention is different from a TI-ADC structure which adopts a plurality of identical analog-to-digital converters to directly perform multi-sampling on external analog signals to improve the sampling rate. In order to reduce sampling errors, the sampling clock generation circuit can dynamically adjust the frequency and the phase of a clock generated by the sampling clock generation circuit, so that the dynamic configuration of the sampling rate is realized, and the power consumption matching of a digital-to-analog converter and an application scene is controlled.
The specific mode is as follows:
s21, the multi-phase clock sampling circuit collects the oscillation frequency signals to obtain multi-channel data;
and S22, filtering the multi-channel data to obtain sampling data.
S3, the multi-channel signal error correction and reconstruction circuit corrects errors and reconstructs the sampled data in real time to obtain reconstructed data;
specifically, after the multi-channel signal error correction and reconstruction circuit finishes real-time error correction and reconstruction of the output signals of the corresponding M sampling circuits, M signals y are obtained 0 (t)+δ 0 (t),...,y M-1 (t)+δ M-1 And (t) the measurement accuracy is further improved, and the configurable correction item is provided, so that the temperature characteristic can be better matched, and the production difference between the individual digital-to-analog converters can be corrected.
And S4, combining the reconstructed data by using a digital filtering and signal combining circuit to obtain an equivalent sampling signal.
Specifically, output signals of the M paths of signal error correction and reconstruction circuits are subjected to multi-phase FIR down-sampling filtering operation, and one path of digital signal output is obtained after combination and addition, due to the noise shaping effect of the VCO quantizer, the noise power is pushed to higher frequency along with the improvement of the equivalent sampling rate, and most of the noise power can be filtered through low-complexity digital extraction filtering processing.
The specific mode is as follows:
s41, the digital filtering and signal combining circuit carries out filtering pretreatment on the reconstructed data to obtain processed data;
specifically, the filtering preprocessing is a polyphase FIR downsampling filtering operation.
And S42, combining the processed data to generate one output signal to obtain an equivalent sampling signal.
The clock generated by the multiphase sampling clock generation circuit according to the embodiment of the present invention is shown in fig. 2. f. of 0 Is a first phase clock having a phase of 0,f 1 Is a second phase clock with a phase of 2 pi/M, f M-1 The phase of the M-th phase clock is 2 pi (M-1)/M.
The working flow of the embodiment of the invention is shown in fig. 3. After the analog input voltage signal is converted into a frequency change signal by the VCO, the multi-path multi-phase acquisition circuit finishes sampling the frequency signal, then error correction and reconstruction are carried out on multi-path data obtained by sampling, and finally the multi-path data after pretreatment are filtered and merged into one path to be output.
The noise shaping effect of the VCO quantizer in the analog-to-digital converter provided by the embodiment of the present invention is shown in fig. 4. It can be seen that for an input full scale test signal, the quantized noise-shaped distribution meets the noise-shaping characteristics of a first order Sigma-Delta modulator with a 20dB increase per decade of frequency.
The high sampling rate analog-to-digital converter provided by the embodiment of the invention is subjected to performance evaluation and analysis by combining specific data as follows:
for convenience of evaluating different sampling channels M (total equivalent sampling frequency M multiplied by f) s ) To the embodiment of the inventionThe performance of the high sampling rate analog-to-digital converter is improved, and the following dynamic performance index test adopts the same single-channel sampling rate f s =48MHz, the same full amplitude range test tone signal, the same signal frequency 3MHz, and the VCO quantizer frequency range remains the same.
For the evaluation of the dynamic performance index of the analog-to-digital converter, the following 5 common quantitative indexes are provided, respectively: SFDR (sparse Free Dynamic Range), SNR (Signal-to-Noise Ratio), THD (Total Harmonic Distortion), SINAD (Signal-to-Noise-And-interference Ratio) And ENOB (Effective Number Of Bits). Wherein SFDR refers to the ratio of the rms value of the signal to the rms value of the worst spurious signal, which represents the minimum signal value that can be distinguished from large interfering signals, and is calculated below relative to the actual signal amplitude (dBc); THD refers to the ratio of the root mean square value of the fundamental signal to the average of the sum square of its first 5 harmonics; SINAD refers to the ratio of the root mean square value of the fundamental signal to the average of the sum of its harmonics plus all noise components (except for direct current), noting that in specific applications, the measurement bandwidth is not necessarily the nyquist bandwidth, and the measurement bandwidths adopted in the following performance analysis are the down-sampling bandwidths after the sampled signal passes through the decimation filter; the SNR noise is calculated according to FFT data as SINAD, except that the first 5 signal harmonics are removed by calculation, and only a noise item is left; ENOB is a parameter used to measure the conversion quality of a data converter relative to an input signal over the Nyquist bandwidth, and the SINAD is converted to ENOB, often using the theoretical SNR calculation formula of an ideal N-bit ADC (SNR =6.02N + 1.76dB), so that the calculation formula is:
for the number of channels M =1, the configuration condition of the analog-to-digital converter without the decimation filter is equivalent to that of a traditional VCO analog-to-digital converter design architecture, and due to the influence of the noise shaping characteristic, the ratio of the frequency of the input signal to the sampling frequency is large, and more in-band noise energy is introduced. Therefore, as shown in fig. 5, the SFDR at this time is 75.12db and the sinad is 68.55dB, and therefore the effective bit number ENOB is only 11.09bit, which can be calculated from the normalized power spectrum of the sampled signal. To further illustrate the performance improvement of the analog-to-digital converter provided by the embodiment of the present invention due to the high sampling rate, especially the noise shaping characteristic, compared with the dynamic performance of the sampled signal of fig. 5 after further decimation filtering, as shown in fig. 6, since the high frequency noise and distortion signal are filtered, the SFDR is increased to 86.59db, the sinad is increased to 84.90dB, so the ENOB is increased to 13.81bit, and 2.72bit is increased relative to fig. 5.
Furthermore, due to the flexible expansion capability of the high sampling rate analog-to-digital converter provided by the embodiment of the invention, more sampling channels can be supported only with very low implementation complexity, so that the effect of improving the total equivalent sampling frequency is achieved. For the number of channels M =4, the configuration condition of the analog-to-digital converter without the decimation filter is equivalent to that the total equivalent sampling frequency reaches 192MHz, and the nyquist bandwidth is improved by 4 times compared with that of a single-channel analog-to-digital converter. As shown in fig. 7, it can be calculated from the normalized power spectrum of the sampled signal that the SFDR in 48MHz at this time is 82.79db, the sinad is 76.30dB, and therefore the ENOB is 12.38bit, which is 1.29bit higher than the single-channel analog-to-digital converter in fig. 5. Similarly, to illustrate the ENOB improvement caused by the noise shaping characteristic under the condition of high oversampling rate, compared with the dynamic performance of the sampled signal of fig. 7 after further decimation filtering, as shown in fig. 8, the SFDR is increased to 106.33db, the sinad is increased to 102.56dB, and therefore, the ENOB is increased by 2.94bit compared with fig. 6.
Further, for the number of channels M =16, the configuration condition of the analog-to-digital converter without the decimation filter is equivalent to that the total equivalent sampling frequency reaches 768MHz, and the nyquist bandwidth is improved by 16 times compared with that of a single-channel analog-to-digital converter. As shown in fig. 9, it can be calculated from the normalized power spectrum of the sampled signal that the SFDR in 48MHz at this time is 84.44db, the sinad is 80.07dB, and therefore the ENOB is 13.01bit, which is 1.92bit higher than the single channel analog-to-digital converter in fig. 5. Similarly, to illustrate the ENOB improvement caused by the noise shaping characteristic under the high over-sampling rate, compared with the dynamic performance of the sampled signal of fig. 9 after further decimation filtering, as shown in fig. 10, the SFDR is increased to 111.20dB, and the sinad is increased to 108.33dB, so that ENOB is increased by 3.89bit compared with fig. 6.
In summary, fig. 5 to fig. 10 show the dynamic performance characteristics of the high sampling rate analog-to-digital converter provided by the embodiment of the invention under the condition of different sampling channel numbers. Compared with the traditional high-sampling-rate time-interleaved analog-to-digital converter, the implementation cost required by the embodiment of the invention for achieving the same sampling rate is lower. With the increase of the number of sampling channels, the total equivalent sampling frequency is correspondingly improved, the in-band noise is pushed to a higher frequency through noise shaping, the in-band SINAD is correspondingly improved, and ENOB is correspondingly improved.
While the invention has been described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (5)
1. A method for increasing the sampling rate of an analog-to-digital converter, comprising the steps of:
converting the analog input signal into an oscillation frequency signal through a voltage-controlled oscillation circuit;
the multiphase clock sampling circuit preprocesses the oscillation frequency signal to obtain sampling data;
the multi-channel signal error correction and reconstruction circuit corrects and reconstructs the sampled data in real time to obtain reconstructed data;
and combining the reconstructed data by a digital filtering and signal combining circuit to obtain an equivalent sampling signal.
2. The method of increasing the sampling rate of an analog-to-digital converter of claim 1,
the specific way of converting the analog input signal into the oscillation frequency signal by the voltage-controlled oscillation circuit is as follows:
an external input analog signal is input into the voltage-controlled oscillation circuit;
the voltage-controlled oscillation circuit converts the external input analog signal into an oscillation frequency signal.
3. The method of increasing the sampling rate of an analog-to-digital converter of claim 1,
the multiphase clock sampling circuit preprocesses the oscillation frequency signal to obtain a specific mode of sampling data:
the multi-phase clock sampling circuit collects the oscillation frequency signals to obtain multi-channel data;
and filtering the multi-path data to obtain sampling data.
4. The method of increasing the sampling rate of an analog-to-digital converter of claim 1,
the digital filtering and signal combining circuit combines the reconstructed data to obtain an equivalent sampling signal:
the digital filtering and signal combining circuit carries out filtering pretreatment on the reconstructed data to obtain processed data;
and combining the processing data to generate an output signal to obtain an equivalent sampling signal.
5. The method of increasing the sampling rate of an analog-to-digital converter of claim 4,
the filtering preprocessing is polyphase FIR downsampling filtering operation.
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| US20090115650A1 (en) * | 2007-11-07 | 2009-05-07 | Lockheed Martin Corporation | System and method for wideband direct sampling and beamforming using complex analog to digital converter |
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