CN115694511B - Continuous time Sigma-Delta analog-to-digital conversion system and operation method and application thereof - Google Patents

Abstract

The invention relates to a continuous time Sigma-Delta analog-digital conversion system and an operation method and application thereof. The operation method comprises the following steps: s1: the analog-to-digital converter carries out cross sampling; and sending the data to a digital-to-analog converter; s2: transmitting the output signal of the digital-to-analog converter in the step 1 to a differential integrator unit; meanwhile, accumulating the output data; s3: and (3) accumulating the data once in the step (2) and then outputting the data, and then clearing the accumulator. The system can be used to produce single bare or multi-bare chip. The invention has the beneficial effects that: the invention improves the oversampling rate without increasing power consumption, simplifies the design of a driver and a filter of the analog-to-digital converter, and is beneficial to the realization of integrated transceiver chips of Wi-Fi6 and Wi-Fi7 \5G communication, and the like.

Description

Continuous time Sigma-Delta analog-to-digital conversion system and operation method and application thereof

Technical Field

The invention relates to the technical field of electronic equipment and electronic devices, in particular to a continuous time Sigma-Delta analog-to-digital conversion system and an operation method and application thereof.

Background

In order to increase data rates, wireless cellular communication technologies have been developed from 20MHz/100MHz bandwidth of 4G (mainly LTE in TDD mode) to 100MHz/200MHz bandwidth of 5G centimeter band (NR 1 of SUB-6 GHz) or 400MHz/800MHz bandwidth of 5G millimeter band (NR 2 represented by 28GHz, 39GHz in the united states). Wi-Fi technology also evolves from a 160MHz bandwidth for Wi-Fi6 to a 320MHz bandwidth for Wi-Fi 7. According to nyquist sampling law, the sampling clock of the analog-to-digital converter must be more than 2 times the bandwidth, which requires an intermediate frequency sampling analog-to-digital converter of more than 500Msps or a radio frequency sampling analog-to-digital converter of more than 1 Gsps. Limited by the highest speed and power consumption of the CMOS circuit, the general implementation method of the high-speed analog-to-digital converter (ADC) is to design a plurality of multi-stage pipeline analog-to-digital converters (PIPE LINE ADCs) and perform cross sampling by using a multi-phase clock. For example, some 4Gsps ADCs, up to 20 sub-ADCs may be used for cross-sampling. The problem with cross-sampling is that the Spurious Free Dynamic Range (SFDR) metric is degraded due to the non-uniformity of the characteristics of the sub-ADCs. In addition, the plurality of sub-ADCs are in a parallel input mode, and the design difficulty of an ADC driver is increased. In addition, the method uses a germanium-silicon (GeSi) process to improve the characteristic frequency of a single tube, or uses a fin-type (FinFET) technology, and advances the manufacture procedure of a CMOS chip to the advanced manufacture procedure of 28nm or 16nm and other deep submicron, thereby improving the intrinsic frequency of a semiconductor, improving the clock speed, reducing the power consumption of a comparator, realizing an amplifier with higher bandwidth and gain product, and finally improving the sampling rate of an analog-to-digital converter.

Although the number of comparators of the pipeline analog-to-digital converter is reduced compared with that of a flash analog-to-digital converter, the sampling rate cannot be reduced as that of a successive comparison analog-to-digital converter, the pipeline analog-to-digital converter has reasonable compromise between speed and power consumption and is widely adopted, an anti-aliasing filter becomes an insurmountable obstacle in an integrated receiving chip of a direct down-conversion (zero intermediate frequency) architecture of an integrated frequency synthesizer and an I/Q demodulator. Because the high-order passive anti-aliasing filter cannot be implemented in a chip by using an inductor and a capacitor. The use of multiple active filters can substantially increase power consumption. In addition, the successive comparison analog-to-digital converter uses a switched capacitor input structure as a sampling holder, so that a driver with good index is required to ensure the performance, otherwise, the Stray Free Dynamic Range (SFDR) index of the chip can be greatly reduced. While the power consumption of high bandwidth low distortion drivers is also large. Therefore, the design of a receiver or System On Chip (SOC) integrating an analog-to-digital converter is very difficult.

In order to facilitate the design of the anti-aliasing filter, the sampling rate of the analog-to-digital converter needs to be increased. A normal flash analog-to-digital converter (ADC) or pipeline analog-to-digital converter (ADC) improves the signal-to-noise ratio (SNR) by 3dB because the quantization noise energy is halved if oversampled by 1 times (e.g., the sampling rate is 2 times the lowest sampling rate needed to satisfy the nyquist sampling theorem). That is, the 1-bit effective precision is improved by 4 times the oversampling rate. Therefore, with the common oversampling technique, the accuracy of an 8-bit analog-to-digital converter (ADC) is improved to 12 bits, requiring 256 times the oversampling rate. Even an 8Gsps flash ADC, then, using oversampling to improve the signal-to-noise ratio, would only be equivalent to a 125Msps 12-bit ADC. If the cross-sampling technique is reused, 8 flash ADCs of 8Gsps are required to cross-sample into a 12 bit ADC of 1 Gsps. This is not commercially viable because a 2-in-2-out integrated wideband transceiver chip for a direct conversion architecture requires 4 identical ADCs and 4 identical DACs. The power consumption problem of doing so is essentially unsolved, even though the cost is not relatively high.

In order to support 320MHz and 400MHz bandwidths, in an I and Q sampling direct conversion architecture (zero intermediate frequency) receiver, 2-way ADC needs to reach a sampling rate of more than 500Msps (20% of bandwidth needs to be reserved for a transition band of a filter). If a 1 st order Sigma Delta modulation technique is used, more than 16 times the oversampling rate is required to improve the 6-bit accuracy. At this point, the Sigma-Delta quantized sub-ADC requires 8 bits, 8Gsps, to achieve an equivalent 14 bit 500Msps ADC. In general, the clock frequency of a CMOS circuit is limited. For example, in a planar CMOS chip of 130nm, even if a high-speed clock circuit is designed using the CML level, only about 8GHz can be achieved. Clock frequencies above 8GHz are easier to achieve, albeit with more advanced deep sub-micron processes. However, as the operating voltage is reduced, the full swing range of the sample-holder and amplifier of the analog part becomes smaller, i.e. the power of the useful signal becomes smaller. If the noise power remains the same, the signal-to-noise ratio drops. Therefore, it is difficult to maintain the signal-to-noise ratio (SNR) and Spurious Free Dynamic Range (SFDR) of the ADC by using more advanced processes to increase the sampling rate of the ADC.

Disclosure of Invention

The invention aims to: a continuous time Sigma-Delta analog-to-digital conversion system and an operation method and application thereof are provided.

The invention is realized by the following technical scheme: a continuous time Sigma-Delta analog-to-digital conversion system comprises

The analog-to-digital converter unit is provided with N analog-to-digital converters, each analog-to-digital converter is driven through an independent clock phase, the analog-to-digital converters are connected in parallel to achieve cross sampling, and N is a positive integer;

the digital-to-analog converter units are provided with digital-to-analog converters which are the same in number as the analog-to-digital converters and correspond to the analog-to-digital converters one by one, and each analog-to-digital converter is correspondingly connected with one digital-to-analog converter to realize the generation of a feedback voltage signal;

the differential integrator unit is made of a differential amplifier and a resistor capacitor, is connected with the digital-to-analog converter and is used for receiving an output signal of the digital-to-analog converter;

the data accumulator is connected with the analog-to-digital converter and used for receiving the output signal of the analog-to-digital converter for accumulation;

the filter is connected with the data accumulator and used for digitally filtering and calibrating the accumulated signals;

and a differential integrator unit which is made by a differential amplifier and a resistance capacitor is used for integrating the difference value of the input signal and the output signal of the analog-to-digital converter to form the Sigma-Delta modulator. The analog-to-digital converter is of a differential input type, the digital-to-analog converter is of a differential output type, and the differential integrator unit is enabled to integrate the difference value of an input signal and an output signal when the analog-to-digital converter and the digital-to-analog converter are connected.

An operation method of a continuous time Sigma-Delta analog-to-digital conversion system comprises the following steps:

step 1: n analog-to-digital converters are driven by respective clock phases to carry out cross sampling; simultaneously, the output data of each analog-to-digital converter is sent to the corresponding digital-to-analog converter;

step 2: the output signal of the digital-to-analog converter in the step 1 is transmitted to a differential integrator unit, and a differential amplifier integrates the difference value of the input signal and the feedback signal output by the digital-to-analog converter to form a Sigma-Delta modulator; simultaneously, the output data of each analog-to-digital converter is sent to a data accumulator for accumulation;

and step 3: in step 2, the accumulator outputs the data to the digital filter after the data of N analog-to-digital converters are accumulated once, and then the accumulator is cleared to be ready for the next accumulation; and the data fed to the filter is digitally filtered and calibrated.

The chip manufactured by the continuous time Sigma-Delta analog-to-digital conversion system is a single bare chip or a sealed chip of multiple bare chips.

Compared with the prior art, the invention has the beneficial effects that:

1. the invention improves the oversampling rate without obviously increasing power consumption, simplifies the design of a driver of an analog-to-digital converter (ADC), simplifies the design of a filter, is beneficial to the realization of integrated transceiving chips of Wi-Fi6 and Wi-Fi7 and the design of an integrated transceiving chip of 5G communication, and can also be used for Wi-Fi6/Wi-Fi7 SOC and 5G small base station SOC.

Drawings

FIG. 1 is a schematic diagram of the working principle of the continuous-time Sigma-Delta analog-to-digital conversion system of the present invention.

Detailed description of the preferred embodiments

The invention is described in detail below with reference to the following description of the drawings:

as shown in fig. 1: a continuous time Sigma-Delta analog-to-digital conversion system comprises

The analog-to-digital converter unit is provided with N analog-to-digital converters, each analog-to-digital converter is driven through an independent clock phase, and the analog-to-digital converters are connected in parallel to achieve cross sampling, wherein N is a positive integer; the clock phase is generated by generating a high frequency clock through a phase-locked loop and dividing the frequency of the high frequency clock. Generally, the analog-to-digital converter is an M-bit flash-model sub-analog-to-digital converter.

And the digital-to-analog converter units are provided with the same number of digital-to-analog converters as the analog-to-digital converters, and correspond to the analog-to-digital converters one by one, and each analog-to-digital converter is correspondingly connected with one digital-to-analog converter to realize the generation of the feedback voltage signal. The analog-to-digital converters (DACs) are of a differential current output type, and each DAC needs to be connected with the same resistor RL (not shown) in series after the DAC to send the same signal to one end of the feedback resistor Rf of the integrator, or directly connected with one end of the feedback resistor Rf if the DAC is of a voltage output type.

The differential integrator unit is made of a differential amplifier and a resistor capacitor, is connected with the digital-to-analog converter and is used for receiving an output signal of the digital-to-analog converter;

the data accumulator is connected with the analog-to-digital converter and used for receiving and accumulating the output signal of the analog-to-digital converter; and

the filter is connected with the data accumulator and is used for digitally filtering and calibrating the accumulated signals; accumulating and taking the appropriate word length here is equivalent to averaging over a number of sample points. Averaging corresponds to a low-pass filter. Even if the passband of the low pass filter is not flat enough over its entire bandwidth, the problem of non-flatness in the band will not arise as long as it is flat enough over the bandwidth of interest, because the oversampling ratio is high. And because the word length is lengthened after accumulation, the data can not overflow, division is not needed, and the data rate can be reduced, so that the gate number of a high-speed circuit is reduced, and the power consumption is reduced. For example, 4 1Gsps 8-bit flash digital-to-analog converters perform cross sampling, a 4GHz phase-locked loop is used to multiply the frequency of a 1GHz clock to 4GHz, then 4 frequency division is performed to obtain 4 different-phase 1GHz clocks (each 2 clocks have a phase difference of 90 degrees), 4 binary data are accumulated, an accumulator uses the 4GHz clock, and the word length of the accumulated data is increased to 10 bits. The binary offset code data is converted into complement codes for accumulation, the accumulator uses 10-bit word length, 4 data are accumulated and then output at one time, and the accumulator is cleared immediately after output. I.e., the output data rate is still 1Gsps so that data does not overflow due to continuous accumulation. Only the phase-locked loop works at 4GHz, the accumulator works at 4Gsps, and other circuits can work at 1Gsps, so that the output data rate is reduced, and the power consumption is reduced.

The data output after passing through this particular accumulator can be filtered according to conventional digital filtering methods, such as CIC filtering followed by FIR filtering. After each CIC filtering, the data rate can be reduced by 2 times, and the order and the power consumption of the FIR filter are reduced.

The data of each path of sub-ADC can be corrected before being sent to the accumulator to solve the problem of the deterioration of the free dynamic range (SFDR) index caused by cross sampling, and calibration can also be carried out after accumulation.

And a differential integrator unit which is made by a differential amplifier and a resistance capacitor, and integrates the difference value of the input signal and the output signal of the analog-to-digital converter to form a Sigma-Delta modulator; the Sigma-Delta modulator shapes quantization noise, the low-frequency end noise is small, the high-frequency end noise is large, and the total quantization noise is kept unchanged.

The analog-to-digital converter is of a differential input type, the digital-to-analog converter is of a differential output type, and the differential integrator unit is enabled to integrate the difference value of an input signal and an output signal when the analog-to-digital converter and the digital-to-analog converter are connected.

Because the present invention employs a Sigma-Delta modulator, as with all Sigma-Delta ADCs, noise within the passband of interest (typically the low end) is pushed out of band (typically the high end), which corresponds to an increase in the signal-to-noise ratio (SNR) of the analog-to-digital converter (ADC). The invention does not limit the filtering method of the filter and the specific correction method, and the correction method can adopt the correction method of the prior cross sampling ADC.

Specifically, if a 1 st order Sigma-Delta modulator is used for noise shaping, the 1.5 bit accuracy can be improved every 1 time oversampling. And 2-order Sigma-Delta modulator is used for noise shaping, and the 2.5-bit precision can be improved by 1 time of oversampling. Thus, the Sigma-Delta modulator can substantially reduce the oversampling rate. Therefore, N flash type sub analog-to-digital converters with M bits and the sampling rate of Fs are modulated by a cross sampling and Sigma-Delta modulator, and K times of extraction is performed through CIC filtering, so that the output data rate is Fs/K, the equivalent is an analog-to-digital converter with the output data rate of Fs/K, and the signal-to-noise ratio (SNR) of the analog-to-digital converter is 6.02M +1.78-5.17+9.03 log2 (N + K).

The difference between the present invention and a common Sigma-Delta ADC is that the speed of the front-end quantizer is reduced. For example, an industry-advanced Sigma-Delta ADC with a SIN3 filter has an output data rate of 4.8ksps at 16-bit resolution, a reduction in the output data rate to 20sps at 24-bit resolution, and an increase in the 8-bit resolution achieved by 256 oversampling ratios. According to the calculation, if the conventional Sigma-Delta ADC structure of a 1-bit quantization front end is used, the sampling rate of the quantization front end of 256 Gsps is needed when 8-bit data of 1Gsps is output, and the sampling rate of the quantization front end of 4096 Gspsd is needed when 12-bit data of 1GSPS is output, which is completely unrealistic under the current chip process condition.

The great advantage of the analog-to-digital converter adopting the Sigma-Delta modulator is that an anti-aliasing filter in front of the analog-to-digital converter is easy to design when the system is integrated. Because the front-end analog-to-digital converter operates at a sampling rate of multiple oversampling, and the cross sampling further increases the equivalent sampling rate, the transition band allowed by the anti-aliasing filter is very long, and the anti-aliasing filter with a smaller order can be used for system integration. For example, as a multi-channel transceiver for 5G communication, only 2-order active low-pass filters (implemented by adding resistance capacitors to the input and feedback ends of an amplifier) are needed in front of a high-speed Sigma-delta adc manufactured according to the method of the present invention. If the oversampling rate is very high and the design is reasonable, the first-order RC passive low-pass filter can achieve the purpose of anti-aliasing. The improvement of the oversampling rate greatly reduces the difficulty of designing a filter of a receiving chip of an integrated frequency synthesizer and direct down converter (an I demodulator and a Q demodulator which are composed of 2 mixers). Thus, the problem of the anti-aliasing filter in the integrated chip is solved. By using the continuous time Sigma-Delta ADC technology with cross sampling, the oversampling multiple is easily more than 32 times, and by using a second-order active low-pass filter with the suppression degree of each octave increased by 12dB, the stop band suppression degree of more than 60dB can be easily realized, and the power consumption can not be increased too much due to aliasing. Another benefit of the continuous-time Sigma-Delta ADC is that the input impedance has a small change compared to a switched capacitor analog-to-digital converter with sample and hold, and a driver with a large output current capability is not required before the analog-to-digital converter, thereby reducing the power consumption and design difficulty of the analog-to-digital converter driver. The differential integrator unit itself in fig. 1 takes over the role of the driver of the analog-to-digital converter. Because cross-sampling is used, the operating frequency of the sample holder of each analog-to-digital converter is reduced, as is the drive speed of the analog-to-digital converter. Of course, the design difficulty of the present invention is caused by the differential integrator unit made of the differential amplifier and the resistor-capacitor. After the differential amplifier is designed, a gain circuit at the front end of the analog-to-digital converter has no requirement on driving capability, for example, a 2-order active low-pass filter can be used for driving the differential integrator unit, and an additional analog-to-digital converter driver is not needed, so that the design difficulty is reduced.

In principle, the order of the Sigma-Delta modulation is not limited in the present invention, and only the Sigma-Delta modulation of order 1 is not necessarily required as shown in fig. 1. The essence of the invention is that the working speed of the comparator in each sub-analog-to-digital converter is reduced by using a multi-phase clock as a cross sampling mode, the switching speed and the stability requirement of the digital-to-analog converter are reduced by using a cross output mode, a differential integrator unit is used as a Sigma-Delta modulator, and the design of a first-stage digital filter working at high speed is simplified by using a summation mode. These parts are all high speed operations, typically requiring careful design simulation and verification by analog chip design engineers. In addition, the design difficulty of the analog anti-aliasing filter is simplified by using a high-magnification oversampling mode, and the design difficulty of an integrated transceiver is solved from the framework.

It should be noted that, the differential integrator unit made of the differential amplifier and the resistor-capacitor here includes two feedback resistors Rf, two input resistors Ri, two capacitors C and the differential amplifier; a resistor Ri and a differential amplifier are sequentially connected in series between the input end of the forward voltage and the output end of the reverse voltage, and a resistor Ri and a differential amplifier are sequentially connected in series between the input end of the reverse voltage and the output end of the forward voltage; capacitors C are arranged between the output end of the reverse voltage and the resistor Ri and between the output end of the forward voltage and the resistor Ri, a branch circuit is arranged on a circuit where the two capacitors C are arranged and connected with the digital-to-analog converter, and a feedback resistor Rf is arranged on the branch circuit;

the differential input type analog-digital converter is connected with the output end of the reverse voltage and the output end of the forward voltage.

A method for operating a continuous time Sigma-Delta analog-to-digital conversion system comprises the following steps:

step 1: n analog-to-digital converters are driven by respective clock phases to carry out cross sampling; simultaneously, the output data of each analog-to-digital converter is sent to the corresponding digital-to-analog converter;

step 2: the output signal of the digital-to-analog converter in the step 1 is transmitted to a differential integrator unit consisting of a differential amplifier and a resistor capacitor, and the differential integrator unit integrates the output signal of the digital-to-analog converter and the error signal of the input signal to form a Sigma-Delta modulator; simultaneously, the output data of each analog-to-digital converter is sent to a data accumulator for accumulation;

and step 3: in step 2, the accumulator outputs the data to the digital filter after the data of N analog-to-digital converters are accumulated once, and then the accumulator is cleared to be ready for the next accumulation; and the data fed to the filter is digitally filtered and calibrated.

In step 3, the specific manner of digital filtering by the filter is as follows: CIC filtering is firstly carried out, K times of extraction is carried out to reduce the data rate, the output data rate is Fs/K, then FIR filtering is carried out, and proper calibration is carried out, wherein Fs is the sampling rate of N flash type sub analog-to-digital converters.

The chips manufactured by the continuous time Sigma-Delta analog-to-digital conversion system are single bare chip or multi-bare chip sealing chips. Specifically, the system and method of the present invention can be used as a stand-alone analog-to-digital conversion chip or as an integrated transceiver chip (a class of chips that integrate multiple analog-to-digital converters, digital-to-analog converters, wideband frequency synthesizers, and direct conversion I/Q modems to perform bi-directional conversion of radio frequency to digital work).

The concrete application is as follows:

an integrated Wi-Fi7 receiver is exemplified. The increase in data bandwidth from Wi-Fi to Wi-Fi5 and Wi-Fi6 has increased from 40MHz to 160MHz, and the increase in modulation from 64 QAM to 256 QAM and 1024 QAM has presented significant challenges to chip design. After the Wi-Fi6 is promoted to the Wi-Fi7, the radio frequency bandwidth is 320MHz at most, the modulation mode is 4096 QAM at most, and the design difficulty of an analog-digital converter is very high. Many domestic Wi-Fi chip design companies can not independently complete the design of the high-speed analog-to-digital converter, and need to purchase IP from the outside. A zero intermediate frequency receiver scheme adopting a direct frequency conversion framework needs frequency synthesis within a range of 5.8GHz to 7GHz, and radio frequency signals are directly converted into baseband analog signals by an I/Q demodulator in a down-conversion mode. Because the radio frequency bandwidth is 320MHz, the I/Q baseband analog signal bandwidth is 160MHz. Selecting an oversampling rate of 2.5 times for quantization for subsequent data extraction requires a high speed ADC with an output data rate of 400Msps or more. For a common 2-receiving 2-sending system, 4 high-speed analog-to-digital converters are needed, the power consumption and the cost need to be strictly controlled, and the indexes required by the standard cannot be reduced. The bit width of the analog-to-digital converter also increases the requirements due to the change of the modulation mode. If Wi-Fi5 requires an analog-to-digital converter (8-bit ADC) with a significand of about 7 bits, then Wi-Fi6 requires a significand of about 9 bits (10-bit ADC) and Wi-Fi7 requires a significand of about 11 bits (12-bit ADC). If a pipelined ADC with a sampling rate of 400Msps and a significand of around 11 bits is used directly, the filter has a passband bandwidth of 160MHz and a stopband of 240MHz. If the effective number of bits of the analog-to-digital converter needs about 11 bits, i.e. the signal-to-noise ratio needs about 66dB, the stopband rejection of the ideal anti-aliasing filter needs about 66 dB. With such a narrow transition band, it is not possible to make the rejection of the stop band around 66dB with an analog low-pass filter.

Now, a Voltage Controlled Oscillator (VCO) of 12.8GHz and a phase locked loop (a VCO of 6.4GHz can also be used for frequency doubling) are selected to generate a clock of 12.8GHz (12.8 GHz is not easy to mutually pull with a local oscillator of 5.8GHz to 7GHz by frequency synthesis, but the frequency doubling mode needs to consider the phase locked loop pulling problem caused by the isolation), frequency division is performed by 4 to obtain 4 pairs of 4 phase clocks of 3.2GHz, and the phase difference of each 2 clocks is 90 degrees. 4 FLASH analog-to-digital converters (FLASH ADCs) of 4 bits of 3.2Gsps were designed, each using one differential sample holder and 15 comparators, for a total of 60 comparators. Cross-sampling with 4 flash ADCs is equivalent to a sampling rate of 12.8 Gsps. Similarly, 4 current output digital-to-analog converters (DACs) are made, each digital-to-analog converter (DAC) uses 16 identical current sources (the current sources with the same current can be easily obtained by using a current mirror), and the output data of the FLASH analog-to-digital converter (FLASH ADC) is used for driving an analog switch to switch the current sources, so that the 4-bit current output type digital-to-analog converter (DAC) is equivalent. The current output of a digital-to-analog converter (DAC) is converted into voltage output by using a proper grounding resistor, and then the voltage output is connected to a feedback resistor Rf of a differential integrator unit to form a 1-order Sigma-Delta modulator. Meanwhile, the output data of 4 paths of FLASH analog-to-digital converters (FLASH ADCs) with 3.2Gsps are accumulated, the accumulator is driven by a 12.8GHz clock, the final accumulation result (equivalent to 4 times of extraction) is obtained, and then the accumulator is cleared to prepare for accumulation in the next period. If the word length of 6 bits is taken, the overflow will not occur, and the output data clock is 3.2GHz. The data is sent to a CIC3 filter, taking coefficients with a proper word length (for example, 8 bits) and a proper output word length (for example, 10 bits), and performing 4 times of decimation, and outputting a data clock of 800MHz (the operating rate of the CIC3 filter is too high, and the digital filter may still need to be made by using a CML level in an analog mode). And performing CIC3 filtering again in the same CIC3 filter design mode, performing 2-time extraction, and outputting a data clock of 400MHz. A Finite Impulse Response (FIR) filter is designed by selecting 40% bandwidth, and proper coefficient word length (such as 10 bits) and output word length (such as 12 bits) are selected, and are not extracted after FIR filtering is finished and are output as baseband data. The latter digital filter has low working frequency, can be realized by using a common CMOS circuit and using a Verlog code design, and reduces the workload.

The signal to noise ratio is now calculated. Based on a 4-bit flash ADC, M =4, the equivalent sampling rate 12.8Gsps, the oversampling rate is 32 times, and the final output signal-to-noise ratio (SNR) is 6.02 × M +1.78-5.17+9.03 × log2 (4 × 8) = 65.84dB. This signal-to-noise ratio index is close to that of a 12-bit pipeline high-speed analog-to-digital converter. In addition, since the front-end sampling rate is equivalent to 12.8Gsps, the number of multiplication cycles to 12.64GHz is 79 times (greater than the 6 th power of 2) relative to a 160MHz passband low pass filter. According to the calculation of a second-order active low-pass filter with 12dB increase of the suppression degree per octave, the suppression degree can be more than 72dB, and the signal-to-noise ratio can not be reduced due to aliasing reasons.

In summary, with the system and the method of the patent, the oversampling rate is improved without obviously increasing power consumption, the design of an ADC driver is simplified, the design of a filter is simplified, and the design of the integrated transceiver chip for Wi-Fi6 and Wi-Fi7 and the integrated transceiver chip for 5G communication (including NR1 and NR2 of SUB 6 GHz) are facilitated, and the integrated transceiver chip can also be used for Wi-Fi6/Wi-Fi7 SOC and 5G small base station SOC, and has great commercial value.

It should be noted that the above-mentioned embodiments are only preferred embodiments of the present invention, and the present invention is not limited thereto, and although the present invention has been described in detail with reference to the foregoing embodiments, it will be apparent to those skilled in the art that modifications can be made to the technical solutions described in the foregoing embodiments or equivalent substitutions for some technical features, and any modifications, equivalent substitutions, improvements and the like made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims (6)

1. Continuous-time Sigma-Delta analog-to-digital conversion system, characterized by: it comprises

The analog-to-digital converter unit is provided with N analog-to-digital converters, each analog-to-digital converter is driven through an independent clock phase, and the analog-to-digital converters are connected in parallel to achieve cross sampling, wherein N is a positive integer;

the digital-to-analog converter units are provided with digital-to-analog converters which are the same in number as the analog-to-digital converters and correspond to the analog-to-digital converters one by one, and each analog-to-digital converter is correspondingly connected with one digital-to-analog converter to realize the generation of a feedback voltage signal;

the differential integrator unit is made of a differential amplifier and a resistor capacitor, is connected with the digital-to-analog converter and is used for receiving an output signal of the digital-to-analog converter;

the data accumulator is connected with the analog-to-digital converter and used for receiving the output signals of the analog-to-digital converter for accumulation;

the filter is connected with the data accumulator and used for digitally filtering and calibrating the accumulated signals; and

the differential integrator unit integrates the difference value of the input signal and the output signal of the analog-to-digital converter to form a Sigma-Delta modulator;

the analog-digital converter is of a differential input type, the digital-analog converter is of a differential output type, and the differential integrator unit is ensured to integrate the difference value of an input signal and an output signal when the analog-digital converter and the digital-analog converter are connected;

the differential integrator unit comprises two feedback resistors Rf, two input resistors Ri, two integrating capacitors C and a differential amplifier; a resistor Ri and a differential amplifier are sequentially connected in series between the input end of the forward voltage and the output end of the reverse voltage, and a resistor Ri and a differential amplifier are sequentially connected in series between the input end of the reverse voltage and the output end of the forward voltage; capacitors C are connected in parallel between the output end of the reverse voltage and the resistor Ri and between the output end of the forward voltage and the resistor Ri, a branch circuit is arranged on a circuit where the two capacitors C are located and connected with the digital-to-analog converter, and a feedback resistor Rf is arranged on the branch circuit;

the analog-to-digital converter is connected with the output end of the reverse voltage and the output end of the forward voltage.

2. The continuous-time Sigma-Delta analog-to-digital conversion system of claim 1, wherein: the analog-to-digital converter is an M-bit flash model sub-analog-to-digital converter.

3. The continuous-time Sigma-Delta analog-to-digital conversion system of claim 1, wherein: the clock phase is generated by generating a high-frequency clock through a phase-locked loop and dividing the frequency of the high-frequency clock.

4. The method of operating a continuous-time Sigma-Delta analog-to-digital conversion system of claim 1, wherein:

step 1: n analog-to-digital converters are driven by respective clock phases to carry out cross sampling; simultaneously, the output data of each analog-to-digital converter is sent to the corresponding digital-to-analog converter;

step 2: the output signal of the digital-to-analog converter in the step 1 is transmitted to a differential integrator unit, and a differential amplifier integrates the difference value of the input signal and the feedback signal output by the digital-to-analog converter to form a Sigma-Delta modulator; simultaneously, the output data of each analog-to-digital converter is sent to a data accumulator for accumulation;

and 3, step 3: in the step 2, the accumulator outputs the data to the digital filter after the data of N analog-to-digital converters are accumulated once, and then the accumulator is cleared to prepare for the next accumulation; and the data fed to the filter is digitally filtered and calibrated.

5. The method of operating a continuous-time Sigma-Delta analog-to-digital conversion system of claim 4, wherein:

in step 3, the specific manner of digital filtering by the filter is as follows: CIC filtering is firstly carried out, K times of extraction is carried out to reduce the data rate, the output data rate is Fs/K, then FIR filtering is carried out, and proper calibration is carried out, wherein Fs is the sampling rate of N flash type sub analog-to-digital converters.

6. A chip made by a continuous-time Sigma-Delta analog-to-digital conversion system according to any of claims 1 to 3, wherein: the chip is a single bare wafer chip or a sealed chip of multiple bare wafers.

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