CN114791556A - On-chip clock network delay test method and test circuit - Google Patents
On-chip clock network delay test method and test circuit Download PDFInfo
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- CN114791556A CN114791556A CN202210387635.6A CN202210387635A CN114791556A CN 114791556 A CN114791556 A CN 114791556A CN 202210387635 A CN202210387635 A CN 202210387635A CN 114791556 A CN114791556 A CN 114791556A
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- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
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- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2882—Testing timing characteristics
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Abstract
The invention discloses a method and a circuit for testing the delay of an on-chip clock network, which relate to the integrated circuit technology, and comprise the following steps: 1) a clock management circuit module in the chip provides a control clock signal and N paths of test clock signals, the phases of the test clock signals are the same, and N is an integer greater than 2; 2) constructing N test branches, wherein each test branch comprises a clock network path and a trigger connected with the clock network path, and the test branches and test clock signals are accessed in a one-to-one corresponding mode; 3) the control clock signal is accessed to the trigger area in the chip through the same path and then shunted to each trigger so as to take the control clock signal as the control clock of each trigger; 4) through a clock management circuit module, the phase of a clock signal is adjusted and controlled in a waveform sliding mode, and the output of each trigger is recorded; 5) and judging the time delay difference value between the test branches according to the phase difference of the output signals of the triggers. The invention has low test cost and high precision.
Description
Technical Field
The present invention relates to integrated circuit technology, and more particularly, to integrated circuit testing technology.
Background
The FPGA field programmable logic array device is internally provided with a complex clock network, and a clock signal is transmitted from a sending end circuit to a receiving end circuit through the clock network. Due to the difference of signal transmission delay of different clock network paths, the timing relationship of the internal logic circuit of the chip is affected. In addition, the signal transmission delay parameter of the clock network is related to factors such as power supply voltage, chip temperature saving, chip process and the like, so that the research on the test method of the clock network delay parameter has certain engineering value.
In the traditional clock network delay parameter test, part of I/O interfaces of an FPGA chip to be tested are selected to be used as an input end and an output end of a signal respectively. And then testing the time sequence delay between the input end signal and the output end signal by using an oscilloscope or other testing equipment, and subtracting the signal transmission delay of a signal transmission channel on the testing circuit board. The test method has strong dependence on the test port, has low test flexibility and is easily influenced by external test conditions. Especially, for some special clock network paths inside the FPGA chip, the test through the I/O input/output port is difficult.
Disclosure of Invention
The invention aims to solve the technical problem of providing a test technology of an FPGA (field programmable gate array) on-chip clock network independent of special test instrument equipment, which comprises an on-chip clock network delay test method and an on-chip clock network delay test circuit.
The technical scheme adopted by the invention for solving the technical problems is that the on-chip clock network delay testing method is characterized by comprising the following steps:
1) a clock management circuit module in the chip provides a control clock signal and N paths of test clock signals, the phases of the test clock signals are the same, and N is an integer greater than 2;
2) constructing N test branches, wherein each test branch comprises a clock network path and a trigger connected with the clock network path, and the test branches and test clock signals are accessed in a one-to-one corresponding mode;
3) the control clock signal is accessed to the trigger area in the chip through the same path and then shunted to each trigger so as to take the control clock signal as the control clock of each trigger;
4) through a clock management circuit module, the phase of a clock signal is adjusted and controlled in a waveform sliding mode, and the output of each trigger is recorded;
5) and judging the time delay difference value between the test branches according to the phase difference of the output signals of the triggers.
In the step 4), after the clock management circuit module outputs the control clock signal for the first time, the phase of the control clock signal output each time is delayed by a preset time unit from the phase of the control clock signal output last time.
The frequency of the control clock signal is an even multiple of the frequency of the test clock signal.
The invention provides an on-chip clock network delay test circuit which comprises a clock management circuit module, a control clock signal branch and N test branches, wherein each test branch comprises a clock network path and a trigger connected with the clock network path;
the control/storage module is connected with the clock management circuit module;
the test clock signal port of the clock management circuit module is connected with the sampling signal input end of the trigger of each test branch circuit through a clock network path in the branch circuit;
and a control clock signal port of the clock management circuit module is connected with the clock end of each trigger through a control clock signal branch.
Further, the control/storage module has a phase shift control module, and the phase shift control module is configured to generate a signal indicating that the time length equal difference between two adjacent trigger points is increased. The trigger point refers to a characteristic point in the signal as a trigger, such as a rising edge or a falling edge.
The testing method has the advantages of simple working principle, convenient application, low testing cost and high testing precision (the precision can reach 25 ps).
Drawings
FIG. 1 is a schematic diagram of a built-in test architecture for signal transmission delay of a clock network according to the present invention.
Fig. 2 is an exemplary diagram of the initial phase relationship of the output clocks of the clock management circuit module at the source end.
Fig. 3 is a diagram illustrating an example of the phase relationship between the output clocks of the clock management circuit module and the flip-flops via different clock networks.
FIG. 4 is a schematic diagram of the address assignment of the memory portion of the control/memory module.
FIG. 5 is a schematic view of example 1.
FIG. 6 is a schematic view of example 2.
Detailed Description
The invention provides a signal transmission delay parameter testing method of a clock network based on chip built-in testing. Because the testing links of the chip are numerous, the testing method is mainly suitable for the board-level testing of the finished chip. Under the condition of not depending on special test instrument equipment, the internal function circuit of the FPGA chip is used for testing the clock network, and original test data are uploaded to a computer so as to carry out data statistics and analysis at a later stage.
The invention combines the clock management module with dynamic phase shift adjusting function in the FPGA chip with the measured clock network, and can realize the signal transmission delay test of the clock network in part of the chip by a built-in test method.
The invention discloses a method for testing the network delay of an on-chip clock, which comprises the following steps:
1) a clock management circuit module in the chip provides a control clock signal and N paths of test clock signals, the phases of the test clock signals are the same, and N is an integer greater than 2;
2) constructing N test branches, wherein each test branch comprises a clock network path and a trigger connected with the clock network path, and the test branches and test clock signals are accessed in a one-to-one corresponding mode;
3) the control clock signal is accessed to the trigger area in the chip through the same path and then shunted to each trigger so as to take the control clock signal as the control clock of each trigger;
4) through a clock management circuit module, the phase of a clock signal is adjusted and controlled in a waveform sliding mode, and the output of each trigger is recorded;
5) and judging the time delay difference value between the test branches according to the phase difference of the output signals of the triggers.
In the step 4), after the clock management circuit module outputs the control clock signal for the first time, the phase of the control clock signal output each time is delayed by a preset time unit from the phase of the control clock signal output last time.
The frequency of the control clock signal is an even multiple of the frequency of the test clock signal.
The on-chip clock network delay test circuit comprises a clock management circuit module 100, a control clock signal branch circuit 105 and N test branch circuits, wherein each test branch circuit comprises a clock network path and a trigger connected with the clock network path, the output end of each trigger is connected with a control/storage module, and the control/storage module is connected with an external output interface; fig. 1 is a case of 4 test branches, 4 test branches being shown at 101, 102, 103 and 104, respectively.
The control/storage module is connected with the clock management circuit module;
the test clock signal port of the clock management circuit module is connected with the sampling signal input end of the trigger of each test branch circuit through a clock network path in the branch circuit;
and a control clock signal port of the clock management circuit module is connected with the clock end of each trigger through a control clock signal branch.
The control/storage module is provided with a phase shift control module which is used for generating signals with the time length equal difference between two adjacent trigger points increasing. The trigger point refers to a characteristic point in the signal as a trigger, such as a rising edge or a falling edge. The clock management circuit module takes the trigger point as a trigger signal of the output phase-shifted clock.
Specifically, the test system is shown in FIG. 1. The FPGA chip to be tested is carried on the board-level test board and is connected with the PC computer through a JTAG interface. The board-level test board provides peripheral functional circuits such as power supply, a clock signal source, power-on reset and the like for the FPGA chip to be tested.
The core of the clock network built-in test circuit mainly comprises a clock management circuit module, each clock network path, a trigger and a built-in test data storage module.
The clock management circuit module has the main function of outputting a plurality of paths of clock signals, and 5 paths of output clocks are exemplified; the clock network paths NO. 1-5 are different clock network paths; the trigger is used for sampling the logic state of the clock network signal; the built-in test control and storage module is used for controlling the working state of the clock management circuit module, storing the logic level acquired by the trigger and uploading the acquired test data under the control of the PC computer.
The clock management circuit module can have a plurality of output clocks, and the output clock 5 works in a dynamic phase shift state, namely, the phase relative to the output clocks 1-4 can be dynamically adjusted; the output clock phases of the output clocks 1-4 are in a fixed state. For later data analysis, the frequency (fclk) and duty cycle of the output clocks 1-4 are preferably set to the same value. The frequency (fs) of the output clock 5 may be equal to fclk or may be divided by an even multiple of fclk.
As shown in FIG. 2, the output frequencies of the output clocks 1-5 are the same and the duty ratios are all 50%. After the clock management circuit module is reset stably, the relative phase relations of the output clocks at the source ends are kept consistent.
Due to the fact that paths of clock network paths NO. 1-4 are different, signal transmission delay characteristics are different. If the signal transmission delay of the clock network path No.2 is greater than the path No.1, the difference of the transmission delays is set to be Δ T21. Since the phases of the output clocks 1 and 2 at the source terminals are the same, the relative phases change when the clock signals output by the clock management circuit unit reach the input terminals of the flip-flops 1 and 2, respectively. The D input signal of flip-flop 2 lags in phase with flip-flop 1.
Because the frequencies of the output clock 5 and the output clocks 1-4 are equal or even frequency division, the output logic of the flip-flop corresponding to any 1 sampling clock trigger edge is fixed (note: if the sampling clock edge of the flip-flop and the edge of the input signal of the flip-flop D occur at adjacent time, the output logic of the flip-flop is in a random state). Therefore, by using the test method, the frequency setting of the output clock 5 is more flexible, and the frequency can be divided to a lower frequency so as to adapt to the working frequency range of the logic and storage circuit of the FPGA chip to be tested.
On the basis, the phase of the output clock 5 relative to the output clocks 1-4 can be dynamically and continuously adjusted, as shown in fig. 3, each phase adjustment step corresponds to the phase delay of Ts, and the value of Ts is a known parameter that can be configured by a built-in test control program.
The logic level of each measured clock network under each phase condition can be obtained through the triggers 1-4 respectively, and data are stored into corresponding storage addresses in a data storage circuit inside the FPGA chip to be measured respectively. As shown in fig. 4, the data is then transmitted to the PC computer via JTAG or other data bus interface, so that the phase relationship between the D input signals of the flip-flops 1-4 as shown in the above figure can be restored. The above figure is an example where the D input signals of flip-flops 1 and 2 differ by 3 phase adjustment steps, i.e. 3 × Ts. I.e. the measurement of the signal transmission delay between clock network paths No.1 and 2 is 3 x Ts.
Example 1
As shown in FIG. 5, the measured clock networks 1-4 are all BUFH horizontal clock networks inside the FPGA chip (the interior of the FPGA can be divided into a plurality of clock domains according to different physical location areas, wherein the paths of the BUFH horizontal clock networks are only distributed in the corresponding clock domains. The difference of signal transmission delay between different BUFH horizontal clock networks in the same clock domain can be tested by using the framework of the embodiment.
Example 2
As shown in fig. 6, the measured clock networks 1-2 are a BUFH horizontal clock network and 1 BUFG global clock network inside the FPGA chip to be measured, respectively. The signal transmission path of the BUFG global clock network is longer, and the signal transmission delay is also larger. The difference value of the signal transmission delay of the network paths of the BUFH clock and the BUFG clock to be tested can be obtained through the test architecture.
And (3) MMCM: clock management circuit module
BUFH: horizontal clock network
FDCE: flip-flop
Detect: detector
BRAM: data storage
The description and drawings clearly illustrate the principles and operation of the invention and can be implemented by those skilled in the art. The clock management circuit module, the control/storage module and other functional modules belong to an internal functional module of the FPGA, and a person skilled in the art can completely understand the functional modules, and detailed descriptions of specific structures of the functional modules are omitted.
Claims (5)
1. The method for testing the time delay of the on-chip clock network is characterized by comprising the following steps:
1) a clock management circuit module in the chip provides a control clock signal and N paths of test clock signals, the phases of the test clock signals are the same, and N is an integer greater than 2;
2) constructing N test branches, wherein each test branch comprises a clock network path and a trigger connected with the clock network path, and the test branches and test clock signals are accessed in a one-to-one corresponding mode;
3) the control clock signal is accessed to the trigger area in the chip through the same path and then shunted to each trigger so as to take the control clock signal as the control clock of each trigger;
4) through a clock management circuit module, the phase of a clock signal is adjusted and controlled in a waveform sliding mode, and the output of each trigger is recorded;
5) and judging the time delay difference value between the test branches according to the phase difference of the output signals of the triggers.
2. The method for testing delay of on-chip clock network of claim 1, wherein in the step 4), after the clock management circuit module outputs the control clock signal for the first time, the phase of the control clock signal outputted each time is delayed by a predetermined time unit from the phase of the control clock signal outputted the previous time.
3. The on-chip clock network delay test method of claim 1, wherein the frequency of the control clock signal is an even multiple of the frequency of the test clock signal.
4. The on-chip clock network delay test circuit is characterized by comprising a clock management circuit module, a control clock signal branch and N test branches, wherein each test branch comprises a clock network path and a trigger connected with the clock network path;
the control/storage module is connected with the clock management circuit module;
the test clock signal port of the clock management circuit module is connected with the sampling signal input end of the trigger of each test branch circuit through a clock network path in the branch circuit;
and a control clock signal port of the clock management circuit module is connected with the clock end of each trigger through a control clock signal branch.
5. The on-chip clock network delay test circuit of claim 4, wherein the control/storage module has a phase shift control module, and the phase shift control module is used for generating signals with increasing time length equal difference between two adjacent trigger points.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116400205A (en) * | 2023-06-07 | 2023-07-07 | 中国汽车技术研究中心有限公司 | Chip clock network delay cross-validation test method |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116400205A (en) * | 2023-06-07 | 2023-07-07 | 中国汽车技术研究中心有限公司 | Chip clock network delay cross-validation test method |
| CN116400205B (en) * | 2023-06-07 | 2023-09-19 | 中国汽车技术研究中心有限公司 | Chip clock network delay cross-validation test method |
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