WO2009150816A1 - Multi-strobe circuit, method for calibration of the same, and test equipment using the same - Google Patents

Multi-strobe circuit, method for calibration of the same, and test equipment using the same Download PDF

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Publication number
WO2009150816A1
WO2009150816A1 PCT/JP2009/002573 JP2009002573W WO2009150816A1 WO 2009150816 A1 WO2009150816 A1 WO 2009150816A1 JP 2009002573 W JP2009002573 W JP 2009002573W WO 2009150816 A1 WO2009150816 A1 WO 2009150816A1
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delay
strobe
under test
signal
delay amount
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PCT/JP2009/002573
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French (fr)
Japanese (ja)
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宜保徹
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株式会社アドバンテスト
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31903—Tester hardware, i.e. output processing circuits tester configuration
    • G01R31/31908—Tester set-up, e.g. configuring the tester to the device under test [DUT], down loading test patterns
    • G01R31/3191—Calibration
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31917—Stimuli generation or application of test patterns to the device under test [DUT]
    • G01R31/31922—Timing generation or clock distribution

Definitions

  • the present invention relates to a multi-strobe circuit that generates a multi-phase strobe signal (multi-strobe signal) and evaluates the level of a signal to be evaluated at timings of a plurality of edges of the multi-strobe signal.
  • Multi-strobe circuits are used in test equipment for testing semiconductor devices such as memory and DSP (Digital Signal Processor).
  • the multi-strobe circuit generates a multi-strobe signal (also referred to as a multi-phase strobe signal) having a plurality of edges within one cycle period of a signal under test (for example, a binary digital signal) output from a semiconductor device.
  • the level of the signal output from the semiconductor device is determined at the edge timing.
  • FIG. 1 is a circuit diagram showing a configuration example of the multi-strobe circuit 300.
  • N first delay elements D1 1 to D1 N (collectively referred to as first delay elements D1) are cascade-connected in multiple stages.
  • the first delay element D1 1 of the first stage is input under test signal S1 outputted from the DUT, the DUT signal S1 each time through the first delay element D1 1 stage, given the predetermined delay Tpd . That is, the i-th first delay element D1 i outputs the signal under test S1 i delayed by i ⁇ Tpd with respect to the signal under test S1 output from the DUT.
  • N second delay elements D2 1 to D2 N are provided for each of the N first delay elements D1 1 to D1 N and cascaded in multiple stages. .
  • the first stage second delay element D2 1 of the strobe signal STRB to be a reference are input.
  • the strobe signal STRB is given a predetermined delay (Tpd + ⁇ t) every time one stage passes through the second delay element D2.
  • the i-th strobe signal STRB i delayed by i ⁇ (Tpd + ⁇ t) with respect to the reference strobe signal STRB is output from the i- th second delay element D2.
  • N latch elements L 1 to L N are also provided for each of the N first delay elements D1 1 to D1 N.
  • the i (i is a natural number satisfying 1 ⁇ i ⁇ N) -th latch element L i latches the output signal of the i-th first delay element D1 i at the timing of the edge of the i-phase strobe signal STRBi.
  • the latch element L1 indicated by the D flip-flop in FIG. 2 can be replaced by various elements such as other flip-flops and latch circuits.
  • Output signals SL 1 to SL N of the N latch elements L are input to the logic operation unit 310.
  • the logical operation unit 310 performs predetermined signal processing according to the evaluation items of the DUT.
  • the output signals SL 1 to SL N are thermometer codes in which 0 and 1 change at a certain bit. Therefore, the logical operation unit 310 includes a priority encoder.
  • the levels of the signal under test S1 input to the first delay element D1 and the strobe signal STRB input to the second delay element D2 The phase difference (timing) is adjusted.
  • the relative time difference between the signal under test S1 and the strobe signal STRB changes by ⁇ t. That is, the value of the signal under test S1 is determined at the timing of N strobe signals (multi-strobe signals) STRB 1 to STRB N whose phases are shifted from each other by ⁇ t.
  • N strobe signals multi-strobe signals
  • the present invention has been made in view of such problems, and one of exemplary purposes of an aspect thereof is to provide a multi-strobe circuit and a calibration method capable of calibration.
  • An aspect of the present invention relates to a multi-strobe circuit that latches a signal under test to be evaluated at each edge timing of a multi-strobe signal having a plurality of edges.
  • This multi-strobe circuit is configured by connecting N (N is a natural number) first delay elements in multiple stages, and delays each stage of the signal under test to generate a plurality of signals under test.
  • a circuit and N second delay elements provided for each of the N first delay elements are connected in multiple stages, and a delay is provided for each stage with respect to a reference strobe signal.
  • the i-th latch element is output from the i-th first delay element.
  • a latch circuit configured to latch the signal at the timing of the strobe signal output from the i-th second delay element, and at least one of the N first delay elements and the N second delay elements
  • the delay amount adjusting unit increments i (i is a natural number) from 1 to N during calibration so that the edge timing of the signal under test input to the i-th latch element and the strobe signal coincide with each other.
  • a resolution setting step for changing only a fixed amount.
  • the delay amount variation between the first delay element and the second delay element in each phase (stage) is canceled in order from the first stage, and then the delay amount corresponding to the resolution is set to the second delay.
  • the multi-strobe circuit can be calibrated with high accuracy.
  • the N first delay elements and the N second delay elements may be variable delay elements.
  • the delay amount adjusting unit may execute the zero adjustment step by setting a state in which the delay amounts of the N first delay elements and the second delay elements are set to a minimum as an initial state.
  • the delay amount of the i-th first delay element is increased
  • the delay amount of the i-th second delay element may be increased.
  • the delay amount adjustment unit may perform the following processing when performing the i-th adjustment in the zero adjustment step.
  • (1) The relative delay amount of the i-th first delay element and the second delay element is changed stepwise.
  • (2) In the process of (1), the relative delay amount when the value latched by the i-th latch element is fixed at the first level is acquired as the first relative delay amount.
  • (3) In the process of (1), the relative delay amount when the value latched by the i-th latch element is determined to be a second level complementary to the first level is defined as a second relative delay. Get as a quantity.
  • the relative delay amount of the i-th first delay element and the second delay element is set to a value between the first relative delay amount and the second relative delay amount. In (4), the relative delay amount between the first delay element and the second delay element may be the midpoint between the first relative delay amount and the second relative delay amount.
  • test apparatus includes a comparator that compares a signal output from a device under test with a threshold voltage, a timing generator that generates a strobe signal whose level transitions at an arbitrary timing, a strobe signal, and a signal under test. And any one of the multi-strobe circuits described above that receives the output signal of the comparator.
  • Still another aspect of the present invention relates to a multi-strobe circuit calibration method for latching a signal under test to be evaluated at each edge timing of a multi-strobe signal having a plurality of edges.
  • the multi-strobe circuit is configured by connecting N (N is a natural number) first delay elements in multiple stages, and delays each stage of the signal under test to generate a plurality of signals under test.
  • N second delay elements provided for each of the N first delay elements are connected in multiple stages, and a plurality of strobe signals are generated by delaying the reference strobe signal for each stage.
  • the i-th latch element is a signal under test output from the i-th first delay element. Is latched at the timing of the strobe signal output from the i-th second delay element.
  • i (i is a natural number) is incremented from 1 to N so that the timing of the edge of the signal under test inputted to the i-th latch element and the strobe signal coincide with each other.
  • a zero adjustment step for adjusting a delay amount of at least one of the first delay element and the second delay element, and a delay amount of at least one of the first delay element and the second delay element is changed by a predetermined amount.
  • the N first delay elements and the N second delay elements may be variable delay elements.
  • the calibration method executes the zero adjustment step with the state in which the delay amounts of the N first delay elements and the second delay elements are set to the minimum as the initial state.
  • the zero adjustment step When the edge timing of the signal under test input to the latch element is earlier than the edge timing of the strobe signal, the delay amount of the i-th first delay element is increased and the signal input to the i-th latch element is increased.
  • the delay amount of the i-th second delay element may be increased.
  • the relative delay amount of the i-th first delay element and the second delay element is changed stepwise and held in the i-th latch element.
  • a relative delay amount when the value to be determined is determined to be the first level is defined as a first relative delay amount, and a value latched by the i-th latch element is complementary to the first level. Is obtained as the second relative delay amount, and the relative delay amounts of the i-th first delay element and the second delay element are determined as the first relative delay amount and the second relative delay amount.
  • a value between the delay amounts may be set.
  • a multi-strobe circuit that is highly accurate in time is provided.
  • FIG. 4 is a time chart showing the relationship between the timing of a strobe signal STRBi and a signal under test S1i and latch data LDi.
  • FIGS. 6A and 6B are time charts showing the timing relationship between the strobe signal and the signal under test when the calibration according to the embodiment is not performed.
  • FIGS. 7A and 7B are time charts showing how the multi-strobe circuit of FIG. 2 is calibrated.
  • the member A is connected to the member B means that the member A and the member B are physically directly connected, or the member A and the member B are electrically connected.
  • the case where it is indirectly connected through another member that does not affect the state is also included.
  • the state in which the member C is provided between the member A and the member B refers to the case where the member A and the member C or the member B and the member C are directly connected, as well as an electrical condition. It includes the case of being indirectly connected through another member that does not affect the connection state.
  • FIG. 2 is a block diagram illustrating a configuration of the test apparatus 100 including the multi-strobe circuit 10 according to the embodiment.
  • the test apparatus 100 receives a signal under test S1 output from a device under test (DUT) 110 such as a memory, DSP, or other digital circuit, and executes a predetermined test.
  • DUT device under test
  • the test apparatus 100 includes a timing generator 30 and a level comparator 40 in addition to the multi-strobe circuit 10.
  • the level comparator 40 includes a first comparator 42 and a second comparator 44.
  • the first comparator 42 compares the potential of the signal under test S1 output from the DUT 110 with a low level threshold voltage VOL, and generates a signal under test S1L whose high level and low level change according to the comparison result.
  • the second comparator 44 compares the potential of the signal under test S1 with a high level threshold voltage VOH, and generates a signal under test S1H according to the comparison result.
  • the level comparator 40 can be constituted by a comparator for comparing the potential of the signal under test S1 with a single threshold voltage, or a simple inverter (buffer).
  • the timing generator 30 generates a strobe signal STRB whose level transitions (that is, has an edge) at an arbitrary timing according to a sequence defined by the test program.
  • the multi-strobe circuit 10 receives signals under test S1L and S1H and a strobe signal STRB.
  • the multi-strobe circuit 10 is divided into two blocks for evaluating each of the signals under test S1L and S1H using the multi-strobe signal.
  • the blocks that process the signal under test S1L are marked with “L”, and the blocks that process the signal under test S1H are marked with “H”.
  • the configuration of the signal under test S1L will be described in detail using a block as an example. In the description, the subscript “L” is omitted.
  • the multi-strobe circuit 10 latches the signal under test to be evaluated at the timing of each edge of the multi-strobe signal having a plurality of edges, and evaluates the value at each timing.
  • the multi-strobe circuit 10 includes a first delay circuit 12, a second delay circuit 14, a latch circuit 16, a logic operation unit 18, and a delay amount adjustment unit 20.
  • the first delay circuit 12 includes N (N is a natural number) first delay elements D1 1 to D1 N (collectively referred to as first delay elements D1) cascaded in multiple stages.
  • the first delay element D1 1 of the first stage under test signals S1L from the level comparator 40 is input.
  • the second delay circuit 14 includes N second delay elements D2 1 to D2 N (collectively referred to as second delay elements D2) cascaded in multiple stages.
  • the second delay elements D2 1 to D2 N are provided for each of the N first delay elements D1 1 to D1 N.
  • the reference strobe signal STRB generated by the timing generator 30 is input to the first delay element D21 at the first stage via the third delay element D3.
  • the strobe signal STRB includes the second delay element ST21.
  • the i-th strobe signal STRB i delayed by i ⁇ (Tpd + ⁇ t) with respect to the reference strobe signal STRB is output from the i- th second delay element D2.
  • FIG. 3 is a circuit diagram showing a configuration example of the variable delay circuit 50 that can be used as the first delay element and the second delay element.
  • the variable delay circuit 50 includes a buffer 52, a plurality of m (m is a natural number) capacitors C1 to Cm, and a plurality of switches SW1 to SWm provided for the plurality of capacitors C1 to Cm.
  • the capacitance values of the plurality of capacitors C1 to Cm are weighted with binary numbers.
  • the i (1 ⁇ ) -th capacity value is expressed as 2 m ⁇ 1 C.
  • the i-th capacitor Ci and the i-th switch SWi are connected in series between the output terminal of the buffer 52 and a fixed voltage terminal (ground terminal).
  • the capacitor Ci corresponding to the switch SWi is connected to the output terminal of the buffer 52. That is, the time constant increases, the change speed of the waveform of the signal output to the subsequent stage becomes slow, and as a result, the delay amount increases.
  • the delay amount can be switched in 2 m steps.
  • variable delay circuit 50 in FIG. 3 can switch the delay amount stepwise with high resolution by reducing the unit capacitance C.
  • the variable delay circuit can be configured with a plurality of inverters cascaded in series.
  • a variable delay circuit can be configured by providing a tap at the output of the inverter of each stage and providing a selector for selecting signals from a plurality of taps.
  • a variable delay circuit may be realized by configuring the bias voltage and bias current of the inverter and the buffer so as to be adjustable in multiple stages.
  • the latch circuit 16 includes N latch elements L 1 to L N (collectively referred to as latch elements L). N latch elements L are provided for each of the N first delay elements D1 1 to D1 N and the second delay elements D2 1 to D2 N.
  • the i-th (i is a natural number satisfying 1 ⁇ i ⁇ N) -th latch element L i is the output signal of the corresponding i-th first delay element D1 i at the edge timing of the corresponding i-phase strobe signal STRBi.
  • S1 i is latched.
  • Output signals SL 1 to SL N of the N latch elements L are input to the logic operation unit 18.
  • the logical operation unit 18 performs predetermined signal processing according to the evaluation items of the DUT 110.
  • the output signals SL 1 to SL N are thermometer codes in which 0 and 1 change at a certain bit. Therefore, the logical operation unit 18 may include a priority encoder that generates data indicating the position of the bit where the values of the output signals SL 1 to SL N change.
  • the delay amount adjusting unit 20 is configured to include at least one of N first delay elements D1 1 to D1 N and N second delay elements D2 1 to D2 N. Perform a calibration process to adjust the delay amount. The relative amounts of the first delay amount ⁇ 1 and the second delay amount ⁇ 2 of all the stages are adjusted by the delay amount adjusting unit 20, and the edge timings of the multi-strobe signals STRB 1 to STRB N are set to desired positions. .
  • this calibration process will be described.
  • FIG. 4 is a flowchart showing the calibration procedure of the multi-strobe circuit 10.
  • the delay amount adjusting unit 20 first initializes the first delay amount ⁇ 1 and the second delay amount ⁇ 2 of all stages (S100). When both the first delay element D1 and the second delay element D2 are configured as variable delay elements, the delay amounts of all the delay elements D1 and D2 are set to a settable minimum value.
  • the zero adjustment step is repeated while i (i is a natural number) is incremented by 1 from 1 to N (S102).
  • the zero adjustment step (S104) is performed so that the timing of the edge of the signal under test S1 i input to the i- th stage latch element Li matches the edge timing of the i-phase strobe signal STRB i . 1 to adjust the delay amount .tau.1 i of the delay element D1 i, at least one of the delay amount of the delay amount .tau.2 i of the second delay element D2 i.
  • the zero adjustment step S104 can be executed as follows. That is, when the edge timing of the signal under test S1 i input to the i-th latch element L i is earlier than the edge timing of the strobe signal STRB i , the delay amount of the i- th first delay element D1 i Increase ⁇ 1 i by the minimum width. Conversely, when the edge timing of the signal under test S1 i is later than the edge timing of the strobe signal STRB i , the delay amount ⁇ 2 i of the i- th second delay element D2 i is increased. If this process is repeated, the convergence is made so that the timing of the edge of the signal under test S1 i and the edge of the strobe signal STRB i coincide.
  • the zero adjustment step S104 may include the following steps A to D.
  • Step A The relative delay amount TR of the i- th first delay element D1 i and the second delay element D2 i is changed stepwise. For example, consider the case where the signal under test S1 i transitions from a low level (first level) to a high level (second level). At this time, when the strobe signal STRB i is located before the signal under test S1 i transits to the high level and is stable at the low level, the output signal (latch) of the i-th latch element Li Data LD i ) is determined at the first level (low level).
  • FIG. 5 is a time chart showing the relationship between the timing of the strobe signal STRB i and the signal under test S1 i and the latch data LD i .
  • the state in which the latch data LD i is indefinite is indicated by “X”.
  • Step B In the process of step A, the relative delay amount TR when the latch data LD i is fixed at the first level (for example, low level) is acquired as the first relative delay amount TR1.
  • Step C In the process of Step A, the relative delay amount TR when the latch data LD i is fixed at the second level (for example, high level) is acquired as the second relative delay amount TR2.
  • Step D The relative delay amount TR between the i- th first delay element D1 i and the second delay element D2 i is set to a value between the first relative delay amount TR1 and the second relative delay amount TR2.
  • the midpoint TRc of the first relative delay amount TR1 and the second relative delay amount TR2 may be selected.
  • the first relative delay amount TR1 or the second relative delay amount TR2 may be selected.
  • the resolution setting step S106 is executed.
  • the delay amount adjusting unit 20 changes the delay amounts of all the stages of at least one of the first delay element D1 and the second delay element D2 by a predetermined amount ⁇ t. For example, the delay amounts ⁇ 2 1 to ⁇ 2 N of all stages of the second delay element D2 may be increased by ⁇ t.
  • FIGS. 6A and 6B are time charts showing the timing relationship between the strobe signal and the signal under test when the calibration according to the embodiment is not performed.
  • the timings of the i-phase strobe signal STRB i and the i-phase signal under test S1 i will match.
  • the strobe signals STRB 1 to STRB N of each phase are set to ideal timing.
  • the delay amount of the first delay element D1 and the second delay element D2 may deviate from the design value due to the influence of process variations, power supply voltage fluctuations, and temperature fluctuations. Is done. Even if the delay amounts of the first delay element D1 and the second delay element D2 increase or decrease by ⁇ t1 and ⁇ t2 with respect to the design value Tpd, respectively, if they are integrated on the same semiconductor substrate, both delays Since the amounts vary following each other, ⁇ t1 ⁇ t2. That is, in the stage of step 1 before setting the resolution, the timings of the i-phase strobe signal STRB i and the i-phase signal under test S1 i substantially coincide.
  • FIGS. 7A and 7B are time charts showing how the multi-strobe circuit 10 shown in FIG. 2 is calibrated.
  • FIG. 7A shows a zero adjustment step
  • FIG. 7B shows a resolution setting step.
  • the delay amount ⁇ 2 of the second delay element D2 is increased or decreased while the delay amount ⁇ 1 of the first delay element D1 is fixed, and the strobe signal STRB i The case where the timing of the test signal S1 i is aligned is illustrated.
  • the present invention is not limited to this, and while the delay amount ⁇ 2 of the second delay element D2 is fixed, the delay amount ⁇ 1 of the first delay element D1 is increased or decreased, and the strobe signal STRB i and the signal under test S1 i are increased.
  • the timing may be aligned.
  • the initial delay of the first delay element D1 and the second delay element D2 is minimized, and the edge timing of the signal under test S1 i is earlier than the edge timing of the strobe signal STRB i.
  • the delay amount ⁇ 1 i of the first delay element D1 i is increased, and conversely, when the edge timing of the signal under test S1 i is later than the edge timing of the strobe signal STRB i , the second delay element D2 i
  • the delay amount ⁇ 2 i may be increased. In this case, since the calibration can be performed in a state where the delay amount ⁇ 2 of the first delay element D1 and the delay amount ⁇ 2 of the second delay element D2 are minimized, it is possible to suppress the influence of variations in the delay amount on the resolution.
  • each phase As shown in FIG. 7B, the delay amount ⁇ 2 of the second delay element D2 increases by a predetermined amount ⁇ t, and the strobe signal STRB is timed with respect to the signal under test S1. Will be late. Since each phase (each stage) is delayed by ⁇ t, the phase difference between the i- th signal under test S1 i and the strobe signal STRB i is given by i ⁇ ⁇ t.
  • the multi-strobe circuit 10 it is possible to preferably cancel the variation in the delay amount of the delay element, and as a result, the signal under test S1 is generated by the highly accurate multi-strobe signals STRB 1 to STRB N. Can be evaluated.
  • SYMBOLS 10 Multi-strobe circuit, 12 ... 1st delay circuit, 14 ... 2nd delay circuit, 16 ... Latch circuit, 18 ... Logic operation part, 20 ... Delay amount adjustment part, 30 ... Timing generator, 40 ... Level comparator, 42 DESCRIPTION OF SYMBOLS 1st comparator, 44 ... 2nd comparator, D1 ... 1st delay element, D2 ... 2nd delay element, L ... Latch element, 100 ... Test apparatus, 110 ... DUT, S1 ... Signal under test.
  • the present invention can be used for a test apparatus.

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Abstract

N-pieces (N is a natural number) of first delay elements (D1) are multi-stage connected and delay a tested signal (S1) on a per-stage basis.  N-pieces of second delay elements (D2) are multi-stage connected and delay a reference strobe signal (STRB) on a per-stage basis to generate multi-strobe signals (STRB1 to STRBN).  A latch element (Li) at the i-th stage latches the tested signal (S1i) at the timing of the strobe signal (STRBi).  During a calibration period, a delay amount adjustment unit (20), while incrementing i ( i is a natural number) from 1 to N, adjusts the delay amount of at least one of the first delay element (D1i) and the second delay element (D2i) at the i-th stage so that the edge timing of the tested signal (S1i) and the strobe signal (STRBi), which are input to the latch element (Li) at the i-th stage, coincide with each other.  Subsequently, the delay amount adjustment unit (20) changes the delay amounts of all stages of at least one of the first delay elements (D1) and the second delay elements (D2) by a predetermined amount.

Description

マルチストローブ回路およびそのキャリブレーション方法およびそれを用いた試験装置Multi-strobe circuit, calibration method thereof, and test apparatus using the same
　本発明は、多相のストローブ信号（マルチストローブ信号）を生成し、評価対象の信号のレベルをマルチストローブ信号の複数のエッジのタイミングで評価するマルチストローブ回路に関する。 The present invention relates to a multi-strobe circuit that generates a multi-phase strobe signal (multi-strobe signal) and evaluates the level of a signal to be evaluated at timings of a plurality of edges of the multi-strobe signal.
　メモリやＤＳＰ（Digital Signal Processor）をはじめとする半導体デバイスを試験する試験装置にマルチストローブ回路が利用される。マルチストローブ回路は、半導体デバイスから出力される被試験信号（たとえば２値のデジタル信号）の１サイクル期間内に、複数のエッジを有するマルチストローブ信号（多相ストローブ信号ともいう）を発生し、各エッジのタイミングにおいて半導体デバイスから出力される信号のレベルを判定する。マルチストローブ回路を利用することにより、半導体デバイスから出力される信号のレベル遷移のタイミング（変化点）の検出等が可能となり、半導体デバイスの評価に利用することができる。 Multi-strobe circuits are used in test equipment for testing semiconductor devices such as memory and DSP (Digital Signal Processor). The multi-strobe circuit generates a multi-strobe signal (also referred to as a multi-phase strobe signal) having a plurality of edges within one cycle period of a signal under test (for example, a binary digital signal) output from a semiconductor device. The level of the signal output from the semiconductor device is determined at the edge timing. By using the multi-strobe circuit, it becomes possible to detect the level transition timing (change point) of the signal output from the semiconductor device, and to use it for the evaluation of the semiconductor device.
　図１は、マルチストローブ回路３００の構成例を示す回路図である。Ｎ個の第１遅延素子Ｄ１１～Ｄ１Ｎ（第１遅延素子Ｄ１と総称される）は、多段にカスケード接続されている。１段目の第１遅延素子Ｄ１１にはＤＵＴから出力される被試験信号Ｓ１が入力され、被試験信号Ｓ１には第１遅延素子Ｄ１を１段経るごとに、所定の遅延Ｔｐｄが与えられる。つまりｉ段目の第１遅延素子Ｄ１ｉからは、ＤＵＴから出力される被試験信号Ｓ１に対して、ｉ×Ｔｐｄだけ遅延した被試験信号Ｓ１ｉが出力される。 FIG. 1 is a circuit diagram showing a configuration example of the multi-strobe circuit 300. N first delay elements D1 1 to D1 N (collectively referred to as first delay elements D1) are cascade-connected in multiple stages. The first delay element D1 1 of the first stage is input under test signal S1 outputted from the DUT, the DUT signal S1 each time through the first delay element D1 1 stage, given the predetermined delay Tpd . That is, the i-th first delay element D1 i outputs the signal under test S1 i delayed by i × Tpd with respect to the signal under test S1 output from the DUT.
　Ｎ個の第２遅延素子Ｄ２１～Ｄ２Ｎ（第２遅延素子Ｄ２と総称される）はそれぞれ、Ｎ個の第１遅延素子Ｄ１１～Ｄ１Ｎごとに設けられ、多段にカスケード接続されている。１段目の第２遅延素子Ｄ２１には、基準となるストローブ信号ＳＴＲＢが入力される。ストローブ信号ＳＴＲＢには、第２遅延素子Ｄ２を１段経るごとに、所定の遅延（Ｔｐｄ＋Δｔ）の遅延が与えられる。ｉ段目の第２遅延素子Ｄ２からは、基準ストローブ信号ＳＴＲＢに対して、ｉ×（Ｔｐｄ＋Δｔ）だけ遅延したｉ相目のストローブ信号ＳＴＲＢｉが出力される。 N second delay elements D2 1 to D2 N (collectively referred to as second delay elements D2) are provided for each of the N first delay elements D1 1 to D1 N and cascaded in multiple stages. . The first stage second delay element D2 1 of the strobe signal STRB to be a reference are input. The strobe signal STRB is given a predetermined delay (Tpd + Δt) every time one stage passes through the second delay element D2. The i-th strobe signal STRB i delayed by i × (Tpd + Δt) with respect to the reference strobe signal STRB is output from the i- th second delay element D2.
　Ｎ個のラッチ素子Ｌ１～ＬＮ（ラッチ素子Ｌと総称される）もまた、Ｎ個の第１遅延素子Ｄ１１～Ｄ１Ｎごとに設けられる。ｉ（ｉは１≦ｉ≦Ｎを満たす自然数）番目のラッチ素子Ｌｉは、ｉ相目のストローブ信号ＳＴＲＢｉのエッジのタイミングで、ｉ番目の第１遅延素子Ｄ１ｉの出力信号をラッチする。なお図２においてＤフリップフロップで示されるラッチ素子Ｌ１は、その他のフリップフロップやラッチ回路など、さまざまな素子で代替可能であることはいうまでもない。Ｎ個のラッチ素子Ｌの出力信号ＳＬ１～ＳＬＮは、論理演算部３１０へと入力される。論理演算部３１０は、ＤＵＴの評価事項に応じた所定の信号処理を行う。被試験信号Ｓ１がある点を境に０から１（または１から０）に遷移するとき、出力信号ＳＬ１～ＳＬＮはあるビットを境に０と１が変化するサーモメータコードとなる。したがって論理演算部３１０は、プライオリティエンコーダを含んでいる。 N latch elements L 1 to L N (collectively referred to as latch elements L) are also provided for each of the N first delay elements D1 1 to D1 N. The i (i is a natural number satisfying 1 ≦ i ≦ N) -th latch element L i latches the output signal of the i-th first delay element D1 i at the timing of the edge of the i-phase strobe signal STRBi. Needless to say, the latch element L1 indicated by the D flip-flop in FIG. 2 can be replaced by various elements such as other flip-flops and latch circuits. Output signals SL 1 to SL N of the N latch elements L are input to the logic operation unit 310. The logical operation unit 310 performs predetermined signal processing according to the evaluation items of the DUT. When the signal under test S1 transitions from 0 to 1 (or 1 to 0) at a certain point, the output signals SL 1 to SL N are thermometer codes in which 0 and 1 change at a certain bit. Therefore, the logical operation unit 310 includes a priority encoder.
　Ｎ個の第２遅延素子Ｄ２の前段に設けられた第３遅延素子Ｄ３によって、第１遅延素子Ｄ１に入力される被試験信号Ｓ１と、第２遅延素子Ｄ２に入力されるストローブ信号ＳＴＲＢの位相差（タイミング）が調整される。 By means of a third delay element D3 provided in front of the N second delay elements D2, the levels of the signal under test S1 input to the first delay element D1 and the strobe signal STRB input to the second delay element D2 The phase difference (timing) is adjusted.
　第１遅延素子Ｄ１、第２遅延素子Ｄ２を１段通過するごとに、被試験信号Ｓ１とストローブ信号ＳＴＲＢの相対的な時間差は、Δｔだけ変化する。つまり、被試験信号Ｓ１は、互いにΔｔだけ位相がシフトしたＮ個のストローブ信号（マルチストローブ信号）ＳＴＲＢ１～ＳＴＲＢＮのタイミングでその値が判定される。以上がマルチストローブ回路３００の構成の概要とその動作である。 Each time the signal passes through the first delay element D1 and the second delay element D2, the relative time difference between the signal under test S1 and the strobe signal STRB changes by Δt. That is, the value of the signal under test S1 is determined at the timing of N strobe signals (multi-strobe signals) STRB 1 to STRB N whose phases are shifted from each other by Δt. The above is the outline of the configuration of the multi-strobe circuit 300 and its operation.
　このようなマルチストローブ回路３００において、第１遅延素子Ｄ１、第２遅延素子Ｄ２の遅延量が変動すると、被試験信号Ｓ１とマルチストローブ信号ＳＴＲＢ１～ＳＴＲＢＮのタイミング精度が悪化してしまう。特に分解能Δｔが小さければ小さいほど、第１遅延素子Ｄ１、第２遅延素子Ｄ２の遅延量ばらつきの影響は顕著となる。 In such a multi-strobe circuit 300, if the delay amounts of the first delay element D1 and the second delay element D2 vary, the timing accuracy of the signal under test S1 and the multi-strobe signals STRB 1 to STRB N will deteriorate. In particular, as the resolution Δt is smaller, the influence of the delay amount variation of the first delay element D1 and the second delay element D2 becomes more significant.
　本発明はこうした課題に鑑みてなされたものであり、そのある態様の例示的な目的のひとつは、キャリブレーションが可能なマルチストローブ回路およびキャリブレーション方法の提供にある。 The present invention has been made in view of such problems, and one of exemplary purposes of an aspect thereof is to provide a multi-strobe circuit and a calibration method capable of calibration.
　本発明のある態様は、複数のエッジを有するマルチストローブ信号のそれぞれエッジのタイミングで、評価対象の被試験信号をラッチするマルチストローブ回路に関する。このマルチストローブ回路は、Ｎ個（Ｎは自然数）の第１遅延素子が多段接続されて構成され、被試験信号に対し１段ごとに遅延を与え、複数の被試験信号を生成する第１遅延回路と、Ｎ個の第１遅延素子ごとに設けられたＮ個の第２遅延素子が多段接続されて構成され、基準となるストローブ信号に対し１段ごとに遅延を与え、複数のストローブ信号を生成する第２遅延回路と、Ｎ個の第１遅延素子ごとに設けられたＮ個のラッチ素子を含み、ｉ段目のラッチ素子は、ｉ段目の第１遅延素子から出力される被試験信号を、ｉ段目の第２遅延素子から出力されるストローブ信号のタイミングでラッチするように構成されたラッチ回路と、Ｎ個の第１遅延素子とＮ個の第２遅延素子の少なくとも一方の遅延量を調節する遅延量調節部と、を備える。遅延量調節部は、キャリブレーション時に、ｉ（ｉは自然数）を１からＮまでインクリメントしながら、ｉ段目のラッチ素子に入力される被試験信号とストローブ信号のエッジのタイミングが一致するように、ｉ段目の第１遅延素子と第２遅延素子の少なくとも一方の遅延量を調節するゼロアジャストステップと、第１遅延素子および第２遅延素子の少なくとも一方のすべてのステージの遅延量を、所定量だけ変化させる分解能設定ステップと、を実行する。 An aspect of the present invention relates to a multi-strobe circuit that latches a signal under test to be evaluated at each edge timing of a multi-strobe signal having a plurality of edges. This multi-strobe circuit is configured by connecting N (N is a natural number) first delay elements in multiple stages, and delays each stage of the signal under test to generate a plurality of signals under test. A circuit and N second delay elements provided for each of the N first delay elements are connected in multiple stages, and a delay is provided for each stage with respect to a reference strobe signal. A second delay circuit to be generated; and N latch elements provided for each of the N first delay elements. The i-th latch element is output from the i-th first delay element. A latch circuit configured to latch the signal at the timing of the strobe signal output from the i-th second delay element, and at least one of the N first delay elements and the N second delay elements A delay amount adjusting unit for adjusting the delay amount; . The delay amount adjusting unit increments i (i is a natural number) from 1 to N during calibration so that the edge timing of the signal under test input to the i-th latch element and the strobe signal coincide with each other. , A zero adjustment step for adjusting a delay amount of at least one of the first delay element and the second delay element in the i-th stage, and delay amounts of all stages of at least one of the first delay element and the second delay element, And a resolution setting step for changing only a fixed amount.
　この態様によると、１段目から順番に、各相（ステージ）の第１遅延素子と第２遅延素子の遅延量のばらつきをキャンセルしていき、その後、分解能に応じた遅延量を第２遅延素子に付加することにより、マルチストローブ回路を高精度にキャリブレートできる。 According to this aspect, the delay amount variation between the first delay element and the second delay element in each phase (stage) is canceled in order from the first stage, and then the delay amount corresponding to the resolution is set to the second delay. By adding to the element, the multi-strobe circuit can be calibrated with high accuracy.
　Ｎ個の第１遅延素子およびＮ個の第２遅延素子は可変遅延素子であってもよい。遅延量調節部は、Ｎ個の第１遅延素子および第２遅延素子の遅延量を最小に設定した状態を初期状態として、ゼロアジャストステップを実行してもよい。ゼロアジャストステップにおいて、ｉ段目のラッチ素子に入力される被試験信号のエッジのタイミングがストローブ信号のエッジのタイミングより早いとき、ｉ段目の第１遅延素子の遅延量を増加させ、ｉ段目のラッチ素子に入力される被試験信号のエッジのタイミングがストローブ信号のエッジのタイミングより遅いとき、ｉ段目の第２遅延素子の遅延量を増加させてもよい。
　この場合、第１遅延素子および第２遅延素子の初期値を調整幅のセンターに設定してからキャリブレーションを行う場合に比べて、ある段における遅延のばらつきが後段に及ぼす影響を低減できる。 The N first delay elements and the N second delay elements may be variable delay elements. The delay amount adjusting unit may execute the zero adjustment step by setting a state in which the delay amounts of the N first delay elements and the second delay elements are set to a minimum as an initial state. In the zero adjustment step, when the edge timing of the signal under test input to the i-th latch element is earlier than the edge timing of the strobe signal, the delay amount of the i-th first delay element is increased, When the edge timing of the signal under test input to the second latch element is later than the edge timing of the strobe signal, the delay amount of the i-th second delay element may be increased.
In this case, compared to the case where the calibration is performed after setting the initial values of the first delay element and the second delay element to the center of the adjustment width, the influence of the delay variation at a certain stage on the subsequent stage can be reduced.
　遅延量調節部は、ゼロアジャストステップにおいて、ｉ段目の調整を行う際に以下の処理を行ってもよい。
（１）　ｉ段目の第１遅延素子および第２遅延素子の相対的な遅延量を段階的に変化させる。
（２）　（１）の過程において、ｉ段目のラッチ素子によりラッチされた値が、第１のレベルに確定するときの相対的な遅延量を第１相対遅延量として取得する。
（３）　（１）の過程において、ｉ段目のラッチ素子によりラッチされた値が、第１のレベルと相補的な第２のレベルに確定するときの相対的な遅延量を第２相対遅延量として取得する。
（４）　ｉ段目の第１遅延素子および第２遅延素子の相対的な遅延量を、第１相対遅延量と第２相対遅延量の間の値に設定する。
　なお、（４）において、第１遅延素子および第２遅延素子の相対的な遅延量は、第１相対遅延量と第２相対遅延量の中点としてもよい。 The delay amount adjustment unit may perform the following processing when performing the i-th adjustment in the zero adjustment step.
(1) The relative delay amount of the i-th first delay element and the second delay element is changed stepwise.
(2) In the process of (1), the relative delay amount when the value latched by the i-th latch element is fixed at the first level is acquired as the first relative delay amount.
(3) In the process of (1), the relative delay amount when the value latched by the i-th latch element is determined to be a second level complementary to the first level is defined as a second relative delay. Get as a quantity.
(4) The relative delay amount of the i-th first delay element and the second delay element is set to a value between the first relative delay amount and the second relative delay amount.
In (4), the relative delay amount between the first delay element and the second delay element may be the midpoint between the first relative delay amount and the second relative delay amount.
　本発明の別の態様は、試験装置である。この試験装置は、被試験デバイスから出力される信号をしきい値電圧と比較するコンパレータと、任意のタイミングでレベルが遷移するストローブ信号を生成するタイミング発生器と、ストローブ信号と、被試験信号としてのコンパレータの出力信号と、を受ける上述のいずれかのマルチストローブ回路と、を備える。 Another aspect of the present invention is a test apparatus. This test apparatus includes a comparator that compares a signal output from a device under test with a threshold voltage, a timing generator that generates a strobe signal whose level transitions at an arbitrary timing, a strobe signal, and a signal under test. And any one of the multi-strobe circuits described above that receives the output signal of the comparator.
　本発明のさらに別の態様は、複数のエッジを有するマルチストローブ信号のそれぞれエッジのタイミングで、評価対象の被試験信号をラッチするマルチストローブ回路のキャリブレーション方法に関する。マルチストローブ回路は、Ｎ個（Ｎは自然数）の第１遅延素子が多段接続されて構成され、被試験信号に対し１段ごとに遅延を与え、複数の被試験信号を生成する第１遅延回路と、Ｎ個の第１遅延素子ごとに設けられたＮ個の第２遅延素子が多段接続されて構成され、基準となるストローブ信号に対し１段ごとに遅延を与え、複数のストローブ信号を生成する第２遅延回路と、Ｎ個の第１遅延素子ごとに設けられたＮ個のラッチ素子を含み、ｉ段目のラッチ素子は、ｉ段目の第１遅延素子から出力される被試験信号を、ｉ段目の第２遅延素子から出力されるストローブ信号のタイミングでラッチするように構成されたラッチ回路と、を備える。当該キャリブレーション方法は、ｉ（ｉは自然数）を１からＮまでインクリメントしながら、ｉ段目のラッチ素子に入力される被試験信号とストローブ信号のエッジのタイミングが一致するように、ｉ段目の第１遅延素子と第２遅延素子の少なくとも一方の遅延量を調節するゼロアジャストステップと、第１遅延素子および第２遅延素子の少なくとも一方のすべてのステージの遅延量を、所定量だけ変化させる分解能設定ステップと、を備える。 Still another aspect of the present invention relates to a multi-strobe circuit calibration method for latching a signal under test to be evaluated at each edge timing of a multi-strobe signal having a plurality of edges. The multi-strobe circuit is configured by connecting N (N is a natural number) first delay elements in multiple stages, and delays each stage of the signal under test to generate a plurality of signals under test. And N second delay elements provided for each of the N first delay elements are connected in multiple stages, and a plurality of strobe signals are generated by delaying the reference strobe signal for each stage. The i-th latch element is a signal under test output from the i-th first delay element. Is latched at the timing of the strobe signal output from the i-th second delay element. In this calibration method, i (i is a natural number) is incremented from 1 to N so that the timing of the edge of the signal under test inputted to the i-th latch element and the strobe signal coincide with each other. A zero adjustment step for adjusting a delay amount of at least one of the first delay element and the second delay element, and a delay amount of at least one of the first delay element and the second delay element is changed by a predetermined amount. A resolution setting step.
　Ｎ個の第１遅延素子およびＮ個の第２遅延素子は可変遅延素子であってもよい。この場合、キャリブレーション方法は、Ｎ個の第１遅延素子および第２遅延素子の遅延量を最小に設定した状態を初期状態として、ゼロアジャストステップを実行し、ゼロアジャストステップにおいて、ｉ段目のラッチ素子に入力される被試験信号のエッジのタイミングがストローブ信号のエッジのタイミングより早いとき、ｉ段目の第１遅延素子の遅延量を増加させ、ｉ段目のラッチ素子に入力される被試験信号のエッジのタイミングがストローブ信号のエッジのタイミングより遅いとき、ｉ段目の第２遅延素子の遅延量を増加させてもよい。 The N first delay elements and the N second delay elements may be variable delay elements. In this case, the calibration method executes the zero adjustment step with the state in which the delay amounts of the N first delay elements and the second delay elements are set to the minimum as the initial state. In the zero adjustment step, When the edge timing of the signal under test input to the latch element is earlier than the edge timing of the strobe signal, the delay amount of the i-th first delay element is increased and the signal input to the i-th latch element is increased. When the edge timing of the test signal is later than the edge timing of the strobe signal, the delay amount of the i-th second delay element may be increased.
　ゼロアジャストステップにおいて、ｉ段目の調整を行う際に、ｉ段目の第１遅延素子および第２遅延素子の相対的な遅延量を段階的に変化させながら、ｉ段目のラッチ素子に保持される値が第１のレベルに確定するときの相対的な遅延量を第１相対遅延量として、ｉ段目のラッチ素子によりラッチされた値が第１のレベルと相補的な第２のレベルに確定するときの相対的な遅延量を第２相対遅延量として取得し、ｉ段目の第１遅延素子および第２遅延素子の相対的な遅延量を、第１相対遅延量と第２相対遅延量の間の値に設定してもよい。 In the zero adjustment step, when the i-th adjustment is performed, the relative delay amount of the i-th first delay element and the second delay element is changed stepwise and held in the i-th latch element. A relative delay amount when the value to be determined is determined to be the first level is defined as a first relative delay amount, and a value latched by the i-th latch element is complementary to the first level. Is obtained as the second relative delay amount, and the relative delay amounts of the i-th first delay element and the second delay element are determined as the first relative delay amount and the second relative delay amount. A value between the delay amounts may be set.
　なお、以上の構成要素の任意の組み合わせや本発明の構成要素や表現を、方法、装置などの間で相互に置換したものもまた、本発明の態様として有効である。 It should be noted that an arbitrary combination of the above-described constituent elements and those in which constituent elements and expressions of the present invention are mutually replaced between methods and apparatuses are also effective as an aspect of the present invention.
　本発明によれば、時間的に高精度なマルチストローブ回路が提供される。 According to the present invention, a multi-strobe circuit that is highly accurate in time is provided.
マルチストローブ回路の構成例を示す回路図である。It is a circuit diagram which shows the structural example of a multi-strobe circuit. 実施の形態に係るマルチストローブ回路を備える試験装置の構成を示すブロック図である。It is a block diagram which shows the structure of the test apparatus provided with the multi-strobe circuit which concerns on embodiment. 第１遅延素子および第２遅延素子として利用可能な可変遅延回路の構成例を示す回路図である。It is a circuit diagram which shows the structural example of the variable delay circuit which can be utilized as a 1st delay element and a 2nd delay element. マルチストローブ回路のキャリブレーションの手順を示すフローチャートである。It is a flowchart which shows the procedure of the calibration of a multi-strobe circuit. ストローブ信号ＳＴＲＢｉと被試験信号Ｓ１ｉのタイミングと、ラッチデータＬＤｉの関係を示すタイムチャートである。4 is a time chart showing the relationship between the timing of a strobe signal STRBi and a signal under test S1i and latch data LDi. 図６（ａ）、（ｂ）は、実施の形態に係るキャリブレーションを行わない場合のストローブ信号と被試験信号のタイミング関係を示すタイムチャートである。FIGS. 6A and 6B are time charts showing the timing relationship between the strobe signal and the signal under test when the calibration according to the embodiment is not performed. 図７（ａ）、（ｂ）は、図２のマルチストローブ回路のキャリブレーションの様子を示すタイムチャートである。FIGS. 7A and 7B are time charts showing how the multi-strobe circuit of FIG. 2 is calibrated.
　以下、本発明を好適な実施の形態をもとに図面を参照しながら説明する。各図面に示される同一または同等の構成要素、部材、処理には、同一の符号を付するものとし、適宜重複した説明は省略する。また、実施の形態は、発明を限定するものではなく例示であって、実施の形態に記述されるすべての特徴やその組み合わせは、必ずしも発明の本質的なものであるとは限らない。 Hereinafter, the present invention will be described based on preferred embodiments with reference to the drawings. The same or equivalent components, members, and processes shown in the drawings are denoted by the same reference numerals, and repeated descriptions are omitted as appropriate. The embodiments do not limit the invention but are exemplifications, and all features and combinations thereof described in the embodiments are not necessarily essential to the invention.
　本明細書において、「部材Ａが、部材Ｂと接続」された状態とは、部材Ａと部材Ｂが物理的に直接的に接続される場合や、部材Ａと部材Ｂが、電気的な接続状態に影響を及ぼさない他の部材を介して間接的に接続される場合も含む。同様に、「部材Ｃが、部材Ａと部材Ｂの間に設けられた状態」とは、部材Ａと部材Ｃ、あるいは部材Ｂと部材Ｃが直接的に接続される場合のほか、電気的な接続状態に影響を及ぼさない他の部材を介して間接的に接続される場合も含む。 In this specification, “the member A is connected to the member B” means that the member A and the member B are physically directly connected, or the member A and the member B are electrically connected. The case where it is indirectly connected through another member that does not affect the state is also included. Similarly, “the state in which the member C is provided between the member A and the member B” refers to the case where the member A and the member C or the member B and the member C are directly connected, as well as an electrical condition. It includes the case of being indirectly connected through another member that does not affect the connection state.
　図２は、実施の形態に係るマルチストローブ回路１０を備える試験装置１００の構成を示すブロック図である。試験装置１００は、メモリやＤＳＰ、その他のデジタル回路などの被試験デバイス（ＤＵＴ）１１０から出力される被試験信号Ｓ１を受け、所定の試験を実行する。 FIG. 2 is a block diagram illustrating a configuration of the test apparatus 100 including the multi-strobe circuit 10 according to the embodiment. The test apparatus 100 receives a signal under test S1 output from a device under test (DUT) 110 such as a memory, DSP, or other digital circuit, and executes a predetermined test.
　試験装置１００は、マルチストローブ回路１０に加えて、タイミング発生器３０、レベルコンパレータ４０を備える。レベルコンパレータ４０は、第１コンパレータ４２、第２コンパレータ４４を含む。第１コンパレータ４２は、ＤＵＴ１１０から出力される被試験信号Ｓ１の電位をローレベルのしきい値電圧ＶＯＬと比較し、比較結果に応じてハイレベルとローレベルが変化する被試験信号Ｓ１Ｌを生成する。第２コンパレータ４４は被試験信号Ｓ１の電位をハイレベルのしきい値電圧ＶＯＨと比較し、比較結果に応じた被試験信号Ｓ１Ｈを生成する。なお、最も簡易には、レベルコンパレータ４０は被試験信号Ｓ１の電位を単一のしきい値電圧と比較するコンパレータ、もしくは単なるインバータ（バッファ）でも構成可能である。 The test apparatus 100 includes a timing generator 30 and a level comparator 40 in addition to the multi-strobe circuit 10. The level comparator 40 includes a first comparator 42 and a second comparator 44. The first comparator 42 compares the potential of the signal under test S1 output from the DUT 110 with a low level threshold voltage VOL, and generates a signal under test S1L whose high level and low level change according to the comparison result. . The second comparator 44 compares the potential of the signal under test S1 with a high level threshold voltage VOH, and generates a signal under test S1H according to the comparison result. In the simplest case, the level comparator 40 can be constituted by a comparator for comparing the potential of the signal under test S1 with a single threshold voltage, or a simple inverter (buffer).
　タイミング発生器３０は、テストプログラムで規定されるシーケンスに応じた任意のタイミングでレベルが遷移する（つまりエッジを有する）ストローブ信号ＳＴＲＢを生成する。 The timing generator 30 generates a strobe signal STRB whose level transitions (that is, has an edge) at an arbitrary timing according to a sequence defined by the test program.
　マルチストローブ回路１０は、被試験信号Ｓ１Ｌ、Ｓ１Ｈおよびストローブ信号ＳＴＲＢを受ける。マルチストローブ回路１０は、被試験信号Ｓ１Ｌ、Ｓ１Ｈそれぞれをマルチストローブ信号を利用して評価する２つのブロックに分かれている。被試験信号Ｓ１Ｌを処理するブロックには、”Ｌ”を、被試験信号Ｓ１Ｈを処理するブロックには”Ｈ”が付されており、両者の構成は同一である。以下では、被試験信号Ｓ１Ｌを処理するブロックを例に、その構成を詳細に説明する。また説明に際しては、添え字”Ｌ”は省略する。 The multi-strobe circuit 10 receives signals under test S1L and S1H and a strobe signal STRB. The multi-strobe circuit 10 is divided into two blocks for evaluating each of the signals under test S1L and S1H using the multi-strobe signal. The blocks that process the signal under test S1L are marked with “L”, and the blocks that process the signal under test S1H are marked with “H”. In the following, the configuration of the signal under test S1L will be described in detail using a block as an example. In the description, the subscript “L” is omitted.
　マルチストローブ回路１０は、複数のエッジを有するマルチストローブ信号のそれぞれのエッジのタイミングで、評価対象の被試験信号をラッチして各タイミングにおける値を評価する。 The multi-strobe circuit 10 latches the signal under test to be evaluated at the timing of each edge of the multi-strobe signal having a plurality of edges, and evaluates the value at each timing.
　マルチストローブ回路１０は、第１遅延回路１２、第２遅延回路１４、ラッチ回路１６、論理演算部１８、遅延量調節部２０を備える。
　第１遅延回路１２は、多段にカスケード接続されたＮ個（Ｎは自然数）の第１遅延素子Ｄ１１～Ｄ１Ｎ（第１遅延素子Ｄ１と総称される）を含む。１段目の第１遅延素子Ｄ１１にはレベルコンパレータ４０からの被試験信号Ｓ１Ｌが入力される。被試験信号Ｓ１Ｌには第１遅延素子Ｄ１を１段経るごとに、所定の第１遅延量τ１（＝Ｔｐｄ）が与えられる。つまりｉ段目の第１遅延素子Ｄ１ｉからは、被試験信号Ｓ１Ｌに対して（ｉ×Ｔｐｄ）だけ遅延した被試験信号Ｓ１ｉが出力される。 The multi-strobe circuit 10 includes a first delay circuit 12, a second delay circuit 14, a latch circuit 16, a logic operation unit 18, and a delay amount adjustment unit 20.
The first delay circuit 12 includes N (N is a natural number) first delay elements D1 1 to D1 N (collectively referred to as first delay elements D1) cascaded in multiple stages. The first delay element D1 1 of the first stage under test signals S1L from the level comparator 40 is input. A predetermined first delay amount τ1 (= Tpd) is given to the signal under test S1L every time one stage passes through the first delay element D1. That is, the signal under test S1 i delayed from the signal under test S1L by (i × Tpd) is output from the i- th first delay element D1 i .
　第２遅延回路１４は、多段にカスケード接続されたＮ個の第２遅延素子Ｄ２１～Ｄ２Ｎ（第２遅延素子Ｄ２と総称される）を含む。これらの第２遅延素子Ｄ２１～Ｄ２Ｎはそれぞれ、Ｎ個の第１遅延素子Ｄ１１～Ｄ１Ｎごとに設けられている。１段目の第２遅延素子Ｄ２１には、タイミング発生器３０により生成された基準となるストローブ信号ＳＴＲＢが、第３遅延素子Ｄ３を介して入力されており、ストローブ信号ＳＴＲＢには、第２遅延素子Ｄ２を１段経るごとに、所定の第２遅延量τ２（＝Ｔｐｄ＋Δｔ）の遅延が与えられる。ｉ段目の第２遅延素子Ｄ２からは、基準ストローブ信号ＳＴＲＢに対して、ｉ×（Ｔｐｄ＋Δｔ）だけ遅延したｉ相目のストローブ信号ＳＴＲＢｉが出力される。 The second delay circuit 14 includes N second delay elements D2 1 to D2 N (collectively referred to as second delay elements D2) cascaded in multiple stages. The second delay elements D2 1 to D2 N are provided for each of the N first delay elements D1 1 to D1 N. The reference strobe signal STRB generated by the timing generator 30 is input to the first delay element D21 at the first stage via the third delay element D3. The strobe signal STRB includes the second delay element ST21. A delay of a predetermined second delay amount τ2 (= Tpd + Δt) is given each time one stage through the delay element D2. The i-th strobe signal STRB i delayed by i × (Tpd + Δt) with respect to the reference strobe signal STRB is output from the i- th second delay element D2.
　図３は、第１遅延素子および第２遅延素子として利用可能な可変遅延回路５０の構成例を示す回路図である。可変遅延回路５０は、バッファ５２、複数ｍ個（ｍは自然数）のキャパシタＣ１～Ｃｍ、複数のキャパシタＣ１～Ｃｍごとに設けられた複数のスイッチＳＷ１～ＳＷｍを備える。複数のキャパシタＣ１～Ｃｍの容量値は２進数で重み付けされている。重み１に対応する単位容量をＣと書くとき、ｉ（１≦）番目の容量値は２ｍ－１Ｃと表される。ｉ番目のキャパシタＣｉとｉ番目のスイッチＳＷｉは、バッファ５２の出力端子と固定電圧端子（接地端子）の間に直列に接続される。 FIG. 3 is a circuit diagram showing a configuration example of the variable delay circuit 50 that can be used as the first delay element and the second delay element. The variable delay circuit 50 includes a buffer 52, a plurality of m (m is a natural number) capacitors C1 to Cm, and a plurality of switches SW1 to SWm provided for the plurality of capacitors C1 to Cm. The capacitance values of the plurality of capacitors C1 to Cm are weighted with binary numbers. When a unit capacity corresponding to weight 1 is written as C, the i (1 ≦) -th capacity value is expressed as 2 m−1 C. The i-th capacitor Ci and the i-th switch SWi are connected in series between the output terminal of the buffer 52 and a fixed voltage terminal (ground terminal).
　スイッチＳＷｉをオンすると、バッファ５２の出力端子には、そのスイッチＳＷｉに対応したキャパシタＣｉが接続される。つまり時定数が大きくなり、後段に出力される信号の波形の変化速度が遅くなり、結果として遅延量が増加する。複数のスイッチＳＷ１～ＳＷｍのオン、オフを制御することにより、遅延量を２ｍ段階で切り換えることができる。 When the switch SWi is turned on, the capacitor Ci corresponding to the switch SWi is connected to the output terminal of the buffer 52. That is, the time constant increases, the change speed of the waveform of the signal output to the subsequent stage becomes slow, and as a result, the delay amount increases. By controlling on / off of the plurality of switches SW1 to SWm, the delay amount can be switched in 2 m steps.
　図３の可変遅延回路５０は、単位容量Ｃを小さくすることにより、遅延量を高分解能で段階的に切り換えることができる。なお、遅延量の分解能がそれほど要求されない場合、可変遅延回路は、直列にカスケード接続された複数のインバータで構成できる。各ステージのインバータの出力にタップを設け、複数のタップの信号を選択するセレクタを設けることで、可変遅延回路が構成できる。さらに別の構成例では、インバータやバッファのバイアス電圧やバイアス電流を多段階で調節可能に構成することにより、可変遅延回路を実現してもよい。 The variable delay circuit 50 in FIG. 3 can switch the delay amount stepwise with high resolution by reducing the unit capacitance C. When the resolution of the delay amount is not so required, the variable delay circuit can be configured with a plurality of inverters cascaded in series. A variable delay circuit can be configured by providing a tap at the output of the inverter of each stage and providing a selector for selecting signals from a plurality of taps. In yet another configuration example, a variable delay circuit may be realized by configuring the bias voltage and bias current of the inverter and the buffer so as to be adjustable in multiple stages.
　図２に戻る。ラッチ回路１６は、Ｎ個のラッチ素子Ｌ１～ＬＮ（ラッチ素子Ｌと総称される）を含む。Ｎ個のラッチ素子Ｌは、Ｎ個の第１遅延素子Ｄ１１～Ｄ１Ｎ、第２遅延素子Ｄ２１～Ｄ２Ｎごとに設けられる。 Returning to FIG. The latch circuit 16 includes N latch elements L 1 to L N (collectively referred to as latch elements L). N latch elements L are provided for each of the N first delay elements D1 1 to D1 N and the second delay elements D2 1 to D2 N.
　ｉ（ｉは１≦ｉ≦Ｎを満たす自然数）番目のラッチ素子Ｌｉは、対応するｉ相目のストローブ信号ＳＴＲＢｉのエッジのタイミングで、対応するｉ番目の第１遅延素子Ｄ１ｉの出力信号Ｓ１ｉをラッチする。Ｎ個のラッチ素子Ｌの出力信号ＳＬ１～ＳＬＮは、論理演算部１８へと入力される。論理演算部１８は、ＤＵＴ１１０の評価事項に応じた所定の信号処理を行う。被試験信号Ｓ１がある点を境に０から１（または１から０）に遷移するとき、出力信号ＳＬ１～ＳＬＮはあるビットを境に０と１が変化するサーモメータコードとなる。したがって論理演算部１８は、出力信号ＳＬ１～ＳＬＮの値が変化するビットの位置を示すデータを生成するプライオリティエンコーダを含んでもよい。 The i-th (i is a natural number satisfying 1 ≦ i ≦ N) -th latch element L i is the output signal of the corresponding i-th first delay element D1 i at the edge timing of the corresponding i-phase strobe signal STRBi. S1 i is latched. Output signals SL 1 to SL N of the N latch elements L are input to the logic operation unit 18. The logical operation unit 18 performs predetermined signal processing according to the evaluation items of the DUT 110. When the signal under test S1 transitions from 0 to 1 (or 1 to 0) at a certain point, the output signals SL 1 to SL N are thermometer codes in which 0 and 1 change at a certain bit. Therefore, the logical operation unit 18 may include a priority encoder that generates data indicating the position of the bit where the values of the output signals SL 1 to SL N change.
　遅延量調節部２０は、論理演算部１８の信号処理の結果にもとづいて、Ｎ個の第１遅延素子Ｄ１１～Ｄ１Ｎと、Ｎ個の第２遅延素子Ｄ２１～Ｄ２Ｎの少なくとも一方の遅延量を調節するキャリブレーション処理を行う。遅延量調節部２０によってすべてのステージの第１遅延量τ１と第２遅延量τ２の相対的な値が調節され、マルチストローブ信号ＳＴＲＢ１～ＳＴＲＢＮのエッジのタイミングが所望の位置に設定される。以下、このキャリブレーション処理を説明する。 Based on the signal processing result of the logic operation unit 18, the delay amount adjusting unit 20 is configured to include at least one of N first delay elements D1 1 to D1 N and N second delay elements D2 1 to D2 N. Perform a calibration process to adjust the delay amount. The relative amounts of the first delay amount τ1 and the second delay amount τ2 of all the stages are adjusted by the delay amount adjusting unit 20, and the edge timings of the multi-strobe signals STRB 1 to STRB N are set to desired positions. . Hereinafter, this calibration process will be described.
　図４は、マルチストローブ回路１０のキャリブレーションの手順を示すフローチャートである。 FIG. 4 is a flowchart showing the calibration procedure of the multi-strobe circuit 10.
　遅延量調節部２０は、まずすべてのステージの第１遅延量τ１、第２遅延量τ２を初期化する（Ｓ１００）。第１遅延素子Ｄ１、第２遅延素子Ｄ２がいずれも可変遅延素子として構成される場合、すべての遅延素子Ｄ１、Ｄ２の遅延量を設定可能な最小値にセットする。 The delay amount adjusting unit 20 first initializes the first delay amount τ1 and the second delay amount τ2 of all stages (S100). When both the first delay element D1 and the second delay element D2 are configured as variable delay elements, the delay amounts of all the delay elements D1 and D2 are set to a settable minimum value.
　続いて、ｉ（ｉは自然数）を１からＮまで１ずつインクリメントしながら、ゼロアジャストステップを繰り返す（Ｓ１０２）。ゼロアジャストステップ（Ｓ１０４）は、ｉ段目のラッチ素子Ｌｉに入力される被試験信号Ｓ１ｉと、ｉ相目のストローブ信号ＳＴＲＢｉのエッジのタイミングが一致するように、ｉ段目の第１遅延素子Ｄ１ｉの遅延量τ１ｉと、第２遅延素子Ｄ２ｉの遅延量τ２ｉの少なくとも一方の遅延量を調節する。 Subsequently, the zero adjustment step is repeated while i (i is a natural number) is incremented by 1 from 1 to N (S102). The zero adjustment step (S104) is performed so that the timing of the edge of the signal under test S1 i input to the i- th stage latch element Li matches the edge timing of the i-phase strobe signal STRB i . 1 to adjust the delay amount .tau.1 i of the delay element D1 i, at least one of the delay amount of the delay amount .tau.2 i of the second delay element D2 i.
　ゼロアジャストステップＳ１０４は、以下のように実行することができる。すなわち、ｉ段目のラッチ素子Ｌｉに入力される被試験信号Ｓ１ｉのエッジのタイミングが、ストローブ信号ＳＴＲＢｉのエッジのタイミングより早いとき、ｉ段目の第１遅延素子Ｄ１ｉの遅延量τ１ｉを最小幅だけ増加させる。反対に、被試験信号Ｓ１ｉのエッジのタイミングが、ストローブ信号ＳＴＲＢｉのエッジのタイミングより遅いとき、ｉ段目の第２遅延素子Ｄ２ｉの遅延量τ２ｉを増加させる。この処理を繰り返せば、被試験信号Ｓ１ｉのエッジとストローブ信号ＳＴＲＢｉのエッジのタイミングが一致するように収束する。 The zero adjustment step S104 can be executed as follows. That is, when the edge timing of the signal under test S1 i input to the i-th latch element L i is earlier than the edge timing of the strobe signal STRB i , the delay amount of the i- th first delay element D1 i Increase τ1 i by the minimum width. Conversely, when the edge timing of the signal under test S1 i is later than the edge timing of the strobe signal STRB i , the delay amount τ2 i of the i- th second delay element D2 i is increased. If this process is repeated, the convergence is made so that the timing of the edge of the signal under test S1 i and the edge of the strobe signal STRB i coincide.
　あるいはゼロアジャストステップＳ１０４は、以下のステップＡ～Ｄを含んでもよい。 Alternatively, the zero adjustment step S104 may include the following steps A to D.
　ステップＡ．　ｉ段目の第１遅延素子Ｄ１ｉおよび第２遅延素子Ｄ２ｉの相対的な遅延量ＴＲを段階的に変化させる。たとえば被試験信号Ｓ１ｉがローレベル（第１レベル）からハイレベル（第２レベル）に遷移する場合を考える。このときストローブ信号ＳＴＲＢｉが、被試験信号Ｓ１ｉがハイレベルに遷移する前であって、ローレベルに安定している期間に位置するとき、ｉ段目のラッチ素子Ｌｉの出力信号（ラッチデータＬＤｉともいう）は、第１レベル（ローレベル）で確定される。反対に、ストローブ信号ＳＴＲＢｉが、被試験信号Ｓ１ｉがハイレベルに遷移した後であって、ハイレベルに安定している期間に位置するとき、ラッチデータＬＤｉは、第２レベル（ハイレベル）で確定される。ストローブ信号ＳＴＲＢｉが、被試験信号Ｓ１ｉの遷移期間中に位置するとき、その値は不定となる。つまりハイレベルとなるかローレベルとなるかは、確率的な現象となる。図５は、ストローブ信号ＳＴＲＢｉと被試験信号Ｓ１ｉのタイミングと、ラッチデータＬＤｉの関係を示すタイムチャートである。図中、ラッチデータＬＤｉが不定となる状態は”Ｘ”で示される。 Step A. The relative delay amount TR of the i- th first delay element D1 i and the second delay element D2 i is changed stepwise. For example, consider the case where the signal under test S1 i transitions from a low level (first level) to a high level (second level). At this time, when the strobe signal STRB i is located before the signal under test S1 i transits to the high level and is stable at the low level, the output signal (latch) of the i-th latch element Li Data LD i ) is determined at the first level (low level). On the other hand, when the strobe signal STRB i is positioned after the signal under test S1 i has transitioned to the high level and is stable at the high level, the latch data LD i has the second level (high level). ) To confirm. When the strobe signal STRB i is located during the transition period of the signal under test S1 i , its value becomes indefinite. That is, it becomes a probabilistic phenomenon whether it becomes high level or low level. FIG. 5 is a time chart showing the relationship between the timing of the strobe signal STRB i and the signal under test S1 i and the latch data LD i . In the figure, the state in which the latch data LD i is indefinite is indicated by “X”.
　ステップＢ．　ステップＡの過程において、ラッチデータＬＤｉが、第１レベル（たとえばローレベル）に確定するときの相対的な遅延量ＴＲを、第１相対遅延量ＴＲ１として取得する。 Step B. In the process of step A, the relative delay amount TR when the latch data LD i is fixed at the first level (for example, low level) is acquired as the first relative delay amount TR1.
　ステップＣ．　ステップＡの過程において、ラッチデータＬＤｉが、第２レベル（たとえばハイレベル）に確定するときの相対的な遅延量ＴＲを、第２相対遅延量ＴＲ２として取得する。 Step C. In the process of Step A, the relative delay amount TR when the latch data LD i is fixed at the second level (for example, high level) is acquired as the second relative delay amount TR2.
　ステップＤ．　ｉ段目の第１遅延素子Ｄ１ｉと第２遅延素子Ｄ２ｉの相対的な遅延量ＴＲを、第１相対遅延量ＴＲ１と第２相対遅延量ＴＲ２の間の値に設定する。たとえば第１相対遅延量ＴＲ１と第２相対遅延量ＴＲ２の中点ＴＲｃを選んでもよい。あるいは、第１相対遅延量ＴＲ１もしくは第２相対遅延量ＴＲ２を選択しても構わない。 Step D. The relative delay amount TR between the i- th first delay element D1 i and the second delay element D2 i is set to a value between the first relative delay amount TR1 and the second relative delay amount TR2. For example, the midpoint TRc of the first relative delay amount TR1 and the second relative delay amount TR2 may be selected. Alternatively, the first relative delay amount TR1 or the second relative delay amount TR2 may be selected.
　図４に戻る。すべてのステージについてゼロアジャストステップが完了したら、分解能設定ステップＳ１０６を実行する。分解能設定ステップＳ１０６において遅延量調節部２０は、第１遅延素子Ｄ１および第２遅延素子Ｄ２の少なくとも一方のすべてのステージの遅延量を、所定量Δｔだけ変化させる。たとえば第２遅延素子Ｄ２のすべてのステージの遅延量τ２１～τ２ＮをΔｔ増加させてもよい。 Returning to FIG. When the zero adjustment step is completed for all the stages, the resolution setting step S106 is executed. In the resolution setting step S106, the delay amount adjusting unit 20 changes the delay amounts of all the stages of at least one of the first delay element D1 and the second delay element D2 by a predetermined amount Δt. For example, the delay amounts τ2 1 to τ2 N of all stages of the second delay element D2 may be increased by Δt.
　以上がマルチストローブ回路１０の構成である。 The above is the configuration of the multi-strobe circuit 10.
　実施の形態に係るマルチストローブ回路１０の効果を説明する前に、キャリブレーションを行わない場合を考察する。図６（ａ）、（ｂ）は、実施の形態に係るキャリブレーションを行わない場合のストローブ信号と被試験信号のタイミング関係を示すタイムチャートである。 Before explaining the effect of the multi-strobe circuit 10 according to the embodiment, consider the case where calibration is not performed. FIGS. 6A and 6B are time charts showing the timing relationship between the strobe signal and the signal under test when the calibration according to the embodiment is not performed.
　図６（ａ）は、第１遅延素子Ｄ１および第２遅延素子Ｄ２に設定された遅延量の誤差が無視しうる理想的な状態を示す。つまり、第１遅延素子Ｄ１の遅延量をＴｐｄ１、第２遅延素子Ｄ２の遅延量をＴｐｄ２＋Δｔと書くとき、Ｔｐｄ１＝Ｔｐｄ２が成り立つ場合を示す。分解能を設定する前のステップ１の段階において、ｉ相目のストローブ信号ＳＴＲＢｉとｉ相目の被試験信号Ｓ１ｉのタイミングは一致するであろう。この状態において、各ステージの第２遅延素子Ｄ２の遅延量をさらにΔｔだけ増加させれば、各相のストローブ信号ＳＴＲＢ１～ＳＴＲＢＮは理想的なタイミングに設定される。 FIG. 6A shows an ideal state where the error of the delay amount set in the first delay element D1 and the second delay element D2 can be ignored. That is, when the delay amount of the first delay element D1 is written as Tpd1 and the delay amount of the second delay element D2 is written as Tpd2 + Δt, Tpd1 = Tpd2 is satisfied. In the step 1 before setting the resolution, the timings of the i-phase strobe signal STRB i and the i-phase signal under test S1 i will match. In this state, if the delay amount of the second delay element D2 of each stage is further increased by Δt, the strobe signals STRB 1 to STRB N of each phase are set to ideal timing.
　以上は理想的な場合であるが、実際には第１遅延素子Ｄ１と第２遅延素子Ｄ２の遅延量が、プロセスばらつきや電源電圧変動、温度変動の影響によって、設計値から逸脱する場合が想定される。仮に第１遅延素子Ｄ１と第２遅延素子Ｄ２の遅延量がそれぞれ、設計値Ｔｐｄに対してδｔ１、δｔ２だけ増加もしくは減少しても、同じ半導体基板上に集積化されていれば、両者の遅延量は互いに追従して変動するため、δｔ１≒δｔ２となる。つまり、分解能を設定する前のステップ１の段階において、ｉ相目のストローブ信号ＳＴＲＢｉとｉ相目の被試験信号Ｓ１ｉのタイミングはほぼ一致する。 The above is an ideal case, but in reality, the delay amount of the first delay element D1 and the second delay element D2 may deviate from the design value due to the influence of process variations, power supply voltage fluctuations, and temperature fluctuations. Is done. Even if the delay amounts of the first delay element D1 and the second delay element D2 increase or decrease by δt1 and δt2 with respect to the design value Tpd, respectively, if they are integrated on the same semiconductor substrate, both delays Since the amounts vary following each other, δt1≈δt2. That is, in the stage of step 1 before setting the resolution, the timings of the i-phase strobe signal STRB i and the i-phase signal under test S1 i substantially coincide.
　しかしながら分解能Δｔが数ｐｓ程度と小さくなると、遅延量の誤差δｔ１とδｔ２の差分（δｔ１－δｔ２）が無視出来なくなる。この場合、分解能を設定する前のステップ１の段階において、ｉ相目のストローブ信号ＳＴＲＢｉとｉ相目の被試験信号Ｓ１ｉのタイミングにずれが生じてしまう。結果としてステップ２の分解能設定後のストローブ信号ＳＴＲＢｉは、所望の位置から大きくずれてしまう。図６（ｂ）はこの状態を示している。 However, when the resolution Δt is reduced to about several ps, the difference (δt1−δt2) between the delay amount errors δt1 and δt2 cannot be ignored. In this case, in the stage of Step 1 before setting the resolution, the timing of the i-phase strobe signal STRB i and the i-phase signal under test S1 i is shifted. As a result, the strobe signal STRB i after setting the resolution in step 2 is greatly deviated from the desired position. FIG. 6B shows this state.
　続いて実施の形態に係るマルチストローブ回路１０によるキャリブレーションについて説明する。 Subsequently, calibration by the multi-strobe circuit 10 according to the embodiment will be described.
　図７（ａ）、（ｂ）は、図２のマルチストローブ回路１０のキャリブレーションの様子を示すタイムチャートである。図７（ａ）はゼロアジャストステップを、図７（ｂ）は分解能設定ステップを示す。図７（ａ）では、説明を簡潔とするために、第１遅延素子Ｄ１の遅延量τ１を固定した状態で、第２遅延素子Ｄ２の遅延量τ２を増減させて、ストローブ信号ＳＴＲＢｉと被試験信号Ｓ１ｉのタイミングを揃える場合を図示している。しかしながら本発明はこれに限定されず、第２遅延素子Ｄ２の遅延量τ２を固定した状態で、第１遅延素子Ｄ１の遅延量τ１を増減させて、ストローブ信号ＳＴＲＢｉと被試験信号Ｓ１ｉのタイミングを揃えてもよい。 FIGS. 7A and 7B are time charts showing how the multi-strobe circuit 10 shown in FIG. 2 is calibrated. FIG. 7A shows a zero adjustment step, and FIG. 7B shows a resolution setting step. In FIG. 7A, in order to simplify the description, the delay amount τ2 of the second delay element D2 is increased or decreased while the delay amount τ1 of the first delay element D1 is fixed, and the strobe signal STRB i The case where the timing of the test signal S1 i is aligned is illustrated. However, the present invention is not limited to this, and while the delay amount τ2 of the second delay element D2 is fixed, the delay amount τ1 of the first delay element D1 is increased or decreased, and the strobe signal STRB i and the signal under test S1 i are increased. The timing may be aligned.
　より好ましい態様では、上述したように、第１遅延素子Ｄ１と第２遅延素子Ｄ２の初期遅延を最小としておき、被試験信号Ｓ１ｉのエッジのタイミングが、ストローブ信号ＳＴＲＢｉのエッジのタイミングより早いとき、第１遅延素子Ｄ１ｉの遅延量τ１ｉを増加させ、反対に、被試験信号Ｓ１ｉのエッジのタイミングが、ストローブ信号ＳＴＲＢｉのエッジのタイミングより遅いとき、第２遅延素子Ｄ２ｉの遅延量τ２ｉを増加させてもよい。この場合、第１遅延素子Ｄ１の遅延量τ２と第２遅延素子Ｄ２の遅延量τ２が最小となる状態でキャリブレーションがとれるため、遅延量のばらつきが分解能に及ぼす影響を抑制することができる。 In a more preferable aspect, as described above, the initial delay of the first delay element D1 and the second delay element D2 is minimized, and the edge timing of the signal under test S1 i is earlier than the edge timing of the strobe signal STRB i. The delay amount τ1 i of the first delay element D1 i is increased, and conversely, when the edge timing of the signal under test S1 i is later than the edge timing of the strobe signal STRB i , the second delay element D2 i The delay amount τ2 i may be increased. In this case, since the calibration can be performed in a state where the delay amount τ2 of the first delay element D1 and the delay amount τ2 of the second delay element D2 are minimized, it is possible to suppress the influence of variations in the delay amount on the resolution.
　ゼロアジャストステップが完了すると、各相において、図７（ｂ）に示すように、第２遅延素子Ｄ２の遅延量τ２が所定量Δｔだけ増加し、ストローブ信号ＳＴＲＢが被試験信号Ｓ１に対して時間的に遅れることになる。各相（各ステージ）ごとにΔｔずつ遅れることになるため、ｉ相目の被試験信号Ｓ１ｉとストローブ信号ＳＴＲＢｉの位相差は、ｉ×Δｔで与えられる。 When the zero adjustment step is completed, in each phase, as shown in FIG. 7B, the delay amount τ2 of the second delay element D2 increases by a predetermined amount Δt, and the strobe signal STRB is timed with respect to the signal under test S1. Will be late. Since each phase (each stage) is delayed by Δt, the phase difference between the i- th signal under test S1 i and the strobe signal STRB i is given by i × Δt.
　このように本実施の形態に係るマルチストローブ回路１０によれば、遅延素子の遅延量のばらつきを好適にキャンセルすることができ、ひいては高精度なマルチストローブ信号ＳＴＲＢ１～ＳＴＲＢＮによって被試験信号Ｓ１を評価することができる。 As described above, according to the multi-strobe circuit 10 according to the present embodiment, it is possible to preferably cancel the variation in the delay amount of the delay element, and as a result, the signal under test S1 is generated by the highly accurate multi-strobe signals STRB 1 to STRB N. Can be evaluated.
　実施の形態にもとづき本発明を説明したが、実施の形態は、本発明の原理、応用を示しているにすぎず、実施の形態には、請求の範囲に規定された本発明の思想を逸脱しない範囲において、多くの変形例や配置の変更が可能である。 Although the present invention has been described based on the embodiments, the embodiments merely show the principle and application of the present invention, and the embodiments depart from the idea of the present invention defined in the claims. Many modifications and arrangements can be made without departing from the scope.
１０…マルチストローブ回路、１２…第１遅延回路、１４…第２遅延回路、１６…ラッチ回路、１８…論理演算部、２０…遅延量調節部、３０…タイミング発生器、４０…レベルコンパレータ、４２…第１コンパレータ、４４…第２コンパレータ、Ｄ１…第１遅延素子、Ｄ２…第２遅延素子、Ｌ…ラッチ素子、１００…試験装置、１１０…ＤＵＴ、Ｓ１…被試験信号。 DESCRIPTION OF SYMBOLS 10 ... Multi-strobe circuit, 12 ... 1st delay circuit, 14 ... 2nd delay circuit, 16 ... Latch circuit, 18 ... Logic operation part, 20 ... Delay amount adjustment part, 30 ... Timing generator, 40 ... Level comparator, 42 DESCRIPTION OF SYMBOLS 1st comparator, 44 ... 2nd comparator, D1 ... 1st delay element, D2 ... 2nd delay element, L ... Latch element, 100 ... Test apparatus, 110 ... DUT, S1 ... Signal under test.
　本発明は、試験装置に利用できる。 The present invention can be used for a test apparatus.

Claims (7)

  1. 　複数のエッジを有するマルチストローブ信号のそれぞれエッジのタイミングで、評価対象の被試験信号をラッチするマルチストローブ回路であって、
    　Ｎ個（Ｎは自然数）の第１遅延素子が多段接続されて構成され、前記被試験信号に対し１段ごとに遅延を与え、複数の被試験信号を生成する第１遅延回路と、
    　前記Ｎ個の第１遅延素子ごとに設けられたＮ個の第２遅延素子が多段接続されて構成され、基準となるストローブ信号に対し１段ごとに遅延を与え、複数のストローブ信号を生成する第２遅延回路と、
    　前記Ｎ個の第１遅延素子ごとに設けられたＮ個のラッチ素子を含み、ｉ段目のラッチ素子は、ｉ段目の第１遅延素子から出力される前記被試験信号を、ｉ段目の第２遅延素子から出力されるストローブ信号のタイミングでラッチするように構成されたラッチ回路と、
    　前記Ｎ個の第１遅延素子と前記Ｎ個の第２遅延素子の少なくとも一方の遅延量を調節する遅延量調節部と、
    　を備え、
    　前記遅延量調節部は、キャリブレーション時に、ｉ（ｉは自然数）を１からＮまでインクリメントしながら、ｉ段目のラッチ素子に入力される前記被試験信号と前記ストローブ信号のエッジのタイミングが一致するように、ｉ段目の第１遅延素子と第２遅延素子の少なくとも一方の遅延量を調節するゼロアジャストステップと、
    　前記第１遅延素子および前記第２遅延素子の少なくとも一方のすべてのステージの遅延量を、所定量だけ変化させる分解能設定ステップと、
    　を実行することを特徴とするマルチストローブ回路。     A multi-strobe circuit that latches a signal under test at an edge timing of a multi-strobe signal having a plurality of edges,
    A first delay circuit configured by connecting N (N is a natural number) first delay elements in multiple stages, delaying the signal under test for each stage, and generating a plurality of signals under test;
    The N second delay elements provided for each of the N first delay elements are connected in multiple stages, and a delay is provided for each stage with respect to a reference strobe signal to generate a plurality of strobe signals. A second delay circuit;
    N latch elements provided for each of the N first delay elements, the i-th latch element outputs the signal under test output from the i-th first delay element to the i-th stage A latch circuit configured to latch at the timing of the strobe signal output from the second delay element;
    A delay amount adjusting unit that adjusts a delay amount of at least one of the N first delay elements and the N second delay elements;
    With
    The delay amount adjusting unit increments i (i is a natural number) from 1 to N during calibration, and the timing of the edge of the signal under test input to the i-th latch element coincides with the timing of the strobe signal. A zero adjustment step for adjusting a delay amount of at least one of the i-th first delay element and the second delay element;
    A resolution setting step of changing a delay amount of all stages of at least one of the first delay element and the second delay element by a predetermined amount;
    A multi-strobe circuit characterized by executing
  2. 　前記Ｎ個の第１遅延素子および前記Ｎ個の第２遅延素子は可変遅延素子であり、
    　前記遅延量調節部は、前記Ｎ個の第１遅延素子および前記第２遅延素子の遅延量を最小に設定した状態を初期状態として、前記ゼロアジャストステップを実行し、
    　前記ゼロアジャストステップにおいて、ｉ段目のラッチ素子に入力される前記被試験信号のエッジのタイミングが前記ストローブ信号のエッジのタイミングより早いとき、ｉ段目の第１遅延素子の遅延量を増加させ、ｉ段目のラッチ素子に入力される前記被試験信号のエッジのタイミングが前記ストローブ信号のエッジのタイミングより遅いとき、ｉ段目の第２遅延素子の遅延量を増加させることを特徴とする請求項１に記載のマルチストローブ回路。     The N first delay elements and the N second delay elements are variable delay elements,
    The delay amount adjustment unit performs the zero adjustment step with an initial state of a state in which the delay amounts of the N first delay elements and the second delay elements are set to a minimum.
    In the zero adjustment step, when the edge timing of the signal under test input to the i-th latch element is earlier than the edge timing of the strobe signal, the delay amount of the i-th first delay element is increased. When the edge timing of the signal under test input to the i-th latch element is later than the edge timing of the strobe signal, the delay amount of the i-th second delay element is increased. The multi-strobe circuit according to claim 1.
  3. 　前記遅延量調節部は、前記ゼロアジャストステップにおいて、ｉ段目の調整を行う際に、ｉ段目の前記第１遅延素子および前記第２遅延素子の相対的な遅延量を段階的に変化させながら、ｉ段目の前記ラッチ素子にラッチされた値が第１のレベルに確定するときの相対的な遅延量を第１相対遅延量として、ｉ段目の前記ラッチ素子によりラッチされた値が前記第１のレベルと相補的な第２のレベルに確定するときの相対的な遅延量を第２相対遅延量として取得し、ｉ段目の前記第１遅延素子および前記第２遅延素子の相対的な遅延量を、前記第１相対遅延量と前記第２相対遅延量の間の値に設定することを特徴とする請求項１に記載のマルチストローブ回路。 In the zero adjustment step, the delay amount adjusting unit changes the relative delay amount of the first delay element and the second delay element in the i-th stage in a stepwise manner when performing the i-th stage adjustment. However, the value latched by the i-th latch element is defined as a first relative delay amount, which is a relative delay amount when the value latched by the i-th latch element is determined to be the first level. A relative delay amount when determining a second level complementary to the first level is obtained as a second relative delay amount, and the relative relationship between the first delay element and the second delay element at the i-th stage is obtained. The multi-strobe circuit according to claim 1, wherein an effective delay amount is set to a value between the first relative delay amount and the second relative delay amount.
  4. 　被試験デバイスから出力される信号をしきい値電圧と比較するコンパレータと、
    　任意のタイミングでレベルが遷移するストローブ信号を生成するタイミング発生器と、
    　前記ストローブ信号と、前記被試験信号としての前記コンパレータの出力信号と、を受ける請求項１から３のいずれかに記載のマルチストローブ回路と、
    　を備えることを特徴とする試験装置。     A comparator that compares the signal output from the device under test with a threshold voltage;
    A timing generator that generates a strobe signal whose level transitions at an arbitrary timing;
    The multi-strobe circuit according to any one of claims 1 to 3, which receives the strobe signal and an output signal of the comparator as the signal under test.
    A test apparatus comprising:
  5. 　複数のエッジを有するマルチストローブ信号のそれぞれエッジのタイミングで、評価対象の被試験信号をラッチするマルチストローブ回路のキャリブレーション方法であって、
    　前記マルチストローブ回路は、
    　Ｎ個（Ｎは自然数）の第１遅延素子が多段接続されて構成され、前記被試験信号に対し１段ごとに遅延を与え、複数の被試験信号を生成する第１遅延回路と、
    　前記Ｎ個の第１遅延素子ごとに設けられたＮ個の第２遅延素子が多段接続されて構成され、基準となるストローブ信号に対し１段ごとに遅延を与え、複数のストローブ信号を生成する第２遅延回路と、
    　前記Ｎ個の第１遅延素子ごとに設けられたＮ個のラッチ素子を含み、ｉ段目のラッチ素子は、ｉ段目の第１遅延素子から出力される前記被試験信号を、ｉ段目の第２遅延素子から出力されるストローブ信号のタイミングでラッチするように構成されたラッチ回路と、
    　を備えており、当該キャリブレーション方法は、
    　ｉ（ｉは自然数）を１からＮまでインクリメントしながら、ｉ段目のラッチ素子に入力される前記被試験信号と前記ストローブ信号のエッジのタイミングが一致するように、ｉ段目の第１遅延素子と第２遅延素子の少なくとも一方の遅延量を調節するゼロアジャストステップと、
    　前記第１遅延素子および前記第２遅延素子の少なくとも一方の、すべてのステージの遅延量を、所定量だけ変化させる分解能設定ステップと、
    　を備えることを特徴とするキャリブレーション方法。     A multi-strobe circuit calibration method for latching a signal under test to be evaluated at each edge timing of a multi-strobe signal having a plurality of edges,
    The multi-strobe circuit is
    A first delay circuit configured by connecting N (N is a natural number) first delay elements in multiple stages, delaying the signal under test for each stage, and generating a plurality of signals under test;
    The N second delay elements provided for each of the N first delay elements are connected in multiple stages, and a delay is provided for each stage with respect to a reference strobe signal to generate a plurality of strobe signals. A second delay circuit;
    N latch elements provided for each of the N first delay elements, the i-th latch element outputs the signal under test output from the i-th first delay element to the i-th stage A latch circuit configured to latch at the timing of the strobe signal output from the second delay element;
    The calibration method is
    While the i (i is a natural number) is incremented from 1 to N, the i-th first delay is set so that the timing of the edge of the signal under test input to the i-th latch element and the strobe signal coincide with each other. A zero adjustment step for adjusting a delay amount of at least one of the element and the second delay element;
    A resolution setting step of changing a delay amount of all stages of at least one of the first delay element and the second delay element by a predetermined amount;
    A calibration method comprising:
  6. 　前記Ｎ個の第１遅延素子および前記Ｎ個の第２遅延素子は可変遅延素子であり、
    　前記キャリブレーション方法は、
    　前記Ｎ個の第１遅延素子および前記第２遅延素子の遅延量を最小に設定した状態を初期状態として、前記ゼロアジャストステップを実行し、
    　前記ゼロアジャストステップにおいて、ｉ段目のラッチ素子に入力される前記被試験信号のエッジのタイミングが前記ストローブ信号のエッジのタイミングより早いとき、ｉ段目の第１遅延素子の遅延量を増加させ、ｉ段目のラッチ素子に入力される前記被試験信号のエッジのタイミングが前記ストローブ信号のエッジのタイミングより遅いとき、ｉ段目の第２遅延素子の遅延量を増加させることを特徴とする請求項５に記載のキャリブレーション方法。     The N first delay elements and the N second delay elements are variable delay elements,
    The calibration method is:
    The zero adjustment step is executed by setting a state in which the delay amounts of the N first delay elements and the second delay elements are set to a minimum as an initial state,
    In the zero adjustment step, when the edge timing of the signal under test input to the i-th latch element is earlier than the edge timing of the strobe signal, the delay amount of the i-th first delay element is increased. When the edge timing of the signal under test input to the i-th latch element is later than the edge timing of the strobe signal, the delay amount of the i-th second delay element is increased. The calibration method according to claim 5.
  7. 　前記ゼロアジャストステップにおいて、ｉ段目の調整を行う際に、ｉ段目の前記第１遅延素子および前記第２遅延素子の相対的な遅延量を段階的に変化させながら、ｉ段目の前記ラッチ素子にラッチされた値が第１のレベルに確定するときの相対的な遅延量を第１相対遅延量として、ｉ段目の前記ラッチ素子によりラッチされた値が前記第１のレベルと相補的な第２のレベルに確定するときの相対的な遅延量を第２相対遅延量として取得し、ｉ段目の前記第１遅延素子および前記第２遅延素子の相対的な遅延量を、前記第１相対遅延量と前記第２相対遅延量の間の値に設定することを特徴とする請求項５に記載のキャリブレーション方法。 In the zero adjustment step, when the i-th adjustment is performed, the relative delay amount of the i-th first delay element and the second delay element is changed stepwise, and the i-th stage The relative delay amount when the value latched by the latch element is fixed at the first level is defined as a first relative delay amount, and the value latched by the i-th latch element is complementary to the first level. A relative delay amount when determining the second level is determined as a second relative delay amount, and the relative delay amounts of the first delay element and the second delay element at the i-th stage are obtained as The calibration method according to claim 5, wherein a value between the first relative delay amount and the second relative delay amount is set.
PCT/JP2009/002573 2008-06-13 2009-06-08 Multi-strobe circuit, method for calibration of the same, and test equipment using the same WO2009150816A1 (en)

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