CN113884865B - Test circuit and test method of D trigger - Google Patents
Test circuit and test method of D trigger Download PDFInfo
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- CN113884865B CN113884865B CN202010624254.6A CN202010624254A CN113884865B CN 113884865 B CN113884865 B CN 113884865B CN 202010624254 A CN202010624254 A CN 202010624254A CN 113884865 B CN113884865 B CN 113884865B
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318522—Test of Sequential circuits
- G01R31/318525—Test of flip-flops or latches
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31725—Timing aspects, e.g. clock distribution, skew, propagation delay
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31727—Clock circuits aspects, e.g. test clock circuit details, timing aspects for signal generation, circuits for testing clocks
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
- G01R31/318328—Generation of test inputs, e.g. test vectors, patterns or sequences for delay tests
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
- G01R31/318392—Generation of test inputs, e.g. test vectors, patterns or sequences for sequential circuits
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Abstract
The invention belongs to the technical field of digital integrated circuits, and relates to a test circuit and a test method of a D trigger. The test circuit is used for testing the time sequence information of the D trigger in the digital integrated circuit, and comprises a delay generating module, an oscillator circuit and a path selector; the delay generating module comprises a first delay path and a second delay path, and the first delay path and the second delay path can be dynamically configured so that a variable delay difference exists between a first delay output signal and a second delay output signal which are output by the delay generating module; the path selector is used for respectively connecting the first delay path and the second delay path in corresponding configurations to the oscillator circuit so as to respectively form a first oscillation loop and a second oscillation loop. The test circuit and the test method can eliminate the influence of the interconnection line delay and the process fluctuation of the test circuit on the test result, and have high test accuracy.
Description
Technical Field
The invention belongs to the technical field of digital integrated circuits, and relates to a test circuit and a test method of a D trigger.
Background
As the molar theorem directs the development of semiconductor manufacturing to smaller feature sizes, the number of transistors on a chip increases dramatically, and as one of the most important standard cells on digital integrated circuits, the chip also tends to have a huge number of D flip-flops. Meanwhile, the frequency of the digital integrated circuit is continuously increased, and the time sequence information of the D trigger needs to be accurately modeled and characterized under high clock frequency, so that a reliable circuit netlist can be synthesized in a circuit design stage.
However, the fluctuation of the threshold voltage of the device is increased along with the miniaturization of the process node, so that the time sequence information of the standard unit (namely the D trigger) is influenced significantly, and accordingly, the process fluctuation is more and more difficult to characterize; and, as process nodes shrink, the proportion of interconnect delay to path delay is also increasing.
The timing information of the D flip-flop generally comes from the test of the D flip-flop by the test circuit, but the test circuit itself is susceptible to and is affected by the disturbance of such process fluctuation, and the interconnect delay of the test circuit has an increasing influence on the test result, and thus the test result of the test circuit becomes unreliable or inaccurate.
Currently, the clock frequency of high performance digital integrated circuits has reached above GHz, and the timing margin for logic cells between two D flip-flops is small with one clock period less than 1 ns. In conventional EDA tools, the setup time and hold time of the D flip-flop leave a corresponding safety margin for reliable circuits, however, this reduces the timing margin of the logic circuit. Therefore, if the setup time and the hold time of the timing information of the D flip-flops can be accurately measured, they are then fed back to the circuit design stage, thereby inserting more logic cells between the two D flip-flops or further increasing the operating frequency of the circuit.
It follows that it becomes very meaningful but increasingly difficult to accurately measure the timing information of the D flip-flops.
Disclosure of Invention
The invention aims to improve the test precision of the time sequence information of a D trigger.
To achieve the above object or other objects, the present invention provides the following technical solutions.
According to an aspect of the present invention, there is provided a test circuit of a D flip-flop for testing timing information of the D flip-flop in a digital integrated circuit; the test circuit includes:
a delay generation module comprising a first delay path for providing a first delayed output signal to a clock/data terminal of the D flip-flop under test and a second delay path for providing a second delayed output signal to a data/clock terminal of the D flip-flop under test, wherein the first delay path and the second delay path are dynamically configurable to have a variable delay difference between the first delayed output signal and the second delayed output signal;
an oscillator circuit; and
a path selector for respectively accessing the first and second delay paths in respective configurations to the oscillator circuit when the third output signal of the D flip-flop under test is not consistent in data with the data terminal at a rising edge time point corresponding to the clock terminal so as to respectively form a first oscillation loop for outputting a first oscillation output signal having a first period and a second oscillation loop for outputting a second oscillation output signal having a second period, wherein the first period and the second period are usable for calculating or characterizing the respective timing information.
According to an additional or alternative embodiment, the delay generation module is configured to fix respective configurations of the first and second delay paths when a third output signal of the D flip-flop under test is not data-wise consistent with the data terminal at a rising edge time point corresponding to the clock terminal.
According to an additional or alternative embodiment, the first delay path comprises a first delay chain formed by a plurality of first delay cells connected in series, and the second delay path comprises a second delay chain formed by a plurality of second delay cells connected in series, wherein the delay produced by a single one of the first delay cells differs from the delay produced by a single one of the second delay cells.
According to an additional or alternative embodiment, the first delay path further comprises a first selector arranged in correspondence with the first delay chain, wherein the first selector is biasable by different first configuration control signals to select different numbers of first delay cells in the first delay chain to be configured active so as to enable the first delay path to be dynamically configured;
the second delay path further comprises a second selector arranged corresponding to the second delay chain, wherein the second selector can be biased with different second configuration control signals to select different numbers of second delay cells in the second delay chain to be configured to be active, so that the second delay path is dynamically configured.
According to an additional or alternative embodiment, the first delay unit and the second delay unit are a first inverter and a second inverter, respectively.
According to additional or alternative embodiments, the PMOS and NMOS transistors of the first inverter have the same gate width but different gate lengths than the PMOS and NMOS transistors of the second inverter, respectively.
According to an additional or alternative embodiment, the delay generating module further comprises a third selector configured to select to supply the first and second delayed output signals to the clock and data terminals, respectively, if the setup time of the timing information needs to be tested, and to supply the first and second delayed output signals to the data and clock terminals, respectively, if the hold time of the timing information needs to be tested.
According to additional or alternative embodiments, the test circuit further comprises:
the output module is used for receiving the first oscillation output signal and outputting fourth output information for amplifying the first period, receiving the second oscillation output signal and outputting fifth output information for amplifying the second period, wherein the fourth output information and the fifth output information are used for calculating to obtain corresponding time sequence information.
According to additional or alternative embodiments, the output module includes a frequency divider.
According to an additional or alternative embodiment, the first or second oscillating output signal is output by an and gate with the first or second oscillating loop operating steadily.
According to additional or alternative embodiments, the timing information includes a setup time and/or a hold time.
According to yet another aspect of the present invention, there is provided a chip comprising a digital integrated circuit having a D flip-flop, and further comprising any one of the above test circuits for testing timing information of the D flip-flop.
According to still another aspect of the present invention, there is provided a test method of any one of the above test circuits, comprising the steps of:
providing a first delay output signal output by a first delay path of the delay generating module to a clock end/data end of the D trigger to be tested, and providing a second delay output signal output by a second delay path of the delay generating module to a data end/clock end of the D trigger to be tested;
dynamically configuring the first and second delay paths to vary a delay difference between the first and second delay output signals that they dynamically output until a third output signal of the D flip-flop under test is not data-wise consistent with the data terminal at a rising edge time point corresponding to the clock terminal, stopping dynamically configuring the first and second delay paths;
the first delay path and the second delay path in corresponding configurations are respectively connected to the oscillator circuit, so that a first oscillation loop and a second oscillation loop are respectively formed; and
and receiving a first oscillation output signal with a first period output by the first oscillation loop and a second oscillation output signal with a second period output by the second oscillation loop, wherein the first period and the second period can be used for calculating or representing the corresponding time sequence information.
According to an additional or alternative embodiment, respective configurations of the first and second delay paths are fixed when a third output signal of the D flip-flop under test is not consistent in data with the data terminal at a rising edge time point corresponding to the clock terminal.
According to an additional or alternative embodiment, in dynamically configuring the first delay path, a different number of first delay cells are selected in the first delay chain of the first delay path by a first configuration control signal and are configured to be active;
in the process of dynamically configuring the second delay path, different numbers of second delay units in the second delay chain are selected and configured to be effective through a second configuration control signal.
According to additional or alternative embodiments, the timing information includes a setup time and/or a hold time;
when testing the time for establishing the time sequence information, the first delay output signal and the second delay output signal are respectively provided to the clock end and the data end;
and when testing the retention time of the time sequence information, respectively providing the first delay output signal and the second delay output signal to the data end and the clock end.
According to additional or alternative embodiments, the test method further comprises the steps of:
and receiving the first oscillation output signal and outputting fourth output information for amplifying the first period, and receiving the second oscillation output signal and outputting fifth output information for amplifying the second period, wherein the fourth output information and the fifth output information are used for calculating to obtain corresponding time sequence information.
The above features, operation and advantages of the present invention will become more apparent from the following description and the accompanying drawings.
Drawings
The above and other objects and advantages of the present invention will become more fully apparent from the following detailed description taken in conjunction with the accompanying drawings, in which identical or similar elements are designated by the same reference numerals.
Fig. 1 is a schematic circuit diagram of a chip according to an embodiment of the present invention, in which a test circuit of a D flip-flop according to an embodiment of the present invention is shown.
Fig. 2 is a schematic diagram of the setup time and the hold time of the timing information of the D flip-flop under test, wherein fig. 2 (a) illustrates the setup time and fig. 2 (b) illustrates the hold time.
Fig. 3 is a schematic diagram of a delay generating module of a test circuit according to an embodiment of the invention.
Fig. 4 illustrates that the first delay path and the second delay path of the delay generation module are respectively connected into the oscillator circuit to form an oscillation loop, wherein fig. 4 (a) outputs a first oscillation loop having a first oscillation output signal ro_out1 of a first period, and fig. 4 (b) outputs a second oscillation loop having a second oscillation output signal ro_out2 of a second period.
Fig. 5 is a schematic diagram of an inverter of a delay unit according to an embodiment of the present invention, wherein fig. 5 (a) illustrates a structure of an inverter in a first delay path and fig. 5 (b) illustrates a structure of an inverter in a second delay path.
Fig. 6 is a schematic diagram of a test principle of a test circuit of a D flip-flop according to an embodiment of the present invention when testing a setup time of the D flip-flop.
Fig. 7 is a schematic diagram of a test principle of a test circuit of a D flip-flop according to an embodiment of the present invention when testing a hold time of the D flip-flop.
Detailed Description
The following presents a number of possible embodiments of the invention in order to provide a basic understanding of the invention and is not intended to identify key or critical elements of the invention or to delineate the scope of the invention. The terms "first," "second," and the like, when used herein, do not necessarily denote any order or priority, but rather may be used to more clearly distinguish one subject matter defined thereby from another.
Examples
Fig. 1 shows a schematic circuit diagram of a chip 90 according to an embodiment of the present invention, in which a digital integrated circuit 20 using a D flip-flop 21 and a test circuit 10 of the D flip-flop according to an embodiment of the present invention are disposed in the chip 10. The chip 90 may be a digital IC chip with the test circuit 10 or a test chip manufactured specifically for testing the digital integrated circuit 20. The particular type, structure, and/or function of digital integrated circuit 20 is not limiting. A plurality of D flip-flops 21 in the digital integrated circuit 20 may be an object to be tested, which may be arranged in an array of time-ordered cells (SCUT, sequential Circuit Under Test) to form a SCUT array as shown in fig. 1. The number of D flip-flops 21 in the SCUT array is not limited, and one or more D flip-flops 21 in the SCUT array may be selected for testing of timing information by the decoder 22 or the like in the digital integrated circuit 20; wherein sel_ff [7:0] is a selection signal input to the decoder 22 for selecting the D flip-flop 21 to be tested, RST is a set signal of the decoder 22, and EN is an enable signal of the decoder 22.
In the chip 90, the test circuit 10 may be provided independently from the digital integrated circuit 20, and the two parts of the test circuit 10 and the digital integrated circuit 20 may be manufactured together under the process condition of a certain node. It will be appreciated that the test circuit 10 itself is also prone to process fluctuation disturbances and has some interconnect line delay, particularly as feature sizes become smaller and smaller. The test circuit 10 may be used to test timing information of a selected D flip-flop 21 in the digital integrated circuit 20, such as parameters of setup time and hold time of the D flip-flop 21. As shown in fig. 2, the setup time refers to the time that the data needs to remain unchanged immediately before the sampling edge of the clock CLK, and includes both low (d_low) and high (d_high) data; the hold time refers to the time after the sampling edge of the clock CLK that the data needs to remain unchanged, and the data is also both high (d_high) and low (d_low).
Referring to fig. 1, the test circuit 10 mainly includes a delay generating module 110, a path selector 130, an oscillator circuit 140, and in an embodiment, an output module implemented by, for example, a frequency divider 150, a third selector 119, and the like.
Referring to fig. 1 and 3, the delay generation module 110 may include a first delay path 111, and a second delay path 112; in an embodiment, the first delay path 111 may be used to provide the first delayed output signal p1 to the clock terminal CLK of the D flip-flop under test 21, and the second delay path 112 may be used to provide the second delayed output signal p2 to the data terminal D of the D flip-flop under test 21; in yet another alternative embodiment, the first delay path 111 may be used to provide the first delayed output signal p1 to the data terminal D of the D flip-flop under test 21 and the second delay path 112 may be used to provide the second delayed output signal p2 to the clock terminal CLK of the D flip-flop under test 21. The first delay path 111 and the second delay path 112 may be dynamically configured such that they output the first delay output signal p1 and the second delay output signal p2 with a variable delay difference Δd (as shown in fig. 6, for example, the delay difference Δd is continuously decreasing from Δd0, Δd1, Δd2, …, to Δd_out), and a dynamic configuration manner of the first delay path 111 and the second delay path 112 will be exemplified and applied to a dynamic configuration stage of the test method as shown in fig. 6.
In an embodiment, as shown in fig. 3, the first delay path 111 includes a first delay chain 1111 formed by connecting a plurality of first delay units 1101 in series, and the second delay path includes a second delay chain 1121 formed by connecting a plurality of second delay units 1102 in series, where the first delay units 1101 and the second delay units 1102 may be implemented as delay gates, for example, specifically implemented by inverters. The delay time generated by the single first delay unit 1101 may be different from the delay time generated by the single second delay unit 1102, e.g. the delay time generated by the single second delay unit 1102 is shorter than the delay time generated by the single first delay unit 1101. Specifically, referring to fig. 5, different delays may be achieved by setting gate structures of the first inverter 1101 corresponding to the first delay unit and the second inverter 1102 corresponding to the second delay unit, for example, a PMOS transistor and an NMOS transistor of the first inverter 1101 have the same gate width but have different gate lengths as those of the second inverter 1102, respectively, and their gate length differences from each other may determine the magnitude of the delay difference between the first inverter 1101 and the second inverter 1102, and further may determine the maximum accuracy of the delay difference Δd change (for example, reaching picosecond level) during dynamic configuration.
The number of first delay units 1101 preset in the first delay chain 1111 may be determined at the time of manufacture (for example, 256), but whether they are configured to be valid may be controlled by the first configuration control signal sel1_del [7:0 ]; likewise, the number of second delay cells 1102 preset in the second delay chain 1112 may be determined at the time of manufacture (e.g., 255), but whether they are configured to be valid may be controlled by the second configuration control signal sel2_del [7:0 ]. To this end, the first delay path 111 further comprises a first selector 1112 arranged corresponding to the first delay chain 1111, wherein the first selector 1112 may be set with different first configuration control signals sel1_del [7:0] to select different numbers of the first delay cells 1101 in the first delay chain 1111 to be configured to be active, thereby enabling the first delay path 111 to be dynamically configured, and the first delay output signal p1 of the first delay path 111 may be dynamically adjusted to vary; the second delay path 112 further includes a second selector 1122 arranged corresponding to the second delay chain 1121, wherein the second selector 1122 may be arranged with different second configuration control signals sel2_del [7:0] to select different numbers of the second delay cells 1102 in the second delay chain 1121 to be configured active, thereby enabling the second delay path 112 to be dynamically configured, and the second delay output signal p2 of the second delay path 112 may be dynamically adjusted. The first selector 1112 and the second selector 1122 may be specifically 256-choice 1 selectors.
In particular, in the case where the delay generated by the single first delay unit 1101 may be different from the delay generated by the single second delay unit 1102, the first configuration control signal sel1_del [7:0] and the second configuration control signal sel2_del [7:0] may be the same (e.g., both the sel_del [7:0] as shown in fig. 6 are input), so that the number of the first delay units 1101 configured to be active in the first delay chain 1111 is equal to the number of the second delay units 1102 configured to be active in the second delay chain 1121 (i.e., the effective chain lengths of the first delay chain 1111 and the second delay chain 1121 are equal), the effective chain lengths of the first delay chain 1111 and the second delay chain 1121 are synchronously changed, and different delay differences Δd may also be generated between the first delay output signal p1 and the second delay output signal p2 with the synchronous change of the effective chain lengths, and thus, it is relatively easy to control the dynamic configuration and the change of the delay differences Δd is finer.
For example, referring to fig. 3 and 6, in the dynamic configuration phase, by controlling the change of the first configuration control signal sel1_del [7:0] and the second configuration control signal sel2_del [7:0], the effective chain length of the first delay chain 1111 and the second delay chain 1121 can be controlled to gradually change from 256 to 1, the delay difference Δd between the first delay output signal p1 of the first delay path 111 and the first delay output signal p2 of the first delay path 112 will gradually linearly decrease until the time point of the rising edge of the third output signal Q of the tested D flip-flop 21 and the corresponding clock terminal CLK (i.e., the rising edge of the second delay output signal p2 or the first delay output signal p 1) is inconsistent with the data terminal D, the change of the first delay output signal p 1_del [7:0] and the second configuration control signal sel2_del [7:0] is stopped, the corresponding configuration of the first delay path 111 and the second delay path 112 is fixed, and the effective delay difference Δd between the first delay chain length of the first delay path 112 and the corresponding delay output signal p1 is also fixed, i.e.e., the first delay chain length 1 and the first delay chain length of delay output signal p1 is fixed.
It will be appreciated that in other alternative embodiments, the delay generated by a single first delay unit 1101 may be equal to the delay generated by a single second delay unit 1102, and during dynamic configuration, the first configuration control signal sel1_del [7:0] and the second configuration control signal sel2_del [7:0] may be different, such that the number of first delay units 1101 in the first delay chain 1111 that are configured to be active is not equal to the number of second delay units 1102 in the second delay chain 1121 that are configured to be active (i.e., the effective chain lengths of the first delay chain 1111 and the second delay chain 1121 are not equal), and the effective chain lengths of the first delay chain 1111 and the second delay chain 1121 vary asynchronously, and the first delay output signal p1 and the second delay output signal p2 may also vary with the difference in effective chain lengths therebetween, until the third output signal Q of the tested D flip-flop 21 and the corresponding data point on the corresponding delay chain 1 and the data point d_delay 1 and the corresponding to the data point on the first delay chain 1 and the second delay chain 1:7 change, and the second delay output signal p2 may also vary in different delay paths [ 1:1 ] and the corresponding to the second delay chain 1 and the data point 1 and the second delay chain 1 change in a fixed manner.
With continued reference to fig. 1 and 4, the oscillator circuit 140 may be formed of several inverters, which may form a loop with either of the first delay path 111 and the second delay path 112, thereby forming a first oscillation loop 1401 or a second oscillation loop 1402.
The path selector 130 may be a MUX of 2 or 1, which may be triggered to operate when the third output signal Q of the D flip-flop 21 under test is not consistent in data with the data terminal D at the rising edge time point of the corresponding clock terminal CLK, that is, is triggered to operate in the oscillation output phase as shown in fig. 6; the path selector 130 respectively switches the first delay path 111 and the second delay path 112 in the respective configurations (e.g., in case of a fixed effective chain length) into the oscillator circuit 140 so as to respectively form a first oscillation loop 1401 and a second oscillation loop 1402, the first oscillation loop 1401 may output a first oscillation output signal ro_out1 having a first period T1 (see fig. 6), and the second oscillation loop 1402 may output a second oscillation output signal ro_out2 having a second period T2 (see fig. 6), wherein the first period T1 and the second period T2 may be used to calculate or characterize the respective timing information (e.g., a setup time or a hold time).
Specifically, the path selection signal sel_ro may be applied to the path selector 130 to select one of the first delay path 111 and the second delay path 112 to be respectively connected to the oscillator circuit 140 in the oscillation output stage.
It should be noted that, unlike the conventional test circuit, the test circuit 10 of the above embodiment may put the whole first delay path 111 or the second delay path 112 outside the tested time sequence unit into the oscillation loop, and the period of the oscillation output signal of the oscillation loop 1401 or 1402 includes the whole delay of the delay path of the test circuit 10, so that the test result easily eliminates the influence of the process fluctuation and the interconnect delay on the two delay paths on the test result, that is, the influence of the interconnect delay and the process fluctuation of the test circuit 10 itself on the time sequence information of the D flip-flop 21 to be tested, and the test result is relatively more accurate, for example, may reach picoseconds.
In an embodiment, referring to fig. 1 and 4, the first oscillation output signal ro_out1 or the second oscillation output signal ro_out2 is output through the and gate 141 in case that the first oscillation loop 1401 or the second oscillation loop 1402 stably operates; wherein the output process can be controlled by controlling the oscillation loop output enable signal rst_freq applied to the and gate 141.
As further shown in fig. 1, in one embodiment, considering that the first period T1 and the second period T2 are too short to be used to calculate or characterize the setup time or the hold time, the test circuit 10 may further include an output module, which may be implemented by, but not limited to, the frequency divider 150, where the frequency divider 150 may receive the first oscillation output signal ro_out1 and output the fourth output information out_t1 (e.g., frequency-divided output information) for amplifying the first period T1, and may also receive the second oscillation output signal ro_out2 and output the fifth output information out_t2 (e.g., frequency-divided output information) for amplifying the second period T2, where the fourth output information out_t1 and the fifth output information out_t2 are used to calculate corresponding timing information.
As shown in fig. 1, in an embodiment, to conveniently implement the test circuit 10 while being compatible with the test setup time and the hold time, the corresponding delay generating module 110 further includes a third selector 119, the third selector 119 being configured to: under the condition that the time for establishing the test time sequence information is required, the first delay output signal p1 and the second delay output signal p2 are selected to be respectively provided to the clock end CLK and the data end D, and under the mode of testing the retention time of the time sequence information, the first delay output signal p1 and the second delay output signal p2 are selected to be respectively provided to the data end D and the clock end CLK; that is, the third selector 119 may output the two delay paths interchangeably to switch between the test setup time and the hold time conveniently. The third selector 119 may be controlled by a selection signal sel_path to implement the switching operation described above.
It should be noted that the test circuit 10 may operate in one of a dynamic configuration mode and an oscillation output mode. The switching of the two modes can be realized by a mode control signal mode; when mode=1, the test circuit 10 operates in the dynamic configuration mode and enters the dynamic configuration phase of the test procedure, and when mode=0, the test circuit 10 operates in the oscillation output mode and enters the oscillation output phase of the test procedure.
The method of testing the timing information of the D flip-flop 10 according to an embodiment of the present invention, which includes a dynamic configuration phase and an oscillation output phase, is further illustrated below in conjunction with the operational waveforms shown in fig. 1 and 6.
First, a signal, which is typically a reference square wave signal, is generated, which is applied to the delay generating module 110 to configure delay chains on the first delay path 111 and the second delay path 112 to be longest, and at this time, the first delay output signal p1 and the second delay output signal p2 have the largest delay difference, i.e., the initial delay difference Δd0.
Taking the test to set up a certain set time of the selected D flip-flop 21 as an example, the first delay output signal p1 output by the first delay path 111 of the delay generating module 110 is provided to the clock terminal CLK of the D flip-flop 21 under test, and the second delay output signal p2 output by the second delay path 112 of the delay generating module 110 is provided to the data terminal D of the D flip-flop 21 under test. That is, the data terminal D is connected to the end of the first delay path 111 with smaller delay cells, such as p2 in fig. 3, and the clock terminal CLK is connected to the end with larger delay, such as p1.
Further, the first delay path 111 and the second delay path 112 are dynamically configured such that the delay difference Δd between the first delay output signal p1 and the second delay output signal p2 that they dynamically output changes until the third output signal Q of the D flip-flop 21 under test is not consistent in data at the rising edge of the corresponding clock terminal CLK, and the first delay path 111 and the second delay path 112 are stopped from being dynamically configured. During this dynamic configuration, the effective chain length of the first delay chain 1111 and the second delay chain 1121 may be controlled by controlling the first configuration control signal sel1_del [7:0] and the second configuration control signal sel2_del [7:0] applied to the delay generating module 110, by way of example, the first configuration control signal sel1_del [7:0] and the second configuration control signal sel2_del [7:0] are continuously reduced, the delay chains selected by the first selector 1112 and the second selector 1122 are continuously shortened, at which time the delay difference Δd between the data end D of the D flip-flop and the rising edge of the signal of the clock end CLK (e.g., between the rising edges of p1 and p 2) is continuously reduced (as shown in fig. 6, e.g., the delay difference Δd is continuously linearly reduced from Δd0, Δd1, Δd2, …, to Δd_out); meanwhile, the third output signal Q corresponding to the Q terminal of the D flip-flop 21 is continuously observed, and when the third output signal Q is inconsistent with the second delayed output signal p2 of the data terminal D in data at a certain rising edge time point of the first delayed output signal p1 (i.e. a certain rising edge time point of the clock terminal CLK) (for example, when the sampling value of the Q terminal at the rising edge time point of the p1 is not exactly equal to the input value of the data terminal D at the time point), the setup time is invalid, and the difference between the rising edge of the data terminal D and the rising edge of the clock terminal CLK is the corresponding setup time.
Further, the oscillation output phase is entered, in particular controlled by a transformation of the input value of the mode control signal mode. In the oscillation output phase, first, the first delay path 111 and the second delay path 112 in the corresponding configurations are respectively connected to the oscillator circuit 140, so as to form a first oscillation loop 1401 and a second oscillation loop 1402, respectively; this step may be achieved by applying a corresponding path selection signal sel_ro to the path selector 130.
In the oscillation output stage, further, the first oscillation output signal ro_out1 or the second oscillation output signal ro_out2 (as shown in fig. 6) is output through the and gate 141 in a state where the first oscillation loop 1401 or the second oscillation loop 1402 stably operates, so that the first period T1 of the first oscillation output signal ro_out1 and the second period T2 of the second oscillation output signal ro_out2 can be obtained.
In one embodiment, the oscillation output phase of the test method further comprises the steps of: the method comprises the steps of receiving a first oscillation output signal ro_out1 and outputting fourth output information out_T1 for amplifying a first period T1, receiving a second oscillation output signal ro_out2 and outputting fifth output information out_T2 for amplifying a second period T2, wherein the fourth output information out_T1 and the fifth output information out_T2 are used for calculating corresponding time sequence information. Illustratively, in this step, the received first and second oscillation output signals ro_out1 and ro_out2 are subjected to frequency division processing, and the periods T1 'and T2' are obtained from the first and second periods T1 and T2, respectively. Thus, the setup time can ultimately be calculated by (T1 '-T2')/(2*k), where k is the division multiple.
To this end, the setup time of the resulting D flip-flop 21 can be tested.
When the hold time of the D flip-flop 21 is tested, the test procedure is basically the same as the test setup time procedure described above, and only the first delay output signal p1 and the second delay output signal p2 need to be changed to be respectively provided to the data terminal D and the clock terminal CLK, that is, the two delay paths are output in a switching manner, and the switching operation can be controlled by the selection signal sel_path; accordingly, during the dynamic configuration phase, the third output signal Q corresponding to the Q terminal of the D flip-flop 21 is continuously observed, and at a certain rising edge time point of the second delayed output signal p2 (i.e. a certain rising edge time point of the clock terminal CLK), when the third output signal Q is just inconsistent with the first delayed output signal p1 of the data terminal D in data (e.g. when the value of the sampling of the Q terminal at the rising edge time point of p2 is just unequal to the input value of the data terminal D at the time point), the retention time is invalid, and the difference between the rising edge of the data terminal D and the rising edge of the clock terminal CLK is the corresponding retention time. A timing diagram for testing the hold time of the D flip-flop is shown in fig. 7.
The test method of the above embodiment can effectively eliminate the influence of process fluctuation of the delay path of the test circuit 10 itself and the interconnect delay on the test result, the setup time, the hold time, etc. of the D flip-flop 21 can be accurately tested, and particularly, in the case where the delay time generated by the single first delay unit 1101 can be different from the delay time generated by the single second delay unit 1102, the test accuracy is higher.
The above examples mainly illustrate the test circuit and the test method of the present invention. Although only a few embodiments of the present invention have been described, those skilled in the art will appreciate that the present invention can be embodied in many other forms without departing from the spirit or scope thereof. Accordingly, the present examples and embodiments are to be considered as illustrative and not restrictive, and the invention is intended to cover various modifications and substitutions without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (17)
1. A test circuit for a D flip-flop for testing timing information of the D flip-flop in a digital integrated circuit, the test circuit comprising:
the delay generation module comprises a first delay path and a second delay path, wherein the first delay path and the second delay path are respectively used for providing a first delay output signal to a clock end of the D trigger to be tested and a second delay output signal to the clock end of the D trigger to be tested, or respectively used for providing a first delay output signal to a data end of the D trigger to be tested and a second delay output signal to the clock end of the D trigger to be tested, and the first delay path and the second delay path can be dynamically configured so that a variable delay difference exists between the first delay output signal and the second delay output signal;
an oscillator circuit; and
and a path selector for respectively accessing the first delay path and the second delay path in a corresponding configuration to the oscillator circuit when the third output signal of the D flip-flop under test is not consistent in data with the data terminal at a rising edge time point corresponding to the clock terminal, so as to respectively form a first oscillation loop for outputting a first oscillation output signal having a first period and a second oscillation loop for outputting a second oscillation output signal having a second period, wherein the first period and the second period can be used for calculating or characterizing the corresponding timing information.
2. The test circuit of the D flip-flop of claim 1 wherein said delay generation module is configured to fix respective configurations of said first and second delay paths when a third output signal of said D flip-flop under test is not data-wise coincident with said data terminal at a rising edge time point corresponding to said clock terminal.
3. The test circuit of a D flip-flop of claim 1 or 2, wherein said first delay path comprises a first delay chain formed by a plurality of first delay cells connected in series, and said second delay path comprises a second delay chain formed by a plurality of second delay cells connected in series, wherein the delay produced by a single one of said first delay cells is different from the delay produced by a single one of said second delay cells.
4. The test circuit of the D flip-flop of claim 3 wherein said first delay path further comprises a first selector disposed corresponding to said first delay chain, wherein said first selector is biasable by different first configuration control signals to select different numbers of first delay cells in said first delay chain to be configured active so as to enable said first delay path to be dynamically configured;
the second delay path further comprises a second selector arranged corresponding to the second delay chain, wherein the second selector can be biased with different second configuration control signals to select different numbers of second delay cells in the second delay chain to be configured to be active, so that the second delay path is dynamically configured.
5. The test circuit of the D flip-flop of claim 3 wherein said first delay cell and said second delay cell are a first inverter and a second inverter, respectively.
6. The test circuit of the D flip-flop of claim 5 wherein said PMOS and NMOS transistors of said first inverter have the same gate width but different gate lengths than said PMOS and NMOS transistors of said second inverter, respectively.
7. The test circuit of the D flip-flop of claim 1, wherein said delay generation module further comprises a third selector configured to select to supply said first delay output signal and said second delay output signal to said clock terminal and said data terminal, respectively, in case a setup time of said timing information needs to be tested, and to supply said first delay output signal and said second delay output signal to said data terminal and said clock terminal, respectively, in case a hold time of said timing information needs to be tested.
8. The test circuit of the D flip-flop of claim 1, said test circuit further comprising:
the output module is used for receiving the first oscillation output signal and outputting fourth output information for amplifying the first period, receiving the second oscillation output signal and outputting fifth output information for amplifying the second period, wherein the fourth output information and the fifth output information are used for calculating to obtain corresponding time sequence information.
9. The test circuit of the D flip-flop of claim 8 wherein said output means comprises a frequency divider.
10. The test circuit of a D flip-flop according to claim 1, wherein the first oscillation output signal or the second oscillation output signal is output through an and gate in a case where the first oscillation loop or the second oscillation loop stably operates.
11. The test circuit of a D flip-flop according to claim 1, wherein said timing information comprises a setup time and/or a hold time.
12. A chip comprising a digital integrated circuit having a D flip-flop, further comprising a test circuit for testing timing information of the D flip-flop according to any one of claims 1 to 11.
13. A method of testing a test circuit as claimed in claim 1, comprising the steps of:
providing a first delay output signal output by a first delay path of the delay generating module to a clock end/data end of the D trigger to be tested, and providing a second delay output signal output by a second delay path of the delay generating module to a data end/clock end of the D trigger to be tested;
dynamically configuring the first and second delay paths to vary a delay difference between the first and second delay output signals that they dynamically output until a third output signal of the D flip-flop under test is not data-wise consistent with the data terminal at a rising edge time point corresponding to the clock terminal, stopping dynamically configuring the first and second delay paths;
the first delay path and the second delay path in corresponding configurations are respectively connected to the oscillator circuit, so that a first oscillation loop and a second oscillation loop are respectively formed; and
and receiving a first oscillation output signal with a first period output by the first oscillation loop and a second oscillation output signal with a second period output by the second oscillation loop, wherein the first period and the second period can be used for calculating or representing the corresponding time sequence information.
14. The test method of claim 13, wherein respective configurations of the first delay path and the second delay path are fixed when a third output signal of the D flip-flop under test is not consistent in data with the data terminal at a rising edge time point corresponding to the clock terminal.
15. The test method of claim 13, wherein in dynamically configuring the first delay path, a different number of first delay cells are selected in a first delay chain of the first delay path by a first configuration control signal and are configured to be active;
in the process of dynamically configuring the second delay path, different numbers of second delay units in the second delay chain are selected and configured to be effective through a second configuration control signal.
16. The test method of claim 13, wherein the timing information includes a setup time and/or a hold time; when testing the time for establishing the time sequence information, the first delay output signal and the second delay output signal are respectively provided to the clock end and the data end;
and when testing the retention time of the time sequence information, respectively providing the first delay output signal and the second delay output signal to the data end and the clock end.
17. The test method of claim 13, further comprising the step of:
and receiving the first oscillation output signal and outputting fourth output information for amplifying the first period, and receiving the second oscillation output signal and outputting fifth output information for amplifying the second period, wherein the fourth output information and the fifth output information are used for calculating to obtain corresponding time sequence information.
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1656384A (en) * | 2002-03-26 | 2005-08-17 | 麦克吉尔大学 | Timing measurement device using a component-invariant vernier delay line |
| US20070080701A1 (en) * | 2005-10-08 | 2007-04-12 | Samsung Electronics Co., Ltd. | Apparatus for measuring on-chip characteristics in semiconductor circuits and related methods |
| US20100102890A1 (en) * | 2008-10-27 | 2010-04-29 | Asic North, Inc. | Variable-Loop-Path Ring Oscillator Test Circuit and Systems and Methods Utilizing Same |
| CN102495349A (en) * | 2011-12-12 | 2012-06-13 | 中国科学院深圳先进技术研究院 | Path delay on-line measurement circuit |
| CN104660240A (en) * | 2015-01-04 | 2015-05-27 | 北京化工大学 | Overspeed delay testing clock generator |
| CN110033819A (en) * | 2018-01-11 | 2019-07-19 | 中芯国际集成电路制造(上海)有限公司 | SRAM establishes retention time test circuit |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010028600A (en) * | 2008-07-23 | 2010-02-04 | Sony Corp | Tdc circuit, pll circuit, and wireless communication apparatus |
-
2020
- 2020-07-01 CN CN202010624254.6A patent/CN113884865B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1656384A (en) * | 2002-03-26 | 2005-08-17 | 麦克吉尔大学 | Timing measurement device using a component-invariant vernier delay line |
| US20070080701A1 (en) * | 2005-10-08 | 2007-04-12 | Samsung Electronics Co., Ltd. | Apparatus for measuring on-chip characteristics in semiconductor circuits and related methods |
| US20100102890A1 (en) * | 2008-10-27 | 2010-04-29 | Asic North, Inc. | Variable-Loop-Path Ring Oscillator Test Circuit and Systems and Methods Utilizing Same |
| CN102495349A (en) * | 2011-12-12 | 2012-06-13 | 中国科学院深圳先进技术研究院 | Path delay on-line measurement circuit |
| CN104660240A (en) * | 2015-01-04 | 2015-05-27 | 北京化工大学 | Overspeed delay testing clock generator |
| CN110033819A (en) * | 2018-01-11 | 2019-07-19 | 中芯国际集成电路制造(上海)有限公司 | SRAM establishes retention time test circuit |
Non-Patent Citations (2)
| Title |
|---|
| 施朝霞等.D触发器动态参数与电路结构关系分析.《科技创新导报》.2017,第14卷(第19期),全文. * |
| 苟军林等.一种延长NAND闪存寿命的新策略.《半导体技术》.2019,第44卷(第09期),全文. * |
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