CN113724773A - Memory management method, memory storage device and memory control circuit unit - Google Patents

Memory management method, memory storage device and memory control circuit unit Download PDF

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Publication number
CN113724773A
CN113724773A CN202111076097.0A CN202111076097A CN113724773A CN 113724773 A CN113724773 A CN 113724773A CN 202111076097 A CN202111076097 A CN 202111076097A CN 113724773 A CN113724773 A CN 113724773A
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temperature state
unit
memory
data
temperature
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CN202111076097.0A
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CN113724773B (en
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简佳帆
林纬
许祐诚
杨宇翔
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Phison Electronics Corp
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Phison Electronics Corp
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/12005—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising voltage or current generators
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/14—Implementation of control logic, e.g. test mode decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38—Response verification devices
    • G11C29/42—Response verification devices using error correcting codes [ECC] or parity check
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C2029/1802—Address decoder
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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Abstract

The invention provides a memory management method, a memory storage device and a memory control circuit unit. The method comprises the following steps: detecting a first temperature state of the rewritable nonvolatile memory module; performing a first write operation on the first physical unit at a first temperature state to store first data into the first physical unit; after the first writing operation is executed, detecting a second temperature state of the rewritable nonvolatile memory module; and in response to the first temperature state and the second temperature state meeting the first condition, performing a data refresh operation on the first physical unit at the second temperature state to restore the first data to a second physical unit, wherein the second physical unit is different from the first physical unit. Therefore, the reliability of data access to the rewritable nonvolatile memory module in an environment with severe temperature change can be improved.

Description

Memory management method, memory storage device and memory control circuit unit
Technical Field
The present invention relates to a memory management technology, and more particularly, to a memory management method, a memory storage device and a memory control circuit unit.
Background
Portable electronic devices such as mobile phones and notebook computers have grown rapidly in these years, so that the demand of consumers for storage media has also increased rapidly. Since a rewritable non-volatile memory module (e.g., a flash memory) has the characteristics of non-volatility, power saving, small volume, and no mechanical structure, it is very suitable for being built in various portable electronic devices as exemplified above.
The memory cells in a rewritable non-volatile memory module store data in the form of voltages. For example, data is stored by applying a write voltage to the memory cell and/or read by applying a read voltage to the memory cell. However, if the temperature difference between reading and writing to a certain memory cell is too large, the error rate of data read from the memory cell subsequently tends to be greatly increased.
Disclosure of Invention
The invention provides a memory management method, a memory storage device and a memory control circuit unit, which can improve the reliability of data access to a rewritable nonvolatile memory module in an environment with severe temperature change.
Example embodiments of the present invention provide a memory management method for a memory storage device. The memory storage device comprises a rewritable nonvolatile memory module. The rewritable nonvolatile memory module comprises a plurality of entity units. The memory management method comprises the following steps: detecting a first temperature state of the rewritable nonvolatile memory module; performing a first write operation on a first physical unit of the plurality of physical units in the first temperature state to store first data into the first physical unit; detecting a second temperature state of the rewritable non-volatile memory module after the first writing operation is executed; and in response to the first temperature state and the second temperature state meeting a first condition, performing a data refresh operation on the first physical cell in the second temperature state to restore the first data to a second physical cell of the plurality of physical cells, wherein the second physical cell is different from the first physical cell.
In an exemplary embodiment of the invention, the memory management method further includes: obtaining a trigger threshold corresponding to the first temperature state; obtaining a temperature value of the rewritable nonvolatile memory module in the second temperature state; comparing the trigger threshold value with the temperature value; and judging whether the first temperature state and the second temperature state meet the first condition according to the comparison result.
In an exemplary embodiment of the invention, the memory management method further includes: obtaining first temperature state identification information corresponding to the first temperature state; obtaining second temperature state identification information corresponding to the second temperature state; performing a logical operation on the first temperature state identification information and the second temperature state identification information; and judging whether the first temperature state and the second temperature state meet the first condition according to the execution result of the logic operation.
In an exemplary embodiment of the invention, the step of detecting the second temperature state of the rewritable non-volatile memory module comprises: receiving a write command from a host system; and responding to the write instruction to judge whether the first temperature state and the second temperature state meet the first condition.
In an exemplary embodiment of the invention, the memory management method further includes: in response to the first temperature state and the second temperature state meeting the first condition, performing a second write operation on the second physical unit at the second temperature state to store second data indicated by the write instruction into the second physical unit; and updating the temperature state identification information corresponding to the second entity unit according to the second temperature state.
In an exemplary embodiment of the invention, the memory management method further includes: performing a second write operation on the first physical unit in the second temperature state to store second data indicated by the write instruction into the first physical unit; and in the data refreshing operation, reading the first data and the second data out of the first entity unit and storing the first data and the second data into the second entity unit.
In an exemplary embodiment of the invention, the memory management method further includes: recording temperature state identification information corresponding to the first entity unit according to the first temperature state; in response to the first temperature state and the second temperature state not meeting the first condition, performing a third write operation on the first physical unit at the second temperature state to store second data indicated by the write instruction into the first physical unit; and updating the temperature state identification information corresponding to the first entity unit according to the second temperature state.
In an exemplary embodiment of the invention, the memory management method further includes: under the first temperature state, instructing the rewritable non-volatile memory module to program at least one memory cell in the first entity unit by using a first electrical parameter; and instructing the rewritable non-volatile memory module to program the at least one memory cell by using a second electrical parameter in the second temperature state, wherein the first electrical parameter is different from the second electrical parameter.
An exemplary embodiment of the present invention further provides a memory storage device, which includes a connection interface unit, a rewritable nonvolatile memory module and a memory control circuit unit. The connection interface unit is used for connecting to a host system. The rewritable nonvolatile memory module comprises a plurality of entity units. The memory control circuit unit is connected to the connection interface unit and the rewritable nonvolatile memory module. The memory control circuit unit is used for detecting a first temperature state of the rewritable nonvolatile memory module. The memory control circuit unit is further configured to perform a first write operation on a first physical unit of the plurality of physical units in the first temperature state to store first data in the first physical unit. After the first write operation is performed, the memory control circuit unit is further configured to detect a second temperature state of the rewritable non-volatile memory module. In response to the first temperature state and the second temperature state meeting a first condition, the memory control circuit unit is further configured to perform a data refresh operation on the first physical unit in the second temperature state to restore the first data to a second physical unit of the plurality of physical units, wherein the second physical unit is different from the first physical unit.
In an exemplary embodiment of the invention, the memory control circuit unit is further configured to: obtaining a trigger threshold corresponding to the first temperature state; obtaining a temperature value of the rewritable nonvolatile memory module in the second temperature state; comparing the trigger threshold value with the temperature value; and judging whether the first temperature state and the second temperature state meet the first condition according to the comparison result.
In an exemplary embodiment of the invention, the memory control circuit unit is further configured to: obtaining first temperature state identification information corresponding to the first temperature state; obtaining second temperature state identification information corresponding to the second temperature state; performing a logical operation on the first temperature state identification information and the second temperature state identification information; and judging whether the first temperature state and the second temperature state meet the first condition according to the execution result of the logic operation.
In an exemplary embodiment of the invention, the memory control circuit unit is further configured to: in response to the first temperature state and the second temperature state meeting the first condition, performing a second write operation on the second physical unit at the second temperature state to store second data indicated by the write instruction into the second physical unit; and updating the temperature state identification information corresponding to the second entity unit according to the second temperature state.
In an exemplary embodiment of the invention, the memory control circuit unit is further configured to: performing a second write operation on the first physical unit in the second temperature state to store second data indicated by the write instruction into the first physical unit; and in the data refreshing operation, instructing the rewritable nonvolatile memory module to read the first data and the second data from the first entity unit and store the first data and the second data into the second entity unit.
In an exemplary embodiment of the invention, the memory control circuit unit is further configured to: recording temperature state identification information corresponding to the first entity unit according to the first temperature state; in response to the first temperature state and the second temperature state not meeting the first condition, performing a third write operation on the first physical unit at the second temperature state to store second data indicated by the write instruction into the first physical unit; and updating the temperature state identification information corresponding to the first entity unit according to the second temperature state.
In an exemplary embodiment of the invention, the memory control circuit unit is further configured to: under the first temperature state, instructing the rewritable non-volatile memory module to program at least one memory cell in the first entity unit by using a first electrical parameter; and instructing the rewritable non-volatile memory module to program the at least one memory cell by using a second electrical parameter in the second temperature state, wherein the first electrical parameter is different from the second electrical parameter.
An exemplary embodiment of the present invention further provides a memory control circuit unit for controlling a rewritable nonvolatile memory module. The rewritable nonvolatile memory module comprises a plurality of entity units. The memory control circuit unit comprises a host interface, a memory interface and a memory management circuit. The host interface is used for connecting to a host system. The memory interface is used for connecting to the rewritable nonvolatile memory module. The memory management circuit is connected to the host interface and the memory interface. The memory control circuit unit is used for detecting a first temperature state of the rewritable nonvolatile memory module. The memory management circuit is further configured to perform a first write operation on a first physical unit of the plurality of physical units at the first temperature state to store first data in the first physical unit. After the first write operation is performed, the memory management circuit is further configured to detect a second temperature state of the rewritable non-volatile memory module. In response to the first temperature state and the second temperature state meeting a first condition, the memory management circuit is further configured to perform a data refresh operation on the first physical cells in the second temperature state to restore the first data to a second physical cell of the plurality of physical cells, wherein the second physical cell is different from the first physical cell.
In an exemplary embodiment of the invention, the first condition includes that a temperature difference between the temperature value corresponding to the first temperature state and the temperature value corresponding to the second temperature state reaches a threshold value or falls within a specific value range.
In an exemplary embodiment of the invention, the memory management circuit is further configured to: obtaining a trigger threshold corresponding to the first temperature state; obtaining a temperature value of the rewritable nonvolatile memory module in the second temperature state; comparing the trigger threshold value with the temperature value; and judging whether the first temperature state and the second temperature state meet the first condition according to the comparison result.
In an exemplary embodiment of the invention, the memory management circuit is further configured to: obtaining first temperature state identification information corresponding to the first temperature state; obtaining second temperature state identification information corresponding to the second temperature state; performing a logical operation on the first temperature state identification information and the second temperature state identification information; and judging whether the first temperature state and the second temperature state meet the first condition according to the execution result of the logic operation.
In an exemplary embodiment of the invention, the operation of detecting the second temperature state of the rewritable non-volatile memory module comprises: receiving a write command from a host system; and responding to the write instruction to judge whether the first temperature state and the second temperature state meet the first condition.
In an exemplary embodiment of the invention, the memory management circuit is further configured to: in response to the first temperature state and the second temperature state meeting the first condition, performing a second write operation on the second physical unit at the second temperature state to store second data indicated by the write instruction into the second physical unit; and updating the temperature state identification information corresponding to the second entity unit according to the second temperature state.
In an exemplary embodiment of the invention, the memory management circuit is further configured to: performing a second write operation on the first physical unit in the second temperature state to store second data indicated by the write instruction into the first physical unit; and in the data refreshing operation, instructing the rewritable nonvolatile memory module to read the first data and the second data from the first entity unit and store the first data and the second data into the second entity unit.
In an exemplary embodiment of the invention, the memory management circuit is further configured to: recording temperature state identification information corresponding to the first entity unit according to the first temperature state; in response to the first temperature state and the second temperature state not meeting the first condition, performing a third write operation on the first physical unit at the second temperature state to store second data indicated by the write instruction into the first physical unit; and updating the temperature state identification information corresponding to the first entity unit according to the second temperature state.
In an exemplary embodiment of the invention, the memory management circuit is further configured to: under the first temperature state, instructing the rewritable non-volatile memory module to program at least one memory cell in the first entity unit by using a first electrical parameter; and instructing the rewritable non-volatile memory module to program the at least one memory cell by using a second electrical parameter in the second temperature state, wherein the first electrical parameter is different from the second electrical parameter.
Based on the above, after the first write operation is performed on the first entity unit to store the first data in the first temperature state of the rewritable non-volatile memory module, the second temperature state of the rewritable non-volatile memory module can be detected. In response to the first temperature state and the second temperature state meeting a first condition, a data refresh operation may be performed on a first physical cell in the second temperature state to restore first data to a second physical cell different from the first physical cell. Therefore, the reliability of data access to the rewritable nonvolatile memory module in an environment with severe temperature change can be improved.
Drawings
FIG. 1 is a diagram illustrating a host system, a memory storage device, and an input/output (I/O) device according to an example embodiment of the invention shown in FIG. 1;
FIG. 2 is a diagram illustrating a host system, a memory storage device, and an I/O device according to an example embodiment of the invention;
FIG. 3 is a schematic diagram of a host system and a memory storage device according to an exemplary embodiment of the invention;
FIG. 4 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention;
FIG. 5 is a schematic block diagram illustrating a memory control circuit unit according to an exemplary embodiment of the present invention;
FIG. 6 is a diagram illustrating management of a rewritable nonvolatile memory module according to an exemplary embodiment of the present invention;
FIG. 7 is a schematic diagram illustrating a first write operation according to an exemplary embodiment of the present invention;
FIG. 8 is a schematic diagram illustrating a data refresh operation according to an exemplary embodiment of the present invention;
FIG. 9 is a diagram illustrating a data refresh operation and a second write operation according to an exemplary embodiment of the present invention;
FIG. 10 is a diagram illustrating a third write operation according to an exemplary embodiment of the present invention;
FIG. 11 is a diagram illustrating triggering or not triggering a data refresh operation in different temperature change states according to an exemplary embodiment of the present invention;
FIG. 12 is a diagram illustrating triggering or not triggering a data refresh operation in different temperature change states according to an exemplary embodiment of the present invention;
FIG. 13 is a flowchart illustrating a memory management method according to an example embodiment of the invention.
Detailed Description
Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts.
Generally, a memory storage device (also referred to as a memory storage system) includes a rewritable non-volatile memory module (rewritable non-volatile memory module) and a controller (also referred to as a control circuit). The memory storage device may be used with a host system so that the host system can write data to or read data from the memory storage device.
FIG. 1 is a diagram illustrating a host system, a memory storage device, and an input/output (I/O) device according to an example embodiment of the invention. FIG. 2 is a diagram illustrating a host system, a memory storage device, and an I/O device according to an example embodiment of the invention.
Referring to fig. 1 and 2, the host system 11 may include a processor 111, a Random Access Memory (RAM) 112, a Read Only Memory (ROM) 113, and a data transmission interface 114. The processor 111, the RAM 112, the ROM 113, and the data transmission interface 114 may be connected to a system bus (system bus) 110.
In an example embodiment, the host system 11 may be connected to the memory storage device 10 through the data transmission interface 114. For example, host system 11 may store data to memory storage device 10 or read data from memory storage device 10 through data transfer interface 114. In addition, the host system 11 may be connected to the I/O device 12 via a system bus 110. For example, the host system 11 may transmit output signals to the I/O device 12 or receive input signals from the I/O device 12 over the system bus 110.
In an exemplary embodiment, the processor 111, the RAM 112, the ROM 113 and the data transmission interface 114 may be disposed on the motherboard 20 of the host system 11. The number of data transfer interfaces 114 may be one or more. The motherboard 20 may be connected to the memory storage device 10 by wire or wirelessly through the data transmission interface 114.
In an example embodiment, the memory storage device 10 may be, for example, a usb disk 201, a memory card 202, a Solid State Drive (SSD) 203, or a wireless memory storage device 204. The wireless memory storage 204 may be, for example, Near Field Communication (NFC) memory storage, wireless fidelity (WiFi) memory storage, Bluetooth (Bluetooth) memory storage, or Bluetooth low energy memory storage (e.g., iBeacon) based memory storage based on various wireless Communication technologies. In addition, the motherboard 20 may also be connected to various I/O devices such as a Global Positioning System (GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, and a speaker 210 via the System bus 110. For example, in an exemplary embodiment, the motherboard 20 may access the wireless memory storage device 204 via the wireless transmission device 207.
In an example embodiment, the host system 11 is a computer system. In an example embodiment, host system 11 may be any system that may substantially cooperate with a memory storage device to store data. In an example embodiment, the memory storage device 10 and the host system 11 may include the memory storage device 30 and the host system 31 of fig. 3, respectively.
FIG. 3 is a diagram illustrating a host system and a memory storage device according to an exemplary embodiment of the invention. Referring to FIG. 3, the memory storage device 30 can be used with a host system 31 to store data. For example, the host system 31 may be a system such as a digital camera, a video camera, a communication device, an audio player, a video player, or a tablet computer. For example, the memory storage device 30 may be a Secure Digital (SD) card 32, a Compact Flash (CF) card 33, or an embedded storage device 34 used by the host system 31. The embedded storage device 34 includes embedded Multi Media Card (eMMC) 341 and/or embedded Multi Chip Package (eMCP) storage device 342, which connect the memory module directly to the host system motherboard.
FIG. 4 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention. Referring to fig. 4, the memory storage device 10 includes a connection interface unit 41, a memory control circuit unit 42, and a rewritable nonvolatile memory module 43.
The connection interface unit 41 is used to connect the memory storage device 10 to the host system 11. The memory storage device 10 may communicate with the host system 11 through the connection interface unit 41. In an exemplary embodiment, the connection interface unit 41 is compatible with the PCI Express (Peripheral Component Interconnect Express) standard. However, it should be understood that the present invention is not limited thereto, and the connection interface unit 41 may also conform to Serial Advanced Technology Attachment (SATA) standard, Parallel Advanced Technology Attachment (PATA) standard, Institute of Electrical and Electronic Engineers (IEEE) 1394 standard, Universal Serial Bus (USB) standard, SD interface standard, Ultra High Speed-I (UHS-I) interface standard, Ultra High Speed-II (UHS-II) interface standard, Memory Stick (Memory Stick, MS) interface standard, MCP interface standard, MMC interface standard, eMMC interface standard, Universal Flash Memory (Flash) interface standard, CF interface standard, Device interface standard, and Electronic drive interface (Electronic interface), IDE) standard or other suitable standard. The connection interface unit 41 may be packaged with the memory control circuit unit 42 in one chip, or the connection interface unit 41 may be disposed outside a chip including the memory control circuit unit 42.
The memory control circuit unit 42 is connected to the connection interface unit 41 and the rewritable nonvolatile memory module 43. The memory control circuit unit 42 is used for executing a plurality of logic gates or control commands implemented in hardware or firmware and performing operations such as writing, reading and erasing data in the rewritable nonvolatile memory module 43 according to commands of the host system 11.
The rewritable nonvolatile memory module 43 is used for storing data written by the host system 11. The rewritable nonvolatile memory module 43 may include a Single Level Cell (SLC) NAND type flash memory module (i.e., a flash memory module that can store 1 bit in one memory Cell), a two-Level Cell (MLC) NAND type flash memory module (i.e., a flash memory module that can store 2 bits in one memory Cell), a Triple Level Cell (TLC) NAND type flash memory module (i.e., a flash memory module that can store 3 bits in one memory Cell), a Quad Level Cell (QLC) NAND type flash memory module (i.e., a flash memory module that can store 4 bits in one memory Cell), other flash memory modules, or other memory modules having the same characteristics.
Each memory cell in the rewritable nonvolatile memory module 43 stores one or more bits by a change in voltage (hereinafter also referred to as a threshold voltage). Specifically, each memory cell has a charge trapping layer between the control gate and the channel. By applying a write voltage to the control gate, the amount of electrons in the charge trapping layer can be varied, thereby varying the threshold voltage of the memory cell. This operation of changing the threshold voltage of the memory cell is also referred to as "writing data to the memory cell" or "programming" the memory cell. Each memory cell in the rewritable nonvolatile memory module 43 has a plurality of memory states as the threshold voltage changes. The read voltage is applied to determine which memory state a memory cell belongs to, thereby obtaining one or more bits stored in the memory cell.
In an exemplary embodiment, the memory cells of the rewritable nonvolatile memory module 43 may constitute a plurality of physical programming cells, and the physical programming cells may constitute a plurality of physical erasing cells. Specifically, memory cells on the same word line may constitute one or more physically programmed cells. If each memory cell can store more than 2 bits, the physical program cells on the same word line can be classified into at least a lower physical program cell and an upper physical program cell. For example, the Least Significant Bit (LSB) of a cell belongs to the lower physical program cell, and the Most Significant Bit (MSB) of a cell belongs to the upper physical program cell. Generally, in the MLC NAND flash memory, the writing speed of the lower physical program cell is faster than that of the upper physical program cell, and/or the reliability of the lower physical program cell is higher than that of the upper physical program cell.
In an exemplary embodiment, the physical program cell is a programmed minimum cell. That is, the physical programming unit is the minimum unit for writing data. For example, a physical programming unit can be a physical page (page) or a physical fan (sector). If the physical programming units are physical pages, the physical programming units may include a data bit region and a redundancy (redundancy) bit region. The data bit region includes a plurality of physical sectors for storing user data, and the redundancy bit region stores system data (e.g., management data such as error correction codes). In an exemplary embodiment, the data bit region includes 32 physical fans, and one physical fan has a size of 512 bytes (B). However, in other exemplary embodiments, the data bit region may include 8, 16 or more or less physical fans, and the size of each physical fan may be larger or smaller. On the other hand, the physically erased cell is the minimum unit of erase. That is, each physically erased cell contains the minimum number of memory cells that are erased together. For example, the physical erase unit is a physical block (block).
FIG. 5 is a schematic block diagram illustrating a memory control circuit unit according to an exemplary embodiment of the present invention. Referring to fig. 5, the memory control circuit unit 42 includes a memory management circuit 51, a host interface 52, and a memory interface 53.
The memory management circuit 51 is used to control the overall operation of the memory control circuit unit 42. Specifically, the memory management circuit 51 has a plurality of control commands, and the control commands are executed to perform data writing, reading, and erasing operations during the operation of the memory storage device 10. When the operation of the memory management circuit 51 is explained below, it is equivalent to the operation of the memory control circuit unit 42.
In an exemplary embodiment, the control instructions of the memory management circuit 51 are implemented in firmware. For example, the memory management circuit 51 has a microprocessor unit (not shown) and a read only memory (not shown), and the control commands are burned into the read only memory. When the memory storage device 10 is in operation, the control instructions are executed by the microprocessor unit to perform operations such as writing, reading, and erasing data.
In an exemplary embodiment, the control instructions of the memory management circuit 51 can also be stored in a program code type in a specific area of the rewritable nonvolatile memory module 43 (e.g., a system area dedicated to storing system data in the memory module). Further, the memory management circuit 51 has a microprocessor unit (not shown), a read only memory (not shown), and a random access memory (not shown). In particular, the ROM has a boot code (BOOT code), and when the memory control circuit unit 42 is enabled, the microprocessor unit first executes the boot code to load the control instructions stored in the rewritable nonvolatile memory module 43 into the RAM of the memory management circuit 51. Then, the microprocessor unit operates the control commands to perform data writing, reading, erasing, and the like.
In an exemplary embodiment, the control instructions of the memory management circuit 51 may also be implemented in a hardware form. For example, the memory management circuit 51 includes a microcontroller, a memory cell management circuit, a memory writing circuit, a memory reading circuit, a memory erasing circuit, and a data processing circuit. The memory unit management circuit, the memory writing circuit, the memory reading circuit, the memory erasing circuit and the data processing circuit are connected to the microcontroller. The cell management circuit is used to manage the cells or cell groups of the rewritable nonvolatile memory module 43. The memory write circuit is configured to issue a write command sequence to the rewritable nonvolatile memory module 43 to write data into the rewritable nonvolatile memory module 43. The memory reading circuit is used for issuing a reading instruction sequence to the rewritable nonvolatile memory module 43 to read data from the rewritable nonvolatile memory module 43. The memory erasing circuit is used for issuing an erasing command sequence to the rewritable nonvolatile memory module 43 so as to erase data from the rewritable nonvolatile memory module 43. The data processing circuit is used for processing data to be written into the rewritable nonvolatile memory module 43 and data read from the rewritable nonvolatile memory module 43. The write command sequence, the read command sequence and the erase command sequence may respectively include one or more program codes or command codes and instruct the rewritable nonvolatile memory module 43 to perform corresponding write, read and erase operations. In an exemplary embodiment, the memory management circuit 51 may issue other types of command sequences to the rewritable nonvolatile memory module 43 to instruct the corresponding operations to be performed.
The host interface 52 is connected to the memory management circuit 51. The memory management circuitry 51 may communicate with the host system 11 through a host interface 52. The host interface 52 is used for receiving and recognizing commands and data transmitted by the host system 11. For example, commands and data transmitted by the host system 11 may be transmitted to the memory management circuit 51 through the host interface 52. In addition, the memory management circuit 51 may transmit data to the host system 11 through the host interface 52. In the exemplary embodiment, host interface 52 is compatible with the PCI Express standard. However, it should be understood that the present invention is not limited thereto, and the host interface 52 may be compatible with the SATA standard, PATA standard, IEEE 1394 standard, USB standard, SD standard, UHS-I standard, UHS-II standard, MS standard, MMC standard, eMMC standard, UFS standard, CF standard, IDE standard or other suitable data transmission standard.
The memory interface 53 is connected to the memory management circuit 51 and is used for accessing the rewritable nonvolatile memory module 43. For example, the memory management circuit 51 can access the rewritable nonvolatile memory module 43 through the memory interface 53. That is, the data to be written into the rewritable nonvolatile memory module 43 is converted into a format accepted by the rewritable nonvolatile memory module 43 through the memory interface 53. Specifically, if the memory management circuit 51 wants to access the rewritable nonvolatile memory module 43, the memory interface 53 transmits a corresponding command sequence. For example, the command sequences may include a write command sequence for indicating data to be written, a read command sequence for indicating data to be read, an erase command sequence for indicating data to be erased, and corresponding command sequences for indicating various memory operations (e.g., changing read voltage levels or performing garbage collection operations, etc.). These instruction sequences are generated by the memory management circuit 51 and transferred to the rewritable non-volatile memory module 43 via the memory interface 53, for example. The sequences of instructions may include one or more signals or data on a bus. These signals or data may include instruction code or program code. For example, the read command sequence includes read identification code, memory address, and the like.
In an exemplary embodiment, the memory control circuitry unit 42 further includes error checking and correction circuitry 54, buffer memory 55, and power management circuitry 56.
The error checking and correcting circuit 54 is connected to the memory management circuit 51 and is used for performing error checking and correcting operations to ensure the correctness of data. Specifically, when the memory management circuit 51 receives a write command from the host system 11, the error checking and correcting circuit 54 generates an Error Correcting Code (ECC) and/or an Error Detecting Code (EDC) for data corresponding to the write command, and the memory management circuit 51 writes the data corresponding to the write command and the corresponding ECC and/or EDC into the rewritable nonvolatile memory module 43. Thereafter, when the memory management circuit 51 reads data from the rewritable nonvolatile memory module 43, the error correction code and/or the error check code corresponding to the data are simultaneously read, and the error checking and correcting circuit 54 performs an error checking and correcting operation on the read data according to the error correction code and/or the error check code. For example, the error checking and correcting circuit 54 may support various encoding/decoding algorithms such as Low Density Parity Check code (LDPC code) and BCH.
The buffer memory 55 is connected to the memory management circuit 51 and is used for temporarily storing data. The power management circuit 56 is a power supply connected to the memory management circuit 51 and used to control the memory storage device 10.
In an example embodiment, the memory control circuit unit 42 further includes a temperature sensor 57. The temperature sensor 57 is connected to the memory management circuit 51. The temperature sensor 57 is used to sense the ambient temperature and provide a corresponding temperature value. In an exemplary embodiment, the memory management circuit 51 can obtain the current temperature status of the rewritable nonvolatile memory module 43 according to the temperature value provided by the temperature sensor 57. The temperature status can be expressed by a specific status parameter or directly by a temperature value, but the invention is not limited thereto. In addition, the temperature sensor 57 may be disposed inside or outside the memory control circuit unit 42, and the present invention is not limited thereto.
In an example embodiment, the rewritable nonvolatile memory module 43 of fig. 4 may include a flash memory module. In an example embodiment, the memory control circuit unit 42 of FIG. 4 may include a flash memory controller. In an example embodiment, the memory management circuit 51 of FIG. 5 may include a flash memory management circuit.
FIG. 6 is a diagram illustrating management of a rewritable nonvolatile memory module according to an exemplary embodiment of the present invention. Referring to FIG. 6, the memory management circuit 51 can logically group the physical units 610(0) to 610(B) in the rewritable nonvolatile memory module 43 into a storage area 601 and an idle (spare) area 602. One physical unit refers to one Virtual Block (VB). One virtual block may include a plurality of physical program cells. For example, a virtual block may include one or more physically erased cells.
The physical units 610(0) -610 (A) in the storage area 601 are used to store user data (e.g., user data from the host system 11 of FIG. 1). For example, entity units 610(0) -610 (A) in the storage area 601 may store valid (valid) data and invalid (invalid) data. The physical units 610(a +1) to 610(B) in the idle region 602 store no data (e.g., valid data). For example, if a physical unit does not store valid data, the physical unit may be associated (or added) to the idle region 602. In addition, the physical cells in the idle region 602 (or the physical cells not storing valid data) can be erased. When new data is written, one or more physical units may be fetched from the idle region 602 to store the new data. In an exemplary embodiment, the idle region 602 is also referred to as a free pool.
Memory management circuitry 51 may configure logic units 612(0) - (612 (C) to map physical units 610(0) - (610 (A) in memory area 601. In an exemplary embodiment, each logical unit corresponds to a logical address. For example, a Logical Address may include one or more Logical Block Addresses (LBAs) or other Logical management units.
It is noted that a logical unit may be mapped to one or more physical units. If a certain entity unit is mapped by a certain logic unit, it indicates that the data currently stored in the entity unit contains valid data. On the contrary, if a certain physical unit is not currently mapped by any logical unit, it indicates that the data currently stored in the physical unit does not include any valid data.
The memory management circuit 51 may record management data (also referred to as logic-to-entity mapping information) describing mapping relationships between the logical units and the physical units in at least one logic-to-entity mapping table. When the host system 11 wants to read data from the memory storage device 10 or write data to the memory storage device 10, the memory management circuit 51 can access the rewritable nonvolatile memory module 43 according to the information in the logical-to-physical mapping table.
In an example embodiment, the memory management circuit 51 can detect and record a temperature state (also referred to as a first temperature state) when a physical unit (also referred to as a first physical unit) in the rewritable non-volatile memory module 43 is programmed to store data (also referred to as first data). Thereafter, in response to the current temperature state (also referred to as the second temperature state) of the rewritable non-volatile memory module 43 and the first temperature state meeting a specific condition (also referred to as the first condition), the memory management circuit 51 may perform a data refresh operation on the first physical unit. Thereafter, in the second temperature state (or other temperature states), when the first data is read from the second physical unit, since the temperature state of the first data when programmed to the second physical unit is the same as or similar to the temperature state of the first data when read from the second physical unit, the total number of error bits generated in the read first data due to the excessive read-write temperature difference can be reduced. Therefore, the data reliability of the rewritable nonvolatile memory module in the environment with severe temperature change can be improved.
FIG. 7 is a diagram illustrating a first write operation according to an exemplary embodiment of the invention. Referring to fig. 7, the memory management circuit 51 may set the physical unit 71 (i.e., the first physical unit) as an open unit (also referred to as an open block) to receive new data from the host system 11. For example, the entity unit 71 may be selected from the entity units 610(a +1) to 610(B) of fig. 6. On the other hand, the memory management circuit 51 may detect a temperature state (i.e., a first temperature state) of the rewritable nonvolatile memory module 43. For example, the memory management circuit 51 may receive the temperature value 710 from the temperature sensor 57. Temperature value 710 may reflect an ambient temperature sensed by temperature sensor 57 at a point in time (also referred to as a first point in time). The memory management circuit 51 may obtain a first temperature state from the temperature value 710.
In the first temperature state, the memory management circuit 51 may receive a write instruction 701 from the host system 11. The write instruction 701 may indicate to store data 702 (i.e., the first data). For example, the write instruction 701 may indicate to store the data 702 to a particular logical unit. After receiving the write command 701, the memory management circuit 51 may perform a write operation (also referred to as a first write operation) on the physical unit 71 in the first temperature state. The first write operation may be used to store the data 702 indicated by the write instruction 701 into the physical unit 71. For example, the memory management circuit 51 can send at least one write command sequence to the rewritable nonvolatile memory module 43 to instruct the rewritable nonvolatile memory module 43 to store the data 702 in the entity unit 71 under the first temperature state.
The memory management circuit 51 may update the table information 700 corresponding to storing the data 702 to the entity unit 71. The table information 700 can be used to record the temperature status of at least one entity unit in the rewritable nonvolatile memory module 43 when it was programmed last time. For example, the temperature state may be represented by temperature state identification information and described in table information 700. The temperature state identification information may have different parameter values in different temperature states.
In the example embodiment of fig. 7, the memory management circuit 51 may update the temperature status identification information corresponding to the entity unit 71 in the table information 700 to the parameter value "101". Parameter value 101 may be determined according to temperature value 710 and reflects a temperature state (i.e., a first temperature state) of physical unit 71 when programmed to store data 702. It should be noted that, in another exemplary embodiment, the first temperature state can also be represented by other parameter values or directly by the temperature value 710, and the invention is not limited thereto.
FIG. 8 is a diagram illustrating a data refresh operation according to an exemplary embodiment of the present invention. Referring to FIG. 8, continuing with the example embodiment of FIG. 7, after the first write operation is performed, the memory management circuit 51 can detect another temperature state (i.e., a second temperature state) of the rewritable non-volatile memory module 43. For example, the memory management circuit 51 may receive the temperature value 810 from the temperature sensor 57. Temperature value 810 may reflect an ambient temperature sensed by temperature sensor 57 at a point in time (also referred to as a second point in time). The second time point is later than the first time point. Between the first point in time and the second point in time, a change in the temperature state of the rewritable non-volatile memory module 43 can occur, for example from a first temperature state to a second temperature state. The memory management circuit 51 may obtain the second temperature state from the temperature value 810.
In an exemplary embodiment, the memory management circuit 51 may determine whether the first temperature state and the second temperature state meet a specific condition (i.e., a first condition). For example, the first condition may include that a temperature difference between a temperature value corresponding to the first temperature state (e.g., temperature value 710 of FIG. 7) and a temperature value corresponding to the second temperature state (e.g., temperature value 810 of FIG. 8) reaches a threshold value or that the temperature difference falls within a certain range of values.
In an exemplary embodiment, the memory management circuit 51 may determine that the first temperature state and the second temperature state meet the first condition if a temperature difference between the temperature value corresponding to the first temperature state and the temperature value corresponding to the second temperature state reaches a threshold value. For example, the threshold may be 70 degrees. If the temperature difference between the temperature value corresponding to the first temperature state and the temperature value corresponding to the second temperature state reaches 70 degrees, the memory management circuit 51 may determine that the first temperature state and the second temperature state meet the first condition. It should be noted that the threshold value can be adjusted according to practical requirements, and the invention is not limited thereto.
In an exemplary embodiment, if the temperature difference between the temperature value corresponding to the first temperature state and the temperature value corresponding to the second temperature state is within a specific range, the memory management circuit 51 may determine that the first temperature state and the second temperature state meet the first condition. For example, the specific range may be between 60 degrees and 80 degrees. If the temperature difference between the temperature value corresponding to the first temperature state and the temperature value corresponding to the second temperature state is between 60 degrees and 80 degrees, the memory management circuit 51 may determine that the first temperature state and the second temperature state meet the first condition. It should be noted that the specific value ranges can be adjusted according to practical requirements, and the invention is not limited thereto.
In the exemplary embodiment of fig. 8, it is assumed that the first temperature state and the second temperature state satisfy the first condition. In response to the first temperature state and the second temperature state meeting the first condition, the memory management circuit 51 may perform a data refresh operation on the physical unit 71 in the second temperature state. This data refresh operation is used to restore data 702 previously stored in physical unit 71 in the first temperature state to physical unit 81 (i.e., the second physical unit) in the second temperature state. For example, the entity unit 81 can also be selected from the entity units 610(a +1) to 610(B) in fig. 6, and the entity unit 81 is different from the entity unit 71. For example, the memory management circuit 51 can send at least one read command sequence to the rewritable nonvolatile memory module 43 to instruct the rewritable nonvolatile memory module 43 to read the data 702 from the entity unit 71 in the second temperature state. Then, the memory management circuit 51 can send at least one write command sequence to the rewritable nonvolatile memory module 43 to instruct the rewritable nonvolatile memory module 43 to restore the read data 702 to the entity unit 81 under the second temperature state.
Corresponding to the data refresh operation, the memory management circuit 51 may update the table information 700. For example, based on the temperature value 810, the memory management circuit 51 may update the temperature state identification information corresponding to the physical cell 81 in the table information 700 to be the parameter value "010" to reflect the temperature state (i.e., the second temperature state) when the physical cell 81 is programmed to store the data 702. It should be noted that, in another exemplary embodiment, the second temperature state can also be represented by other parameter values or directly by the temperature value 810, and the invention is not limited thereto.
In an example embodiment, the memory management circuit 51 may reset (reset) the temperature status identification information corresponding to the physical unit 71 corresponding to the data refresh operation. For example, the memory management circuit 51 may reset the temperature state identification information corresponding to the entity unit 71 in the table information 700 to the parameter value "000". Thereafter, the memory management circuit 51 can re-associate the physical unit 71 to the idle area 602 of FIG. 6 and erase the physical unit 71.
In an example embodiment, a particular temperature state may correspond to a particular temperature range. For example, when the temperature of the rewritable nonvolatile memory module 43 falls within a certain temperature range, the memory management circuit 51 may determine that the temperature state of the rewritable nonvolatile memory module 43 is the temperature state corresponding to the temperature range. Further, different temperature states may correspond to different temperature ranges. For example, the first temperature state may correspond to a first temperature range and the second temperature state may correspond to a second temperature range. In an example embodiment, the data refresh operation may include restoring all or a portion of the data in the first physical unit to a second physical unit, and the data restored to the second physical unit may include data previously stored in the first physical unit at one or more temperature states.
In the example embodiment of fig. 7, data 702 is stored or programmed into physical unit 71 at a first temperature state. During the time that the data 702 is stored in the entity unit 71, the temperature state of the rewritable non-volatile memory module 43 changes from the first temperature state to the second temperature state. That is, the temperature of the rewritable non-volatile memory module 43 may gradually increase or decrease, going from one temperature range to another temperature range, and even further going to other temperature ranges. In the example embodiment of fig. 7, after the temperature state of the rewritable non-volatile memory module 43 changes to the second temperature state, if the data refresh operation is not performed, as the temperature of the rewritable non-volatile memory module 43 continuously changes (e.g., continuously increases or decreases), more errors may be carried in the data 702 subsequently read from the physical unit 71. Such errors may reduce the efficiency of subsequent decoding of the data 702, and may even result in a failed decoding of the data 702.
In an example embodiment of fig. 8, the memory management circuit 51 may perform the data refresh operation on the physical unit 71 as soon as possible when the temperature state of the rewritable non-volatile memory module 43 enters the second temperature state, so as to restore the data 702 to the physical unit 81 in the second temperature state. At this time, there is a high probability that the data 702 can be successfully decoded (e.g., all errors in the data 702 can be successfully corrected) based on the high probability that the errors in the data 702 read from the physical unit 71 under the second temperature state are still controllable or acceptable. After the data 702 is restored to the physical unit 81, the temperature of the rewritable non-volatile memory module 43 may continuously increase or decrease, even entering another temperature range (also referred to as a third temperature range). In a temperature state corresponding to the third temperature range (also referred to as a third temperature state), errors in the data 702 read from the physical unit 81 may be more easily corrected than the data 702 read from the physical unit 71, so that the efficiency of decoding the data 702 subsequently is improved. Thus, the data reliability of the rewritable nonvolatile memory module 43 in the case of data access in an environment with severe temperature change can be effectively improved.
In an example embodiment, the data refresh operation may be triggered by a write command from the host system 11. For example, in an example embodiment, the memory management circuit 51 may receive a write command from the host system 11. The memory management circuit 51 may determine whether the first temperature state and the second temperature state meet the first condition according to the write command, and further determine whether to perform the data refresh operation. In an exemplary embodiment, the data refresh operation may be performed when the memory storage device 10 is in an idle state, before shutdown, after startup, or at any time, which is not limited by the invention.
FIG. 9 is a diagram illustrating a data refresh operation and a second write operation according to an exemplary embodiment of the invention. Referring to FIG. 9, continuing with the example embodiment of FIG. 7, after the first write operation is performed, the memory management circuit 51 detects a second temperature state of the rewritable non-volatile memory module 43. For example, the memory management circuit 51 may receive the temperature value 910 from the temperature sensor 57. Temperature value 910 may reflect the ambient temperature sensed by temperature sensor 57 at the second point in time. The second time point is later than the first time point. The memory management circuit 51 may obtain a second temperature state from the temperature value 910.
Near the second point in time, the memory management circuit 51 may receive a write instruction 901 from the host system 11. The write instruction 901 may indicate to store data 902 (also referred to as second data). For example, a write instruction 901 may indicate that data 902 is to be stored to a particular logical unit. In response to receiving the write command 901, the memory management circuit 51 may determine whether the first temperature state and the second temperature state meet the first condition.
In the exemplary embodiment of fig. 9, it is assumed that the first temperature state and the second temperature state meet the first condition. In response to the first temperature state and the second temperature state meeting the first condition, the memory management circuit 51 may perform a data refresh operation on the physical cell 71 in the second temperature state. For example, in a data refresh operation, the memory management circuit 51 can send at least one read command sequence to the rewritable nonvolatile memory module 43 to instruct the rewritable nonvolatile memory module 43 to read the data 702 from the physical unit 71 in the second temperature state. Then, the memory management circuit 51 can send at least one write command sequence to the rewritable nonvolatile memory module 43 to instruct the rewritable nonvolatile memory module 43 to restore the read data 702 to the physical unit 91 (i.e. the second physical unit) under the second temperature state. For example, the entity unit 91 may also be selected from the entity units 610(a +1) to 610(B) in fig. 6, and the entity unit 91 is different from the entity unit 71. Further, the memory management circuit 51 may update the table information 700 corresponding to the data refresh operation. For example, the memory management circuit 51 may reset the temperature status identification information corresponding to the entity unit 71. For example, the memory management circuit 51 may reset the temperature state corresponding to the entity unit 71 in the table information 700 to the parameter value "000".
On the other hand, in response to the first temperature state and the second temperature state meeting the first condition, in the second temperature state, the memory management circuit 51 may perform a write operation (also referred to as a second write operation) on the physical unit 91 according to the write instruction 901. The second write operation is used to store the data 902 indicated by the write command 901 into the physical unit 91. For example, in the second write operation, the memory management circuit 51 may send at least one write command sequence to the rewritable nonvolatile memory module 43 to instruct the rewritable nonvolatile memory module 43 to store the data 902 in the physical unit 91 in the second temperature state. For example, in the entity unit 91, the data 902 may be stored before or after the data 702 (fig. 9 is an example in which the data 902 is stored after the data 702), and the invention is not limited thereto.
The memory management circuit 51 may update the table information 700 corresponding to storing the data 902 to the entity unit 91. For example, according to the temperature value 910, the memory management circuit 51 may update the temperature state identification information corresponding to the physical cell 91 in the table information 700 to be the parameter value "010" to reflect the temperature state (i.e., the second temperature state) when the physical cell 91 is programmed to store the data 902. It should be noted that, in another exemplary embodiment, the second temperature state can also be represented by other parameter values or directly by the temperature value 910, and the invention is not limited thereto.
It is noted that in the exemplary embodiment of fig. 7, the entity unit 71 is configured as an on unit. Thereafter, in the example embodiments of fig. 8 or 9, the memory management circuit 51 may set the physical unit 81 or 91 as a new on unit instead of the physical unit 71. Thereafter, new data from the host system 11 may be stored to the entity unit 81 or 91.
In another exemplary embodiment of fig. 9, the physical unit 71 is still an open unit when the write command 901 is received. Therefore, the memory management circuit 51 may store the data 902 indicated by the write command 901 in the physical unit 71 first. At this time, the entity unit 71 stores the data 702 and 902 at the same time. Thereafter, in response to the first temperature state and the second temperature state meeting the first condition, in the second temperature state, memory management circuit 51 may restore data 702 and 902 (and the rest of the data in physical unit 71) to physical unit 91 in a data refresh operation.
In an exemplary embodiment, if the first temperature state and the second temperature state do not meet the first condition, the memory management circuit 51 may not perform the data refresh operation on the physical unit 71. In the case where the data refresh operation is not performed, the physical unit 71 may be maintained as an on unit to continue receiving new data from the host system 11 until the physical unit 71 is full.
FIG. 10 is a diagram illustrating a third write operation according to an exemplary embodiment of the invention. Referring to FIG. 10, continuing with the example embodiment of FIG. 7, after the first write operation is performed, the memory management circuit 51 detects a second temperature state of the rewritable non-volatile memory module 43. For example, the memory management circuit 51 may receive a temperature value 1010 from the temperature sensor 57. Temperature value 1010 may reflect the ambient temperature sensed by temperature sensor 57 at the second point in time. The second time point is later than the first time point. The memory management circuit 51 may obtain a second temperature state from the temperature value 1010.
Near the second point in time, the memory management circuit 51 may receive a write instruction 1001 from the host system 11. The write instruction 1001 may indicate to store data 1002 (i.e., the second data). For example, a write instruction 1001 may indicate that data 1002 is to be stored to a particular logical unit. In response to receiving the write command 1001, the memory management circuit 51 may determine whether the first temperature state and the second temperature state meet the first condition.
In the exemplary embodiment of fig. 10, it is assumed that the first temperature state and the second temperature state do not meet the first condition. In response to the first and second temperature states not meeting the first condition, the memory management circuit 51 may not perform the data refresh operation on the physical unit 71. Instead, in the second temperature state, the memory management circuit 51 may perform a write operation (also referred to as a third write operation) on the physical unit 71 according to the write command 1001. The third write operation is used to store the data 1002 indicated by the write command 1001 into the physical unit 71. For example, in the third write operation, the memory management circuit 51 can send at least one write command sequence to the rewritable nonvolatile memory module 43 to instruct the rewritable nonvolatile memory module 43 to store the data 1002 in the entity unit 71 under the second temperature state. For example, in the entity unit 71, the data 1002 may be stored after the data 702, as shown in fig. 10.
The memory management circuit 51 may update the table information 700 corresponding to storing the data 1002 to the entity unit 71. For example, according to the temperature value 1010, the memory management circuit 51 may update the temperature state identification information corresponding to the entity unit 71 in the table information 700 from the parameter value "101" of fig. 7 to the parameter value "001". The parameter value "001" may reflect the temperature state (i.e., the second temperature state) at which the physical unit 71 is programmed to store the data 1002. It should be noted that, in another exemplary embodiment, the second temperature state can also be represented by other parameter values or directly by the temperature value 1010, and the invention is not limited thereto.
It is noted that in the exemplary embodiment of fig. 10, the memory management circuit 51 does not perform a data refresh operation on the physical cells 71 in the second temperature state. Therefore, when the temperature change of the rewritable nonvolatile memory module 43 is not large (for example, the temperature difference value does not reach the threshold value or the temperature difference value does not fall within a specific value range), the loss caused by excessive data movement to the memory cell can be reduced.
It should be noted that the memory management circuit 51 may determine whether the first temperature state and the second temperature state meet the first condition by using one or more logic determination manners, such as determining whether a temperature difference between a temperature value corresponding to the first temperature state and a temperature value corresponding to the second temperature state reaches a threshold value and/or determining whether the temperature difference falls within a specific value range. Then, the memory management circuit 51 may determine whether to perform or trigger the data refresh operation according to the determination result.
FIG. 11 is a diagram illustrating triggering or not triggering a data refresh operation under different temperature change conditions according to an exemplary embodiment of the invention. Referring to fig. 11, the temperature status identification information corresponding to the first entity unit (e.g., the entity unit 71 in fig. 7) may include parameter values "101", "001", "010", and "110". Parameter value "101" may reflect that the temperature of the first physical unit when programmed last falls between temperature values T (5) and T (3). The parameter value "001" may reflect that the temperature of the first physical unit when programmed last falls between the temperature values T (3) and T (1). Parameter value "010" may reflect that the temperature at which the first physical unit was last programmed falls between temperature values T (2) to T (4). The parameter value "110" may reflect that the temperature of the first physical unit when programmed last falls between the temperature values T (4) to T (6).
After the temperature change (e.g., from the first temperature state to the second temperature state), the memory management circuit 51 can obtain a trigger threshold THR and a temperature T of the rewritable nonvolatile memory module 43 in the second temperature state. The trigger threshold THR may be determined corresponding to a first temperature state of the first physical unit. For example, assuming that the first temperature state of the first physical unit is represented by the parameter value 101 (i.e., the temperature of the first physical unit when programmed last falls between the temperature values T (5) to T (3)), the trigger threshold THR corresponding to the first physical unit may be set to be the same as or similar to the temperature value T (1), as shown in fig. 11. In other words, the trigger threshold THR can be used to determine whether the temperature difference between the temperature value corresponding to the first temperature state and the temperature value corresponding to the second temperature state reaches a threshold. The determined trigger threshold THR may be different according to different first temperature states of the first physical unit.
The memory management circuit 51 may compare the temperature value T with the trigger threshold value THR. Then, the memory management circuit 51 may determine whether the first temperature state and the second temperature state meet the first condition according to the comparison result. For example, in the exemplary embodiment of fig. 11, if the temperature value T is greater than the trigger threshold THR (which is equivalent to the temperature difference between the first temperature state and the second temperature state reaching the threshold), the memory management circuit 51 may determine that the first temperature state and the second temperature state meet the first condition and trigger or initiate the data refresh operation. Alternatively, in another exemplary embodiment of fig. 11, if the temperature value T is not greater than the trigger threshold THR (which is equivalent to the temperature difference between the first temperature state and the second temperature state not reaching the threshold), the memory management circuit 51 may determine that the first temperature state and the second temperature state do not satisfy the first condition and not trigger or initiate the data refresh operation.
FIG. 12 is a diagram illustrating triggering or not triggering a data refresh operation under different temperature change conditions according to an exemplary embodiment of the invention. Referring to fig. 12, the temperature status identification information corresponding to the first entity unit (e.g., the entity unit 71 in fig. 7) may include parameter values "101", "001", "010", and "110". After the temperature change occurs, the memory management circuit 51 may obtain temperature state identification information corresponding to a first temperature state of the first physical unit (also referred to as first temperature state identification information) and temperature state identification information corresponding to a second temperature state (also referred to as second temperature state identification information). The memory management circuit 51 may perform a logic operation with the first temperature state identification information and the second temperature state identification information. For example, this logical operation may comprise an Exclusive OR (XOR) operation. The memory management circuit 51 can determine whether the first temperature state and the second temperature state meet the first condition according to the execution result of the logic operation.
For example, in an example embodiment of fig. 12, it is assumed that the first temperature state identification information corresponding to the first temperature state includes a parameter value "001" and the second temperature state identification information corresponding to the second temperature state includes a parameter value "010". According to the execution result of this logic operation (e.g., the execution result of the XOR operation is "011", which is not equal to a predetermined value "111") (which is equivalent to the temperature difference between the temperature value corresponding to the first temperature state and the temperature value corresponding to the second temperature state not falling within the specific value range), the memory management circuit 51 may determine that the first temperature state and the second temperature state do not satisfy the first condition and does not trigger or initiate the data refresh operation. Alternatively, in the example embodiment of fig. 12, it is assumed that the first temperature state identification information corresponding to the first temperature state includes a parameter value "101" and the second temperature state identification information corresponding to the second temperature state includes a parameter value "010". According to the execution result of this logical operation (e.g., the execution result of the XOR operation is "111", which is equal to the preset value "111") (which is equivalent to the temperature difference between the temperature value corresponding to the first temperature state and the temperature value corresponding to the second temperature state falling within the specific value range), the memory management circuit 51 may determine that the first temperature state and the second temperature state meet the first condition and trigger or initiate the data refresh operation. It should be noted that the logic determination methods mentioned in the exemplary embodiments of fig. 11 and 12 are only examples, and are not intended to limit the present invention.
In an example embodiment, the memory management circuit 51 may allow the data refresh operation to be initiated only when the temperature state of the rewritable non-volatile memory module 43 changes and remains in the second temperature state for more than a certain period of time. Thereby, it is possible to prevent the data refresh operation from being performed too frequently due to frequent changes in the temperature state of the rewritable non-volatile memory module 43.
In an exemplary embodiment, the memory management circuit 51 can instruct the rewritable nonvolatile memory module 43 to perform a programming operation on the physical units using different electrical parameters under different temperature states, so as to satisfy the electrical characteristics of the memory cells in the rewritable nonvolatile memory module 43 under different temperature states. For example, the electrical parameter may include a programming voltage (i.e., a pulse voltage) and/or a programming time, etc., and the invention is not limited thereto. For example, in the first temperature state, the memory management circuit 51 may instruct the rewritable non-volatile memory module 43 to program at least one memory cell of the first physical unit with a specific electrical parameter (also referred to as a first electrical parameter). Thereafter, in the second temperature state, the memory management circuit 51 may instruct the rewritable non-volatile memory module 43 to program the at least one memory cell in the first physical unit with a different electrical parameter (also referred to as a second electrical parameter). Thus, the electrical characteristics of the memory cells in the rewritable nonvolatile memory module 43 at different temperature states can be satisfied by different electrical references, so that the programmed memory cells have a better voltage state at the current temperature state.
FIG. 13 is a flowchart illustrating a memory management method according to an example embodiment of the invention. Referring to fig. 13, in step S1301, a first temperature state of the rewritable nonvolatile memory module is detected. In step S1302, in the first temperature state, a first write operation is performed on a first entity unit in the rewritable nonvolatile memory module to store first data in the first entity unit. After the first write operation is performed, in step S1303, a second temperature state of the rewritable non-volatile memory module is detected. In step S1304, it is determined whether the first temperature state and the second temperature state meet a first condition. In response to that the first temperature state and the second temperature state meet a first condition, in step S1305, a data refresh operation is performed on the first physical unit in the second temperature state to restore the first data to a second physical unit in the rewritable non-volatile memory module, where the second physical unit is different from the first physical unit. In addition, if the first temperature state and the second temperature state do not meet the first condition, step S1303 may be repeatedly executed.
However, the steps in fig. 13 have been described in detail above, and are not described again here. It is to be noted that, the steps in fig. 13 can be implemented as a plurality of program codes or circuits, and the invention is not limited thereto. In addition, the method of fig. 13 can be used with the above exemplary embodiments, or can be used alone, and the invention is not limited thereto.
In summary, the exemplary embodiments of the invention can perform a data refresh operation on a specific physical unit under an environment with a severe temperature variation. Therefore, the reliability of data access to the rewritable nonvolatile memory module in an environment with severe temperature change can be improved.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.

Claims (27)

1. A memory management method for a memory storage device, wherein the memory storage device includes a rewritable nonvolatile memory module, the rewritable nonvolatile memory module includes a plurality of physical units, and the memory management method includes:
detecting a first temperature state of the rewritable nonvolatile memory module;
performing a first write operation on a first physical unit of the plurality of physical units in the first temperature state to store first data into the first physical unit;
detecting a second temperature state of the rewritable non-volatile memory module after the first writing operation is executed; and
in response to the first temperature state and the second temperature state meeting a first condition, performing a data refresh operation on the first physical cell in the second temperature state to restore the first data to a second physical cell of the plurality of physical cells, wherein the second physical cell is different from the first physical cell.
2. The memory management method of claim 1, wherein the first condition comprises a temperature difference between a temperature value corresponding to the first temperature state and a temperature value corresponding to the second temperature state reaching a threshold value or falling within a specific range of values.
3. The memory management method of claim 1, further comprising:
obtaining a trigger threshold corresponding to the first temperature state;
obtaining a temperature value of the rewritable nonvolatile memory module in the second temperature state;
comparing the trigger threshold value with the temperature value; and
and judging whether the first temperature state and the second temperature state meet the first condition or not according to the comparison result.
4. The memory management method of claim 1, further comprising:
obtaining first temperature state identification information corresponding to the first temperature state;
obtaining second temperature state identification information corresponding to the second temperature state;
performing a logical operation on the first temperature state identification information and the second temperature state identification information; and
and judging whether the first temperature state and the second temperature state meet the first condition or not according to the execution result of the logic operation.
5. The memory management method of claim 1, wherein detecting the second temperature state of the rewritable non-volatile memory module comprises:
receiving a write command from a host system; and
and responding to the write instruction to judge whether the first temperature state and the second temperature state meet the first condition.
6. The memory management method of claim 5, further comprising:
in response to the first temperature state and the second temperature state meeting the first condition, performing a second write operation on the second physical unit at the second temperature state to store second data indicated by the write instruction into the second physical unit; and
and updating the temperature state identification information corresponding to the second entity unit according to the second temperature state.
7. The memory management method of claim 5, further comprising:
performing a second write operation on the first physical unit in the second temperature state to store second data indicated by the write instruction into the first physical unit; and
in the data refresh operation, the first data is read out from the first physical unit together with the second data and stored in the second physical unit.
8. The memory management method of claim 5, further comprising:
recording temperature state identification information corresponding to the first entity unit according to the first temperature state;
in response to the first temperature state and the second temperature state not meeting the first condition, performing a third write operation on the first physical unit at the second temperature state to store second data indicated by the write instruction into the first physical unit; and
updating the temperature state identification information corresponding to the first entity unit according to the second temperature state.
9. The memory management method of claim 1, further comprising:
under the first temperature state, instructing the rewritable non-volatile memory module to program at least one memory cell in the first entity unit by using a first electrical parameter; and
and in the second temperature state, instructing the rewritable non-volatile memory module to program the at least one memory cell by using a second electrical parameter, wherein the first electrical parameter is different from the second electrical parameter.
10. A memory storage device, comprising:
a connection interface unit for connecting to a host system;
a rewritable nonvolatile memory module including a plurality of entity units; and
a memory control circuit unit connected to the connection interface unit and the rewritable nonvolatile memory module,
wherein the memory control circuit unit is used for detecting a first temperature state of the rewritable non-volatile memory module,
the memory control circuit unit is further configured to perform a first write operation on a first physical unit of the plurality of physical units in the first temperature state to store first data in the first physical unit,
after the first write operation is performed, the memory control circuit unit is further used for detecting a second temperature state of the rewritable nonvolatile memory module, and
in response to the first temperature state and the second temperature state meeting a first condition, the memory control circuit unit is further configured to perform a data refresh operation on the first physical unit in the second temperature state to restore the first data to a second physical unit of the plurality of physical units, wherein the second physical unit is different from the first physical unit.
11. The memory storage device of claim 10, wherein the first condition comprises a temperature difference between a temperature value corresponding to the first temperature state and a temperature value corresponding to the second temperature state reaching a threshold value or falling within a specified range of values.
12. The memory storage device of claim 10, wherein the memory control circuitry is further configured to:
obtaining a trigger threshold corresponding to the first temperature state;
obtaining a temperature value of the rewritable nonvolatile memory module in the second temperature state;
comparing the trigger threshold value with the temperature value; and
and judging whether the first temperature state and the second temperature state meet the first condition or not according to the comparison result.
13. The memory storage device of claim 10, wherein the memory control circuitry is further configured to:
obtaining first temperature state identification information corresponding to the first temperature state;
obtaining second temperature state identification information corresponding to the second temperature state;
performing a logical operation on the first temperature state identification information and the second temperature state identification information; and
and judging whether the first temperature state and the second temperature state meet the first condition or not according to the execution result of the logic operation.
14. The memory storage device of claim 10, wherein detecting the second temperature state of the rewritable non-volatile memory module comprises:
receiving a write command from a host system; and
and responding to the write instruction to judge whether the first temperature state and the second temperature state meet the first condition.
15. The memory storage device of claim 14, wherein the memory control circuitry is further configured to:
in response to the first temperature state and the second temperature state meeting the first condition, performing a second write operation on the second physical unit at the second temperature state to store second data indicated by the write instruction into the second physical unit; and
and updating the temperature state identification information corresponding to the second entity unit according to the second temperature state.
16. The memory storage device of claim 14, wherein the memory control circuitry is further configured to:
performing a second write operation on the first physical unit in the second temperature state to store second data indicated by the write instruction into the first physical unit; and
and in the data refreshing operation, instructing the rewritable nonvolatile memory module to read the first data and the second data from the first entity unit and store the first data and the second data into the second entity unit.
17. The memory storage device of claim 14, wherein the memory control circuitry is further configured to:
recording temperature state identification information corresponding to the first entity unit according to the first temperature state;
in response to the first temperature state and the second temperature state not meeting the first condition, performing a third write operation on the first physical unit at the second temperature state to store second data indicated by the write instruction into the first physical unit; and
updating the temperature state identification information corresponding to the first entity unit according to the second temperature state.
18. The memory storage device of claim 10, wherein the memory control circuitry is further configured to:
under the first temperature state, instructing the rewritable non-volatile memory module to program at least one memory cell in the first entity unit by using a first electrical parameter; and
and in the second temperature state, instructing the rewritable non-volatile memory module to program the at least one memory cell by using a second electrical parameter, wherein the first electrical parameter is different from the second electrical parameter.
19. A memory control circuit unit for controlling a rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module includes a plurality of physical units, and the memory control circuit unit includes:
a host interface for connecting to a host system;
a memory interface for connecting to the rewritable nonvolatile memory module; and
a memory management circuit connected to the host interface and the memory interface,
wherein the memory control circuit unit is used for detecting a first temperature state of the rewritable non-volatile memory module,
the memory management circuit is further configured to perform a first write operation on a first physical unit of the plurality of physical units at the first temperature state to store first data into the first physical unit,
after the first write operation is performed, the memory management circuit is further used for detecting a second temperature state of the rewritable nonvolatile memory module, and
in response to the first temperature state and the second temperature state meeting a first condition, the memory management circuit is further configured to perform a data refresh operation on the first physical cells in the second temperature state to restore the first data to a second physical cell of the plurality of physical cells, wherein the second physical cell is different from the first physical cell.
20. The memory control circuit unit of claim 19, wherein the first condition comprises a temperature difference between a temperature value corresponding to the first temperature state and a temperature value corresponding to the second temperature state reaching a threshold value or falling within a specific range of values.
21. The memory control circuitry unit of claim 19, wherein the memory management circuitry is further configured to:
obtaining a trigger threshold corresponding to the first temperature state;
obtaining a temperature value of the rewritable nonvolatile memory module in the second temperature state;
comparing the trigger threshold value with the temperature value; and
and judging whether the first temperature state and the second temperature state meet the first condition or not according to the comparison result.
22. The memory control circuitry unit of claim 19, wherein the memory management circuitry is further configured to:
obtaining first temperature state identification information corresponding to the first temperature state;
obtaining second temperature state identification information corresponding to the second temperature state;
performing a logical operation on the first temperature state identification information and the second temperature state identification information; and
and judging whether the first temperature state and the second temperature state meet the first condition or not according to the execution result of the logic operation.
23. The memory control circuit unit of claim 19, wherein detecting the second temperature state of the rewritable non-volatile memory module comprises:
receiving a write command from a host system; and
and responding to the write instruction to judge whether the first temperature state and the second temperature state meet the first condition.
24. The memory control circuitry unit of claim 23, wherein the memory management circuitry is further configured to:
in response to the first temperature state and the second temperature state meeting the first condition, performing a second write operation on the second physical unit at the second temperature state to store second data indicated by the write instruction into the second physical unit; and
and updating the temperature state identification information corresponding to the second entity unit according to the second temperature state.
25. The memory control circuitry unit of claim 23, wherein the memory management circuitry is further configured to:
performing a second write operation on the first physical unit in the second temperature state to store second data indicated by the write instruction into the first physical unit; and
and in the data refreshing operation, instructing the rewritable nonvolatile memory module to read the first data and the second data from the first entity unit and store the first data and the second data into the second entity unit.
26. The memory control circuitry unit of claim 23, wherein the memory management circuitry is further configured to:
recording temperature state identification information corresponding to the first entity unit according to the first temperature state;
in response to the first temperature state and the second temperature state not meeting the first condition, performing a third write operation on the first physical unit at the second temperature state to store second data indicated by the write instruction into the first physical unit; and
updating the temperature state identification information corresponding to the first entity unit according to the second temperature state.
27. The memory control circuitry unit of claim 19, wherein the memory management circuitry is further configured to:
under the first temperature state, instructing the rewritable non-volatile memory module to program at least one memory cell in the first entity unit by using a first electrical parameter; and
and in the second temperature state, instructing the rewritable non-volatile memory module to program the at least one memory cell by using a second electrical parameter, wherein the first electrical parameter is different from the second electrical parameter.
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