CN114115739B

CN114115739B - Memory management method, memory storage device and memory control circuit unit

Info

Publication number: CN114115739B
Application number: CN202111417695.XA
Authority: CN
Inventors: 塞巴斯蒂安·尚; 梁鸣仁
Original assignee: Phison Electronics Corp
Current assignee: Phison Electronics Corp
Priority date: 2021-11-25
Filing date: 2021-11-25
Publication date: 2023-11-07
Anticipated expiration: 2041-11-25
Also published as: CN114115739A

Abstract

The invention provides a memory management method, a memory storage device and a memory control circuit unit. The method comprises the following steps: transmitting a first operation instruction sequence to the rewritable nonvolatile memory modules so as to instruct a first memory module in the rewritable nonvolatile memory modules to execute a first operation; obtaining a first time threshold corresponding to a first operation; updating a first count value corresponding to the first memory module; and in response to the first count value reaching the first time threshold, sending a first query instruction sequence to the rewritable non-volatile memory module to query the state of the first memory module. Therefore, the state query efficiency of the memory module can be improved.

Description

Memory management method, memory storage device and memory control circuit unit

Technical Field

The present invention relates to a memory management technology, and more particularly, to a memory management method, a memory storage device, and a memory control circuit unit.

Background

Portable electronic devices such as mobile phones and notebook computers have grown very rapidly over the years, and consumer demand for storage media has also increased rapidly. Since a rewritable non-volatile memory module (e.g., flash memory) has characteristics of non-volatility of data, power saving, small size, and no mechanical structure, it is very suitable for being built in the above-exemplified various portable electronic devices.

In general, if the rewritable nonvolatile memory module includes a plurality of memory modules, each memory module may be used individually to perform data reading or data writing. To obtain the current state of each memory module (e.g., on a busy or standby basis), the memory controller typically polls each memory module sequentially at intervals for its current state. However, as the number of memory modules included in the rewritable nonvolatile memory module increases, the longer it takes for each polling, resulting in a decrease in the system operation efficiency.

Disclosure of Invention

In view of the above, the present invention provides a memory management method, a memory storage device and a memory control circuit unit, which can improve the status query efficiency of a memory module.

Example embodiments of the present invention provide a memory management method for a rewritable nonvolatile memory module. The rewritable nonvolatile memory module includes a plurality of memory modules. The memory management method comprises the following steps: transmitting a first sequence of operation instructions to the rewritable non-volatile memory module to instruct a first memory module of the plurality of memory modules to perform a first operation; obtaining a first time threshold corresponding to the first operation; updating a first count value corresponding to the first memory module; and in response to the first count value of the first counter reaching the first time threshold, sending a first query instruction sequence to the rewritable non-volatile memory module to query the state of the first memory module.

In an exemplary embodiment of the invention, the memory management method further includes: and if the first count value does not reach the first time critical value, not sending the first query instruction sequence.

In an exemplary embodiment of the present invention, the step of obtaining a first time threshold corresponding to the first operation includes: according to the type of the first operation, the first time critical value corresponding to the first operation is obtained.

In an example embodiment of the present invention, the step of obtaining the first time threshold corresponding to the first operation according to the instruction type of the first operation includes: determining the first time threshold as a first time value in response to the type of the first operation being a first type of operation; and responsive to the type of the first operation being a second type of operation, determining the first time threshold as a second time value, wherein the first time value is different from the second time value.

In an exemplary embodiment of the invention, the memory management method further includes: and adjusting the first time critical value according to the actual completion time of the first operation.

In an example embodiment of the present invention, the step of obtaining the first time threshold corresponding to the first operation includes: receiving time assessment information corresponding to the first memory module from the rewritable non-volatile memory module; and determining the first time threshold according to the time evaluation information.

In an exemplary embodiment of the invention, the memory management method further includes: sending a second sequence of operation instructions to the rewritable non-volatile memory module to instruct a second memory module of the plurality of memory modules to perform a second operation; obtaining a second time threshold corresponding to the second operation, wherein the second time threshold is different from the first time threshold; updating a second count value corresponding to the second memory module; and in response to the second count value reaching the second time threshold, sending a second query sequence of instructions to the rewritable non-volatile memory module to query a state of the second memory module.

In an exemplary embodiment of the invention, the memory management method further includes: transmitting a third sequence of operating instructions to the rewritable non-volatile memory module to instruct the first memory module to perform a third operation; obtaining a third time threshold corresponding to the third operation, wherein the third time threshold is different from the first time threshold; updating a third count value corresponding to the third memory module; and in response to the third count value reaching the third time threshold, sending a third query instruction sequence to the rewritable non-volatile memory module to query the state of the first memory module.

The exemplary embodiments of the present invention further provide a memory storage device, which includes a connection interface unit, a rewritable nonvolatile memory module, and a memory control circuit unit. The connection interface unit is used for being connected to a host system. The rewritable nonvolatile memory module includes a plurality of memory modules. The memory control circuit unit is connected to the connection interface unit and the rewritable nonvolatile memory module. The memory control circuit unit is used for: transmitting a first sequence of operation instructions to the rewritable non-volatile memory module to instruct a first memory module of the plurality of memory modules to perform a first operation; obtaining a first time threshold corresponding to the first operation; updating a first count value corresponding to the first memory module; and in response to the first count value reaching the first time threshold, sending a first query instruction sequence to the rewritable non-volatile memory module to query the state of the first memory module.

In an exemplary embodiment of the present invention, if the first count value does not reach the first time threshold, the memory control circuit unit does not send the first query instruction sequence.

In an example embodiment of the present invention, the operation of obtaining a first time threshold corresponding to the first operation comprises: according to the type of the first operation, the first time critical value corresponding to the first operation is obtained.

In an example embodiment of the present invention, the operation of obtaining the first time threshold corresponding to the first operation according to the instruction type of the first operation comprises: determining the first time threshold as a first time value in response to the type of the first operation being a first type of operation; and responsive to the type of the first operation being a second type of operation, determining the first time threshold as a second time value, wherein the first time value is different from the second time value.

In an exemplary embodiment of the present invention, the memory control circuit unit is further configured to: and adjusting the first time critical value according to the actual completion time of the first operation.

In an example embodiment of the present invention, the operation of obtaining the first time threshold corresponding to the first operation comprises: receiving time assessment information corresponding to the first memory module from the rewritable non-volatile memory module; and determining the first time threshold according to the time evaluation information.

In an exemplary embodiment of the present invention, the memory control circuit unit is further configured to: sending a second sequence of operation instructions to the rewritable non-volatile memory module to instruct a second memory module of the plurality of memory modules to perform a second operation; obtaining a second time threshold corresponding to the second operation, wherein the second time threshold is different from the first time threshold; updating a second count value corresponding to the second memory module; and in response to the second count value reaching the second time threshold, sending a second query sequence of instructions to the rewritable non-volatile memory module to query a state of the second memory module.

In an exemplary embodiment of the present invention, the memory control circuit unit is further configured to: transmitting a third sequence of operating instructions to the rewritable non-volatile memory module to instruct the first memory module to perform a third operation; obtaining a third time threshold corresponding to the third operation, wherein the third time threshold is different from the first time threshold; updating a third count value corresponding to the third memory module; and in response to the third count value reaching the third time threshold, sending a third query instruction sequence to the rewritable non-volatile memory module to query the state of the first memory module.

The exemplary embodiments of the present invention further provide a memory control circuit unit for controlling a rewritable nonvolatile memory module. The rewritable nonvolatile memory module includes a plurality of memory modules. The memory control circuit unit comprises a host interface, a memory interface and a memory management circuit. The host interface is configured to connect to a host system. The memory interface is configured to connect to a rewritable non-volatile memory module. The memory management circuit is connected to the host interface and the memory interface. The memory management circuit is to: transmitting a first sequence of operation instructions to the rewritable non-volatile memory module to instruct a first memory module of the plurality of memory modules to perform a first operation; obtaining a first time threshold corresponding to the first operation; updating a first count value corresponding to the first memory module; and in response to the first count value reaching the first time threshold, sending a first query instruction sequence to the rewritable non-volatile memory module to query the state of the first memory module.

In an example embodiment of the present invention, the memory management circuit does not send the first query instruction sequence if the first count value does not reach the first time threshold.

In an exemplary embodiment of the present invention, the memory management circuit is further configured to: and adjusting the first time critical value according to the actual completion time of the first operation.

In an exemplary embodiment of the present invention, the memory management circuit is further configured to: sending a second sequence of operation instructions to the rewritable non-volatile memory module to instruct a second memory module of the plurality of memory modules to perform a second operation; obtaining a second time threshold corresponding to the second operation, wherein the second time threshold is different from the first time threshold; updating a second count value corresponding to the second memory module; and in response to the second count value reaching the second time threshold, sending a second query sequence of instructions to the rewritable non-volatile memory module to query a state of the second memory module.

In an exemplary embodiment of the present invention, the memory management circuit is further configured to: transmitting a third sequence of operating instructions to the rewritable non-volatile memory module to instruct the first memory module to perform a third operation; obtaining a third time threshold corresponding to the third operation, wherein the third time threshold is different from the first time threshold; updating a third count value corresponding to the third memory module; and in response to the third count value reaching the third time threshold, sending a third query instruction sequence to the rewritable non-volatile memory module to query the state of the first memory module.

Based on the above, after the first operation instruction sequence is sent to the rewritable nonvolatile memory module to instruct the first memory module to perform the first operation, the first time critical value corresponding to the first operation may be obtained and the first count value corresponding to the first memory module may be updated. Thereafter, in response to the first count value reaching the first time threshold, a first sequence of inquiry instructions may be sent to the rewritable non-volatile memory module to inquire a state of the first memory module. Compared with the traditional polling mechanism, the memory management method, the memory storage device and the memory control circuit unit according to the exemplary embodiment of the invention can effectively improve the state query efficiency of the memory module.

Drawings

FIG. 1 is a schematic diagram of a host system, a memory storage device, and an input/output (I/O) device, according to an example embodiment of the invention;

FIG. 2 is a schematic diagram of a host system, a memory storage device, and an I/O device according to an example embodiment of the invention;

FIG. 3 is a schematic diagram of a host system and a memory storage device according to an example embodiment of the invention;

FIG. 4 is a schematic diagram of a memory storage device according to an example embodiment of the invention;

FIG. 5 is a schematic diagram of a memory control circuit unit shown according to an example embodiment of the invention;

FIG. 6 is a schematic diagram illustrating managing a rewritable non-volatile memory module according to an example embodiment of the present invention;

FIG. 7 is a schematic diagram showing a memory management circuit in communication with a rewritable non-volatile memory module via a plurality of channels according to an example embodiment of the present invention;

FIG. 8 is a schematic diagram illustrating the status of an interrogated memory module according to an example embodiment of the invention;

FIG. 9 is a diagram illustrating time thresholds corresponding to different types of operations according to an example embodiment of the present invention;

fig. 10 is a flowchart of a memory management method according to an exemplary embodiment of the present invention.

Detailed Description

Reference will now be made in detail to the exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts.

Generally, a memory storage device (also referred to as a memory storage system) includes a rewritable nonvolatile memory module (rewritable non-volatile memory module) and a controller (also referred to as a control circuit). The memory storage device may be used with a host system such that the host system may write data to or read data from the memory storage device.

FIG. 1 is a schematic diagram of a host system, a memory storage device, and an input/output (I/O) device according to an example embodiment of the invention. FIG. 2 is a schematic diagram of a host system, a memory storage device, and an I/O device according to an example embodiment of the invention.

Referring to fig. 1 and 2, the host system 11 may include a processor 111, a random access memory (random access memory, RAM) 112, a Read Only Memory (ROM) 113, and a data transfer interface 114. The processor 111, the random access memory 112, the read only memory 113, and the data transfer interface 114 may be connected to a system bus 110.

In an example embodiment, host system 11 may be coupled to memory storage device 10 via data transfer interface 114. For example, host system 11 may store data to memory storage device 10 or read data from memory storage device 10 via data transfer interface 114. In addition, host system 11 may be connected to I/O device 12 via system bus 110. For example, host system 11 may transmit output signals to I/O device 12 or receive input signals from I/O device 12 via system bus 110.

In an exemplary embodiment, the processor 111, the ram 112, the rom 113, and the data transfer interface 114 may be disposed on the motherboard 20 of the host system 11. The number of data transfer interfaces 114 may be one or more. The motherboard 20 may be connected to the memory storage device 10 via a wired or wireless connection via the data transmission interface 114.

In an example embodiment, the memory storage device 10 may be, for example, a usb flash disk 201, a memory card 202, a solid state disk (Solid State Drive, SSD) 203, or a wireless memory storage device 204. The wireless memory storage 204 may be, for example, a near field communication (Near Field Communication, NFC) memory storage, a wireless fidelity (WiFi) memory storage, a Bluetooth (Bluetooth) memory storage, or a Bluetooth low energy memory storage (such as iBeacon) or the like based on a wide variety of wireless communication technologies. In addition, the motherboard 20 may also be connected to various I/O devices such as a global positioning system (Global Positioning System, GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, and a speaker 210 through the system bus 110. For example, in an exemplary embodiment, the motherboard 20 may access the wireless memory storage device 204 through the wireless transmission device 207.

In an example embodiment, host system 11 is a computer system. In an example embodiment, host system 11 may be any system that may substantially cooperate with a memory storage device to store data. In an example embodiment, the memory storage device 10 and the host system 11 may include the memory storage device 30 and the host system 31 of fig. 3, respectively.

FIG. 3 is a schematic diagram of a host system and a memory storage device according to an example embodiment of the invention. Referring to fig. 3, the memory storage device 30 may be used with the host system 31 to store data. For example, the host system 31 may be a system such as a digital camera, video camera, communication device, audio player, video player, or tablet computer. For example, the memory storage device 30 may be a Secure Digital (SD) card 32, a Compact Flash (CF) card 33, or an embedded memory device 34 used by a host system 31. The embedded storage device 34 includes embedded storage devices of various types such as an embedded multimedia card (embedded Multi Media Card, eMMC) 341 and/or an embedded multi-chip package (embedded Multi Chip Package, eMCP) storage device 342 that directly connect the memory module to a substrate of the host system.

Fig. 4 is a schematic diagram of a memory storage device according to an example embodiment of the invention. Referring to fig. 4, the memory storage device 10 includes a connection interface unit 41, a memory control circuit unit 42, and a rewritable nonvolatile memory module 43.

The connection interface unit 41 is used to connect the memory storage device 10 to the host system 11. The memory storage device 10 may communicate with the host system 11 via the connection interface unit 41. In an exemplary embodiment, the connection interface unit 41 is compatible with the PCI Express (Peripheral Component Interconnect Express) standard. However, it should be understood that the present invention is not limited thereto, and the connection interface unit 41 may be a serial advanced technology attachment (Serial Advanced Technology Attachment, SATA) compliant standard, a parallel advanced technology attachment (Parallel Advanced Technology Attachment, PATA) standard, an institute of electrical and electronics engineers (Institute of Electrical and Electronic Engineers, IEEE) 1394 standard, a universal serial bus (Universal Serial Bus, USB) standard, an SD interface standard, a Ultra High Speed-I (UHS-I) interface standard, a Ultra High Speed-II (UHS-II) interface standard, a Memory Stick (MS) interface standard, an MCP interface standard, an MMC interface standard, an eMMC interface standard, a universal flash Memory (Universal Flash Storage, UFS) interface standard, an eMCP interface standard, a CF interface standard, an integrated drive electronics interface (Integrated Device Electronics, IDE) standard, or other suitable standard. The connection interface unit 41 may be packaged in one chip with the memory control circuit unit 42, or the connection interface unit 41 may be disposed outside a chip including the memory control circuit unit 42.

The memory control circuit unit 42 is connected to the connection interface unit 41 and the rewritable nonvolatile memory module 43. The memory control circuit unit 42 is used for executing a plurality of logic gates or control instructions implemented in hardware or firmware and performing operations of writing, reading and erasing data in the rewritable nonvolatile memory module 43 according to the instructions of the host system 11.

The rewritable nonvolatile memory module 43 is used for storing data written by the host system 11. The rewritable nonvolatile memory module 43 may include a single-Level memory Cell (Single Level Cell, SLC) NAND type flash memory module (i.e., a flash memory module that can store 1 bit in one memory Cell), a second-Level memory Cell (MLC) NAND type flash memory module (i.e., a flash memory module that can store 2 bits in one memory Cell), a third-Level memory Cell (Triple Level Cell, TLC) NAND type flash memory module (i.e., a flash memory module that can store 3 bits in one memory Cell), a fourth-Level memory Cell (QLC) NAND type flash memory module (i.e., a flash memory module that can store 4 bits in one memory Cell), other flash memory modules, or other memory modules having the same characteristics.

Each memory cell in the rewritable nonvolatile memory module 43 stores one or more bits with a change in voltage (hereinafter also referred to as a threshold voltage). Specifically, there is a charge trapping layer between the control gate (control gate) and the channel of each memory cell. By applying a write voltage to the control gate, the amount of electrons in the charge trapping layer can be changed, thereby changing the threshold voltage of the memory cell. This operation of changing the threshold voltage of the memory cell is also referred to as "writing data to the memory cell" or "programming" the memory cell. As the threshold voltage changes, each memory cell in the rewritable nonvolatile memory module 43 has a plurality of memory states. By applying the read voltage, it can be determined which memory state a memory cell belongs to, thereby obtaining one or more bits stored in the memory cell.

In an exemplary embodiment, the memory cells of the rewritable nonvolatile memory module 43 may constitute a plurality of physical program units, and the physical program units may constitute a plurality of physical erase units. Specifically, memory cells on the same word line may constitute one or more physical programming units. If each memory cell can store more than 2 bits, the physical programming units on the same word line can be categorized into at least a lower physical programming unit and an upper physical programming unit. For example, the least significant bit (Least Significant Bit, LSB) of a memory cell is that belonging to the lower physical programming cell, and the most significant bit (Most Significant Bit, MSB) of a memory cell is that belonging to the upper physical programming cell. In general, in MLC NAND-type flash memory, the writing speed of the lower physical programming unit is greater than the writing speed of the upper physical programming unit, and/or the reliability of the lower physical programming unit is higher than the reliability of the upper physical programming unit.

In an exemplary embodiment, the physical programming unit is a minimum unit of programming. That is, the physical programming unit is the smallest unit of write data. For example, the physical programming unit may be a physical page (page) or a physical sector (sector). If the physical programming units are physical pages, the physical programming units may include data bits and redundancy bits. The data bit area includes a plurality of physical sectors for storing user data, and the redundant bit area is used for storing system data (e.g., management data such as error correction codes). In an exemplary embodiment, the data bit area includes 32 physical sectors, and one physical sector has a size of 512 bytes (B). However, in other exemplary embodiments, 8, 16 or a greater or lesser number of physical fans may be included in the data bit zone, and the size of each physical fan may be greater or lesser. On the other hand, a physical erase unit is the minimum unit of erase. That is, each physically erased cell contains a minimum number of memory cells that are erased together. For example, the physical erased cells are physical blocks (blocks).

Fig. 5 is a schematic diagram of a memory control circuit unit according to an example embodiment of the invention. Referring to fig. 5, the memory control circuit unit 42 includes a memory management circuit 51, a host interface 52 and a memory interface 53.

The memory management circuit 51 is used for controlling the overall operation of the memory control circuit unit 42. Specifically, the memory management circuit 51 has a plurality of control commands, and when the memory storage device 10 is operated, the control commands are executed to perform operations such as writing, reading and erasing data. The operation of the memory management circuit 51 is explained as follows, which is equivalent to the explanation of the operation of the memory control circuit unit 42.

In an example embodiment, the control instructions of the memory management circuit 51 are implemented in firmware. For example, the memory management circuit 51 has a microprocessor unit (not shown) and a read-only memory (not shown), and the control instructions are burned into the read-only memory. When the memory storage device 10 is in operation, the control instructions are executed by the microprocessor unit to perform operations such as writing, reading and erasing data.

In an exemplary embodiment, the control instructions of the memory management circuit 51 may also be stored in a program code format in a specific area of the rewritable nonvolatile memory module 43 (e.g., a system area dedicated to storing system data in the memory module). In addition, the memory management circuit 51 has a microprocessor unit (not shown), a read only memory (not shown), and a random access memory (not shown). In particular, the rom has a boot code (boot code), and when the memory control circuit unit 42 is enabled, the microprocessor unit executes the boot code to load the control instructions stored in the rewritable nonvolatile memory module 43 into the ram of the memory management circuit 51. Then, the microprocessor unit operates the control instructions to perform operations such as writing, reading and erasing of data.

In an exemplary embodiment, the control instructions of the memory management circuit 51 may also be implemented in a hardware type. For example, the memory management circuit 51 includes a microcontroller, a memory cell management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The memory cell management circuit, the memory write circuit, the memory read circuit, the memory erase circuit and the data processing circuit are connected to the microcontroller. The memory cell management circuit is used to manage the memory cells or groups of memory cells of the rewritable nonvolatile memory module 43. The memory write circuit is used for issuing a write instruction sequence to the rewritable nonvolatile memory module 43 to write data into the rewritable nonvolatile memory module 43. The memory read circuit is used for issuing a read instruction sequence to the rewritable nonvolatile memory module 43 to read data from the rewritable nonvolatile memory module 43. The memory erase circuit is used for issuing an erase command sequence to the rewritable nonvolatile memory module 43 to erase data from the rewritable nonvolatile memory module 43. The data processing circuit is used for processing data to be written into the rewritable nonvolatile memory module 43 and data read from the rewritable nonvolatile memory module 43. The write command sequence, the read command sequence, and the erase command sequence may each include one or more program codes or command codes and are used to instruct the rewritable nonvolatile memory module 43 to perform corresponding writing, reading, and erasing operations. In an example embodiment, the memory management circuit 51 may also issue other types of instruction sequences to the rewritable nonvolatile memory module 43 to instruct the corresponding operations to be performed.

The host interface 52 is connected to the memory management circuit 51. Memory management circuitry 51 may communicate with host system 11 through host interface 52. The host interface 52 is used to receive and identify the commands and data transmitted by the host system 11. For example, instructions and data transmitted by host system 11 may be transmitted to memory management circuit 51 via host interface 52. In addition, the memory management circuitry 51 may communicate data to the host system 11 through the host interface 52. In the present example embodiment, host interface 52 is compatible with the PCI Express standard. However, it should be understood that the present invention is not limited thereto, and the host interface 52 may also be compatible with SATA standards, PATA standards, IEEE 1394 standards, USB standards, SD standards, UHS-I standards, UHS-II standards, MS standards, MMC standards, eMMC standards, UFS standards, CF standards, IDE standards, or other suitable data transfer standards.

The memory interface 53 is connected to the memory management circuit 51 and is used to access the rewritable nonvolatile memory module 43. For example, the memory management circuit 51 may access the rewritable nonvolatile memory module 43 through the memory interface 53. That is, the data to be written into the rewritable nonvolatile memory module 43 is converted into a format acceptable to the rewritable nonvolatile memory module 43 through the memory interface 53. Specifically, if the memory management circuit 51 is to access the rewritable nonvolatile memory module 43, the memory interface 53 transmits the corresponding instruction sequence. For example, the instruction sequences may include a write instruction sequence that indicates write data, a read instruction sequence that indicates read data, an erase instruction sequence that indicates erase data, and corresponding instruction sequences to indicate various memory operations (e.g., changing read voltage levels or performing garbage collection operations, etc.). These sequences of instructions are, for example, generated by the memory management circuit 51 and transferred to the rewritable non-volatile memory module 43 via the memory interface 53. These instruction sequences may include one or more signals, or data, on a bus. Such signals or data may include instruction code or program code. For example, the read instruction sequence may include information such as a read identification code and a memory address.

In an exemplary embodiment, the memory control circuit unit 42 further includes an error checking and correction circuit 54, a buffer memory 55, and a power management circuit 56.

The error checking and correcting circuit 54 is connected to the memory management circuit 51 and is used for performing error checking and correcting operations to ensure the correctness of the data. Specifically, when the memory management circuit 51 receives a write command from the host system 11, the error checking and correcting circuit 54 generates a corresponding error correction code (error correcting code, ECC) and/or error checking code (error detecting code, EDC) for the data corresponding to the write command, and the memory management circuit 51 writes the data corresponding to the write command and the corresponding error correction code and/or error checking code into the rewritable nonvolatile memory module 43. Then, when the memory management circuit 51 reads data from the rewritable nonvolatile memory module 43, the error correction code and/or the error check code corresponding to the data are read at the same time, and the error check and correction circuit 54 performs an error check and correction operation on the read data according to the error correction code and/or the error check code.

The buffer memory 55 is connected to the memory management circuit 51 and is used for temporarily storing data. The power management circuit 56 is connected to the memory management circuit 51 and is used to control the power of the memory storage device 10.

In an example embodiment, the rewritable non-volatile memory module 43 of fig. 4 may include a flash memory module. In an example embodiment, the memory control circuit unit 42 of fig. 4 may include a flash memory controller. In an example embodiment, the memory management circuit 51 of fig. 5 may include a flash memory management circuit.

FIG. 6 is a schematic diagram illustrating managing a rewritable non-volatile memory module according to an example embodiment of the present invention. Referring to FIG. 6, the memory management circuit 51 can logically group the physical units 610 (0) -610 (B) in the rewritable nonvolatile memory module 43 into a memory area 601 and a spare (spare) area 602.

In an exemplary embodiment, a physical unit refers to a physical address or a physical programming unit. In an exemplary embodiment, a physical unit may also be composed of a plurality of consecutive or non-consecutive physical addresses. In an exemplary embodiment, a physical unit may also be referred to as a Virtual Block (VB). A virtual block may include multiple physical addresses or multiple physical programming units.

The physical units 610 (0) -610 (a) in the storage area 601 are configured to store user data (e.g., user data from the host system 11 of fig. 1). For example, the entity units 610 (0) to 610 (a) in the storage area 601 may store valid (valid) data and invalid (invalid) data. The physical units 610 (a+1) -610 (B) in the free area 602 do not store data (e.g., valid data). For example, if a physical unit does not store valid data, the physical unit may be associated (or added) to the idle area 602. In addition, the physical cells in the free area 602 (or the physical cells that do not store valid data) may be erased. When writing new data, one or more physical units may be extracted from the spare area 602 to store the new data. In an exemplary embodiment, the free area 602 is also referred to as a free pool (free pool).

The memory management circuit 51 may configure the logic units 612 (0) through 612 (C) to map the physical units 610 (0) through 610 (A) in the memory area 601. In an exemplary embodiment, each logical unit corresponds to a logical address. For example, a logical address may include one or more logical block addresses (Logical Block Address, LBAs) or other logical management units. In an exemplary embodiment, a logic unit may also correspond to a logic programming unit or be composed of a plurality of consecutive or non-consecutive logic addresses.

It should be noted that a logical unit may be mapped to one or more physical units. If a certain entity unit is currently mapped by a certain logic unit, the data currently stored in the entity unit includes valid data. Otherwise, if a certain entity unit is not mapped by any logic unit, the data stored in the entity unit is invalid.

The memory management circuit 51 may record management data (also referred to as logic-to-entity mapping information) describing a mapping relationship between the logic units and the entity units in at least one logic-to-entity mapping table. When the host system 11 wants to read data from the memory storage device 10 or write data to the memory storage device 10, the memory management circuit 51 can access the rewritable nonvolatile memory module 43 according to the information in the logical-to-physical mapping table.

FIG. 7 is a schematic diagram illustrating a memory management circuit in communication with a rewritable non-volatile memory module via multiple channels according to an example embodiment of the present invention. Referring to fig. 7, the rewritable nonvolatile memory module 43 may include a plurality of memory modules 71 (0) to 71 (n). n may be any positive integer. Each of the memory modules 71 (0) -71 (n) may include a plurality of physical units. Each of the memory modules 71 (0) -71 (n) may perform data reading, writing, or erasing operations individually. In addition, a plurality of memory modules 71 (0) to 71 (n) may perform data reading, writing or erasing operations in parallel. For example, one of the memory modules 71 (0) -71 (n) may refer to a plane (plane), a Chip Enable (CE) area, a die (die), or other entity management unit.

Memory management circuit 51 may communicate with memory modules 71 (0) through 71 (n) via channels 70 (0) through 70 (n), respectively. For example, the memory management circuitry 51 may issue operating instructions to the memory module 71 (i) via the channel 70 (i). Memory module 71 (i) may receive this operating instruction via channel 70 (i) and perform the corresponding operating behavior. In addition, the memory module 71 (i) may communicate data back to the memory management circuit 51 via the channel 70 (i). Alternatively, in an exemplary embodiment, a plurality of memory modules 71 (0) -71 (n) may share the same channel 70 (i).

The memory management circuit 51 may send a sequence of operation instructions (also referred to as a first sequence of operation instructions) to the rewritable nonvolatile memory module 43 to instruct one of the memory modules 71 (0) to 71 (n) (also referred to as a first memory module) to perform a specific operation (also referred to as a first operation). For example, assuming the first memory module is memory module 71 (i), memory module 71 (i) may perform the first operation according to the first sequence of operation instructions. For example, the first operation may include reading data from at least one physical cell in memory module 71 (i), writing data to at least one physical cell in memory module 71 (i), or erasing at least one physical cell in memory module 71 (i).

In addition, the memory management circuit 51 may obtain a time threshold (also referred to as a first time threshold) corresponding to the first operation. The first time threshold may be close to the time required for the first memory module to perform the first operation. For example, assuming that the time required for the first memory module to fully perform the first operation is approximately 30 microseconds (μs), the first time threshold may be approximately and/or slightly less than 30 microseconds.

After sending the first sequence of operation instructions, the memory management circuit 51 may continually update a count value (also referred to as a first count value) corresponding to the first memory module. The first count value may be positively correlated to the length of time elapsed after the memory management circuit 51 issued the first sequence of operation instructions. For example, assume that the first count value is 20, which means that approximately 20 microseconds has elapsed after the memory management circuit 51 issues the first operation instruction sequence.

In an example embodiment, the memory management circuit 51 may determine whether the first count value reaches (e.g., is greater than or equal to) a first time threshold. If the first count value reaches the first time threshold, it indicates that the first operation performed by the first memory module has a high probability of being completed or nearly completed. If the first operation performed by the first memory module is completed, the first memory module may switch to a ready (ready) state. In the standby state, the first memory module may begin to perform the next operation. In addition, if the first count value does not reach the first time threshold, it indicates that the first operation performed by the first memory module has a high probability of not being completed. If the first operation performed by the first memory module is not yet completed, the first memory module may be continuously in a busy state. In a busy state, the first memory module cannot perform other operations.

In response to the first count value reaching the first time threshold, the memory management circuit 51 may send a query instruction sequence (also referred to as a first query instruction sequence) to the rewritable nonvolatile memory module 43 to query the status of the first memory module. For example, assuming the first memory module is memory module 71 (i), the first query instruction sequence may be transmitted via channel 70 (i). In response to the first query sequence, the rewritable nonvolatile memory module 43 may transmit a status information (also referred to as a first status information) back to the memory management circuit 51. The memory management circuit 51 may obtain the state of the first memory module based on this state information. For example, assuming the first memory module is memory module 71 (i), the first state information may be transmitted via channel 70 (i). Alternatively, in an exemplary embodiment, if the first count value does not reach the first time threshold, the memory management circuit 51 may not send the first query instruction sequence.

Fig. 8 is a schematic diagram illustrating a state of an interrogating memory module according to an example embodiment of the invention. Referring to fig. 7 and 8, in an exemplary embodiment, at a certain point in time (also referred to as a first point in time), the memory management circuit 51 may send a query command sequence to the rewritable nonvolatile memory module 43 to query the states of the memory modules 71 (0) and 71 (2). However, memory module 71 (1) is skipped. In response to the query instruction sequence, memory modules 71 (0) and 71 (2) may report their respective states to memory management circuit 51, but memory module 71 (1) does not have to report its states to memory management circuit 51. Thus, status queries may be made for memory modules that are about to complete or have completed a task, such as memory modules 71 (0) and 71 (2). On the other hand, for a memory module whose task is significantly not yet completed (e.g., memory module 71 (1)), its status may be temporarily not queried to avoid occupying the communication bandwidth between the memory management circuit 51 and the rewritable nonvolatile memory module 43. Furthermore, in the example embodiment of FIG. 8, at a first point in time, the status of more or fewer memory modules may be queried and/or more or fewer memory modules may be skipped, as the invention is not limited.

In an example embodiment, the memory management circuit 51 may obtain a first time threshold corresponding to the first operation according to the type of the first operation. For example, the first time threshold obtained may be different depending on the different types of first operations.

In an example embodiment, in response to the type of the first operation being the first type of operation, the memory management circuit 51 may determine the first time threshold as a certain time value (also referred to as a first time value). Alternatively, in response to the type of the first operation being the second type of operation, the memory management circuit 51 may determine the first time threshold as another time value (also referred to as a second time value). The first time value may be different from the second time value. For example, assuming the first operation is a read operation, the first time threshold may be determined to be 27 or 30 microseconds. Alternatively, assuming the first operation is a write operation, the first time threshold may be determined to be 115 or 120 microseconds.

Fig. 9 is a diagram illustrating time thresholds corresponding to different types of operations according to an exemplary embodiment of the present invention. Referring to FIG. 9, in an exemplary embodiment, the memory management circuit 51 may query the table information 91 to obtain a time threshold corresponding to a particular type of operation. The table information 91 may be stored in the rewritable nonvolatile memory module 43. For example, the table information 91 may record time thresholds T (a), T (B), and T (C) corresponding to different types of operations (a), B, and C, respectively. For example, operations (a), (B), and (C) may be a read operation, a write operation, and an erase operation, respectively. Depending on the type of the first operation, the memory management circuit 51 may obtain a first time threshold corresponding to the first operation from the table information 91. For example, assuming that the first operation belongs to operation (a), the memory management circuit 51 may set the first time threshold according to the time threshold T (a).

In an example embodiment, the memory management circuit 51 may record the actual completion time of the first operation. The memory management circuit 51 may then adjust the first time threshold according to the actual completion time of the first operation. For example, it is assumed that the first operation belongs to operation (a) in the table information 91. After the first memory module performs the first operation, the memory management circuit 51 may record the actual completion time of the first operation and update or adjust the time threshold T (a) in the table information 91 according to the actual completion time. Thereby, the table information 91 can be continuously maintained according to the latest state of each memory module.

In an example embodiment, after sending the first sequence of operation instructions, the memory management circuit 51 may receive time assessment information corresponding to the first memory module from the rewritable non-volatile memory module 43. This time assessment information may reflect the length of time required for the first memory module to perform the first operation. For example, assume that the first memory module is memory module 70 (i) and that the length of time required for memory module 70 (i) to fully perform the first operation is approximately 30 microseconds. The rewritable nonvolatile memory module 43 may transfer time evaluation information corresponding to the first memory module to the memory management circuit 51 via the channel 70 (i). The memory management circuit 51 may obtain the time required for the memory module 70 (i) to completely perform the first operation for about 30 microseconds based on the time evaluation information. Then, the memory management circuit 51 may determine a first time threshold according to the time evaluation information, for example, set the first time threshold to 27 microseconds (for example, 30×0.9=27).

Referring back to fig. 7, in an example embodiment, the memory management circuit 51 may send another operation instruction sequence (also referred to as a second operation instruction sequence) to the rewritable nonvolatile memory module 43 to instruct another memory module (also referred to as a second memory module) in the rewritable nonvolatile memory module 43 to perform a specific operation (also referred to as a second operation). The memory management circuit 51 may obtain a time threshold value (also referred to as a second time threshold value) corresponding to the second operation. In particular, the second time threshold may be different from the first time threshold. For example, the first time threshold may be 27 microseconds (corresponding to the first operation being a read operation) and the second time threshold may be 115 microseconds (corresponding to the second operation being a write operation).

After sending the second sequence of operation instructions, the memory management circuit 51 may continually update a count value (also referred to as a second count value) corresponding to the second memory module. In response to the second count value reaching the second time threshold, the memory management circuit 51 may send a query instruction sequence (also referred to as a second query instruction sequence) to the rewritable nonvolatile memory module 43 to query the status of the second memory module. In addition, if the second count value does not reach the second time threshold, the memory management circuit 51 may not send the second query instruction sequence. Details of the related operations may be referred to the description of the foregoing exemplary embodiments, and are not repeated herein.

In an example embodiment, the memory management circuit 51 may send another sequence of operation instructions (also referred to as a third sequence of operation instructions) to the rewritable nonvolatile memory module 43 to instruct the first memory module to perform a specific operation (also referred to as a third operation). The memory management circuit 51 may obtain a time threshold value (also referred to as a third time threshold value) corresponding to the third operation. In particular, the third time threshold may be different from the first time threshold. For example, the first time threshold may be 27 microseconds (corresponding to the first operation being a read operation) and the third time threshold may be 115 microseconds (corresponding to the third operation being a write operation).

After sending the third sequence of operation instructions, the memory management circuit 51 may continually update the first count value corresponding to the first memory module. In response to the first count value reaching the third time threshold, the memory management circuit 51 may send a query instruction sequence (also referred to as a third query instruction sequence) to the rewritable nonvolatile memory module 43 to query the status of the first memory module. In addition, if the first count value does not reach the third time threshold, the memory management circuit 51 may not send the third query instruction sequence. Details of the related operations may be referred to the description of the foregoing exemplary embodiments, and are not repeated herein.

In an exemplary embodiment, if the state of a certain memory module (e.g., the first memory module) obtained by the query is a busy state, the memory module may be added to a polling list. Thereafter, the memory management circuit 51 may resend the inquiry command sequence to inquire the state of the memory module at intervals according to the polling list until the state of the memory module is switched to the standby state. In addition, the memory management circuit 51 may issue a new operation instruction sequence to the memory module in the standby state to instruct the memory module in the standby state to execute the next operation.

Fig. 10 is a flowchart of a memory management method according to an exemplary embodiment of the present invention. Referring to fig. 10, in step S1001, a first operation instruction sequence is sent to the rewritable nonvolatile memory module to instruct the first memory module to perform a first operation. In step S1002, a first time threshold corresponding to a first operation is obtained. In step S1003, a first count value corresponding to the first memory module is updated. In step S1004, it is determined whether the first count value reaches a first time threshold. In response to the first count value reaching the first time threshold, in step S1005, a first query command sequence is sent to the rewritable non-volatile memory module to query the state of the first memory module. Alternatively, if the first count value does not reach the first time threshold, step S1004 may be repeated.

However, the steps in fig. 10 are described in detail above, and will not be described again here. It should be noted that each step in fig. 10 may be implemented as a plurality of program codes or circuits, and the present invention is not limited thereto. In addition, the method of fig. 10 may be used with the above exemplary embodiment, or may be used alone, and the present invention is not limited thereto.

In summary, the exemplary embodiments of the present invention set the time threshold for the operation task performed by the specific memory module. Then, only when the count value corresponding to the memory module meets the time critical value, the memory module is subjected to state inquiry. Therefore, even if the total number of the memory modules is continuously increased, the state query efficiency of the memory modules can be effectively improved.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the invention.

Claims

1. A memory management method for a rewritable nonvolatile memory module including a plurality of memory modules, the memory management method comprising:

transmitting a first sequence of operation instructions to the rewritable non-volatile memory module to instruct a first memory module of the plurality of memory modules to perform a first operation;

obtaining a first time threshold corresponding to the first operation;

updating a first count value corresponding to the first memory module, wherein the first count value is positively correlated to an elapsed length of time after the first sequence of operating instructions is issued;

responsive to the first count value reaching the first time threshold, sending a first query sequence of instructions to the rewritable non-volatile memory module to query a state of the first memory module; and

and if the first count value does not reach the first time critical value, not sending the first query instruction sequence.

2. The memory management method of claim 1, wherein the step of obtaining a first time threshold corresponding to the first operation comprises:

According to the type of the first operation, the first time critical value corresponding to the first operation is obtained.

3. The memory management method of claim 2, wherein obtaining the first time threshold corresponding to the first operation according to the type of the first operation comprises:

determining the first time threshold as a first time value in response to the type of the first operation being a first type of operation; and

in response to the type of the first operation being a second type of operation, determining the first time threshold as a second time value,

wherein the first time value is different from the second time value.

4. The memory management method of claim 1, further comprising:

and adjusting the first time critical value according to the actual completion time of the first operation.

5. The memory management method of claim 1, wherein obtaining the first time threshold corresponding to the first operation comprises:

receiving time assessment information corresponding to the first memory module from the rewritable non-volatile memory module, wherein the time assessment information reflects a length of time required for the first memory module to perform the first operation; and

And determining the first time critical value according to the time evaluation information.

6. The memory management method of claim 1, further comprising:

sending a second sequence of operation instructions to the rewritable non-volatile memory module to instruct a second memory module of the plurality of memory modules to perform a second operation;

obtaining a second time threshold corresponding to the second operation, wherein the second time threshold is different from the first time threshold;

updating a second count value corresponding to the second memory module, wherein the second count value is positively correlated to an elapsed length of time after the second sequence of operating instructions was issued; and

and in response to the second count value reaching the second time critical value, sending a second query instruction sequence to the rewritable nonvolatile memory module so as to query the state of the second memory module.

7. The memory management method of claim 1, further comprising:

transmitting a third sequence of operating instructions to the rewritable non-volatile memory module to instruct the first memory module to perform a third operation;

obtaining a third time threshold corresponding to the third operation, wherein the third time threshold is different from the first time threshold;

Updating a third count value corresponding to the first memory module, wherein the third count value is directly related to an elapsed length of time after the third sequence of operating instructions was issued; and

and in response to the third count value reaching the third time threshold, sending a third query instruction sequence to the rewritable non-volatile memory module to query the state of the first memory module.

8. A memory storage device, comprising:

a connection interface unit for connecting to a host system;

a rewritable nonvolatile memory module including a plurality of memory modules; and

a memory control circuit unit connected to the connection interface unit and the rewritable nonvolatile memory module,

wherein the memory control circuit unit is configured to:

obtaining a first time threshold corresponding to the first operation;

if the first count value does not reach the first time threshold, the memory control circuit unit does not send the first query instruction sequence.

9. The memory storage device of claim 8, wherein obtaining a first time threshold corresponding to the first operation comprises:

10. The memory storage device of claim 9, wherein obtaining the first time threshold corresponding to the first operation according to the type of the first operation comprises:

wherein the first time value is different from the second time value.

11. The memory storage device of claim 8, wherein the memory control circuit unit is further to:

12. The memory storage device of claim 8, wherein obtaining the first time threshold corresponding to the first operation comprises:

13. The memory storage device of claim 8, wherein the memory control circuit unit is further to:

14. The memory storage device of claim 8, wherein the memory control circuit unit is further to:

15. A memory control circuit unit for controlling a rewritable nonvolatile memory module including a plurality of memory modules, the memory control circuit unit comprising:

a host interface for connecting to a host system;

a memory interface for connecting to a rewritable non-volatile memory module; and

a memory management circuit coupled to the host interface and the memory interface,

wherein the memory management circuit is to:

obtaining a first time threshold corresponding to the first operation;

If the first count value does not reach the first time threshold, the memory management circuit does not send the first query instruction sequence.

16. The memory control circuit unit of claim 15, wherein obtaining a first time threshold corresponding to the first operation comprises:

17. The memory control circuit unit of claim 16, wherein obtaining the first time threshold corresponding to the first operation according to the type of the first operation comprises:

wherein the first time value is different from the second time value.

18. The memory control circuit unit of claim 15, wherein the memory management circuit is further to:

19. The memory control circuit unit of claim 15, wherein obtaining the first time threshold corresponding to the first operation comprises:

20. The memory control circuit unit of claim 15, wherein the memory management circuit is further to:

21. The memory control circuit unit of claim 15, wherein the memory management circuit is further to: