CN113720455A

CN113720455A - Infrared detector based on CMOS (complementary Metal oxide semiconductor) process

Info

Publication number: CN113720455A
Application number: CN202110324077.4A
Authority: CN
Inventors: 翟光杰; 武佩; 潘辉; 翟光强
Original assignee: Beijing North Gaoye Technology Co ltd
Current assignee: Beijing North Gaoye Technology Co ltd
Priority date: 2021-03-26
Filing date: 2021-03-26
Publication date: 2021-11-30

Abstract

The present disclosure relates to an infrared detector based on a CMOS process, the infrared detector comprising: infrared detector pixels arranged in an array; the pixel comprises a CMOS measuring circuit system and a CMOS infrared sensing structure on the CMOS measuring circuit system, and is prepared by adopting a full CMOS process; the CMOS infrared sensing structure comprises a reflecting layer, an infrared conversion structure and a plurality of columnar structures, wherein the reflecting layer, the infrared conversion structure and the plurality of columnar structures are positioned on the CMOS measuring circuit system; at least two infrared detector pixels share at least one columnar structure. By the technical scheme, the problems of low performance, low pixel scale, low yield and the like of the traditional MEMS process infrared detector are solved; and the occupied space of the columnar structure is reduced, correspondingly, the layout area of the infrared conversion structure is increased, and the duty ratio of the infrared detector is favorably improved.

Description

Infrared detector based on CMOS (complementary Metal oxide semiconductor) process

Technical Field

The present disclosure relates to the field of infrared detection technologies, and in particular, to an infrared detector based on a CMOS process.

Background

The fields of monitoring markets, vehicle and auxiliary markets, home markets, intelligent manufacturing markets, mobile phone applications and the like have strong demands on uncooled high-performance chips, certain requirements are provided for the performance of the chips, the performance consistency and the product price, the potential demands of more than one hundred million chips are expected every year, and the current process scheme and architecture cannot meet the market demands.

At present, an infrared detector adopts a mode of combining a measuring circuit and an infrared sensing structure, the measuring circuit is prepared by adopting a Complementary Metal-Oxide-Semiconductor (CMOS) process, and the infrared sensing structure is prepared by adopting a Micro-Electro-Mechanical System (MEMS) process, so that the following problems are caused:

(1) the infrared sensing structure is prepared by adopting an MEMS (micro-electromechanical systems) process, polyimide is used as a sacrificial layer, and the infrared sensing structure is incompatible with a CMOS (complementary metal oxide semiconductor) process.

(2) Polyimide is used as a sacrificial layer, so that the problem that the vacuum degree of a detector chip is influenced due to incomplete release exists, the growth temperature of a subsequent film is limited, and the selection of materials is not facilitated.

(3) Polyimide can cause the height of the resonant cavity to be inconsistent, and the working dominant wavelength is difficult to guarantee.

(4) The control of the MEMS process is far worse than that of the CMOS process, and the performance consistency and the detection performance of the chip are restricted.

(5) MEMS has low productivity, low yield and high cost, and can not realize large-scale batch production.

(6) The existing process capability of the MEMS is not enough to support the preparation of a detector with higher performance, and the MEMS has smaller line width and thinner film thickness, thereby being not beneficial to realizing the miniaturization of a chip.

Meanwhile, each infrared detector pixel is provided with a respective columnar structure, and the occupied space of the columnar structures is large, so that the area of an infrared conversion structure is small, and the duty ratio of the infrared detector is small.

Disclosure of Invention

In order to solve the technical problems or at least partially solve the technical problems, the present disclosure provides an infrared detector based on a CMOS process, which solves the problems of low performance, low pixel scale, low yield, etc. of the conventional MEMS process infrared detector; and the occupied space of the columnar structure is reduced, correspondingly, the layout area of the infrared conversion structure is increased, and the duty ratio of the infrared detector is favorably improved.

The present disclosure provides an infrared detector based on a CMOS process, the infrared detector including:

infrared detector pixels arranged in an array; the infrared detector pixel comprises a readout circuit substrate CMOS measuring circuit system and a sensor structure CMOS infrared sensing structure positioned on the readout circuit substrate CMOS measuring circuit system, the readout circuit substrate CMOS measuring circuit system and the sensor structure CMOS infrared sensing structure are both prepared by adopting CMOS technology, and the CMOS infrared sensing structure is directly prepared on the CMOS measuring circuit system;

The CMOS measurement circuit system comprises at least one layer of closed release isolation layer above the CMOS measurement circuit system, wherein the closed release isolation layer is used for protecting the CMOS measurement circuit system from being influenced by a process in the etching process of manufacturing the CMOS infrared sensing structure;

the CMOS manufacturing process of the CMOS infrared sensing structure comprises a metal interconnection process, a through hole process and an RDL (remote data link) process, wherein the CMOS infrared sensing structure comprises at least two metal layers, at least two dielectric layers and a plurality of interconnection through holes;

the CMOS infrared sensing structure comprises a reflecting layer, an infrared conversion structure and a plurality of columnar structures, wherein the reflecting layer, the infrared conversion structure and the columnar structures are positioned on the CMOS measuring circuit system;

at least two infrared detector pixels share at least one columnar structure.

In some embodiments, the CMOS infrared sensing structure comprises a sacrificial layer, the sacrificial layer is used for enabling the CMOS infrared sensing structure to form a hollow structure, the material forming the sacrificial layer is silicon oxide, and the sacrificial layer is etched by a post-CMOS process;

The post-CMOS process etches the sacrificial layer using at least one of gaseous hydrogen fluoride, carbon tetrafluoride, and trifluoromethane.

In some embodiments, the same columnar structure is shared by at least two adjacent infrared detector pixels.

In some embodiments, the infrared detector pixels are arranged in rows and columns;

two adjacent infrared detector pixels in the same row share at least one columnar structure; and/or

Two adjacent infrared detector pixels in the same column share at least one columnar structure.

In some embodiments, the columnar structures comprise a single layer of pillars.

In some embodiments, the columnar structure comprises at least two superimposed layers of pillars;

the columns of each layer are arranged in a one-to-one correspondence mode.

In some embodiments, the columnar structure comprises a lower layer pillar and an upper layer pillar, the lower layer pillar being connected between the upper layer pillar and the support base, the upper layer pillar being connected between the lower layer pillar and the infrared conversion structure;

one lower layer column correspondingly supports at least two upper layer columns;

at least two infrared detector pixels share at least one lower-layer pillar;

And each infrared detector pixel is independently provided with the upper layer pillar.

In some embodiments, the pillars corresponding to the same infrared detector pixel are all the same size;

alternatively, the size of the column that is shared is larger than the size of the column that is not shared.

In some embodiments, each of the infrared detector pixels is supported by four of the columnar structures;

or each infrared detector pixel is supported by two columnar structures.

In some embodiments, the total height of the columnar structures is greater than or equal to 1.5 micrometers and less than or equal to 2.5 micrometers.

In some embodiments, a unidirectional width of a cross section of one side of the columnar structure, which is connected with the infrared conversion structure, is less than or equal to 3 micrometers.

Compared with the prior art, the technical scheme provided by the embodiment of the disclosure has the following advantages:

(1) in the infrared detector pixel provided by the embodiment of the disclosure, the CMOS process is utilized to realize the integrated preparation of the CMOS measurement circuit system and the CMOS infrared sensing structure on the CMOS production line, compared with the MEMS process, the CMOS has no process compatibility problem, the technical difficulty faced by the MEMS process is solved, and the transportation cost can be reduced and the risk caused by the problems of transportation and the like can be reduced by adopting the CMOS process production line process to prepare the infrared detector; the infrared detector takes silicon oxide as a sacrificial layer, the silicon oxide is completely compatible with a CMOS (complementary metal oxide semiconductor) process, the preparation process is simple and easy to control, the CMOS process does not have the problem that the polyimide of the sacrificial layer is not released cleanly to influence the vacuum degree of a detector chip, the subsequent film growth temperature is not limited by the material of the sacrificial layer, the multilayer process design of the sacrificial layer can be realized, the process is not limited, the planarization can be easily realized by using the sacrificial layer, and the process difficulty and the possible risks are reduced; the infrared detector prepared by the integrated CMOS process can realize the aims of high yield, low cost, high yield and large-scale integrated production of chips, and provides a wider application market for the infrared detector; the infrared detector based on the CMOS process can realize smaller size and thinner film thickness of a characteristic structure, so that the infrared detector has larger duty ratio, lower thermal conductivity and smaller thermal capacity, and the infrared detector has higher detection sensitivity, longer detection distance and better detection performance; the infrared detector based on the CMOS process can make the pixel size of the detector smaller, realize smaller chip area under the same array pixel, and is more beneficial to realizing the miniaturization of a chip; the infrared detector based on the CMOS process has mature process production line and higher process control precision, can better meet the design requirement, has better product consistency, is more beneficial to the adjustment performance of a circuit chip and is more beneficial to industrialized mass production;

(2) Through setting up at least one columnar structure by two at least infrared detector pixel commons, for setting up its respective columnar structure respectively to every infrared detector pixel, the quantity of columnar structure in the reducible infrared detector to reduce the shared space of columnar structure in infrared detector, correspondingly, increased the effective area percentage in the infrared conversion structure, promoted infrared detector's duty cycle.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and together with the description, serve to explain the principles of the disclosure.

In order to more clearly illustrate the embodiments or technical solutions in the prior art of the present disclosure, the drawings used in the description of the embodiments or prior art will be briefly described below, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without inventive exercise.

Fig. 1 is a schematic perspective view of an infrared detector according to an embodiment of the present disclosure;

fig. 2 is a schematic cross-sectional view of an infrared detector according to an embodiment of the disclosure;

Fig. 3 is a schematic plan view of an infrared detector according to an embodiment of the present disclosure;

FIG. 4 is a schematic plan view of another infrared detector according to an embodiment of the present disclosure;

FIG. 5 is a schematic plan view of another infrared detector according to an embodiment of the disclosure;

FIG. 6 is a schematic plan view of another infrared detector according to an embodiment of the disclosure;

FIG. 7 is a schematic cross-sectional view of another infrared detector according to an embodiment of the disclosure;

FIG. 8 is a schematic diagram of a CMOS measurement circuitry according to an embodiment of the disclosure;

FIG. 9 is a schematic cross-sectional view of another infrared detector in accordance with an embodiment of the present disclosure;

FIG. 10 is a schematic cross-sectional view of another infrared detector in accordance with an embodiment of the present disclosure;

FIG. 11 is a schematic cross-sectional view of another infrared detector in accordance with an embodiment of the present disclosure;

FIG. 12 is a schematic cross-sectional view of another infrared detector in accordance with an embodiment of the disclosure;

fig. 13 is a schematic perspective view of another infrared detector according to an embodiment of the disclosure.

Detailed Description

In order that the above objects, features and advantages of the present disclosure may be more clearly understood, aspects of the present disclosure will be further described below. It should be noted that the embodiments and features of the embodiments of the present disclosure may be combined with each other without conflict.

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure, but the present disclosure may be practiced in other ways than those described herein; it is to be understood that the embodiments disclosed in the specification are only a few embodiments of the present disclosure, and not all embodiments.

Fig. 1 is a schematic perspective structure diagram of an infrared detector according to an embodiment of the present disclosure, fig. 2 is a schematic sectional structure diagram of an infrared detector according to an embodiment of the present disclosure, and fig. 3 is a schematic plan structure diagram of an infrared detector according to an embodiment of the present disclosure. Fig. 2 shows a partial cross-sectional structure of the infrared detector in an XZ plane, a YZ plane, or a plane extending in a Z direction to form a plane, and fig. 3 shows a partial cross-sectional structure of the infrared detector in an XY plane, which is provided only for explaining the structure of the infrared detector provided by the embodiment of the present disclosure and does not constitute a limitation to the infrared detector provided by the embodiment of the present disclosure. Referring to fig. 1 to 3, the infrared detector includes: infrared detector pixels 10 arranged in an array; the infrared detector pixel 10 comprises a CMOS measuring circuit system 1 and a CMOS infrared sensing structure 2 positioned on the CMOS measuring circuit system 1, wherein the CMOS measuring circuit system 1 and the CMOS infrared sensing structure 2 are both prepared by adopting a CMOS process; the CMOS infrared sensing structure 2 is fabricated directly on the CMOS measurement circuitry 1.

Specifically, the CMOS infrared sensing structure 2 is configured to convert an external infrared signal into an electrical signal and transmit the electrical signal to the CMOS measurement circuit system 1, and the CMOS measurement circuit system 1 reflects temperature information corresponding to the infrared signal according to the received electrical signal, thereby implementing a temperature detection function of the infrared detector. The CMOS measuring circuit system 1 and the CMOS infrared sensing structure 2 are both prepared by using a CMOS process, and the CMOS infrared sensing structure 2 is directly prepared on the CMOS measuring circuit system 1, namely, the CMOS measuring circuit system 1 is prepared by using the CMOS process, and then the CMOS infrared sensing structure 2 is continuously prepared by using the CMOS process by using the CMOS production line and parameters of various processes compatible with the production line.

Therefore, the CMOS measurement circuit system 1 and the CMOS infrared sensing structure 2 are integrally prepared on the CMOS production line by utilizing the CMOS process, compared with the MEMS process, the CMOS process does not have the process compatibility problem, the technical difficulty of the MEMS process is solved, the transportation cost can be reduced by adopting the CMOS production line process to prepare the infrared detector, and the risk caused by the transportation problem and the like is reduced; the infrared detector takes silicon oxide as a sacrificial layer, the silicon oxide is completely compatible with a CMOS (complementary metal oxide semiconductor) process, the preparation process is simple and easy to control, the CMOS process does not have the problem that the polyimide of the sacrificial layer is not released cleanly to influence the vacuum degree of a detector chip, the subsequent film growth temperature is not limited by the material of the sacrificial layer, the multilayer process design of the sacrificial layer can be realized, the process is not limited, the planarization can be easily realized by using the sacrificial layer, and the process difficulty and the possible risks are reduced; the infrared detector prepared by the integrated CMOS process can realize the aims of high yield, low cost, high yield and large-scale integrated production of chips, and provides a wider application market for the infrared detector; the infrared detector based on the CMOS process can realize smaller size and thinner film thickness of a characteristic structure, so that the infrared detector has larger duty ratio, lower thermal conductivity and smaller thermal capacity, and the infrared detector has higher detection sensitivity, longer detection distance and better detection performance; the infrared detector based on the CMOS process can make the pixel size of the detector smaller, realize smaller chip area under the same array pixel, and is more beneficial to realizing the miniaturization of a chip; the infrared detector based on the CMOS process has the advantages of mature process production line, higher process control precision, better meeting design requirements, better product consistency, more contribution to circuit chip adjustment performance and more contribution to industrialized mass production.

With continued reference to fig. 1-3, the CMOS infrared sensing structure 2 includes a reflective layer 21, an infrared conversion structure 23, and a plurality of columnar structures 22 on the CMOS measurement circuitry 1, the columnar structures 22 are located between the reflective layer 21 and the infrared conversion structure 23, the reflective layer 21 includes a reflective plate 212 and a supporting base 211, and the infrared conversion structure 23 is electrically connected to the CMOS measurement circuitry 1 through the columnar structures 22 and the supporting base 211; at least two infrared detector picture elements 10 share at least one columnar structure 22.

The reflecting layer 21 is used for reflecting infrared rays to an infrared conversion structure 23 in the CMOS infrared sensing structure, and is matched with the resonant cavity to realize secondary absorption of the infrared rays; the plurality of columnar structures 22 are located between the reflective layer 21 and the infrared conversion structure 23, and are used for supporting the infrared conversion structure 23 in the CMOS infrared sensing structure 2 after the sacrificial layer on the CMOS measurement circuit system 1 is released, the infrared conversion structure 23 detects an infrared radiation signal and converts the detected infrared radiation signal into an electrical signal, the electrical signal is transmitted to the CMOS measurement circuit system 1 through the columnar structures 22, and the CMOS measurement circuit system 1 processes the electrical signal to reflect temperature information, so that non-contact infrared temperature detection of the infrared detector is realized. Specifically, the CMOS infrared sensing structure 2 outputs a positive electric signal and a ground electric signal through different electrode structures, and the positive electric signal and the ground electric signal are transmitted to the supporting base 211 electrically connected to the pillar structures 22 through different pillar structures 22. In addition, the reflective layer 21 includes a reflective plate 212 and a supporting base 211, a portion of the reflective layer 21 serves as a dielectric for electrically connecting the columnar structure 22 with the CMOS measurement circuit system 1, that is, the supporting base 211, and the reflective plate 212 is used for reflecting the infrared rays to the infrared conversion structure 23, and the secondary absorption of the infrared rays is realized by matching with a resonant cavity formed between the reflective layer 21 and the infrared conversion structure 23, so as to improve the infrared absorption rate of the infrared detector and optimize the infrared detection performance of the infrared detector.

Specifically, referring to fig. 3, the infrared conversion structure 23 may structurally include an absorption plate 2301 and a beam structure 2302, the absorption plate 2301 being used to convert an infrared signal into an electrical signal and electrically connected with the corresponding pillar structure 22 through the beam structure 2302; meanwhile, the film structure of the infrared conversion structure 23 may include a thermosensitive layer, an electrode layer, and a passivation layer; wherein the thermosensitive layer is only on the absorption plate 2301 for converting a temperature signal into an electrical signal, the electrode layer for adjusting the resistance of the thermosensitive layer and transmitting the electrical signal of the thermosensitive layer to the CMOS measuring circuit system 1 through the beam structure 2302, and the passivation layer for protecting the thermosensitive layer and the electrode layer.

Or, the absorption plate 2301 includes a support layer, an electrode layer, a thermal sensitive layer and a passivation layer, the beam structure 2302 may include the support layer, the electrode layer and the passivation layer, the beam structure 2302 may further include the thermal sensitive layer, the support layer is located on a side of the passivation layer adjacent to the CMOS measurement circuit system 1, the electrode layer and the thermal sensitive layer are located between the support layer and the passivation layer, the passivation layer covers the electrode layer, the thermal sensitive layer may be disposed to cover the beam structure 2302, the thermal conductivity of the beam structure 2302 is reduced by using the characteristic of small thermal conductivity of the thermal sensitive material such as amorphous silicon, amorphous germanium or amorphous silicon germanium, and the thermal sensitive layer may serve as a support material of the beam structure 2302 instead of the support layer, or may serve as an electrode protection material of the beam structure 2302 instead of the passivation layer.

Specifically, the supporting layer is used for supporting the upper film layer in the infrared conversion structure 23 after the sacrificial layer is released, the thermosensitive layer is used for converting infrared temperature detection signals into infrared detection electric signals, the electrode layer is used for transmitting the infrared detection electric signals converted from the thermosensitive layer to the CMOS measurement circuit system 1 through the beam structures 2302 on the left side and the right side, the two beam structures 2302 respectively transmit positive and negative signals of the infrared detection electric signals, the read-out circuit in the CMOS measurement circuit system 1 realizes non-contact infrared temperature detection through analysis of the acquired infrared detection electric signals, and the passivation layer is used for protecting the electrode layer from oxidation or corrosion. In addition, the thermosensitive layer may be located above the electrode layer or below the electrode layer. Can set up and correspond absorption plate 2301, temperature sensing layer and electrode layer are located the airtight space that supporting layer and passivation layer formed, realize the protection to temperature sensing layer and electrode layer in absorption plate 2301, correspond beam structure 2302, and the electrode layer is located the airtight space that supporting layer and passivation layer formed, realizes the protection to electrode layer in beam structure 2302.

For example, the material forming the heat sensitive layer may include at least one of amorphous silicon, amorphous germanium, amorphous silicon germanium, titanium oxide, vanadium oxide, or titanium vanadium oxide, the material forming the support layer may include one or more of amorphous carbon, aluminum oxide, amorphous silicon, amorphous germanium, or amorphous silicon germanium, the material forming the electrode layer may include one or more of titanium, titanium nitride, tantalum nitride, titanium tungsten alloy, nickel-chromium alloy, nickel-silicon alloy, nickel, or chromium, and the material forming the passivation layer may include one or more of amorphous carbon, aluminum oxide, amorphous silicon, amorphous germanium, or amorphous silicon germanium. In addition, when the absorbing plate 2301 is configured to include a thermal sensitive layer, and the thermal sensitive layer is made of amorphous silicon, amorphous carbon, amorphous germanium, or amorphous silicon germanium, the supporting layer and/or the passivation layer on the beam structure 2302 may be replaced by the thermal sensitive layer, because the thermal conductivity of the amorphous silicon, amorphous germanium, or amorphous silicon germanium is relatively low, which is beneficial to reducing the thermal conductivity of the beam structure 2302 and further improving the infrared responsivity of the infrared detector.

In other embodiments, the infrared detector pixel may further include other structures, which are not described or limited herein.

The reflective layer 21 includes a reflective plate 212 and a supporting base 211, the reflective plate 212 reflects infrared radiation, the supporting base 211 is electrically connected to the pillar structure 22 and the CMOS measurement circuit system 1, when the infrared conversion structure 23 detects an infrared radiation signal and converts the detected infrared radiation signal into an electrical signal, the electrical signal can be transmitted to the CMOS measurement circuit system 1 through the pillar structure 22 and the supporting base 211, and the CMOS measurement circuit system 1 receives the electrical signal.

The CMOS measurement circuitry 1 may further include at least one hermetic release isolation layer (not shown) above the CMOS measurement circuitry 1, where the hermetic release isolation layer is used to protect the CMOS measurement circuitry 1 from process effects during an etching process for fabricating the CMOS infrared sensing structure 2.

Optionally, a hermetic release barrier is located at an interface between the CMOS measurement circuitry 1 and the CMOS infrared sensing structure 2 and/or in the CMOS infrared sensing structure 2, the hermetic release barrier is used to protect the CMOS measurement circuitry 1 from erosion when performing a corrosion process to release the sacrificial layer, and the hermetic release barrier uses a CMOS process corrosion resistant material including at least one of silicon, germanium, silicon germanium alloy, amorphous silicon, amorphous germanium, amorphous silicon germanium, amorphous carbon, silicon carbide, aluminum oxide, silicon nitride, or silicon carbonitride.

Illustratively, the close-release isolation layer is located in the CMOS infrared sensing structure 2, and the close-release isolation layer may be located above a metal interconnection layer (also referred to as a "metal layer") of the reflection layer 21, and the close-release isolation layer covers the columnar structure 22, and by providing the close-release isolation layer to cover the columnar structure 22, on one hand, the close-release isolation layer may be used as a support at the columnar structure 22, so as to improve the stability of the columnar structure 22, and ensure the electrical connection between the columnar structure 22 and the infrared conversion structure 23 as well as the support base 211. On the other hand, the airtight release insulating layer coating the columnar structure 22 can reduce the contact between the columnar structure 22 and the external environment, reduce the contact resistance between the columnar structure 22 and the external environment, further reduce the noise of the infrared detector pixel, and improve the detection sensitivity of the infrared detection sensor. In addition, the resonant cavity of the infrared detector is realized by releasing the vacuum cavity after the silicon oxide sacrificial layer is released, the reflecting layer 21 is used as the reflecting layer of the resonant cavity, the sacrificial layer is positioned between the reflecting layer 21 and the infrared conversion structure 23, and when at least one layer of closed release isolating layer positioned on the reflecting layer 21 is arranged to select silicon, germanium, silicon-germanium alloy, amorphous silicon, amorphous germanium or amorphous silicon-germanium as a part of the resonant cavity, the reflecting effect of the reflecting layer is not influenced, the height of the resonant cavity can be reduced, the thickness of the sacrificial layer is further reduced, and the release difficulty of the sacrificial layer formed by silicon oxide is reduced. In addition, a closed release isolation layer and the columnar structure 22 are arranged to form a closed structure, so that the CMOS measurement circuit system 1 is completely separated from the sacrificial layer, and the CMOS measurement circuit system 1 is protected.

Alternatively, the hermetic release isolation layer 11 is located at the interface between the CMOS measurement circuitry 1 and the CMOS infrared sensing structure 2, for example, the hermetic release isolation layer is located between the reflection layer 21 and the CMOS measurement circuitry 1, that is, the hermetic release isolation layer is located below the metal interconnection layer of the reflection layer 21, and the support base 211 is electrically connected to the CMOS measurement circuitry 1 through a through hole penetrating through the hermetic release isolation layer, as shown in fig. 11. Specifically, because the CMOS measurement circuit system 1 and the CMOS infrared sensing structure 2 are both formed by using a CMOS process, after the CMOS measurement circuit system 1 is formed, a wafer including the CMOS measurement circuit system 1 is transferred to a next process to form the CMOS infrared sensing structure 2, and since silicon oxide is the most commonly used dielectric material in the CMOS process and silicon oxide is mostly used as an insulating layer between metal layers on the CMOS circuit, if no insulating layer is used as a barrier when silicon oxide with a thickness of about 2um is corroded, the circuit will be seriously affected, so a hermetic release insulating layer is provided to release the silicon oxide on the CMOS measurement circuit system without corroding the silicon oxide on the sacrificial layer. After the CMOS measurement circuit system 1 is prepared and formed, a closed release isolation layer is prepared and formed on the CMOS measurement circuit system 1, the CMOS measurement circuit system 1 is protected by the closed release isolation layer, and in order to ensure the electrical connection between the support base 211 and the CMOS measurement circuit system 1, after the closed release isolation layer is prepared and formed, a through hole is formed in a region of the closed release isolation layer corresponding to the support base 211 by using an etching process, and the support base 211 is electrically connected with the CMOS measurement circuit system 1 through the through hole. In addition, a closed release isolation layer and the support base 211 are arranged to form a closed structure, so that the CMOS measurement circuit system 1 is completely separated from the sacrificial layer, and the CMOS measurement circuit system 1 is protected.

Or, in the infrared detector, the interface between the CMOS measurement circuit system 1 and the CMOS infrared sensing structure 2 is provided with at least one layer of closed release insulating layer, that is, at least one layer of closed release insulating layer is provided between the reflection layer 21 and the CMOS measurement circuit system 1, and at least one layer of closed release insulating layer is provided on the reflection layer 21, as shown in fig. 12, the effect is the same as above, and details are not repeated here.

Illustratively, the material constituting the hermetic release barrier layer may include silicon, germanium, a silicon-germanium alloy, amorphous silicon, amorphous germanium, amorphous silicon-germanium, amorphous carbon, silicon carbideAt least one of silicon carbide, aluminum oxide, silicon nitride or silicon carbonitride, the thickness of the closed release isolating layer is more than or equal to

Is less than or equal to

Specifically, silicon, germanium, a silicon-germanium alloy, amorphous silicon, amorphous germanium, amorphous silicon-germanium, amorphous carbon, silicon carbide, aluminum oxide, silicon nitride, and silicon carbonitride are all CMOS process corrosion-resistant materials, i.e., these materials are not corroded by the sacrificial layer release agent, so the hermetic release barrier layer can be used to protect the CMOS measurement circuitry 1 from corrosion when the corrosion process is performed to release the sacrificial layer. In addition, the closed release isolation layer covers the CMOS measurement circuit system 1, and the closed release isolation layer can also be used for protecting the CMOS measurement circuit system 1 from being influenced by the process in the etching process of manufacturing the CMOS infrared sensing structure 2. In addition, when at least one airtight release insulating layer is disposed on the reflective layer 21, the material for forming the airtight release insulating layer includes at least one of silicon, germanium, silicon-germanium alloy, amorphous silicon, amorphous germanium, amorphous silicon-germanium, amorphous carbon, silicon carbide, aluminum oxide, silicon nitride or silicon carbonitride, and the thickness of the first dielectric layer is greater than that of the first dielectric layer

Is less than or equal to

When setting up airtight release insulating layer and improving columnar structure 22 stability, airtight release insulating layer can hardly influence the reflection process in the resonant cavity, can avoid airtight release insulating layer to influence the reflection process of resonant cavity, and then avoids airtight release insulating layer to infrared detector detectivity's influence.

The CMOS manufacturing process of the CMOS infrared sensing structure 2 comprises a metal interconnection process, a through hole process and an RDL (remote description language) process, and the CMOS infrared sensing structure 2 comprises at least two metal interconnection layers, at least two dielectric layers and a plurality of interconnection through holes so as to construct and communicate all structural components in the infrared detector.

Illustratively, the dielectric layer at least comprises a sacrificial layer and a heat-sensitive dielectric layer, the heat-sensitive dielectric layer at least comprises a heat-sensitive layer, and also comprises a supporting layer and/or a passivation layer, and the metal interconnection layer at least comprises a reflecting layer 21 and an electrode layer; the thermal sensitive medium layer comprises a thermal sensitive material with a resistance temperature coefficient larger than a set value, the resistance temperature coefficient can be larger than or equal to 0.015/K, for example, the thermal sensitive material with the resistance temperature coefficient larger than the set value forms a thermal sensitive layer in the thermal sensitive medium layer, the thermal sensitive medium layer is used for converting temperature change corresponding to infrared radiation absorbed by the thermal sensitive medium layer into resistance change, and then an infrared target signal is converted into a signal capable of being read electrically through the CMOS measuring circuit system 1.

Specifically, the metal interconnection process is used for realizing the electrical connection of an upper metal interconnection layer and a lower metal interconnection layer, the through hole process is used for forming an interconnection through hole for connecting the upper metal interconnection layer and the lower metal interconnection layer, the RDL process is a rewiring layer process, specifically, a layer of metal is re-distributed above the top metal of the circuit and is electrically connected with the top metal of the circuit through a tungsten column, the RDL process can be used for preparing a reflection layer in the infrared detector on the top metal of the CMOS measurement circuit system 1, and a supporting base on the reflection layer is electrically connected with the top metal of the CMOS measurement circuit system 1. In addition, the heat-sensitive dielectric layer comprises a heat-sensitive material with a resistance temperature coefficient larger than a set value, and the resistance temperature coefficient can be larger than or equal to 0.015/K, so that the detection sensitivity of the infrared detector can be improved.

In addition, the CMOS manufacturing process of the CMOS measurement circuit system 1 may also include a metal interconnection process and a via process, the CMOS measurement circuit system 1 includes metal interconnection layers, dielectric layers, and a silicon substrate at the bottom, which are disposed at intervals, and the upper and lower metal interconnection layers are electrically connected through vias.

Optionally, the sacrificial layer is used to form the CMOS infrared sensing structure 2 into a hollow structure, the material of the sacrificial layer is silicon oxide, and the sacrificial layer is etched by a post-CMOS process, which may, for example, use at least one of gaseous hydrogen fluoride, carbon tetrafluoride and trifluoromethane to etch the sacrificial layer. Specifically, a sacrificial layer (not shown in the figure) is arranged between the reflection layer and the beam structure, when the reflection layer is provided with the closed release isolation layer, the sacrificial layer is arranged between the closed release isolation layer and the beam structure, the material forming the sacrificial layer is silicon oxide, so as to be compatible with a CMOS process, and a post-CMOS process can be adopted, that is, the post-CMOS process corrodes the sacrificial layer to release the sacrificial layer in the final infrared detection chip product.

In this infrared detector pixel, through setting up at least one columnar structure 22 by two at least infrared detector pixel 10 commons, set up its respective columnar structure 22 respectively for every infrared detector pixel 10, the quantity of columnar structure 22 in the reducible infrared detector to reduce the occupied space of columnar structure 22 in infrared detector, correspondingly, increased the effective area in the infrared conversion structure 23 and occupied the ratio, promoted infrared detector's duty cycle.

Exemplarily, the common manner of the columnar structures 22 is exemplarily described later.

Illustratively, fig. 1 shows that the infrared detector pixel 10 is arranged in 3 rows and 3 columns, but does not constitute a limitation of the infrared detector provided by the embodiment of the present disclosure.

In other embodiments, the number and arrangement of the infrared detector pixels 10 in the infrared detector can also be set based on the requirement of the infrared detector, which is not limited herein.

Exemplarily, fig. 2 shows that one columnar structure 22 can be shared by two infrared detector pixel elements 10 adjacent to each other left and right, and fig. 3 shows that two columnar structures 22 located in the middle of two adjacent infrared detector pixel elements can be shared by the two adjacent infrared detector pixel elements 10, which can both achieve the reduction of the number of columnar structures 22 and the improvement of the duty ratio of the infrared detector.

In other embodiments, the sharing manner of the columnar structures 22 may be set in other manners, which will be exemplarily described in conjunction with fig. 4 to 6.

In some embodiments, with continued reference to fig. 2 and 3, the same columnar structure 22 is shared by at least two adjacent infrared detector pixels 10.

According to the arrangement, on one hand, the connection relation is simple, cross-region connection lines do not exist, the overall structure of the infrared detector is simple, and the process difficulty is low; on the other hand, the more the number of infrared detector pixels 10 sharing the same columnar structure 22 is, the less the total number of the columnar structures 22 is, and the more the duty ratio is improved.

Illustratively, in fig. 2 and 3, the same columnar structure 22 can be shared by two adjacent infrared detector pixels 10. In other embodiments, when the infrared detector pixels are arranged in other manners, the same pillar structure 22 can be used for three, four or more adjacent infrared detector pixels, and is not limited herein.

In some embodiments, to minimize the number of columnar structures 22, i.e., to maximize the duty cycle of the infrared detector, it may also be desirable to share as many columnar structures 22 as possible with each infrared detector pixel 10 adjacent to it.

Exemplarily, in conjunction with fig. 1, an infrared detector pixel located at a middle position may share each of its columnar structures located at four vertex angles with infrared detector pixels at 8 peripheral positions surrounding it; at this time, each columnar structure is shared by four infrared detector pixels, which can be understood by referring to fig. 6 later.

In some embodiments, fig. 4 is a schematic plan view of another infrared detector according to an embodiment of the present disclosure, fig. 5 is a schematic plan view of another infrared detector according to an embodiment of the present disclosure, and fig. 6 is a schematic plan view of another infrared detector according to an embodiment of the present disclosure. On the basis of fig. 1, in conjunction with fig. 4-6, the infrared detector pixels 10 are arranged in rows and columns; two adjacent infrared detector pixels 10 in the same row share at least one columnar structure 22; and/or two infrared detector pixels 10 that are adjacent in the same column share at least one columnar structure 22.

In fig. 4-6, with the X direction as the row direction and the Y direction as the column direction, the columnar structure 22 can be shared only between two adjacent infrared detector pixels 10 in the same row, as shown in fig. 5; or the columnar structures 22 may be shared only between two adjacent infrared detector pixels 10 in the same column, as in fig. 4; or the columnar structures 22 are shared between adjacent infrared detector pixels in both rows and columns, as shown in fig. 6.

Illustratively, referring to FIG. 4, when the columnar structures 22 are shared only in the column direction, the same columnar structure 22 is shared by two infrared detector pixels (shown as Y11 and Y12, respectively) that are adjacent in the column direction.

Illustratively, referring to FIG. 5, when the columnar structures 22 are shared only in the row direction, the same columnar structure 22 is shared by two infrared detector pixels (shown at X11 and X12, respectively) that are adjacent along the row direction.

Illustratively, referring to FIG. 6, when the columnar structures 22 are shared in both the row and column directions, the same columnar structure 22 is shared by four infrared detector pixels (shown at Z11, Z12, Z13, and Z14, respectively) that are adjacent in both the row and column directions.

In other embodiments, when the infrared detector pixels are arranged in other manners, the columnar structure can also be shared by other manners, which is neither described nor limited herein.

In some embodiments, with continued reference to FIG. 2, the columnar structures 22 comprise a single layer of pillars.

At least one column in the single-layer columns can be used for at least two infrared detector pixels to be common, so that the total number of columns is reduced, and the duty ratio of the infrared detector is improved; meanwhile, the columnar structure 22 has a simple structure and low corresponding process difficulty.

In some embodiments, the columnar structures 22 comprise at least two superimposed layers of pillars; the columns of each layer are arranged in a one-to-one correspondence mode.

At least two layers of pillars superposed in the same columnar structure 22 are used as a whole and can be used for at least two infrared detector pixels, so that the total number of the columnar structures 22 can be reduced, and the duty ratio of the infrared detector is improved; simultaneously, columnar structure 22 is formed by the stack of at least two-layer post, when the total height of columnar structure 22 is relative, for the structure of individual layer post, can reduce the height of each layer post, because the height of post is lower more, its straightness that steeps is better, therefore, easily form each layer post that the straightness that steeps is better, thereby it is better to make the holistic straightness that steeps of columnar structure, its whole size can accomplish littleer, be favorable to reducing the shared space of columnar structure 22 so, thereby increase infrared conversion structure's effective area, and then improve the duty cycle, improve detection sensitivity.

In some embodiments, fig. 7 is a schematic cross-sectional view of another infrared detector according to embodiments of the present disclosure. The columnar structure 22 comprises a lower-layer pillar 222 and an upper-layer pillar 221, the lower-layer pillar 222 is connected between the upper-layer pillar 221 and the support base 211, and the upper-layer pillar 221 is connected between the lower-layer pillar 222 and the infrared conversion structure 23; one lower-layer pillar 222 supports at least two (two are exemplarily shown in fig. 7) upper-layer pillars 221, respectively; at least two (three are exemplarily shown in fig. 7) infrared detector pixel 10 in common with at least one (two are exemplarily shown in fig. 7) underlying pillar 222; each infrared detector pixel 10 is individually provided with its respective upper pillar 221.

With such an arrangement, the temperature of the lower pillar 222 is substantially the same as that of the CMOS measurement circuit system 1, and the infrared detector pixels share only the lower pillar 222, but do not share the upper pillar 221, so that the heat cross phenomenon between the infrared detector pixels sharing the same lower pillar 222 can be improved, the mutual influence therebetween can be reduced, i.e., crosstalk can be avoided, and the detection accuracy can be improved.

It should be noted that, since the lower-layer pillars 222 can be shared and the upper-layer pillars 221 are not shared, the number of upper-layer pillars 221 supported on the same lower-layer pillar 222 is the maximum value of the number of infrared detector pixels that can simultaneously share the lower-layer pillar 222. Optionally, in order to fully utilize the space in the infrared detector and ensure that the infrared detector has a higher duty ratio, the number of the upper-layer pillars 221 supported on the same lower-layer pillar 222 is equal to the number of the infrared detector pixels sharing the lower-layer pillar 222.

In the above embodiments, the upright column may be a hollow column or a solid column, may be a metal solid column, or may be a solid column filled with a non-metal material and having a metal shell, which is not limited herein.

In some embodiments, with continued reference to FIGS. 1 and 3, the pillars corresponding to support the same infrared detector pixel 10 are all the same size.

By the arrangement, the corresponding pillars can be formed by adopting the same process conditions, process parameters and the like, the process difficulty is low, the yield is high, and the cost is reduced.

In some embodiments, with continued reference to any of fig. 4-6, the size of the shared posts is greater than the size of the unshared posts.

The column shared by the two infrared detector pixels is required to support at least two infrared detector pixels, the column not shared by the two infrared detector pixels is required to support only one infrared detector pixel, the column shared by the two infrared detector pixels is larger than the column not shared by the two infrared detector pixels, the column shared by the two infrared detector pixels is ensured to have larger mechanical strength and is enough to support the at least two infrared detector pixels sharing the column, and therefore the infrared detector is ensured to have higher structural stability.

It is understood that the size of the pillar can be characterized by physical quantities such as the cross-sectional width, cross-sectional area or volume of the pillar, and is not limited thereto.

In some embodiments, to improve the mechanical strength of the shared columns, additional support structures may be added to ensure effective support. Alternatively, the auxiliary support layer may be coated on the outer side of the shared pillar, or may be implemented in other ways known to those skilled in the art, which is not limited herein.

In some embodiments, each infrared detector pixel 10 is supported by four columnar structures 22.

So set up, be favorable to improving support stability to improve infrared detector's overall structure stability.

In some embodiments, each infrared detector pixel 10 is supported by two columnar structures 22.

With such an arrangement, the space occupied by the columnar structure 22 can be further reduced, thereby being beneficial to improving the duty ratio of the infrared detector.

In some embodiments, the total height of the columnar structures 22 is greater than or equal to 1.5 microns and less than or equal to 2.5 microns.

The total height of the columnar structure 22 is the height of the columnar structure in the direction perpendicular to the plane of the reflection plate 212, the stacking height of each layer of the columns, which may also be referred to as the axial height of the columnar structure 22, and may be the supporting height of the columnar structure 22, and also the distance between two parallel planes of the resonant cavity of the infrared detector pixel, that is, the distance between the reflection surface of the reflection plate 212 and the absorption surface of the infrared conversion structure 23.

On the basis, the total height of the columnar structure 22 is larger than or equal to 1.5 microns, so that the implementation of a CMOS process is facilitated, and the process difficulty is reduced; on the other hand, the distance requirement between the parallel planes of the resonant cavity can be met, and the infrared absorption efficiency is improved, so that the detection sensitivity is improved. Meanwhile, by setting the total height of the columnar structure 22 to be less than or equal to 2.5 micrometers, the total height of the columnar structure 22 can not be too high, so that the problem of poor stability caused by too high columnar structure 22 is avoided, namely, the structural stability is favorably improved; meanwhile, the size of the infrared detector pixel and the size of the whole infrared detector in the height direction are reduced, and the light, thin and small design of the infrared detector is achieved.

Illustratively, the total height of the pillar structures 22 may be 1.5 microns, 1.8 microns, 2.0 microns, 2.1 microns, 2.4 microns, 2.5 microns, or other height values, and may be set based on the performance requirements of the infrared detector and the CMOS process requirements, but is not limited thereto.

In some embodiments, the unidirectional width of the cross section of one side of the columnar structure 22 connected with the infrared conversion structure 23 is less than or equal to 3 micrometers; optionally, the width may also be less than or equal to 1 micron.

By the arrangement, the size of the columnar structure 22 on the plane where the reflecting plate 212 is located can be reduced while stable support is achieved by the columnar structure 22, so that the smaller chip area under the same array pixel is realized, and the miniaturization of a chip is realized; in addition, the occupation ratio of the effective areas of the reflection plate 212 and the corresponding infrared conversion structure 23 is favorably improved, the signal intensity is enhanced, and the detection performance is improved.

Illustratively, when the uppermost pillar is circular in cross-section, its diameter is less than or equal to 3 microns; when the section of the uppermost upright post is square, the side length is less than or equal to 3 micrometers; when the cross section of the uppermost upright post is polygonal, the diagonal length of the uppermost upright post is less than or equal to 3 micrometers; when the section of the uppermost upright post is in a long strip shape, the length of the long side of the uppermost upright post is less than or equal to 3 micrometers.

Illustratively, the cross-sectional maximum unidirectional width of the uppermost pillar may be 3 microns, 2.5 microns, 2 microns, 1 micron, 0.8 microns or other width values, which may be set based on the requirements of the infrared detector, and is not limited herein.

In some embodiments, to meet other requirements of the infrared detector, the maximum unidirectional width of the cross section of the uppermost pillar may be set to be greater than 3 micrometers, which is not limited herein.

In some embodiments, the infrared detector type may be an amorphous silicon detector, a titanium oxide detector, a vanadium oxide detector, or the like, that is, the material constituting the thermosensitive layer may include at least one of amorphous silicon, titanium oxide, or vanadium oxide, which is not limited by the embodiments of the present disclosure.

In some embodiments, fig. 8 is a schematic structural diagram of a CMOS measurement circuit system according to an embodiment of the present disclosure. Referring to fig. 1 and 8, the CMOS measurement circuit system 1 includes a bias voltage generation circuit 7, a column-level analog front-end circuit 8 and a row-level circuit 9, an input end of the bias voltage generation circuit 7 is connected to an output end of the row-level circuit 9, an input end of the column-level analog front-end circuit 8 is connected to an output end of the bias voltage generation circuit 7, the row-level circuit 9 includes a row-level mirror image element Rsm and a row selection switch K1, and the column-level analog front-end circuit 8 includes a blind image element RD; the row-level circuit 9 is distributed in each pixel, selects a signal to be processed according to a row strobe signal of the timing sequence generating circuit, and outputs a current signal to the column-level analog front-end circuit 8 under the action of the bias generating circuit 7 to perform current-voltage conversion output; the row stage circuit 9 outputs a third bias voltage VRsm to the bias generation circuit 7 when being controlled by the row selection switch K1 to be gated, the bias generation circuit 7 outputs a first bias voltage V1 and a second bias voltage V2 according to the input constant voltage and the third bias voltage VRsm, and the column stage analog front-end circuit 8 obtains two currents according to the first bias voltage V1 and the second bias voltage V2, performs transimpedance amplification on the difference between the two generated currents, and outputs the amplified current as an output voltage.

Specifically, the row-level circuit 9 includes a row-level mirror image element Rsm and a row selection switch K1, and the row-level circuit 9 is configured to generate a third bias voltage VRsm according to a gating state of the row selection switch K1. Illustratively, the row-level image elements Rsm may be subjected to a light-shielding process such that the row-level image elements Rsm are subjected to a fixed radiation by a light-shielding sheet having a temperature constantly equal to a substrate temperature, the row selection switch K1 may be implemented by a transistor, the row selection switch K1 is closed, and the row-level image elements Rsm are connected to the bias generation circuit 7, that is, the row-level circuit 9 outputs the third bias voltage VRsm to the bias generation circuit 7 when being gated by the row selection switch K1. The bias generation circuit 7 may include a first bias generation circuit 71 and a second bias generation circuit 72, the first bias generation circuit 71 being configured to generate a first bias voltage V1 according to an input constant voltage, which may be, for example, a positive power supply signal with a constant voltage. The second bias generating circuit 72 may include a bias control sub-circuit 721 and a plurality of gate driving sub-circuits 722, the bias control sub-circuit 721 controlling the gate driving sub-circuits 722 to generate the corresponding second bias voltages V, respectively, according to the third bias voltage VRsm.

The column-level analog front-end circuit 8 includes a plurality of column control sub-circuits 81, the column control sub-circuits 81 are disposed in correspondence with the gate driving sub-circuits 722, and exemplarily, the column control sub-circuits 81 may be disposed in one-to-one correspondence with the gate driving sub-circuits 722, and the gate driving sub-circuits 722 are configured to provide the second bias voltage V2 to the corresponding column control sub-circuits 81 according to their own gate states. For example, it may be set that when the gate driving sub-circuit 722 is gated, the gate driving sub-circuit 722 supplies the second bias voltage V2 to the corresponding column control sub-circuit 81; when the gate driving sub-circuit 722 is not gated, the gate driving sub-circuit 722 stops supplying the second bias voltage V2 to the corresponding column control sub-circuit 81.

The column-level analog front-end circuit 8 comprises an effective pixel RS and a blind pixel RD, the column control sub-circuit is used for generating a first current I1 according to a first bias voltage V1 and the blind pixel RD, generating a second current I2 according to a second bias voltage V2 and the effective pixel RS, performing transimpedance amplification on a difference value of the first current I1 and the second current I2, and outputting the difference value, and the row-level mirror image pixel Rsm and the effective pixel RS have the same temperature drift amount at the same ambient temperature.

Illustratively, the row-level image elements Rsm are thermally insulated from the CMOS measurement circuitry 1 and are shaded, and the row-level image elements Rsm are subjected to a fixed radiation from a shade sheet having a temperature constantly equal to the substrate temperature. The absorption plate 10 of the active pixel RS is thermally insulated from the CMOS measurement circuitry 1 and the active pixel RS receives external radiation. The absorbing plates 10 of the row-level mirror image elements Rsm and the effective elements RS are thermally insulated from the CMOS measuring circuit system 1, so that the row-level mirror image elements Rsm and the effective elements RS have a self-heating effect.

When the corresponding row-level mirror image element Rsm is gated through the row selection switch K1, the resistance value of the row-level mirror image element Rsm and the resistance value of the effective element RS are changed due to joule heat, but when the row-level mirror image element Rsm and the effective element RS are subjected to the same fixed radiation, the resistance value of the row-level mirror image element Rsm and the resistance value of the effective element RS are the same, the temperature coefficients of the row-level mirror image element Rsm and the temperature coefficient of the effective element RS are the same, the temperature drift amounts of the row-level mirror image element Rsm and the effective element RS are the same at the same ambient temperature, the change of the row-level mirror image element Rsm and the temperature drift amounts of the effective element RS at the same ambient temperature are synchronized, the resistance value change of the row-level mirror image element Rsm and the effective element RS due to the self-heating effect is effectively compensated, and the stable output of the reading circuit is achieved.

In addition, by arranging the second bias generating circuit 7 to include a bias control sub-circuit 721 and a plurality of gate driving sub-circuits 722, the bias control sub-circuit 721 is configured to control the gate driving sub-circuits 722 to generate the corresponding second bias voltages V2 respectively according to the row control signals, so that each row of pixels has one path to drive the whole columns of pixels of the row individually, the requirement for the second bias voltage V2 is reduced, that is, the driving capability of the bias generating circuit 7 is improved, and the readout circuit is advantageously used to drive a larger-scale infrared detector pixel array. In addition, the specific detailed operation principle of the CMOS measurement circuit system 1 is well known to those skilled in the art and will not be described herein.

Fig. 9 is a schematic cross-sectional view of another infrared detector according to an embodiment of the disclosure. As shown in fig. 9, on the basis of the above embodiment, the CMOS manufacturing process of the CMOS measurement circuit system 1 may also include a metal interconnection process and a via process, the CMOS measurement circuit system 1 includes metal interconnection layers 101, dielectric layers 102 and a silicon substrate 103 at the bottom, the upper and lower metal interconnection layers 101 are electrically connected through vias 104,

with reference to fig. 1 to 9, the CMOS infrared sensing structure 2 includes a resonant cavity formed by a reflective layer 21 and a thermal sensitive medium layer, a suspended microbridge structure for controlling heat transfer, and a pillar structure 22 having electrical connection and support functions, and the CMOS measurement circuit system 1 is configured to measure and process an array resistance value formed by one or more CMOS infrared sensing structures 2, and convert an infrared signal into an electrical image signal.

Specifically, the resonant cavity may be formed by a cavity between the reflective layer 21 and the absorbing plate 2301, for example, infrared light is reflected back and forth in the resonant cavity through the absorbing plate 2301 to improve the detection sensitivity of the infrared detector, and due to the arrangement of the columnar structures 22, the beam structures 2302 and the absorbing plate 2301 constitute a suspended micro-bridge structure for controlling heat transfer, and the columnar structures 22 are electrically connected to the supporting base 211 and the corresponding beam structures 2302 and are used for supporting the infrared conversion structures 23 on the columnar structures 22.

Alternatively, the CMOS infrared sensing structure 2 may be disposed on a metal interconnect layer of the CMOS measurement circuitry 1 or fabricated on the same layer. Specifically, the metal interconnection layer of the CMOS measurement circuitry 1 may be a top metal layer in the CMOS measurement circuitry 1, and in conjunction with fig. 9, the CMOS infrared sensing structure 2 may be fabricated on the metal interconnection layer of the CMOS measurement circuitry 1, and the CMOS infrared sensing structure 2 is electrically connected to the CMOS measurement circuitry 1 through a supporting base 211 on the metal interconnection layer of the CMOS measurement circuitry 1, so as to transmit an electrical signal converted from an infrared signal to the CMOS measurement circuitry 1.

Fig. 10 is a schematic cross-sectional structure view of another infrared detector provided in the embodiment of the present disclosure, and as shown in fig. 10, a CMOS infrared sensing structure 2 is prepared on the same layer of a metal interconnection layer of a CMOS measurement circuit system 1, that is, the CMOS measurement circuit system 1 and the CMOS infrared sensing structure 2 are arranged on the same layer, as shown in fig. 10, the CMOS infrared sensing structure 2 is arranged on one side of the CMOS measurement circuit system 1, and a hermetic release isolation layer 11 may also be arranged on the top of the CMOS measurement circuit system 1 to protect the CMOS measurement circuit system 1.

Optionally, the CMOS infrared sensing structure 2 includes an absorption plate 2301, a beam structure 2302, a reflective layer 21 and a columnar structure 22, the absorption plate 2301 includes a metal interconnection layer and at least one thermal sensitive medium layer, the material constituting the thermal sensitive medium layer includes at least one of amorphous silicon, amorphous germanium, amorphous silicon germanium, titanium oxide, vanadium oxide or vanadium titanium oxide, the metal interconnection layer in the absorption plate 2301 is an electrode layer in the absorption plate 2301 for transmitting an electrical signal obtained by converting an infrared signal, the thermal sensitive medium layer includes at least a thermal sensitive layer and may further include a support layer and a passivation layer, the material constituting the thermal sensitive medium layer includes at least one of amorphous silicon, amorphous germanium, amorphous silicon germanium, titanium oxide, vanadium oxide or vanadium titanium oxide, that is, the material constituting the thermal sensitive layer includes amorphous silicon, amorphous germanium, amorphous silicon germanium, titanium oxide, vanadium oxide or vanadium oxide, that is to form a thermal sensitive layer, At least one of amorphous germanium, amorphous silicon-germanium, titanium oxide, vanadium oxide or titanium vanadium oxide.

The beam structure 2302 and the columnar structure 22 are used for transmitting electrical signals and for supporting and connecting the absorption plate 2301, the electrode layer in the absorption plate 2301 includes two patterned electrode structures, the two patterned electrode structures output positive electrical signals and ground electrical signals, respectively, the positive electrical signals and the ground electrical signals are transmitted to the supporting base electrically connected with the columnar structure 22 through the different beam structures 2302 and the different columnar structures 22 and further transmitted to the CMOS measurement circuit system 1, the beam structure 2302 includes a metal interconnection layer and at least one dielectric layer, the metal interconnection layer in the beam structure 2302 is an electrode layer in the beam structure 2302, the electrode layer in the beam structure 2302 is electrically connected with the electrode layer in the absorption plate 2301, and the dielectric layer in the beam structure 2302 may include a supporting layer and a passivation layer.

The columnar structures 22 are connected with the beam structure 2302 and the CMOS measurement circuit system 1 by adopting a metal interconnection process and a through hole process, the upper parts of the columnar structures 22 need to be electrically connected with electrode layers in the beam structure 2302 through holes penetrating through a supporting layer in the beam structure 2302, and the lower parts of the columnar structures 22 need to be electrically connected with corresponding supporting bases 211 through holes penetrating through dielectric layers on the supporting bases 211. The reflective plate 212 is used for reflecting infrared signals and forms a resonant cavity with the heat-sensitive medium layer, that is, the reflective plate 212 is used for reflecting infrared signals and forms a resonant cavity with the heat-sensitive medium layer, and the reflective layer 21 includes at least one metal interconnection layer for forming the supporting base 211 and also for forming the reflective plate 212.

Alternatively, at least two ends of the beam structure 2302 and the absorption plate 2301 may be electrically connected, the CMOS infrared sensing structure 2 includes at least two pillar structures 22 and at least two supporting bases 211, and the electrode layer includes at least two electrode terminals. Specifically, as shown in fig. 1, the beam structures 2302 are electrically connected to two ends of the absorption plate 2301, each beam structure 2302 is electrically connected to one end of the absorption plate 2301, the CMOS infrared sensing structure 2 includes two column structures 22, the electrode layer includes at least two electrode terminals, at least a portion of the electrode terminals transmit positive electrical signals, at least a portion of the electrode terminals transmit negative electrical signals, and the signals are transmitted to the supporting base 211 through the corresponding beam structures 2302 and the column structures 22.

Alternatively, as shown in fig. 13, four ends of the beam structures 2302 connected to the absorbing plate 2301 can be electrically connected, each beam structure 2302 connected to two ends of the absorbing plate 2301, and the CMOS infrared sensing structure 2 includes four pillar structures 22, and one beam structure 2302 connects two pillar structures 22. It should be noted that, in the embodiment of the present disclosure, the number of the connecting ends of the beam structure 2302 and the absorbing plate 2301 is not particularly limited, and it is sufficient that the beam structure 2302 corresponds to the electrode terminals, and the beam structure 2302 is used for transmitting the electrical signals output by the corresponding electrode terminals.

Alternatively, the infrared detector may be configured based on a 3nm, 7nm, 10nm, 14nm, 22nm, 28nm, 32nm, 45nm, 65nm, 90nm, 130nm, 150nm, 180nm, 250nm or 350nm CMOS process, which characterizes process nodes of the integrated circuit, i.e., features during the processing of the integrated circuit.

Alternatively, the metal wiring material constituting the metal interconnection layer in the infrared detector may be configured to include at least one of aluminum, copper, tungsten, titanium, nickel, chromium, platinum, silver, ruthenium, or cobalt, and for example, the material constituting the reflective layer may be configured to include at least one of aluminum, copper, tungsten, titanium, nickel, chromium, platinum, silver, ruthenium, or cobalt. In addition, the CMOS measuring circuit system 1 and the CMOS infrared sensing structure 2 are both prepared by using a CMOS process, the CMOS infrared sensing structure 2 is directly prepared on the CMOS measuring circuit system 1, the radial side length of the columnar structure 22 can be more than or equal to 0.5um and less than or equal to 3um, the width of the beam structure 2302, namely the width of a single line in the beam structure 2302 is less than or equal to 0.3um, the height of a resonant cavity is more than or equal to 1.5um and less than or equal to 2.5um, and the side length of a single pixel of the CMOS infrared sensing structure 2 is more than or equal to 6um and less than or equal to 17 um.

It is noted that, in this document, relational terms such as "first" and "second," and the like, may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

The foregoing are merely exemplary embodiments of the present disclosure, which enable those skilled in the art to understand or practice the present disclosure. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the disclosure. Thus, the present disclosure is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An infrared detector based on a CMOS process, comprising:

infrared detector pixels arranged in an array; the infrared detector pixel comprises a CMOS measuring circuit system and a CMOS infrared sensing structure positioned on the CMOS measuring circuit system, the CMOS measuring circuit system and the CMOS infrared sensing structure are both prepared by adopting a CMOS process, and the CMOS infrared sensing structure is directly prepared on the CMOS measuring circuit system;

At least two infrared detector pixels share at least one columnar structure.

2. The infrared detector as claimed in claim 1, wherein the CMOS infrared sensing structure comprises a sacrificial layer, the sacrificial layer is used for making the CMOS infrared sensing structure form a hollow structure, the material constituting the sacrificial layer is silicon oxide, and the sacrificial layer is etched by a post-CMOS process;

3. The infrared detector as claimed in claim 1, wherein the same columnar structure is shared by at least two adjacent infrared detector pixels.

4. The infrared detector of claim 3, wherein the infrared detector pixels are arranged in rows and columns;

5. The infrared detector as claimed in any one of claims 1 to 4, wherein said columnar structure comprises a single layer of columns; or

The columnar structure comprises at least two layers of superposed pillars; the columns of each layer are arranged in a one-to-one correspondence mode.

6. The infrared detector as claimed in any one of claims 1 to 4, wherein said columnar structure comprises a lower layer pillar and an upper layer pillar, said lower layer pillar being connected between said upper layer pillar and said support base, said upper layer pillar being connected between said lower layer pillar and said infrared conversion structure;

at least two infrared detector pixels share at least one lower-layer pillar;

7. The infrared detector of claim 1, characterized in that the pillars supporting the same infrared detector pixel are all the same size;

8. The infrared detector as claimed in claim 1, wherein each of said infrared detector pixels is supported by four of said columnar structures;

or each infrared detector pixel is supported by two columnar structures.

9. The infrared detector as set forth in claim 1, wherein the columnar structures have a total height of 1.5 μm or more and 2.5 μm or less.

10. The infrared detector as claimed in claim 1, wherein a unidirectional width of a cross section of one side of the columnar structure connected with the infrared conversion structure is greater than or equal to 0.5 micrometers and less than or equal to 3 micrometers.