CN111752875A - Inter-module communication method and system - Google Patents
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- CN111752875A CN111752875A CN202010575497.5A CN202010575497A CN111752875A CN 111752875 A CN111752875 A CN 111752875A CN 202010575497 A CN202010575497 A CN 202010575497A CN 111752875 A CN111752875 A CN 111752875A
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Abstract
The embodiment of the invention discloses a method and a system for communication between modules. The communication method is used for controlling data transmission among a first memory, a second memory and a register, wherein the register is connected between the first memory and the second memory, and the communication method comprises the following steps: the first memory receives a first permission signal sent by the register; the first memory provides a first valid signal to the register to write a first segment of data to the register; the register receives a second permission signal sent by the second memory; the register provides a second valid signal to the second memory to write the first segment of data to the second memory. The embodiment of the invention realizes the flexibility of communication data transmission among the modules.
Description
Technical Field
The present invention relates to communications technologies, and in particular, to a method and a system for inter-module communication.
Background
Axi (advanced xtensible inter interface) is a bus protocol, which is the most important part of the amba (advanced microcontroller bus architecture)3.0 protocol proposed by ARM corporation, and is an on-chip bus oriented to high performance, high bandwidth and low latency. The address/control and data phase of the system are separated, unaligned data transmission is supported, meanwhile, in burst transmission, only a first address is needed, simultaneously, a data channel is separately read and written, and outbound transmission access and out-of-order access are supported, and time sequence convergence is easier to perform.
However, the AXI bus protocol is used for communication, data is transmitted in a frame or packet mode, a 4K boundary exists, a large number of control signals such as addresses are needed, and communication data transmission among modules cannot be flexibly suspended at any time.
Disclosure of Invention
The embodiment of the invention provides a method and a system for communication between modules, which are used for realizing the flexibility of communication data transmission between the modules.
To achieve the above object, an embodiment of the present invention provides an inter-module communication method for controlling data transmission between a first memory, a second memory, and a register connected between the first memory and the second memory, the inter-module communication method including:
the first memory receives a first permission signal sent by the register;
the first memory provides a first valid signal to the register to write a first segment of data to the register;
the register receives a second permission signal sent by the second memory;
the register provides a second valid signal to the second memory to write the first segment of data to the second memory.
Further, the receiving, by the first memory, the first permission signal sent by the register includes:
the register pulls the first permission signal of an upstream permission end of the register high;
and the first permission end of the first memory enters a readable state after receiving a high-level first permission signal sent by the uplink permission end of the register.
Further, the first memory providing a first valid signal to the register to write a first segment of data to the register comprises:
the first memory pulls up a first effective signal of a first effective end of the first memory;
and the upstream effective end of the register changes into a writable state after receiving a first effective signal with high level and stores the first segment of data.
Further, the receiving, by the register, the second permission signal sent by the second memory includes:
the second memory pulls up a second permission signal of a second permission end of the second memory;
and the downlink permission end of the register receives a high-level second permission signal sent by the second permission end of the second memory.
Further, the register providing a second valid signal to the second memory to write the first segment of data to the second memory comprises:
the register pulls up a second effective signal of a downlink effective end of the register;
the second effective end of the second memory changes to a writable state after receiving the second effective signal of high level and stores the first segment of data.
In one aspect, embodiments of the present invention also provide an inter-module communication system including a first memory, a second memory, and a register connected between the first memory and the second memory,
the first memory receives a first permission signal sent by the register;
the first memory provides a first valid signal to the register to write a first segment of data to the register;
the register receives a second permission signal sent by the second memory;
the register provides a second valid signal to the second memory to write the first segment of data to the second memory.
Further, in the above-mentioned case,
the register pulls the first permission signal of an upstream permission end of the register high;
and the first permission end of the first memory enters a readable state after receiving a high-level first permission signal sent by the uplink permission end of the register.
Further, in the above-mentioned case,
the first memory pulls up a first effective signal of a first effective end of the first memory;
and the upstream effective end of the register changes into a writable state after receiving a first effective signal with high level and stores the first segment of data.
Further, in the above-mentioned case,
the second memory pulls up a second permission signal of a second permission end of the second memory;
and the downlink permission end of the register receives a high-level second permission signal sent by the second permission end of the second memory.
Further, in the above-mentioned case,
the register pulls up a second effective signal of a downlink effective end of the register;
the second effective end of the second memory changes to a writable state after receiving the second effective signal of high level and stores the first segment of data.
The embodiment of the invention receives a first permission signal sent by a register through a first memory; the first memory provides a first effective signal to the register to write the first segment of data into the register; the register receives a second permission signal sent by the second memory; the register provides a second effective signal for the second memory to write the first section of data into the second memory, so that the problem that the transmission of communication data among the modules cannot be flexibly suspended at any time is solved, and the effect of flexibility of the transmission of the communication data among the modules is realized.
Drawings
Fig. 1 is a schematic flowchart of a communication method between modules according to an embodiment of the present invention;
fig. 2 is a flowchart illustrating an inter-module communication method according to a second embodiment of the present invention;
FIG. 3 is a schematic diagram illustrating an operation timing sequence of the inter-module communication method according to the second embodiment of the present invention;
fig. 4 is a schematic structural diagram of an inter-module communication system according to a third embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are for purposes of illustration and not limitation. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
Before discussing exemplary embodiments in more detail, it should be noted that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although a flowchart may describe the steps as a sequential process, many of the steps can be performed in parallel, concurrently or simultaneously. In addition, the order of the steps may be rearranged. A process may be terminated when its operations are completed, but may have additional steps not included in the figure. A process may correspond to a method, a function, a procedure, a subroutine, a subprogram, etc.
Furthermore, the terms "first," "second," and the like may be used herein to describe various orientations, actions, steps, elements, or the like, but the orientations, actions, steps, or elements are not limited by these terms. These terms are only used to distinguish one direction, action, step or element from another direction, action, step or element. For example, a first memory can be referred to as a second memory, and similarly, a second memory can be referred to as a first memory, without departing from the scope of the present application. The first memory and the second memory are both memories, but they are not the same memory. The terms "first", "second", etc. are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features. In the description of the embodiments of the present invention, "a plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.
Example one
As shown in fig. 1, an embodiment of the present invention provides an inter-module communication method for controlling data transmission between a first memory, a second memory, and a register, where the register is connected between the first memory and the second memory, the inter-module communication method including:
s110, the first memory receives a first permission signal sent by the register.
S120, the first memory provides a first effective signal to the register so as to write the first section of data into the register.
In this embodiment, when the first memory receives the first permission signal sent by the register, that is, the register is ready to receive the data that needs to be written in the first memory, after the first memory receives the first permission signal sent by the register, the first memory may read the first segment of data. When the first memory provides the first effective signal to the register, namely the first memory can write the first segment of data into the register, after the register receives the first effective signal sent by the first memory, the register can write the first segment of data.
When the first memory receives the first permission signal sent by the register and the register also receives the first valid signal sent by the first memory, the first segment of data starts to be written into the register from the first memory. When any signal stops sending, namely the register stops sending the first permission signal to the first memory or the first memory stops sending the first effective signal to the register, the transmission of the communication is stopped immediately.
S130, the register receives a second permission signal sent by the second memory.
S140, the register provides a second effective signal to the second memory so as to write the first section of data into the second memory.
In this embodiment, after step S120 is executed, the first segment of data is already written into the register from the first memory, and the register stores the first segment of data. When the register receives the first permission signal sent by the second memory, that is, the second memory is ready to receive the data to be written in the register, after the register receives the second permission signal sent by the second memory, the register can read the first segment of data. When the register provides the second valid signal to the second memory, that is, the register can write the first segment of data into the second memory, after the second memory receives the second valid signal sent by the register, the second memory can write the first segment of data.
When the register receives the first permission signal sent by the second memory and the second memory also receives the second valid signal sent by the register, the first segment of data starts to be written into the second memory from the register. Wherein the transmission of the communication is stopped immediately when either signal stops sending, i.e. the second memory stops sending the second permission signal to the register or the register stops sending the second valid signal to the second memory. Thereby completing the transfer of the first piece of data from the first memory to the second memory. It should be noted that the first segment of data does not refer to the first segment of data in sequence, and the first segment of data may be any segment of data in actual communication.
In the embodiment of the invention, after the transmission interface between the modules is changed into the communication bus format, the correctness and stability of data transmission between the modules are ensured, and in addition, if the wiring distance between the modules is too far or the transmission data bit width is large, the data transmission between the modules has a time sequence error.
The embodiment of the invention receives a first permission signal sent by a register through a first memory; the first memory provides a first effective signal to the register to write the first segment of data into the register; the register receives a second permission signal sent by the second memory; the register provides a second effective signal for the second memory to write the first section of data into the second memory, so that the problem that the transmission of communication data among the modules cannot be flexibly suspended at any time is solved, and the effect of flexibility of the transmission of the communication data among the modules is realized.
Example two
As shown in fig. 2 and fig. 3, a second embodiment of the present invention provides an inter-module communication method, and the second embodiment of the present invention is further optimized based on the first embodiment of the present invention, where the inter-module communication method is used to control data transmission between a first memory, a second memory, and a register, where the register is connected between the first memory and the second memory.
In this embodiment, the sending of the signal is executed only when the clock cycle rises, the first memory includes a first permission end, a first valid end, and a first data end, the second memory includes a second permission end, a second valid end, and a second data end, the register includes an uplink permission end, an uplink valid end, an uplink data end, a downlink permission end, a downlink valid end, and a downlink data end, the first memory transmits data to the uplink data end of the register through the first data end, and the register transmits data to the second data end of the second memory through the downlink data end.
The inter-module communication method comprises the following steps:
s210, the register pulls the first permission signal at the upstream permission end high.
S220, the first permission end of the first memory enters a readable state after receiving a first permission signal of high level sent by the uplink permission end of the register.
In this embodiment, when no data is stored in the register, or data may also be stored in the register, the register may pull up the first permission signal of its uplink permission end from a low level to a high level, that is, the register is ready to receive data to be written in the first memory. When the clock period is rising, the first permission terminal of the first memory receives the first permission signal of high level sent by the uplink permission terminal of the register, and then the first memory enters a readable state, i.e. the first segment of data can be read.
S230, the first memory pulls up a first effective signal of a first effective end of the first memory.
S240, the upstream effective end of the register changes to a writable state after receiving the first effective signal of high level and stores the first segment of data.
In this embodiment, after the first segment of data stored in the first memory is read, at any time later, the first memory may pull up the first valid signal at the first valid end from a low level to a high level, that is, the first memory may write the first segment of data into the register. When the clock period is rising, the upstream effective end of the register receives a high-level first effective signal sent by the first effective end of the first memory, and then the register enters a writable state and can write and store a first segment of data.
When the first permission end of the first memory receives the first permission signal sent by the uplink permission end of the register and the uplink effective end of the register also receives the first effective signal sent by the first effective end of the first memory, the first segment of data starts to be written into the register from the first memory. When any signal stops sending, namely the register stops sending the first permission signal to the first memory or the first memory stops sending the first effective signal to the register, the transmission of the communication is stopped immediately.
And S250, the second memory pulls up a second permission signal of a second permission end of the second memory.
S260, the downlink permission end of the register receives the high-level second permission signal sent by the second permission end of the second memory.
In this embodiment, at this time, the first segment of data has been written from the first data end of the first memory into the upstream data end of the register, and the register stores the first segment of data. At this time, the second memory can pull up the second permission signal of the second permission terminal from low level to high level, i.e. it indicates that the second memory is ready to receive the data required to be written in the register. When the clock period is rising, the downlink permission end of the register receives a high-level second permission signal sent by the second permission end of the second memory, and then the register enters a readable state, namely the register can read the first segment of data from the uplink data end to the downlink data end.
S270, the register pulls up a second effective signal of the downlink effective end of the register.
And S280, the second effective end of the second memory changes to a writable state after receiving the second effective signal with high level and stores the first segment of data.
In this embodiment, after the first segment of data stored in the register is read, at any time later, the register may pull up the second valid signal at the downstream valid end from a low level to a high level, that is, the register may write the first segment of data into the second memory. When the clock period is rising, the second effective end of the second memory receives the second effective signal of high level sent by the downstream effective end of the register, and then the second memory becomes a writable state, and the first section of data can be written and stored.
When the register receives the first permission signal sent by the second memory and the second memory also receives the second valid signal, the first segment of data starts to be written into the second memory from the register. Wherein the transmission of the communication is stopped immediately when either signal stops sending, i.e. the second memory stops sending the second permission signal to the register or the register stops sending the second valid signal to the second memory. Thereby completing the transfer of the first piece of data from the first memory to the second memory. It should be noted that the first segment of data does not refer to the first segment of data in sequence, and the first segment of data may be any segment of data in actual communication.
Similarly, as shown in fig. 3, the data transmission may be continuous, and the first, second and third segments of data and more data transmission may be completed by the same method as described above.
In the embodiment of the invention, after the transmission interface between the modules is changed into the communication bus format, the correctness and stability of data transmission between the modules are ensured, and in addition, if the wiring distance between the modules is too far or the transmission data bit width is large, the data transmission between the modules has a time sequence error.
The embodiment of the invention receives a first permission signal sent by a register through a first memory; the first memory provides a first effective signal to the register to write the first segment of data into the register; the register receives a second permission signal sent by the second memory; the register provides a second effective signal for the second memory to write the first section of data into the second memory, so that the problem that the transmission of communication data among the modules cannot be flexibly suspended at any time is solved, and the effect of flexibility of the transmission of the communication data among the modules is realized.
EXAMPLE III
As shown in fig. 4, a third embodiment of the present invention provides an inter-module communication system, which includes a first memory 100, a second memory 300, and a register 200, where the register 200 is connected between the first memory 100 and the second memory 300.
Wherein, the first memory 100 receives the first permission signal sent by the register 200; the first memory 100 providing a first valid signal to the register 200 to write a first segment of data to the register 200; the register 200 receives a second permission signal sent by the second memory 300; the register 200 provides a second valid signal to the second memory 300 to write the first segment of data to the second memory 300.
Further, in this embodiment, the first memory 100 includes a first permission end 120, a first valid end 130 and a first data end 110, the second memory 300 includes a second permission end 320, a second valid end 330 and a second data end 310, the register 200 includes an uplink permission end 220, an uplink valid end 230, an uplink data end 210, a downlink permission end 250, a downlink valid end 260 and a downlink data end 240, the first memory 100 transmits data to the uplink data end 210 of the register 200 through the first data end 110, and the register 200 transmits data to the second data end 310 of the second memory 300 through the downlink data end 240.
The register 200 pulls the first grant signal of its upstream grant terminal 220 high; the first grant terminal 120 of the first memory 100 enters a readable state after receiving the first grant signal of the high level sent by the uplink grant terminal 220 of the register 200. The first memory 100 pulls up the first active signal of its first active terminal 130; the upstream active end 230 of the register 200 becomes a writable state after receiving the first active signal of high level and stores the first segment of data. The second memory 300 pulls up the second permission signal of the second permission terminal 320 thereof; the downlink enable terminal 250 of the register 200 receives the high-level second enable signal sent from the second enable terminal 320 of the second memory 300. The register 200 pulls up the second valid signal of its downstream valid end 260; the second active terminal 330 of the second memory 300 becomes a writable state and stores the first segment of data after receiving the second active signal of high level.
Specifically, in this embodiment, the signal is sent only when the clock cycle rises, and when no data is stored in the register 200 or data can also be stored, the register 200 may pull up the first permission signal of its uplink permission terminal 220 from a low level to a high level, that is, the register 200 is ready to receive the data to be written in the first memory 100. When the clock period is rising, the first enable 120 of the first memory 100 receives the first enable signal of high level sent by the upstream enable 220 of the register 200, and then the first memory 100 enters a readable state, i.e. the first segment of data can be read.
When the first segment of data stored in the first memory 100 is read, at any time later, the first memory 100 may pull up the first valid signal of the first valid terminal 130 from low level to high level, i.e. it means that the first memory 100 may write the first segment of data into the register 200. When the clock period is rising, the upstream valid end 230 of the register 200 will receive the high-level first valid signal sent by the first valid end 130 of the first memory 100, and then the register 200 enters a writable state, and can write and store the first segment of data.
When the first enable terminal 120 of the first memory 100 receives the first enable signal sent by the upstream enable terminal 220 of the register 200, and the upstream valid terminal 230 of the register 200 also receives the first valid signal sent by the first valid terminal 130 of the first memory 100, the first segment of data starts to be written into the register 200 from the first memory 100. Wherein the transmission of the communication is stopped immediately when either signal stops sending, i.e. the register 200 stops sending the first permission signal to the first memory 100 or the first memory 100 stops sending the first valid signal to the register 200.
At this time, the first segment of data has been written from the first data terminal 110 of the first memory 100 into the upstream data terminal 210 of the register 200, and the register 200 stores the first segment of data. At this time, the second memory 300 can pull up the second enable signal of the second enable terminal 320 from low level to high level, i.e. it indicates that the second memory 300 is ready to receive the data required to be written in the register 200. When the clock period is rising, the downlink enable terminal 250 of the register 200 receives the high-level second enable signal sent by the second enable terminal 320 of the second memory 300, and then the register 200 enters a readable state, i.e. the first segment of data can be read from the uplink data terminal 210 to the downlink data terminal 240.
After the first segment of data stored in the register 200 is read, at any time later, the register 200 may pull up the second active signal of the downstream active end 260 from a low level to a high level, i.e. the register 200 may write the first segment of data into the second memory 300. When the clock cycle is rising, the second valid terminal 330 of the second memory 300 will receive the second valid signal with high level sent by the downstream valid terminal 260 of the register 200, and then the second memory 300 becomes writable state, and the first segment of data can be written and stored.
When the register 200 receives the first permission signal sent by the second memory 300 and the second memory 300 also receives the second valid signal, the first segment of data starts to be written from the register 200 into the second memory 300. Wherein the transmission of the communication will immediately stop when either signal stops sending, i.e. the second memory 300 stops sending the second permission signal to the register 200 or the register 200 stops sending the second valid signal to the second memory 300. Thereby completing the transfer of the first piece of data from the first memory 100 to the second memory 300. It should be noted that the first segment of data does not refer to the first segment of data in sequence, and the first segment of data may be any segment of data in actual communication.
In the embodiment of the present invention, after the transmission interface between the modules is changed to the communication bus format, the correctness and stability of data transmission between the modules are ensured, and in addition, if the wiring distance between the modules is too far or the transmission data bit width is large, a timing error may occur in the data transmission between the modules.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (10)
1. An inter-module communication method for controlling data transfer between a first memory, a second memory, and a register connected between the first memory and the second memory, comprising:
the first memory receives a first permission signal sent by the register;
the first memory provides a first valid signal to the register to write a first segment of data to the register;
the register receives a second permission signal sent by the second memory;
the register provides a second valid signal to the second memory to write the first segment of data to the second memory.
2. The inter-module communication method of claim 1, wherein the receiving, by the first memory, the first permission signal sent by the register comprises:
the register pulls the first permission signal of an upstream permission end of the register high;
and the first permission end of the first memory enters a readable state after receiving a high-level first permission signal sent by the uplink permission end of the register.
3. The inter-module communication method of claim 1, wherein the first memory providing a first valid signal to the register to write a first piece of data to the register comprises:
the first memory pulls up a first effective signal of a first effective end of the first memory;
and the upstream effective end of the register changes into a writable state after receiving a first effective signal with high level and stores the first segment of data.
4. The inter-module communication method of claim 1, wherein the register receiving a second permission signal sent by the second memory comprises:
the second memory pulls up a second permission signal of a second permission end of the second memory;
and the downlink permission end of the register receives a high-level second permission signal sent by the second permission end of the second memory.
5. The inter-module communication method of claim 1, wherein the register providing a second valid signal to the second memory to write the first segment of data to the second memory comprises:
the register pulls up a second effective signal of a downlink effective end of the register;
the second effective end of the second memory changes to a writable state after receiving the second effective signal of high level and stores the first segment of data.
6. An inter-module communication system comprising a first memory, a second memory and a register, said register being connected between the first memory and the second memory,
the first memory receives a first permission signal sent by the register;
the first memory provides a first valid signal to the register to write a first segment of data to the register;
the register receives a second permission signal sent by the second memory;
the register provides a second valid signal to the second memory to write the first segment of data to the second memory.
7. The inter-module communication system of claim 6,
the register pulls the first permission signal of an upstream permission end of the register high;
and the first permission end of the first memory enters a readable state after receiving a high-level first permission signal sent by the uplink permission end of the register.
8. The inter-module communication system of claim 6,
the first memory pulls up a first effective signal of a first effective end of the first memory;
and the upstream effective end of the register changes into a writable state after receiving a first effective signal with high level and stores the first segment of data.
9. The inter-module communication system of claim 6,
the second memory pulls up a second permission signal of a second permission end of the second memory;
and the downlink permission end of the register receives a high-level second permission signal sent by the second permission end of the second memory.
10. The inter-module communication system of claim 6,
the register pulls up a second effective signal of a downlink effective end of the register;
the second effective end of the second memory changes to a writable state after receiving the second effective signal of high level and stores the first segment of data.
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| WO2021259228A1 (en) * | 2020-06-22 | 2021-12-30 | 深圳鲲云信息科技有限公司 | Inter-module communication method and system |
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| WO2021259228A1 (en) | 2021-12-30 |
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