CN104008076A - Bus data signal transmitting method and device capable of supporting DVFS - Google Patents
Bus data signal transmitting method and device capable of supporting DVFS Download PDFInfo
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- CN104008076A CN104008076A CN201310059075.2A CN201310059075A CN104008076A CN 104008076 A CN104008076 A CN 104008076A CN 201310059075 A CN201310059075 A CN 201310059075A CN 104008076 A CN104008076 A CN 104008076A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
- G06F13/4226—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus with asynchronous protocol
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
- G06F13/4072—Drivers or receivers
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The invention discloses a bus data transmitting method and a bus data transmitting device capable of supporting DVFS, and relates to the field of low-power design of IC. The method comprises the steps of: using an originating-party voltage domain clock signal to send a bus data signal as a cross-voltage domain signal, performing level conversion on the cross-voltage domain signal, and using a receiving-party voltage domain clock signal to receive the cross-voltage domain signal which has been subjected to level conversion. According to the bus data transmitting method and device capable of supporting DVFS, an asynchronous AXI interface is achieved, high-speed and stable bus data signal transmission is performed between two voltage domains through the achieved asynchronous AXI interface, the timing sequence is much easier to closure, and thus stability and reliability of the whole system at dynamic voltage and adjustable frequency are improved.
Description
Technical field
The present invention relates to integrated circuit (IC) low power dissipation design field, be particularly related between two of a kind of DVFS of the support voltage domains of supporting dynamic electric voltage frequencies to adjust DVFS and realize asynchronous AXI interface, and utilize institute to realize and state method and the relevant apparatus that asynchronous AXI Interface realization data signal bus transmits.
Background technology
Along with being in fashion of consumer electronics product, consumer also becomes increasingly complex for requirement that can portable product function.Before the relative capacity at battery does not also further promote, as the most effective mode is how used the energy of battery limited, just become at present the most significant problems of can portable consumer electronic product facing, and carry out seemingly only current option of design chips by Low-power Technology.The power consumption of complementary metal oxide semiconductor (CMOS) cmos circuit is divided dynamic power consumption and quiescent dissipation two parts.Dynamic power consumption is main relevant with load capacitance C with voltage V, frequency of operation F.Quiescent dissipation is mainly relevant with voltage V, subthreshold current.So, by reducing voltage V and frequency of operation F, can effectively reduce the power consumption of circuit.
Industry was adjusted DVFS to dynamic electric voltage frequency in recent years research and application are more extensive, and namely, in lifting voltage V, frequency of operation F, also along with dynamic adjustment, reaches the object that reduces power consumption.With respect to traditional dynamic frequency, adjust DFS, DVFS both can reduce power consumption, and also can be real reach reduces the object that energy consumes.
At present, in order to reduce the implementation complexity of system, improve the application of DVFS, asynchronous interface circuit can first be blocked two bus datas between voltage domain by an indicator signal and be transmitted, after waiting for that DFS has operated, discharge block signal, proceed bus transfer.This asynchronous interface circuit frequency is not high, and data transmission efficiency is low.
For using between two voltage domains of synchronous clock, can also pass through the clock phase of two voltage domains of accurate adjustment, make it reach synchronization, to guarantee the reliability of data transmission.Sort circuit is used fixed frequency, and for DVFS design, the delay jitter producing through Clock Tree due to signal is larger, to timing closure, causes very large difficulty.
Summary of the invention
The method and the device that the object of the present invention is to provide the data signal bus transmission of a kind of DVFS of support, can solve the problem that in prior art, data transmission efficiency is low and sequential is difficult to convergence better.
According to an aspect of the present invention, provide the method for the data signal bus transmission of a kind of DVFS of support, having comprised:
Utilize originating party voltage domain clock signal to send as the data signal bus across voltage domain signal;
By described, across voltage domain signal, carry out level conversion;
Utilize debit's voltage domain clock signal to receive the described across voltage domain signal of process level conversion.
Preferably, during transfer bus data-signal between originating party voltage domain and debit's voltage domain, originating party voltage domain and/or debit's voltage domain carry out dynamic electric voltage frequency and adjust DVFS processing.
Preferably, during transfer bus data-signal between originating party voltage domain and debit's voltage domain, originating party voltage domain is using as send into the first asynchronous FIFO control module across the data signal bus of voltage domain signal, the first asynchronous FIFO control module utilizes described originating party voltage domain clock signal, and described data signal bus is sent to level conversion unit.
Preferably, level conversion unit carries out level conversion by described across voltage domain signal, and using through level conversion across voltage domain signal, as debit's voltage domain data signal bus, send the second asynchronous FIFO control module to.
Preferably, debit's voltage domain utilizes its clock signal to read described debit's voltage domain data signal bus from described the second asynchronous FIFO control module.
Preferably, described originating party voltage domain is CPU voltage domain or BIU voltage domain, and described debit's voltage domain is BIU voltage domain or CPU voltage domain.
According to a further aspect in the invention, provide the device of the data signal bus transmission of a kind of DVFS of support, it is characterized in that, having comprised:
Originating party parts, for utilizing originating party voltage domain clock signal to send as the data signal bus across voltage domain signal;
Level conversion parts, for carrying out level conversion by described across voltage domain signal;
Debit's parts, for utilizing debit's voltage domain clock signal to receive the described across voltage domain signal of process level conversion.
Preferably, described originating party voltage domain and/or described debit's voltage domain, also for during transfer bus data-signal, carry out dynamic electric voltage frequency and adjust DVFS processing.
Preferably, described originating party parts comprise:
Originating party voltage domain unit, for during transfer bus data-signal between originating party voltage domain and debit's voltage domain, originating party voltage domain is using as send into the first asynchronous FIFO control module across the data signal bus of voltage domain signal;
The first asynchronous FIFO control module, for utilizing described originating party voltage domain clock signal, is sent to level conversion parts by described data signal bus.
Preferably, described level conversion parts comprise:
Level conversion unit, for carrying out level conversion by described across voltage domain signal, and using through level conversion across voltage domain signal, as debit's voltage domain data signal bus, send the second asynchronous FIFO control module to.
Preferably, described debit's parts comprise:
The second asynchronous FIFO control module, the debit's voltage domain data signal bus transmitting for incoming level converting member;
Debit's voltage domain unit, for utilizing debit's voltage domain clock signal to read described debit's voltage domain data signal bus from described the second asynchronous FIFO control module.
Preferably, described originating party voltage domain is BIU voltage domain or BIU voltage domain, and described debit's voltage domain is CPU voltage domain or CPU voltage domain.
Compared with prior art, beneficial effect of the present invention is:
The present invention can realize two data high-speed stable transfer between voltage domain, and relatively traditional asynchronous interface circuit will be easier to timing closure, thereby promotes stability and the reliability of whole system when dynamic electric voltage and frequency adjustment.
Accompanying drawing explanation
Fig. 1 is the method flow diagram of the data signal bus transmission of the support DVFS that provides of the embodiment of the present invention;
Fig. 2 is the simple SOC chip overall architecture schematic diagram of the support DVFS that provides of the embodiment of the present invention;
Fig. 3 is the dual core processor overall architecture schematic diagram of the support DVFS that provides of the embodiment of the present invention;
Fig. 4 is the device block diagram of realizing data signal bus transmission of the support DVFS that provides of the embodiment of the present invention;
Fig. 5 is the structural representation of the AXI passage of the separation read-write transmission that provides of the embodiment of the present invention;
Fig. 6 is the structural representation of the asynchronous AXI interface circuit that provides of the embodiment of the present invention.
Embodiment
Below in conjunction with accompanying drawing, to a preferred embodiment of the present invention will be described in detail, should be appreciated that following illustrated preferred embodiment, only for description and interpretation the present invention, is not intended to limit the present invention.
Fig. 1 is the method flow diagram of the data signal bus transmission of the support DVFS that provides of the embodiment of the present invention, and as shown in Figure 1, step comprises:
Step 101, utilize originating party voltage domain clock signal to send as the data signal bus across voltage domain signal.Specifically, during transfer bus data-signal between originating party voltage domain and debit's voltage domain, originating party voltage domain is using as send into the first asynchronous FIFO control module across the data signal bus of voltage domain signal, the first asynchronous FIFO control module utilizes described originating party voltage domain clock signal, and described data signal bus is sent to level conversion unit.
Step 102, by described, across voltage domain signal, carry out level conversion.Specifically, first, level conversion unit carries out level conversion by described across voltage domain signal, and using through level conversion across voltage domain signal, as debit's voltage domain data signal bus, send the second asynchronous FIFO control module to.
Step 103, utilize debit's voltage domain clock signal to receive described across voltage domain signal through level conversion.Specifically, debit's voltage domain utilizes its clock signal to read described debit's voltage domain data signal bus from described the second asynchronous FIFO control module.
In above-mentioned steps, described originating party voltage domain is the CPU voltage domain in chip, and described debit's voltage domain is the BIU voltage domain in chip, and described data signal bus comprises writing address signal, write data signal, reads address signal; Or described originating party voltage domain is the BIU voltage domain in chip, described debit's voltage domain is the CPU voltage domain in chip, and described data signal bus comprises reading data signal, write response signal.
Further, during transfer bus data-signal between originating party voltage domain and debit's voltage domain, originating party voltage domain and/or debit's voltage domain can carry out dynamic electric voltage frequency and adjust DVFS processing.
Fig. 2 is the simple SOC chip overall architecture schematic diagram of the support DVFS that provides of the embodiment of the present invention, as shown in Figure 2, comprises three voltage domains: CPU voltage domain, BIU voltage domain and SOC voltage domain.The functional unit that described CPU voltage domain comprises is mainly two CPU cores.Described BIU voltage domain has mainly comprised for realizing functional unit and the Bus Interface Unit of buffer consistency between two CPU cores, as shown in Figure 3.Described SOC voltage domain comprises system AXI bus, AXI2APB bridge, system clock generator and phaselocked loop.At three respectively corresponding three power supply units of voltage domain described in SOC chip exterior.Described CPU voltage domain need to be realized dynamic electric voltage adjustment, so SOC chip is configured the power supply unit of CPU voltage domain by configuration interface.The technology that the present invention relates to realize by bus interface between CPU voltage domain and BIU voltage domain data signal bus transmission, realizes the transmission of the data signal bus between CPU voltage domain and BIU voltage domain by the cross clock domain in Fig. 3 and voltage domain processing logic.
Owing to adopting the SOC chip of DVFS substantially all to adopt the framework of GALS, Global Asynchronous namely, the timing topology of local synchronization.This structure is easy to the convergence of sequential and the lifting of performance, and between each voltage domain, work clock is independent, does not need overall Clock Tree balance.So, between two voltage domains, just need to adopt asynchronous interface circuit, guarantee the correctness of data transmission.But, the invention is not restricted to SOC chip, in other chip, as long as need to adopt asynchronous interface circuit to carry out the transmission of data signal bus, can use technical solutions according to the invention between CPU voltage domain and BIU voltage domain.
Fig. 4 is the device block diagram of the data signal bus transmission of the support DVFS that provides of the embodiment of the present invention, as shown in Figure 4, comprise for utilize originating party voltage domain clock signal send originating party parts as the data signal bus across voltage domain signal, for carrying out the level conversion parts of level conversion and for utilizing debit's voltage domain clock signal to receive the described debit's parts across voltage domain signal through level conversion, wherein by described across voltage domain signal:
Described originating party parts comprise originating party voltage domain unit and the first asynchronous FIFO control module, described originating party voltage domain unit is during transfer bus data-signal between originating party voltage domain and debit's voltage domain, originating party voltage domain is using as send into the first asynchronous FIFO control module across the data signal bus of voltage domain signal, described the first asynchronous FIFO control module utilizes described originating party voltage domain clock signal, and described data signal bus is sent to level conversion parts.
Described level conversion parts comprise level conversion unit, described level conversion unit carries out level conversion by described across voltage domain signal, and using through level conversion across voltage domain signal, as debit's voltage domain data signal bus, send the second asynchronous FIFO control module to.
Described debit's parts comprise the second asynchronous FIFO control module and debit's voltage domain unit, debit's voltage domain data signal bus that described the second asynchronous FIFO control module incoming level converting member transmits, described debit's voltage domain unit by using debit voltage domain clock signal reads described debit's voltage domain data signal bus from described the second asynchronous FIFO control module.
Further, described originating party voltage domain unit is CPU or BIU in SOC chip, described debit's voltage domain unit is BIU or CPU in SOC chip, and during transfer bus data-signal between CPU and BIU, CPU voltage domain and/or BIU voltage domain can carry out DVFS operation.
Further, described the first asynchronous FIFO control module and described the second asynchronous FIFO control module, between two voltage domains, together with level conversion parts, have been realized asynchronous AXI interface circuit, and the function that described asynchronous AXI interface circuit is realized comprises:
1, for realizing the SOC bus interface of supporting specific protocol;
2, for carry out data interaction between two asynchronous clocks.
In traditional SOC chip design scheme, the interface between two different voltage domains is generally processed by asynchronous interface, is not easy to produce sequence problem like this in the part across voltage domain.The present invention adopts two asynchronous FIFOs that the read-write transmission of asynchronous AXI interface is separated, between two asynchronous FIFOs, cut clock zone and voltage domain, make two data transmission between voltage domain more stable, interfaces frequency is higher, and timing closure is more prone to.Fig. 5 is the structural representation of the asynchronous AXI passage of the separation read-write transmission that provides of the embodiment of the present invention, and as shown in Figure 5, the transmission request that the CPU of take is initiated to BIU is example, and the workflow of whole bus interface is as follows:
1, CPU is initiated to the transmission request of BIU, and bus protocol logic is got off the data signal bus access as across voltage domain signal, then sends into the asynchronous FIFO control module of CPU side;
2, the asynchronous FIFO control module of CPU side utilizes CPU voltage domain clock signal, by the described asynchronous FIFO control module of giving BIU side across voltage domain signal after level conversion unit;
3, BIU utilizes BIU voltage domain clock signal to read the asynchronous FIFO control module of BIU side, by through level conversion across voltage domain signal, be transformed into its clock zone, complete the transmitting procedure of whole data.
Above-mentioned data signal bus comprises writing address signal, write data signal, reads address signal.
Same, if BIU initiates transmission request to CPU, the workflow of whole bus interface is as follows:
1, BIU is initiated to the transmission request of CPU, and bus protocol logic is got off the data signal bus access as across voltage domain signal, then sends into the asynchronous FIFO control module of BIU side;
2, the asynchronous FIFO control module of BIU side utilizes BIU voltage domain clock signal, by the described asynchronous FIFO control module of giving CPU side across voltage domain signal after level conversion unit;
3, CPU utilizes CPU voltage domain clock signal to read the asynchronous FIFO control module of CPU side, by through level conversion across voltage domain signal, be transformed into its clock zone, complete the transmitting procedure of whole data.
In conventional asynchronous interface circuit, the clock of the clock of asynchronous FIFO input logic part and bus logic part is same source, need to do Clock Tree to two-part timing unit like this, and will accomplish the balance of Clock Tree when back-end realization.And for the design of DVFS, carry out being difficult to accomplish across the Clock Tree balance of voltage domain, and because both sides Clock Tree adheres to different voltage domains separately, the delay jitter that signal produces through Clock Tree is also larger, to timing closure, causes very large difficulty.With the contrast of conventional asynchronous interface circuit, the advantage of the asynchronous AXI interface circuit adopting in the present invention is, the asynchronous FIFO steering logic that originating party has adopted respectively separated read-write to transmit with the side of connecing, and the clock of both sides is asynchronous clock.Fig. 6 is the structural representation of the asynchronous AXI interface circuit that provides of the embodiment of the present invention, as shown in Figure 6, reads and writes the whole asynchronous AXI interface circuit of transmission by separation, carries out the transmission of data signal bus.The asynchronous working method of the whole employing of this asynchronous AXI interface circuit, the transmission request that the CPU of take is initiated to BIU is example, the workflow of described asynchronous AXI interface circuit is as follows:
1, during CPU transmit a request to BIU, when cpu_valid signal is effective, data signal bus is given to the asynchronous FIFO control module of CPU side, so that the asynchronous FIFO control module of described CPU side utilizes its asynchronous FIFO steering logic, (being CPU write control logic) carries out respective handling;
2, the asynchronous FIFO control module of CPU side utilizes described asynchronous FIFO steering logic, whether the register that first judges it is full, if less than, by not gate, put cpu_ready signal effective, and by using cpu_valid signal and cpu_ready signal as the input with door, put pushdata signal effective, then, utilize CPU_CLOCK, will be latched in described register across voltage domain signal.
In this process, the asynchronous FIFO steering logic of CPU side need to know that the degree of depth of register in asynchronous FIFO control module and the read pointer of asynchronous BIU side judge the full state of sky of FIFO, a burst transfer of CPU side does not surpass the degree of depth of register in asynchronous FIFO control module, otherwise can affect the performance of whole asynchronous interface circuit.As long as register less than, CPU just can continue to send data signal bus, needn't wait for the biu_ready signal of BIU side.
3, level conversion unit carries out level conversion to described CPU side across voltage domain signal, and send into the asynchronous FIFO control module of BIU side, so that the asynchronous FIFO control module of BIU side utilizes its asynchronous FIFO steering logic, (being that BIU reads steering logic) carries out respective handling;
4, the asynchronous FIFO control module of BIU side utilizes its asynchronous FIFO steering logic, judges that whether its register is not empty, if so, returns to biu_valid signal effective; When the biu_ready of BIU side is effective, by using biu_valid signal and biu_ready signal as the input with door, popdata signal is set to effectively, thereby utilize BIU_CLOCK by reading out from its register across voltage domain signal after level conversion, be transformed into BIU clock zone, complete bus transfer one time.
For 5 passages of asynchronous AXI interface, due to address and separately transmission of data, for originating party, need to record the current quantity that has sent address, when quantity is non-vanishing, data channel could send data.
The present invention can be widely used in supporting in the VLSI (very large scale integrated circuit) VLSI chip design of DVFS, asynchronous AXI interface circuit can steady operation under high frequency clock, the transmission efficient stable of data signal bus, back-end realization also easily reaches timing closure, the asynchronous interface circuit that this asynchronous interface circuit is relatively traditional is changed very little, easily realizes.
Although above the present invention is had been described in detail, the invention is not restricted to this, those skilled in the art of the present technique can carry out various modifications according to principle of the present invention.Therefore, all modifications of doing according to the principle of the invention, all should be understood to fall into protection scope of the present invention.
Claims (12)
1. a method of supporting the data signal bus transmission of DVFS, is characterized in that, comprising:
Utilize originating party voltage domain clock signal to send as the data signal bus across voltage domain signal;
By described, across voltage domain signal, carry out level conversion;
Utilize debit's voltage domain clock signal to receive the described across voltage domain signal of process level conversion.
2. method according to claim 1, is characterized in that, during transfer bus data-signal between originating party voltage domain and debit's voltage domain, originating party voltage domain and/or debit's voltage domain carry out dynamic electric voltage frequency and adjust DVFS processing.
3. method according to claim 2, it is characterized in that, during transfer bus data-signal between originating party voltage domain and debit's voltage domain, originating party voltage domain is using as send into the first asynchronous FIFO control module across the data signal bus of voltage domain signal, the first asynchronous FIFO control module utilizes described originating party voltage domain clock signal, and described data signal bus is sent to level conversion unit.
4. method according to claim 3, it is characterized in that, level conversion unit carries out level conversion by described across voltage domain signal, and using through level conversion across voltage domain signal, as debit's voltage domain data signal bus, send the second asynchronous FIFO control module to.
5. method according to claim 4, is characterized in that, debit's voltage domain utilizes its clock signal to read described debit's voltage domain data signal bus from described the second asynchronous FIFO control module.
6. according to the method described in claim 1-5 any one, it is characterized in that, described originating party voltage domain is BIU voltage domain or BIU voltage domain, and described debit's voltage domain is CPU voltage domain or CPU voltage domain.
7. a device of supporting the data signal bus transmission of DVFS, is characterized in that, comprising:
Originating party parts, for utilizing originating party voltage domain clock signal to send as the data signal bus across voltage domain signal;
Level conversion parts, for carrying out level conversion by described across voltage domain signal;
Debit's parts, for utilizing debit's voltage domain clock signal to receive the described across voltage domain signal of process level conversion.
8. device according to claim 7, is characterized in that, described originating party voltage domain and/or described debit's voltage domain, also for during transfer bus data-signal, carry out dynamic electric voltage frequency and adjust DVFS processing.
9. device according to claim 8, is characterized in that, described originating party parts comprise:
Originating party voltage domain unit, for during transfer bus data-signal between originating party voltage domain and debit's voltage domain, originating party voltage domain is using as send into the first asynchronous FIFO control module across the data signal bus of voltage domain signal;
The first asynchronous FIFO control module, for utilizing described originating party voltage domain clock signal, is sent to level conversion parts by described data signal bus.
10. device according to claim 9, is characterized in that, described level conversion parts comprise:
Level conversion unit, for carrying out level conversion by described across voltage domain signal, and using through level conversion across voltage domain signal, as debit's voltage domain data signal bus, send the second asynchronous FIFO control module to.
11. devices according to claim 10, is characterized in that, described debit's parts comprise:
The second asynchronous FIFO control module, the debit's voltage domain data signal bus transmitting for incoming level converting member;
Debit's voltage domain unit, for utilizing debit's voltage domain clock signal to read described debit's voltage domain data signal bus from described the second asynchronous FIFO control module.
12. the device according to described in claim 7-11 any one, is characterized in that, described originating party voltage domain is BIU voltage domain or BIU voltage domain, and described debit's voltage domain is CPU voltage domain or CPU voltage domain.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
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| CN201310059075.2A CN104008076B (en) | 2013-02-25 | 2013-02-25 | The method and device that a kind of data signal bus for supporting DVFS transmits |
| PCT/CN2013/090729 WO2014127674A1 (en) | 2013-02-25 | 2013-12-27 | Method and device for transmitting bus data signal, supporting dvfs |
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| CN201310059075.2A CN104008076B (en) | 2013-02-25 | 2013-02-25 | The method and device that a kind of data signal bus for supporting DVFS transmits |
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| WO (1) | WO2014127674A1 (en) |
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| CN110636240A (en) * | 2019-08-19 | 2019-12-31 | 南京芯驰半导体科技有限公司 | Signal regulation system and method for video interface |
| CN111752875A (en) * | 2020-06-22 | 2020-10-09 | 深圳鲲云信息科技有限公司 | Inter-module communication method and system |
| CN113093899A (en) * | 2021-04-09 | 2021-07-09 | 思澈科技(上海)有限公司 | Cross-power domain data transmission method |
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| CN101741372A (en) * | 2008-11-11 | 2010-06-16 | 株式会社瑞萨科技 | Semiconductor integrated circuit and control method for clock signal synchronization |
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| CN110636240A (en) * | 2019-08-19 | 2019-12-31 | 南京芯驰半导体科技有限公司 | Signal regulation system and method for video interface |
| CN110636240B (en) * | 2019-08-19 | 2022-02-01 | 南京芯驰半导体科技有限公司 | Signal regulation system and method for video interface |
| CN111752875A (en) * | 2020-06-22 | 2020-10-09 | 深圳鲲云信息科技有限公司 | Inter-module communication method and system |
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| CN113093899B (en) * | 2021-04-09 | 2022-03-22 | 思澈科技(上海)有限公司 | Cross-power domain data transmission method |
Also Published As
| Publication number | Publication date |
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| CN104008076B (en) | 2018-04-10 |
| WO2014127674A1 (en) | 2014-08-28 |
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