CN104991880B - A kind of FC AE ASM Communication Cards based on PCI E interfaces - Google Patents
A kind of FC AE ASM Communication Cards based on PCI E interfaces Download PDFInfo
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- CN104991880B CN104991880B CN201510298319.1A CN201510298319A CN104991880B CN 104991880 B CN104991880 B CN 104991880B CN 201510298319 A CN201510298319 A CN 201510298319A CN 104991880 B CN104991880 B CN 104991880B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
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Abstract
The invention discloses a kind of FC AE ASM Communication Cards based on PCI E interfaces, including fpga chip, DDR2 modules, power management module, optical transceiver module, programmable clock and configuration chip;The storage control signal I/O of the storage control signal input/output terminal connection DDR2 modules of fpga chip；The transmission data input output end of fpga chip and the data output input of optical transceiver module are connected, and fpga chip is connected with PCI E EBIs；The input of the power management module is connected with the PCI E EBIs；The clock input of the fpga chip is also connected with programmable clock；The fpga chip is connected with the configuration chip.After adopting the above technical scheme, the present invention has the advantages that compared with prior art：Transmission rate for that can support highest 4.25Gbps, maximum distance reach 15km fiber optic protocols passage, improve its data transmission bauds 15% between terminal.
Description
Technical field
The present invention relates to communication technique field, more particularly to a kind of FC-AE-ASM Communication Cards based on PCI-E interface.
Background technology
Since nineteen seventies, aviation electronics is developed rapidly as digitization system from simulated system.Aviation
Electronic system architecture experienced discrete, association type, composite type and advanced synthesis type development.Association type avionics system number
According to communication mainly using the communication protocols such as RS-422, RS-485, ARINC429 and MIL-STD-1553, these data communication protocols
View has the characteristics that reliability is high, communication quality is stable, extensively should have been obtained in the military communication such as contemporary aviation, navigation field
With.But in these communication protocols, it is high using the agreement cost of parallel transmission mode, and when long range is transmitted, data
Interference increase between line, data easily produce mistake, therefore it is not suitable for the data transfer of long range, and in general is serial
Data transfer mode（Such as RS-422, RS-485）Although although respectively having feature in data transmission, it is in transmission rate
It is still unsatisfactory with transmission range aspect.In a word, because above-mentioned protocol data transmission rate is low, fault-tolerant ability finite sum maintenance work
The system limitations such as complexity, therefore data volume is less between the subsystem for being usually applicable only to itself to have data-handling capacity
Data transfer, it is impossible to meet the requirement that synthetic aviation electronic system communicates to data.
Fiber channel protocol (FC-AE) under aviation electronics environment includes FC-AE-ASM, FC-AE-1553, FC-AE-
A variety of FC upper-layer protocols such as RDMA, these agreements adapt to the popularity requirement of Unified Network, meet the needs of aviation electronics development,
The support and participation of numerous civilian, military companies are obtained.
At present, there are ARINC 429 and MIL-STD-1553B buses in China using more airborne databus.With America and Europe
Compared etc. national advanced level, there is larger gap with avionic device for the Avionics level of China's opportunity of combat.
China also will clearly use standards of the optical-fibre channel Unified Network FC as a new generation of China military secret avionics system, in a new generation
The avionics system with FC buses will be equipped in opportunity of combat.As a member in FC-AE protocol families, FC-AE-ASM（Aviation electronics ring
The anonymous message transmission protocol of optical-fibre channel under border）With its low latency, high data communication efficiency, real-time Communication for Power ability is strong the advantages that
It has been applied to avionics system of new generation, wide market.
But current FC-AE-ASM agreements, realize that the structure that data transfer is connected with terminal is more complicated, into
This is higher, and the transmission rate deficiency of the connection, occasionally has data transmit-receive situation not in time, to the accurate height of data transportation requirements
The avionics field of speed, this is undoubtedly a key factor for restricting technology development.
In view of this, it is special to propose the present invention.
The content of the invention
The technical problem to be solved in the present invention is overcome the deficiencies in the prior art, there is provided a kind of based on PCI-E interface
FC-AE-ASM Communication Cards, realize the high speed data transfer between terminal and agreement transmission end.
In order to solve the above technical problems, the present invention is using the basic conception of technical scheme：
A kind of FC-AE-ASM communication cards based on PCI-E interface, including fpga chip, DDR2（Second generation Double Data Rate
Synchronous DRAM）Module, power management module, optical transceiver module, programmable clock and configuration chip；
The storage control signal I/O of the storage control signal input/output terminal connection DDR2 modules of fpga chip；
The transmission data input output end of fpga chip and the data output input of optical transceiver module connect, fpga chip and PCI-E
EBI connects；The input of the power management module is connected with the PCI-E EBIs；The clock of the fpga chip
Input is also connected with programmable clock；The fpga chip is connected with the configuration chip；
The input voltage of the power management module is 3.3V, and the power management module provided with voltage be respectively 1.0V,
1.2V, 1.8V and 2.5V at least four voltage outputs.
The above-mentioned FC-AE-ASM communication cards based on PCI-E interface, the top-level module of the fpga chip include FC moulds
Block portion point, data buffer storage part and PCI-E parts；
The PCI-E parts include PCI-E EP（PCI-E endpoint）、DMA（Direct memory access）Controller, register and
GTP（High speed serialization transceiver）；The PCI-E EP are connected by the GTP with the PCI-E buses；The dma controller
It is connected with the register；
The data buffer storage part includes FC channel interface control modules, and the FC channel interfaces control module connects with user
Mouth connection, the FC channel interfaces control module read the information from the dma controller by Tx buffer modules and should
Information transmission gives the user interface, and the FC channel interfaces control module is read by rx buffering module and connect from the user
The information of mouth simultaneously passes it to the dma controller；
The FC module sections include MAC（Medium education）Module, user interface, management interface, credit management mould
Block and link control module；The user interface, credit management module and the link control module connect with the MAC module
Connect；The management interface is connected with the register；The link control module is connected into FC buses by GTP.
The above-mentioned FC-AE-ASM communication cards based on PCI-E interface, each dma controller pass through two data
Caching part is connected with two FC module sections respectively；Each data buffer storage part is only entered using a FC module section as object
Row data buffer storage.
The above-mentioned FC-AE-ASM communication cards based on PCI-E interface, the PCI-E buses are 4 BITBUS networks, the PCI-E
Bus is connected by two GTP with the PCI-E EP.
The above-mentioned FC-AE-ASM communication cards based on PCI-E interface, the SDRAM chips of the DDR2 modules, monolithic are big
Small is 512M, and data-bus width is 16, and two panels uses after synthesizing 32 position datawires, and the chip is Micron companies
MT47H128M16HG-3。
The above-mentioned FC-AE-ASM communication cards based on PCI-E interface, the fpga chip are also associated with reset circuit；
The reset circuit includes resistance R1, resistance R2, reset button switch K, electric capacity C1, diode VD and the reset with fpga chip
Interface is connected reseting terminal；
The negative pole of the diode VD and the resistance R1 one end are connected with power supply positive pole；The resistance R1's
The other end, diode VD positive pole, resistance R2 one end and electric capacity C1 positive pole are connected with the reseting terminal；The resistance
The R2 other end is connected with reset button switch K one end；The other end of the reset button switch K and electric capacity C1 negative pole are equal
Ground connection.
After adopting the above technical scheme, the present invention has the advantages that compared with prior art：
Transmission rate for that can support highest 4.25Gbps, maximum distance reach 15km fiber optic protocols passage, carried
Its data transmission bauds 15% between terminal is risen.
Brief description of the drawings
Fig. 1 is the hardware architecture diagram of the FC-AE-ASM communication cards of the invention based on PCI-E interface.
Fig. 2 is the top-level module structural representation of fpga chip of the present invention.
Fig. 3 is reset circuit figure of the present invention.
Embodiment
Below in conjunction with the accompanying drawings and specific embodiment, the invention will be further described, to help present disclosure is understood.
As shown in figure 1, the invention provides a kind of FC-AE-ASM communication cards based on PCI-E interface, including FPGA cores
Piece, DDR2（Second generation Double Data Rate synchronous DRAM）It is module, power management module, optical transceiver module, programmable
Clock and configuration chip.The XC5VLX110T- of FPGA models Xilinx companies Virtex5 LXT series in the present embodiment
1FFG1136I.The storage control signal output input of the storage control signal input/output terminal connection DDR2 modules of fpga chip
End；DDR2 modules realize FPGA information storage, and the SDRAM chip monolithics sizes of the DDR2 modules is 512M, wide data bus
Spend for 16, two panels uses after synthesizing 32 position datawires, and the information for being capable of effective guarantee FPGA is read to deposit function, in the present embodiment
In, the chip of DDR2 modules is the MT47H128M16HG-3 of Micron companies production, and its working frequency is under 200MHz, effectively
Meet FPGA demands.
The transmission data input output end of fpga chip and the data output input of optical transceiver module connect, fpga chip
It is connected with PCI-E EBIs.In this way, FPGA can complete between high frequency optical signal and electric signal conversion and PCI-E buses and
Information exchange function between FC buses.The input of the power management module is connected with the PCI-E EBIs；The electricity
The input voltage of source control module is 3.3V, and the power management module is respectively 1.0V, 1.2V, 1.8V and 2.5V provided with voltage
At least four voltage outputs.Power management module can be unified for FPGA and its expandable element realizes power supply management, meet not
Same element voltage demand.
The clock input of the fpga chip is also connected with programmable clock；Timing and tally function are realized, is entered for FPGA
Row data simultaneously provide clock foundation.The fpga chip is connected with the configuration chip；Configuration chip is used to realize FPGA's
Initial configuration realizes that assurance function is normally realized.In the present embodiment, the configuration chip model is selected as Xilinx companies
XCF32PVOG48C。
In order to ensure FPGA normal works, reset function is realized.The fpga chip is also associated with reset circuit；Such as Fig. 3 institutes
Show, the reset circuit include resistance R1, resistance R2, reset button switch K, electric capacity C1, diode VD and with fpga chip
Reseting interface is connected reseting terminal；The negative pole of the diode VD and the resistance R1 one end with power supply positive pole phase
Even；The other end of the resistance R1, diode VD positive pole, resistance R2 one end and electric capacity C1 positive pole with the reset terminal
Son is connected；The other end of the resistance R2 is connected with reset button switch K one end；The other end of the reset button switch K
It is grounded with electric capacity C1 negative pole.
The course of work of the reset circuit is as follows：
1st, after system connects electricity, positive source output 3.3V voltages, charged by R1 to C1, now reseting terminal RESET
On obtain low level, through after a period of time, C1 is filled, resets the rise of end points RESET level, finally stablize in high level,
Complete electrification reset process.
When the 2nd, pressing reset button switch K, switch closure, C1 discharges into ground by R2, and reseting terminal RESET is drawn by moment
To low level, after reset button switch K is opened, C1 charges again by R1, complete through being stabilized to high level after a period of time
Into manual reset procedure.
As shown in Fig. 2 the top-level module of the present embodiment fpga chip includes FC module sections 1, the and of data buffer storage part 2
PCI-E parts 3；The PCI-E parts include PCI-E EP（PCI-E endpoint）、DMA（Direct memory access）Controller, deposit
Device and GTP（High speed serialization transceiver）；The PCI-E EP are connected by the GTP with the PCI-E buses；The DMA controls
Device processed is connected with the register；In this way, be based on this, Communication Card of the invention can realize the EndPoint of PCIe buses with
And DMA function, complete the data interaction with host PC Ie buses.
The data buffer storage part includes FC channel interface control modules, and the FC channel interfaces control module connects with user
Mouth connection, the FC channel interfaces control module read the information from the dma controller by Tx buffer modules and should
Information transmission gives the user interface, and the FC channel interfaces control module is read by rx buffering module and connect from the user
The information of mouth simultaneously passes it to the dma controller.Rx buffering module and Tx buffer modules, can be above and below temporary cache
Row data, prevent loss of data, and the integrality of data transfer is effectively ensured.
The FC module sections include MAC（Medium education）Module, user interface, management interface, credit management mould
Block and link control module；The user interface, credit management module and the link control module connect with the MAC module
Connect；The management interface is connected with the register；The link control module is connected into FC buses by GTP.FC modules are main
It is responsible for data encoding and decoding and the conversion of photosignal, and described dma controller can be fitted through data transfer is carried out
Adaptability management and control, realize and realize that data pass under the premise of transmitting the accuracy of data with the complementation of the data function of PCI-E buses, guarantee
The lifting of defeated speed.
In the present embodiment, each dma controller by two data buffer units respectively with two FC modules portions
Split-phase connects；Each data buffer storage part carries out data buffer storage only using a FC module section as object.Dma controller can be located
The data of two FC modules are managed, ensure that processing speed, improve message transmission rate, and each FC modules have exclusive data
Part is cached, data will not be obscured, and ensure that data transfer accuracy rate.The PCI-E buses are 4 BITBUS networks, the PCI-E buses
It is connected by two GTP with the PCI-E EP.In this way, this Communication Card is i.e. real in the case of excessive bus resource is not take up
The high-speed transfer of existing data.
The course of work of this Communication Card is as follows：
Data transmission procedure
1st, Communication Card is initialized, according to the speed and hair that are provided with based on fiber channel protocol of configuration chip
Delivery is put；
2nd, terminal will give PCI-E EP by PCI-E buses with sending data transfer；
3rd, the above-mentioned transmission data of the dma controller aid in treatment, and the transmission data are handled immediately on register
Storage state, FC passed to by Interface Controller and user interface after the transmission data are handled by Tx signals buffer module
The MAC of module carries out signal transacting, then by link control module by this handle after in data transfer to FC buses, so as to complete
Into the transmission of data.
DRP data reception process
1st, Communication Card is initialized, and the speed based on optical-fibre communications agreement is provided with connecing according to configuration chip
Receive configuration；
2nd, FC modules receive the serial data from FC buses, and by link control module and MAC processing after by its
Data buffer section is passed to, the data pass to dma controller after the processing of Rx signals buffer module, the dma controller
The signal is kept in register according to instant situation or is transferred to PCI-E EP, PCI-E EP are by GTP by data transfer
To PCI-E buses, the effect of data receiver is completed.
The transmitting procedure of whole data is aided in using dma controller and PCI-E EP in the present invention, solved
Between FC buses and PCI-E buses data conversion not in time the shortcomings that, ensure data it is complete in the case of, substantially increase biography
Defeated speed.Transmission rate for that can support highest 4.25Gbps, maximum distance reach 15km fiber optic protocols passage, lifting
Its data transmission bauds 15% between terminal.
Described above is only the preferred embodiment of the present invention, it is noted that for the ordinary skill people of the art
For member, under the premise without departing from the principles of the invention, some improvements and modifications can also be made, these improvements and modifications also should
It is considered as protection scope of the present invention.
Claims (5)
- A kind of 1. FC-AE-ASM communication cards based on PCI-E interface, it is characterised in that including fpga chip, DDR2 modules, Power management module, optical transceiver module, programmable clock and configuration chip；The storage control signal I/O of the storage control signal input/output terminal connection DDR2 modules of fpga chip；FPGA The transmission data input output end of chip and the data output input of optical transceiver module connect, fpga chip and PCI-E buses Interface connects；The input of the power management module is connected with the PCI-E EBIs；The clock input of the fpga chip Also it is connected with programmable clock；The fpga chip is connected with the configuration chip；The input voltage of the power management module is 3.3V, and the power management module provided with voltage be respectively 1.0V, 1.2V, 1.8V and 2.5V at least four voltage outputs；The top-level module of the fpga chip includes FC module sections, data buffer storage part and PCI-E parts；The PCI-E parts include PCI-E EP, dma controller, register and high speed serialization transceiver GTP；The PCI-E EP is connected by the high speed serialization transceiver GTP with the PCI-E buses；The dma controller is connected with the register；The data buffer storage part includes FC channel interface control modules, and the FC channel interfaces control module connects with user interface Connect, the FC channel interfaces control module reads the information from the dma controller and by the information by Tx buffer modules The user interface is passed to, the FC channel interfaces control module is read from the user interface by rx buffering module Information simultaneously passes it to the dma controller；The FC module sections include MAC module, user interface, management interface, credit management module and link control module；Institute User interface, credit management module and the link control module is stated to be connected with the MAC module；The management interface and institute State register connection；The link control module is connected into FC buses by high speed serialization transceiver GTP.
- 2. the FC-AE-ASM communication cards according to claim 1 based on PCI-E interface, it is characterised in that each described Dma controller is connected with two FC module sections respectively by two data buffer units；Each data buffer storage part is only with one Individual FC module sections carry out data buffer storage as object.
- 3. the FC-AE-ASM communication cards according to claim 2 based on PCI-E interface, it is characterised in that the PCI- E buses are 4 BITBUS networks, and the PCI-E buses are connected by two high speed serialization transceiver GTP with the PCI-E EP.
- 4. the FC-AE-ASM communication cards according to claim 1 based on PCI-E interface, it is characterised in that the DDR2 The SDRAM chips of module, monolithic size are 512M, and data-bus width is 16, and two panels uses after synthesizing 32 position datawires, should Chip is the MT47H128M16HG-3 of Micron companies.
- 5. the FC-AE-ASM communication cards according to claim 1 based on PCI-E interface, it is characterised in that the FPGA Chip is also associated with reset circuit；The reset circuit includes resistance R1, resistance R2, reset button switch K, electric capacity C1, two poles Pipe VD and the reseting terminal that is connected with the reseting interface of fpga chip；The negative pole of the diode VD and the resistance R1 one end are connected with power supply positive pole；The resistance R1's is another End, diode VD positive pole, resistance R2 one end and electric capacity C1 positive pole are connected with the reseting terminal；The resistance R2's The other end is connected with reset button switch K one end；The other end of the reset button switch K and electric capacity C1 negative pole connect Ground.
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| CN105490819B (en) * | 2015-12-09 | 2019-01-01 | 中国航空工业集团公司西安航空计算技术研究所 | A kind of networking long-distance intelligent interface |
| CN106992830B (en) * | 2017-04-05 | 2018-07-27 | 中国科学院空间应用工程与技术中心 | A kind of clock synchronizing method in FC-AE-1553 networks |
| CN111078626B (en) * | 2019-12-04 | 2024-05-10 | 北京航天福道高技术股份有限公司 | High-speed communication sub-mother board for big data transmission and use method thereof |
| CN112231257A (en) * | 2020-10-29 | 2021-01-15 | 中国航空工业集团公司洛阳电光设备研究所 | Plug-and-play interface of airborne photoelectric product |
| CN113676253A (en) * | 2021-09-18 | 2021-11-19 | 天津津航计算技术研究所 | FlexRay bus optical fiber communication module based on FPGA |
| CN114006811B (en) * | 2021-10-29 | 2023-04-28 | 西安微电子技术研究所 | CPCI gigabit Ethernet board with strong real-time performance and data communication method |
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