CN106992830B - A kind of clock synchronizing method in FC-AE-1553 networks - Google Patents
A kind of clock synchronizing method in FC-AE-1553 networks Download PDFInfo
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- CN106992830B CN106992830B CN201710218254.4A CN201710218254A CN106992830B CN 106992830 B CN106992830 B CN 106992830B CN 201710218254 A CN201710218254 A CN 201710218254A CN 106992830 B CN106992830 B CN 106992830B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
Abstract
The present invention relates to the clock synchronizing methods in a kind of 1553 networks of FC AE, including step：The master clock receiving time information of 1553 networks of FC AE, the clock that master clock is completed according to temporal information synchronize, and the master clock synchronized through oversampling clock is denoted as BMC；Other nodes of 1553 network internals of FC AE are synchronized according to BMC, based on time synchronization frame into row clock.Above-mentioned clock synchronization includes Frequency Synchronization and time synchronization, realizes the estimation and correction to itself frequency deviation by Frequency Synchronization, passes through the compensation of time synchronization implementation delay time.Clock synchronization mode in 1553 networks of FC AE further comprises the method for synchronization, boundary clock/transparent clock interchanger method of synchronization and transparent clock exchange manner step by step.It solves in the prior art that timing tracking accuracy is low by the design of clock synchronization mode in 1553 networks of FC AE, needs to be laid with specialised hardware equipment, lead to the problem that input cost is high, can meet the when same demand of most of a new generation's load.
Description
Technical field
The present invention relates in FC-AE-1553 network communication technology fields more particularly to a kind of FC-AE-1553 networks when
Clock synchronous method.
Background technology
Modern communication networks include mainly two class demand of Frequency Synchronization and time synchronization for synchronous demand.Frequency is same
Step, also referred to as clock synchronize, and refer to the particular kind of relationship for keeping certain stringent in the frequency or phase between signal, corresponding
Significant instant occur with same Mean Speed, run with identical rate with maintaining equipment all in communication network.Clock
After synchronous (Frequency Synchronization), phase/time of two clocks is still different.Time synchronization is also known as Phase synchronization, passes through
Two network nodes of time synchronization, frequency is identical, and time/phase is also identical.
Fibre Channel technologies are by high bandwidth, low latency, highly reliable feature, the at home and abroad application of aerospace field
It is more and more extensive.FC-AE has issued the agreement of 5 kinds of Aviation electronics such as FC-AE-1553, FC-AE-ASM, FC-AE-RDMA
Standard, wherein FC-AE-1553 at home and abroad have extensive application with FC-AE-ASM agreements.Currently, FC-AE is in FC-FS agreements
There are two types of the time synchronizing methods of specification publication, and one is Time Synchronization Mechanisms that is unidirectional, relying on FC bottom primitive；In addition
One is according to ELS frame modes successively synchronous step by step.FC-AE all assumes that transmission delay not in both Time Synchronization Mechanisms
Important, for the synchronization accuracy between adjacent network node in microsecond rank, and with the increase of network level, synchronization accuracy can be further
Deteriorate.Above-mentioned time synchronizing method cannot meet the requirements the application demand for having split-second precision in FC networks, urgently solve at present
FC network time synchronizations application demand certainly is within submicrosecond grade or even 100ns.
In conventional telecommunications net field, the standards such as GSM/WCDMA/Wimax FDD, since uplink and downlink access is according to different frequencies
Band distinguishes, therefore requires nothing more than and can reach corresponding Frequency Synchronization index, should not seeking time synchronize, the usual time is same
Precision is walked in 100ms ranks, provincial backbone network delay has also reached 50ms.TD-SCDMA/CDMA2000/Wimax TDD/
The standards such as TD-LTE rely on the timeslice in network and divide progress uplink and downlink communication, it is desirable that have Frequency Synchronization and Microsecond grade is other
Time synchronization, each base station in telecommunication network carry out the mode of time synchronization dependent on GPS module solution.But GPS module
Difficult to install, installation cost and maintenance cost are high, and feeder line is laid with difficulty, especially for indoor FC networks, each node
A GPS module is loaded, and synchronization accuracy only has us ranks, when this is that FC networks are all unacceptable from cost and in precision
Between synchronization scheme.
In Ethernet field, existing Internet time protocol mainly uses NTP (Network Time
Protocol) and it simplifies version Simple Network Time Protocol SNTP (SimpleNetwork Time Protocol).NTP is by U.S.
The David L Mills professors of Delaware university of state proposed in 1985, in network needed that one or more ntp servers are arranged
Network time synchronization is handled, carries out time synchronization since NTP relies on application layer software, therefore timing tracking accuracy is about 1
~50ms.IEEE1588 agreements are specific to the accurate clock synchronization protocol of the Industrial Ethernet such as Digital reference service proposition,
It is very suitable for the application requirement of Industrial Ethernet in substation, is subject to the synchronization accuracy that hardware auxiliary can reach s grades of μ,
The core concept of 1588 agreements be in network most accurate clock (master clock) synchronized in a manner of based on packet switch it is all other
The shortcomings that clock (from clock), 1588 agreements avoid Network Time Protocol, timestamp is beaten in physical layer, avoids message and send and locate
The uncertainty of reason.
FC-AE-1553 is as a kind of time triggered agreement of command response formula, and with its high speed, highly reliable, support is true in real time
Qualitative transfer behavior can build deterministic network, be suitable for aerospace instruction control, data management, loading device data biography
Defeated etc., application is more and more extensive, and the demand to time synchronization is also higher and higher.FC-AE-1553 networks and telecommunication network/ether
The composition of network is far from each other, a kind of high-precision time synchronization protocol is used in FC networks, and do not influence FC networks simultaneously
Data transmission, for the present invention key component.
In the prior art, by recommending two kinds of time synchronizing methods in the FC-FS agreements of FC-AE publications.
The first is the time synchronization of primitive (Primitive) layer, since primitive is only limitted to the two neighboring node of FC networks
Between transmit, therefore primitive time synchronizing method cannot pass through FC interchangers, can only successively carry out time synchronization step by step.
The primitive method of synchronization is not corrected the frequency at the ends Client, time synchronization error with network size increase and
Become larger, while the frequency difference of each node work clock is influenced very greatly on time synchronization path in by network；In controlled FC-AE-
In 1553 networks, it is also that can not put up with that bottom, which executes the stringent time synchronization period,.
It is for second ELS frame synchronization modes, the claim frame (CSR ELS) that the application layer sending time of client synchronizes, when
Sending time more new frame (CSU ELS) after clock sync server receives, time synchronization may be selected to beat timestamp in physical layer, through FC
Network layer is forwarded to client.Compared to the primitive method of synchronization, the time synchronization request of ELS frame synchronization modes is sent out by client
It rises.
Client can carry out local Frequency Synchronization and time synchronization according to the CSU ELS frames continuously received.This method exists
When network size increases, the network pressure of time synchronization server end can be aggravated.The transmission that the ELS methods of synchronization have ignored network is prolonged
When and each node processing delay, can be accumulated using the method for synchronization step by step successively, synchronous error in FC Fabric, FC
The synchronization accuracy that network reaches is still in ms ranks.
For the deficiency of time synchronization in the prior art, the present invention provides a kind of clock side of synchronization of FC-AE-1553 networks
Method, solution timing tracking accuracy is low, needs to be laid with specialised hardware equipment, leads to the problem that input cost is high.
Invention content
In view of above-mentioned analysis, the present invention is intended to provide the clock synchronizing method in a kind of FC-AE-1553 networks, to
It solves that existing timing tracking accuracy is low, hardware device is needed to lead to problem of high cost.
The purpose of the present invention is mainly achieved through the following technical solutions：
The clock synchronizing method in a kind of FC-AE-1553 networks is provided, is included the following steps：
The master clock receiving time information of step S1.FC-AE-1553 networks, according to temporal information complete master clock when
Clock synchronizes, and the master clock synchronized through oversampling clock is denoted as BMC；
Other nodes of step S2.FC-AE-1553 network internals according to BMC, based on time synchronization frame it is same into row clock
Step.
Wherein, the temporal information that master clock receives derives from the GPS signal of GPS receiver module output.
Above-mentioned steps S1 synchronous with the clock in S2 includes Frequency Synchronization and time synchronization；Frequency Synchronization is realized to itself frequency
Inclined estimation and correction；The compensation of time synchronization implementation delay time.
The FC-AE-1553 networks include master clock, boundary clock, transparent clock, ordinary clock this 4 kinds of network models,
Wherein, network controller/network terminal corresponds to master clock or ordinary clock, when the network switch corresponds to transparent clock or boundary
Clock；
Master clock is NC or NT, by receiving time information, is synchronized into row clock to itself；
Boundary clock is a kind of interchanger in FC-AE-1553 networks, and the Single port of interchanger is used as from port, receives
The temporal information that master clock is sent is completed to synchronize the clock of interchanger itself, other port conducts of boundary clock interchanger
Master port synchronizes the equipment being connected into row clock；
Transparent clock is a kind of interchanger in FC-AE-1553 networks, and the Single port of interchanger receives time synchronization frame
Afterwards, it is forwarded by another port, and residence Time Calculation of the time synchronization frame in interchanger is come out, it is same to be filled in the time
In step-frame；
Ordinary clock is the slave clock node in FC-AE-1553 networks, and ordinary clock is by sending and receiving time synchronization
Frame synchronizes itself into row clock, and output time information.
Being synchronized into row clock in FC-AE-1553 networks is carried out based on time synchronization frame, and the time synchronization frame includes
Following format：
In the front end of the general frame head of FC-FS frames, setting mark is time synchronization frame for identifying the frame；
Data field includes effective time tag mark, TC number, time tag and TC times in FC-FS frames；
Together whether the level of master clock comprising currently transmitted time frame, present clock in effective time tag identifier
In step, the number of contained time tag；
Present frame is recorded in TC number have passed through several transparent clock altogether；
The time of transmission and the arrival of time synchronization frame is recorded in time tag；
Time synchronization frame residence time in transparent clock is recorded in the TC times.
For above-mentioned time synchronization frame, using the processing mode preferentially sent.
Optionally, in step s 2, the clock of other nodes of FC-AE-1553 network internals is synchronized using the side of synchronization step by step
Formula, the method for synchronization step by step are：Using BMC as master clock, the adjacent node of BMC is used as from clock, by master clock to from when
Clock is synchronized into row clock；It is further used as master clock from clock by synchronous, using adjacent node as from clock, by master clock
To being synchronized from clock into row clock, synchronized step by step by this method, until all nodes in FC-AE-1553 networks are complete
It is synchronized at clock.
Include following communication process using the clock synchronization of the method for synchronization step by step：
Sync frames are first sent by master clock to from clock, Sync frames include the time t1 when frame leaves master clock；
After clock receives Sync frames, the time t2 that record t1 and Sync frames reach, and Delay_Req frames are sent immediately
To master clock, from clock log Delay_Req frame time departures t3；
After master clock receives Delay_Req frames, Delay_Req frame arrival time t4 are recorded, and by sending Delay_
Resp frames are sent to t4 from clock, by from clock log t4；
Wherein, Sync frames, Delay_Req frames, Delay_Resp frames are time synchronization frame.
Under the method for synchronization step by step, from the Frequency Synchronization of clock be by it is adjacent twice send Sync frame periods into
Row timing, and local offset estimation is carried out with two t1 time differences for including in two Sync frames by local timing time difference,
Multiple offset estimations are subjected to Kalman filtering or smothing filtering, obtain bias estimation amount, and correction of frequency deviates.
Under the method for synchronization step by step, it is from the time synchronization of clock：In the threshold value that time synchronization is arranged from clock end；
When master clock to from the time difference of clock be more than or equal to threshold value, then from clock direct compensation Offset values；
When master clock to from the time difference of clock be less than threshold value when, using Offset/T as number of frequency steps in a cycle
It is superimposed upon in the time of T on original frequency counting；
Wherein, Offset=((t4-t3)-(t2-t1))/2, T is the synchronizing cycle of master-salve clock.
Optionally, in step S2, the clocks of other nodes of FC-AE-1553 network internals is synchronized using boundary clock/transparent
The clock interchanger method of synchronization, network controller/network terminal under this mode in FC-AE-1553 networks in addition to BMC are
Ordinary clock, the network switch is as transparent clock and boundary clock；
Using BMC as master clock, the interchanger adjacent with BMC as from clock, need traversing switch to be attached
Interchanger is also used as from clock；
By master clock to being synchronized from clock into row clock, it is further used as master clock from clock by synchronous, to connection
The network terminal into row clock synchronize；
Wherein, during master clock from clock into row clock to synchronizing, the interchanger that is crossed as transparent clock,
As from the interchanger of clock be boundary clock.
Optionally, in step s 2, the clock of other nodes of FC-AE-1553 network internals is synchronized is handed over using transparent clock
It changes planes mode.Network controller/network terminal under this mode in FC-AE-1553 networks in addition to BMC is ordinary clock,
The network switch is transparent clock；Using BMC as master clock, remaining network controller/network terminal as from clock, when main
The time synchronization frame of clock passes through the forwarding of the network switch, is sent to from clock, realizes master clock to being synchronized from the clock of clock.
Communication under the boundary clock/transparent clock interchanger method of synchronization and the transparent clock exchange manner
Process is：
Sync frames are first sent by master clock to from clock, Sync frames include time t1 when Sync frames leave master clock；
After clock receives Sync frames, the time t2 that record t1 and Sync frames reach, and Delay_Req frames are sent immediately
To master clock, from clock log Delay_Req frame time departures t3；
After master clock receives Delay_Req frames, Delay_Req frame arrival time t4 are recorded, and by sending Delay_
Resp frames are sent to t4 from clock, by from clock log t4；
Wherein, Sync frames, Delay_Req frames, Delay_Resp frames are time synchronization frame；
When interchanger is as transparent clock, it is same that residence time of the time synchronization frame inside transparent clock is recorded in the time
In step-frame, △ TC are denoted as by the transparent clock institute increased time.
Under the boundary clock/transparent clock interchanger method of synchronization and the transparent clock exchange manner,
Frequency Synchronization not comprising transparent clock is：By carrying out timing to the adjacent Sync frame periods that send twice, and lead to
It crosses local timing time difference and carries out local offset estimation with two t1 time differences for including in two Sync frames, multiple frequency deviations are estimated
Meter carries out Kalman filtering or smothing filtering, obtains bias estimation amount, and correction of frequency deviates；
Including the Frequency Synchronization of transparent clock is：By carrying out timing to the adjacent Sync frame periods that send twice, and pass through
Local timing time difference carries out local offset estimation with two t1 time differences for including in two Sync frames, wherein local zone time
Remove the △ TC in transmission process in difference；Multiple offset estimations are subjected to Kalman filtering or smothing filtering again, offset is obtained and estimates
Metering, and correction of frequency deviates.
Under the boundary clock/transparent clock interchanger method of synchronization and the transparent clock exchange manner, the time
Synchronizing is：In the threshold value that time synchronization is arranged from clock end；When master clock to from the time difference of clock be more than or equal to threshold value, then from
Clock direct compensation Offset values；When master clock to from the time difference of clock be less than threshold value when, using Offset/T as frequency steps
Input is superimposed upon within the time of a cycle T on original frequency counting.
Wherein, Offset=((t4-t3)-(t2-t1))/2 in the time synchronization without transparent clock；
Offset=((t4-t3- △ TC_Delay)-(t2-t1- △ TC_Sync)) in time synchronization containing transparent clock/
2；
Wherein, when sending Sync frames, increase time of the time synchronization frame in transparent clock is denoted as △ TC_Sync；
When sending Delay_Req frames, increase time of the time synchronization frame in transparent clock is denoted as △ TC_Delay；
T is the synchronizing cycle of master-salve clock.
The present invention has the beneficial effect that：
Clock synchronizing method provided by the invention can be based on high speed fibre network and realize that high-precision clock synchronizes, be not required to
Special hardware is wanted, hardware input can be reduced, moreover it is possible to obtain higher timing tracking accuracy.
Other features and advantages of the present invention will illustrate in the following description, also, partial become from specification
It obtains it is clear that understand through the implementation of the invention.The purpose of the present invention and other advantages can be by the explanations write
Specifically noted structure is realized and is obtained in book, claims and attached drawing.
Description of the drawings
Attached drawing is only used for showing the purpose of specific embodiment, and is not considered as limitation of the present invention, in entire attached drawing
In, identical reference mark indicates identical component.
Fig. 1 is FC-AE-1553 network time synchronization topological models；
Fig. 2 is FC-AE-1553 exchange networks synchronistic model step by step；
Fig. 3 are FC master-salve clock node synchronistic models；
Fig. 4 is FC main and subordinate node synchronizing process schematic diagrames；
Fig. 5 is the schematic diagram of FC physical layers transmission/receiving time stamp；
Fig. 6 is the processing mode schematic diagram of FC physical layers transmission/receiving time synchronization frame preferentially sent；
Fig. 7 be FC from clock node to the processing method of time synchronization, in the schematic diagram that local zone time is fast；
Fig. 8 be FC from clock node to the processing method of time synchronization, in the schematic diagram that local zone time is partially slow；
Fig. 9 is the time synchronizing method schematic diagram containing boundary clock/transparent clock interchanger；
Figure 10 is the schematic diagram of the FC principals and subordinates end time synchronizing method containing transparent clock；
Physical layer transceiver time synchronization frame mode when Figure 11 is transparent clock；
Figure 12 is the schematic diagram of the format of FC-FS frames；
Figure 13 is the data format schematic diagram in data field in FC-FS frames；
Figure 14 is the form schematic diagram of time tag in data field；
Figure 15 is the schematic diagram of the Time Synchronization Network scheduling strategy based on the FC-AE-1553 fixed cycles
Specific implementation mode
Specifically describing the preferred embodiment of the present invention below in conjunction with the accompanying drawings, wherein attached drawing constitutes the application part, and
It is used to illustrate the principle of the present invention together with embodiments of the present invention.
The invention discloses the clock synchronizing methods in a kind of FC-AE-1553 networks.In FC-AE-1553 networks, exist
Master clock (time synchronization server, Master Clock), boundary clock (BC), transparent clock (TC) and ordinary clock (OC) this
Four kinds of network models.Wherein, the corresponding master clocks of NC/NT (network controller/network terminal) or ordinary clock, the network switch pair
Answer transparent clock or boundary clock.
The master clock (time synchronization server, Master Clock) refers to the terminal node for receiving GPS signal, is passed through
1PPS the and ToD signals for receiving GPS are corrected own frequency and time, reach and are consistent with GPS time, error does not surpass
Cross 40ns (when 4.25G, error is no more than 20ns).
The boundary clock (BC) refers to a kind of interchanger in FC-AE-1553 networks, some port conduct of the interchanger
From port, the temporal information that master clock is sent is can receive, completes Frequency Synchronization and time synchronization to interchanger.Boundary clock is handed over
Other ports changed planes can be used as master port and carry out time synchronization to the equipment being connected.
The transparent clock (TC) refers to a kind of interchanger in FC-AE-1553 networks, and interchanger is received from the A of port
It to after time synchronization frame, is forwarded as requested by port B, while the residence time counts in interchanger by time synchronization frame
It calculates, is filled in time synchronization frame.
Refer to the slave clock node in FC-AE-1553 networks when ordinary clock (OC), it can be by sending and receiving
Time synchronization frame carries out Frequency Synchronization and time synchronization to itself, and exports 1PPS+ToD signals, supplies the NT (network terminal)
Residing equipment uses.
A specific embodiment according to the present invention, the clock disclosed in a kind of specific FC-AE-1553 networks synchronize
Method carries out the explanation of clock synchronizing method by taking switch type FC-AE-1553 networks as an example.
Switch type FC-AE-1553 networks include multiple FC interchangers, the equal access switch of all-network terminal node,
It is the topological model of interconnection between interchanger.
In above-mentioned switch type FC-AE-1553 networks, (Network Terminal, FC-AE-1553 network are whole by a NT
End) only receive a NC (Network Controller, FC-AE-1553 network controller) control.It may be present in network more
A NC, each NC control one group of NT in local.Master clock can be NC, can also be NT.
In order to improve the reliability of network, the switch type FC-AE-1553 networks in embodiment use dual network redundancy side
Formula, network structure are as shown in Figure 1.
FC-AE-1553 network structures according to figure 1, (active/standby) controls of interchanger G1-SW that NC1 passes through Group1
NT1-NT10, NC2 are by (active/standby) the control NT11-NT30 of interchanger G2-SW1/2 of Group2, the friendship that NC3 passes through Group3
The SW of (active/standby) the control NT31-NT50 of the G3-SW1/2 that changes planes, all main parts form a switched transport network, all backups
SW forms a switched transport network.NT where master clock is named as NT-BMC (Best Master Clock), it is assumed that the NT
In Group3 networks.NT-BMC receives 1PPS the and ToD signals of GPS receiver output and GPS carries out time synchronization.FC-
After AE-1553 network time synchronizations, the exportable 1PPS+ToD signals of all NC, NT are used for residing equipment.
Based on above-mentioned switch type FC-AE-1553 network structures, a kind of clock synchronizing method is present embodiments provided, specifically
Include the following steps：
The master clock receiving time information of S1.FC-AE-1553 networks, the clock that master clock is completed according to temporal information are same
Step, the master clock synchronized through oversampling clock are denoted as BMC.
Temporal information in embodiment derives from the GPS signal of GPS receiver module output.
Specifically, GPS receiver module (GPS receiver) output time information is forwarded to FC-AE-1553 network master clocks institute
NT or NC.Master clock is set as NT by the present embodiment, then the NT where master clock is denoted as NT-BMC (Best Master
Clock), abbreviation BMC in the present embodiment.The temporal information includes 1PPS (pulse per second (PPS)) and ToD (Time of Data) information.
Wherein, 1PPS is pps pulse per second signal, and ToD is the $ GPZDA frames that GPS receiver module is sent by RS232 serial ports.
Master clock receives the temporal information of GPS receiver module output, and the time synchronization with GPS is completed according to temporal information.
Synchronizing process is divided into two steps, and the first step is Frequency Synchronization, and second step is time synchronization.
S11. Frequency Synchronization
Estimation and the correction work to itself frequency deviation can be completed using 1PPS by BMC.Concrete scheme is：It detects on primary
It rises and local timer is reset and immediately begun to timing after, when next rising edge, local timing T is recorded, and
Timer is reset and immediately begins to timing again；Local timing time is compared with 1 second, you can obtains the offset of local clock
Amount.
S12. time synchronization
It is not less than n times when the 1PPS pulse per second (PPS)s that BMC is received can stablize reception, and the frequency deviation of BMC has been corrected to
After acceptable frequency deviation region (after Frequency Synchronization is stablized), time synchronization is carried out to NT-BMC.
According to the time format of the BMC $ GPZDA frames received, the temporal information in BMC is converted into FC-AE-1553 nets
Time synchronization frame (FC-FS frames) information used in network, and compensate delay time therein, you can the deadline synchronizes.
Other nodes of step S2.FC-AE-1553 network internals according to BMC, based on time synchronization frame it is same into row clock
Step.
It is carried out from master clock to switch type FC-AE-1553 networks specifically, time synchronization frame (FC-FS frames) can be based on
The time synchronization of interior other-end and interchanger.
3 kinds of modes may be used in the method for synchronization of entire exchange network：The method of synchronization, boundary clock/transparent clock step by step
The interchanger method of synchronization, transparent clock exchange manner.
A. the method for synchronization step by step, as shown in Figure 2.
The method of synchronization is using BMC as master clock step by step, and the adjacent node of BMC is used as from clock, by master clock to from when
Clock is synchronized into row clock；It is further used as master clock from clock by synchronous, using adjacent node as from clock, by master clock
To being synchronized from clock into row clock, synchronized step by step by this method, until all nodes in FC-AE-1553 networks are complete
It is synchronized at clock.
In the present embodiment, upper level clock will be received, the interchanger of time synchronization is carried out as boundary clock (BC) to subordinate.
Boundary clock both can carry out time synchronization to connected node NC/NT, also can carry out time synchronization to the interchanger connected.
Since the FC-AE-1553 network sizes are smaller, all-network node proceeds by clock step by step from BMC and synchronizes.
Each node in FC-AE-1553 networks is divided into main and subordinate node, and clock is all made of host node to being synchronized from node when synchronizing
Mode.Time synchronization between adjacent node is regarded as master clock to the synchronizing process from clock, simplified model Fig. 3.
Specifically, under the method for synchronization step by step, the time is same between further devising adjacent FC (optical-fibre channel) main and subordinate node
Step process, physical layer transmission/receiving time stamp mode, step by step under the method for synchronization FC from the Frequency Synchronization mode of clock node, by
Time synchronizing methods of the FC from clock node under the grade method of synchronization.
1. communication process such as Fig. 4 between adjacent FC (optical-fibre channel) main and subordinate node in time synchronization.
In FC main and subordinate node time synchronization process, Sync frames are first sent by master clock to from clock, after clock end receives
Delay_Req frames are sent immediately to master clock, master clock, which receives, retransmits Delay_Resp frames after Delay_Req frames to from clock
End.Since transmitting terminal is to stamp timestamp when physical layer is sent, label obtains receiving terminal immediately after extracting frame from physical layer
The time of frame, therefore do not need the Follow frames defined in IEEE1588.
The time synchronization detailed process at the principal and subordinate end in this programme is as follows, and wherein the ends Master represent host node, the ends Slave
It represents from node：
(1) ends Master hair Sync messages record message arrival time t2, Sync message to Slave, Slave after receiving
In time t1 when leaving Master including it simultaneously；
(2) ends Slave hair Delay_Req messages record the time departure t3 of Delay_Req messages to Master, Slave,
The ends Master record its arrival time t4；
(3) t4 is issued Slave by Master by Delay_Resp messages, and Delay_Req messages are known at the ends Slave at this time
Sending time t3 and receiving time t4 and Sync message sending time t1 and receiving time t2.
2. physical layer transmission/receiving time stabs mode
Host node is as transmitting terminal, when sending the time synchronizations frames such as Sync frames, Delay_Req frames, Delay_Resp frames,
Specifically timestamp is stamped when physical layer is sent.It is as shown in Figure 5 in physical layer transmission/receiving time stamp mode.With NT-BMC
Physical layer transmission/receiving time synchronization frame for, the present invention further devise physical layer realize time synchronization frame it is excellent
The processing mode first sent, as shown in Figure 6.
MUX modules are added in transmitting terminal, MUX modules are unified receiving time synchronization frame and others FC frames, set in MUX
Priority, if time synchronization frame highest priority.When having time synchronization frame and other FC frames reach simultaneously, preferential sending time
Synchronization frame；When only one of which frame, sent according to the sequence first sent out is arrived first；In other FC frame transmission process, MUX is received
When to time synchronization frame, currently transmitted sequence, preferential sending time synchronization frame can be interrupted.Framing sending module is when that can send
Between synchronization frame when, with the transmission of time synchronization frame, at the time of sending the local zone time in frame, just from local zone time count module
Time value is obtained in block, is sent immediately.It ensure that the time value of FC time synchronization frames is local last look.
Receiving terminal be opposite process, after DeMUX modules receive FC frames, first in frame head near preceding frame identification into
Row judges, after preferentially identifying time synchronization frame, is forwarded immediately to receipts frame parsing module and is transmitted to other for other FC frames
Resume module.Parsing module demarcates the time received at once, and obtains time value from local zone time counting module,
Record the time value of current received frame.
By designing MUX and DeMUX modules in transmitting terminal and receiving terminal respectively, realize in FC agreements to time synchronization
The preferential transmission and preferential receipt processing of frame, ensure that the high-precision of the time value processing of time synchronization frame.Utmostly ensure
The symmetry of link.
3. Frequency Synchronization modes of the FC from clock node under the method for synchronization step by step
The adjacent main and subordinate node synchronizing processes of FC periodically carry out, and the synchronizing cycle of main side is that (△ T are current FC frames to T ± △ T
It when sending, cannot interrupt, the sending time synchronization frame immediately only after present frame is sent, in the 4G networks of FC, △ T
Maximum value is about 5us, is much smaller than synchronizing cycle T), due to Sync frame periodicity sendings, the ends Slave can be according to the completion pair of Sync frames
The Frequency Synchronization of this node.
Frequency-synchronization process namely frequency correcting process to local zone time counting module, frequency compensation are mainly used for determining
Itself crystal oscillator frequency offset at the ends Slave is simultaneously corrected, and scheme is by being carried out to the adjacent Sync frame periods that send twice
Timing, and local offset estimation is carried out with two T1 time differences for including in two Sync by local timing time difference, it will be more
A offset estimation carries out Kalman filtering or smothing filtering, obtains more correct bias estimation amount, and correct the frequency shift (FS).
4. synchronizing time synchronizing methods of the lower FC from clock node step by step
Since the fiber lengths between the adjacent node of FC networks are identical, and since we are in the hair of physical layer progress time frame
Mode is sent and receives, the time frame processing delay page at both ends is identical, therefore the path delay of transmitting terminal and receiving terminal and processing are delayed
Delay is identical, it is assumed that main side is then-Offset to the time difference of main side from end, then has to being Offset from the time difference at end：
T2-t1=Delay-Offset
T4-t3=Delay+Offset
It can obtain：
Offset=((t4-t3)-(t2-t1))/2
Delay=((t4-t3)+(t2-t1))/2
In the present solution, in the threshold value that time synchronization is arranged from node side, after the time difference is more than the threshold value directly from end
Offset values are compensated, when being less than the threshold value, original is superimposed upon within the time of a cycle T using Offset/T as number of frequency steps
On the frequency counting come, then the readjustment backward from the end time will not be caused.Wherein, T is the synchronizing cycle of master-salve clock.
It is a kind of optimized treatment method using above-mentioned time synchronizing method, optimization processing effect is as shown in Figure 7, Figure 8.It is protecting
Under the precision for demonstrate,proving time synchronization, while ensureing time synchronization process seamlessly transitting in one cycle, will not cause the time
Recession suddenly shifts to an earlier date, and influences use of the user to material time.
B. boundary clock/transparent clock interchanger method of synchronization, as shown in Figure 9.
Boundary clock/transparent clock interchanger method of synchronization refers to the existing boundary clock function of interchanger in network,
Has transparent clock function, the interior network terminal in addition to BMC of FC-AE-1553 networks is ordinary clock.
Using BMC as master clock, the interchanger adjacent with BMC as from clock, need traversing switch to be attached
Interchanger is also used as from clock；
By master clock to being synchronized from clock into row clock, it is further used as master clock from clock by synchronous, to connection
The network terminal into row clock synchronize；
Wherein, during master clock from clock into row clock to synchronizing, the interchanger that is crossed as transparent clock,
As from the interchanger of clock be boundary clock.
Specifically：Upper level clock can across grade to lower level clock into row clock synchronize, NT-BMC can directly with it is indirect
The interchanger of contact is synchronized into row clock；Between cascade interchanger, it can also be synchronized into row clock.The synchronization that clock synchronizes
Mode includes but is not limited to the mode of Fig. 9.
When traversing switch synchronizes, the interchanger being crossed is used as transparent clock (TC).In Fig. 1, G2-SW2
Time synchronization can also be carried out to G3-SW1, specifically using certain port of some interchanger as transparent clock (TC) or boundary
Clock (BC), the required synchronization accuracies of NT/NC depending on being connected.TC can improve the timing tracking accuracy of system.
1. the communication process between master-salve clock is：
Sync frames are first sent by master clock to from clock, Sync frames include the time t1 when frame leaves master clock；
After clock receives Sync frames, record t1 and the frame reach time t2, and immediately send Delay_Req frames to
Master clock, from clock log Delay_Req frame time departures t3；
After master clock receives Delay_Req frames, Delay_Req frame arrival time t4 are recorded, and by sending Delay_
Resp frames are sent to t4 from clock, by from clock log t4；
Above-mentioned Sync frames, Delay_Req frames, Delay_Resp frames are time synchronization frame；
Wherein, when interchanger is as transparent clock, when transparent clock records the stop of time synchronization frame inside it
Between, and recorded in time synchronization frame.Specifically by the way of stamping timestamp on time synchronization frame.
The timestamp that the more TC of synchronizing process between master-salve clock are loaded, the then Frequency Synchronization between master-salve clock and time
The method of synchronization is still Sync frames in Fig. 4, Delay_Req frames, the transmission process of Delay_Resp frames, by TC letters all in the process
Cloud is turned to, the increased time stab of TC institutes is △ TC, then time synchronization schematic diagram is Figure 10.
2. physical layer transmission/receiving time under boundary clock/transparent clock interchanger method of synchronization stabs mode
The physical layer transmission at main and subordinate node end/receiving time stamp mode is identical as the mode under the method for synchronization step by step.Saturating
Under bright clock, transmission/receiving time stamp is still carried out in physical layer, and mode can be simplified.Specifically, local zone time timing exists
It starts counting up after receiving synchronization frame, is reset after which is sent.It is obtained originally transparent from local zone time timing before sending
Residence time in clock, as shown in figure 11.
Preferably, transparent clock of the invention supports multiple time synchronization frames to enter the transparent clock.
3. FC under boundary clock/transparent clock interchanger method of synchronization is from the Frequency Synchronization mode of node
Specifically include the Frequency Synchronization not comprising transparent clock and the Frequency Synchronization comprising transparent clock.
Frequency Synchronization not comprising transparent clock is：By carrying out timing to the adjacent Sync frame periods that send twice, and lead to
It crosses local timing time difference and carries out local offset estimation with two t1 time differences for including in two Sync frames, multiple frequency deviations are estimated
Meter carries out Kalman filtering or smothing filtering, obtains bias estimation amount, and correction of frequency deviates；
Including the Frequency Synchronization of transparent clock is：By carrying out timing to the adjacent Sync frame periods that send twice, and pass through
Local timing time difference carries out local offset estimation with two T1 time differences for including in two Sync, should in local zone time difference
Consider △ TC twice, removes influence of the transparent clock to frequency deviation；Again by multiple offset estimations progress Kalman filtering or smoothly
Filtering, obtains more correct bias estimation amount, and correct the frequency shift (FS).
4. FC under boundary clock/transparent clock interchanger method of synchronization is from the time synchronizing method of node
Since the fiber lengths between the adjacent node of FC networks are identical, therefore the path delay Delay of transmitting terminal and receiving terminal
It is identical, it is assumed that main side is then-Offset to the time difference of main side from end to being Offset from the time difference at end.Send Sync frames
When, it is △ TC_Sync that TC gets to the timestamp in frame altogether, and when sending Delay_Req frames, it is △ that TC gets to the timestamp in frame altogether
TC_Delay, T are the synchronizing cycles of master-salve clock.
Then have：
T2-t1- △ TC_Sync=Delay-Offset
T4-t3- △ TC_Delay=Delay+Offset
It can obtain：
Offset=((t4-t3- △ TC_Delay)-(t2-t1- △ TC_Sync))/2
Delay=((t4-t3- △ TC_Delay)+(t2-t1- △ TC_Sync))/2
In the threshold value from end setting time synchronization, from end direct compensation Offset values after the time difference being more than or equal to threshold value；
When the time difference being less than threshold value, original frequency is superimposed upon within the time of a cycle T using Offset/T as number of frequency steps
On rate counts, then the readjustment backward from the end time will not be caused.Certifiable time synchronization process in one cycle smoothed
It crosses, the unexpected recession of time will not be caused or shifts to an earlier date, influence the use of user.
C. the transparent clock interchanger method of synchronization
The transparent clock interchanger method of synchronization is to regard the SW (interchanger) in all-network as transparent clock, removes BMC
NC/NT in addition is ordinary clock.NT/NC carries out time synchronization by transparent clock interchanger and NT-BMC.Specifically by BMC
Be used as from clock as master clock, NT/NC, the time synchronization frame of master clock passes through the forwarding of the network switch, be sent to from when
Clock realizes master clock to being synchronized from the clock of clock.The synchronizing process of master-salve clock under which, Frequency Synchronization and time are same
Situation under the equal and boundary clock of step process/transparent clock interchanger method of synchronization is identical.
Preferably, in above-mentioned method for synchronizing time, Clock Synchronization Procedure of the invention is based on time synchronization frame.The time
Synchronization frame designs on the basis of general FC-FS frames (format such as Figure 12), and time synchronization frame is typically compliant with the lattice of FC-FS frames
Formula.
The present invention devises the format of the time synchronization frame used in clock synchronizing method：
Time synchronization frame meets the basic format of FC-FS frames, but is arranged in the front end of general frame head and identifies, for marking
It is time synchronization frame to know the frame.Specifically set R_CTL to 26 and 27, it is fast for receiving terminal to be distinguished with other frames
Speed identifies time synchronization frame, reduces processing delay.
The format design of data field such as Figure 13 in FC-FS frames.Data field includes effective time tag mark, TC (when transparent
Clock) number, time tag and TC times,
Wherein, the level of the master clock comprising currently transmitted time frame (determines whether most in effective time tag identifier
Good master clock), whether present clock synchronized upper and the contents such as the number of time tag that is included.
Present frame is recorded in TC number have passed through several transparent clock altogether.
The time of transmission and the arrival of time synchronization frame, particular content such as Figure 14, when including altogether 4 times are recorded in time tag
Between be worth (t1~t4).Each timestamp length is 12 bytes, and 0 divides 0 when indicating 1 day 0 January of 1970 Christian era when timestamp is complete zero
Second.
Time synchronization frame residence time in transparent clock, the time that specifically transparent clock is beaten are recorded in the TC times
Stamp is in the TC times.
Preferably, FC-AE-1553 networks are command/response formula network, and all data transmissions of the network are carried out by NC
Scheduling.When NC periodicity sending data, corresponding arrangement of time is reserved to time synchronization frame within the period, to avoid network congestion
Influence to time synchronization, can be improved timing tracking accuracy.Time Synchronization Network scheduling based on the FC-AE-1553 fixed cycles
Strategy such as Figure 15, within each period before other business of execution FC-AE-1553 networks, the time synchronization for reserving t0~t1 is special
With the business hours, to processing time synchronization frame.
Preferably, the alternative solution of network level is using BMC as the time synchronization server in network, by each NC/NT/
SW is sent to the mode of time synchronization request.
Method for synchronizing time proposed by the present invention can be used for but be not limited to FC-AE-1553 networks, FC network single-protocols
(only FC-AE-1553 protocol nodes or only FC-AE-ASM nodes) or multi-protocols converged network can be used.
In conclusion an embodiment of the present invention provides a kind of high precision clock sides of synchronization based on FC-AE-1553 networks
The precise synchronization based on FC-AE-1553 may be implemented in method, while not influencing the normal work of FC-AE-1553.Entirely
Time Synchronization Network entrance uses 1PPS+ToD modes, and output is also using the object synchronized using 1PPS+ToD modes, unified time
Interface is managed, it is easy to use, compare and manage.Clock synchronizing method using the present invention can be based on high speed fibre network and realize hundred
The time synchronization of nanosecond order does not need special hardware not only, can reduce input, reduce cost, moreover it is possible to when obtaining higher
Between synchronization accuracy, the when same demand of most of of new generation load can be met, it is cost-effective.
It will be understood by those skilled in the art that realizing all or part of flow of above-described embodiment method, meter can be passed through
Calculation machine program is completed to instruct relevant hardware, and the program can be stored in computer readable storage medium.Wherein, institute
It is disk, CD, read-only memory or random access memory etc. to state computer readable storage medium.
The foregoing is only a preferred embodiment of the present invention, but scope of protection of the present invention is not limited thereto,
Any one skilled in the art in the technical scope disclosed by the present invention, the change or replacement that can be readily occurred in,
It should be covered by the protection scope of the present invention.
Claims (12)
1. the clock synchronizing method in a kind of FC-AE-1553 networks, which is characterized in that including step：
The master clock receiving time information of step S1.FC-AE-1553 networks, the clock that master clock is completed according to temporal information are same
Step, the master clock synchronized through oversampling clock are denoted as BMC；
Other nodes of step S2.FC-AE-1553 network internals are synchronized according to BMC, based on time synchronization frame into row clock；
The temporal information that the master clock receives derives from the GPS signal of GPS receiver module output；
Step S1 synchronous with the clock in S2 includes Frequency Synchronization and time synchronization；Frequency Synchronization realizes the estimation to itself frequency deviation
And correction；The compensation of time synchronization implementation delay time；
The FC-AE-1553 networks include master clock, boundary clock, transparent clock, ordinary clock this 4 kinds of network models,
In, network controller/network terminal corresponds to master clock or ordinary clock, and the network switch corresponds to transparent clock or boundary clock；
Master clock is NC or NT, by receiving time information, is synchronized into row clock to itself；
Boundary clock is a kind of interchanger in FC-AE-1553 networks, and the Single port of interchanger is used as from port, when receiving main
The temporal information that clock is sent is completed to synchronize the clock of interchanger itself, other ports of boundary clock interchanger are as main side
Mouth synchronizes the equipment being connected into row clock；
Transparent clock is a kind of interchanger in FC-AE-1553 networks, after the Single port of interchanger receives time synchronization frame,
It is forwarded by another port, and residence Time Calculation of the time synchronization frame in interchanger is come out, be filled in the time synchronization
In frame；
Ordinary clock is the slave clock node in FC-AE-1553 networks, ordinary clock by sending and receiving time synchronization frame,
Itself is synchronized into row clock, and output time information.
2. the clock synchronizing method in FC-AE-1553 networks according to claim 1, which is characterized in that the time is same
Step-frame includes following format：
In the front end of the general frame head of FC-FS frames, setting mark is time synchronization frame for identifying FC-FS frames；
Data field includes effective time tag mark, TC number, time tag and TC times in FC-FS frames；
Whether the level of the master clock comprising currently transmitted time frame, present clock are synchronized in effective time tag identifier
The number of upper, contained time tag；
Present frame is recorded in TC number have passed through several transparent clock altogether；
The time of transmission and the arrival of time synchronization frame is recorded in time tag；
Time synchronization frame residence time in transparent clock is recorded in the TC times.
3. the clock synchronizing method in FC-AE-1553 networks according to claim 2, which is characterized in that when being directed to described
Between synchronization frame, using the processing mode preferentially sent.
4. the clock synchronizing method in FC-AE-1553 networks according to claim 3, which is characterized in that in step S2,
The clock of other nodes of FC-AE-1553 network internals is synchronized using the method for synchronization, the method for synchronization step by step are step by step：By BMC
As master clock, the adjacent node of BMC is used as from clock, by master clock to being synchronized from clock into row clock；By it is synchronous from
Clock is further used as master clock, using adjacent node as from clock, by master clock to being synchronized from clock into row clock, with this side
Formula is synchronized step by step, until all nodes in FC-AE-1553 networks complete clock synchronization.
5. the clock synchronizing method in FC-AE-1553 networks according to claim 4, which is characterized in that use is same step by step
The clock synchronization of step mode includes following communication process：
Sync frames are first sent by master clock to from clock, Sync frames include time t1 when Sync frames leave master clock；
After clock receives Sync frames, the time t2 that record t1 and Sync frames reach, and Delay_Req frames are sent immediately to master
Clock, from clock log Delay_Req frame time departures t3；
After master clock receives Delay_Req frames, Delay_Req frame arrival time t4 are recorded, and by sending Delay_Resp frames
T4 is sent to from clock, by from clock log t4；
Wherein, Sync frames, Delay_Req frames, Delay_Resp frames are time synchronization frame.
6. the clock synchronizing method in FC-AE-1553 networks according to claim 5, which is characterized in that described same step by step
It is by carrying out timing to the adjacent Sync frame periods that send twice, and passing through local meter from the Frequency Synchronization of clock under step mode
When the time difference and two Sync frames in include two t1 time differences carry out local offset estimation, multiple offset estimations are blocked
Kalman Filtering or smothing filtering obtain bias estimation amount, and correction of frequency deviates.
7. the clock synchronizing method in FC-AE-1553 networks according to claim 5, which is characterized in that described same step by step
It is in the threshold value that time synchronization is arranged from clock end from the time synchronization of clock under step mode；
When master clock to from the time difference of clock be more than or equal to threshold value, then from clock direct compensation Offset values；
When master clock to from the time difference of clock be less than threshold value when, using Offset/T as number of frequency steps a cycle T's
It is superimposed upon in time on original frequency counting；
Wherein, Offset=((t4-t3)-(t2-t1))/2, T is the synchronizing cycle of master-salve clock.
8. the clock synchronizing method in FC-AE-1553 networks according to claim 3, which is characterized in that in step S2,
The clock of other nodes of FC-AE-1553 network internals, which synchronizes, uses boundary clock/transparent clock interchanger method of synchronization, this
Network controller/network terminal under mode in FC-AE-1553 networks in addition to BMC is ordinary clock, network switch conduct
Transparent clock and boundary clock；
Using BMC as master clock, the interchanger adjacent with BMC as from clock, the exchange for needing traversing switch to be attached
Machine is also used as from clock；
By master clock to being synchronized from clock into row clock, it is further used as master clock from clock by synchronous, to the net of connection
Network terminal is synchronized into row clock；
Wherein, during master clock from clock into row clock to synchronizing, the interchanger that is crossed as transparent clock, as
It is boundary clock from the interchanger of clock.
9. the clock synchronizing method in FC-AE-1553 networks according to claim 3, which is characterized in that in step S2,
The clock of other nodes of FC-AE-1553 network internals, which synchronizes, uses transparent clock exchange manner, FC-AE- under this mode
Network controller/network terminal in 1553 networks in addition to BMC is ordinary clock, and the network switch is transparent clock；It will
BMC is used as master clock, remaining network controller/network terminal from clock, and the time synchronization frame of master clock is handed over by network
The forwarding changed planes is sent to from clock, realizes master clock to being synchronized from the clock of clock.
10. the clock synchronizing method in FC-AE-1553 networks according to claim 8 or claim 9, which is characterized in that the side
Communication process under boundary's clock/transparent clock interchanger method of synchronization and the transparent clock exchange manner is：By master clock
Sync frames are first sent to from clock, Sync frames include time t1 when Sync frames leave master clock；
After clock receives Sync frames, the time t2 that record t1 and Sync frames reach, and Delay_Req frames are sent immediately to master
Clock, from clock log Delay_Req frame time departures t3；
After master clock receives Delay_Req frames, Delay_Req frame arrival time t4 are recorded, and by sending Delay_Resp frames
T4 is sent to from clock, by from clock log t4；
Wherein, Sync frames, Delay_Req frames, Delay_Resp frames are time synchronization frame；
When interchanger is as transparent clock, residence time of the time synchronization frame inside transparent clock is recorded in time synchronization frame
In, △ TC are denoted as by the transparent clock institute increased time.
11. the clock synchronizing method in FC-AE-1553 networks according to claim 10, which is characterized in that on the side
Under boundary's clock/transparent clock interchanger method of synchronization and the transparent clock exchange manner,
Frequency Synchronization not comprising transparent clock is：By carrying out timing to the adjacent Sync frame periods that send twice, and pass through this
Two t1 time differences for including in ground timing time difference and two Sync frames carry out local offset estimation, by multiple offset estimations into
Row Kalman filtering or smothing filtering obtain bias estimation amount, and correction of frequency deviates；
Including the Frequency Synchronization of transparent clock is：By carrying out timing to the adjacent Sync frame periods that send twice, and pass through local
Timing time difference carries out local offset estimation with two t1 time differences for including in two Sync frames, wherein in local zone time difference
Remove the △ TC in transmission process；Multiple offset estimations are subjected to Kalman filtering or smothing filtering again, obtain bias estimation amount,
And correction of frequency deviates.
12. the clock synchronizing method in FC-AE-1553 networks according to claim 10, which is characterized in that on the side
Under boundary's clock/transparent clock interchanger method of synchronization and the transparent clock exchange manner, time synchronization is from clock end
The threshold value of time synchronization is set；
When master clock to from the time difference of clock be more than or equal to threshold value, then from clock direct compensation Offset values；
When master clock to from the time difference of clock be less than threshold value when, using Offset/T as number of frequency steps a cycle T's
It is superimposed upon in time on original frequency counting；
Wherein, Offset=((t4-t3)-(t2-t1))/2 in the time synchronization without transparent clock；
Offset=((t4-t3- △ TC_Delay)-(t2-t1- △ TC_Sync))/2 in time synchronization containing transparent clock；
Wherein, when sending Sync frames, increase time of the time synchronization frame in transparent clock is denoted as △ TC_Sync；
When sending Delay_Req frames, increase time of the time synchronization frame in transparent clock is denoted as △ TC_Delay；
T is the synchronizing cycle of master-salve clock.
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| CN107800529B (en) * | 2017-11-07 | 2020-10-20 | 北京飞利信电子技术有限公司 | Clock frequency synchronization method of network node |
| CN108183762B (en) * | 2017-12-28 | 2019-07-26 | 天津芯海创科技有限公司 | The method for synchronizing time of RapidIO network system and RapidIO network system |
| CN108471337B (en) * | 2018-04-04 | 2019-07-26 | 电子科技大学 | A method of realizing time synchronization in FC network |
| CN108809845B (en) * | 2018-05-28 | 2019-06-25 | 北京航空航天大学 | A kind of data transmission stream amount control method based on FC |
| CN111092713B (en) * | 2018-10-23 | 2022-08-12 | 智邦科技股份有限公司 | Clock synchronization device and clock synchronization method |
| CN110035020B (en) * | 2018-12-29 | 2021-04-06 | 清华大学 | Scheduling and synchronizing strategy for time-triggered Ethernet switch |
| CN110166159A (en) * | 2019-05-24 | 2019-08-23 | 南方电网科学研究院有限责任公司 | One kind being based on GPRS network clock synchronization, electric energy meter time synchronization method and system |
| CN111092687B (en) * | 2019-12-10 | 2021-06-25 | 西安云维智联科技有限公司 | Calendar clock synchronization system of FC switching network system |
| CN111953442A (en) * | 2020-06-28 | 2020-11-17 | 成都星辰瀑布通信技术有限公司 | Quick high-precision time synchronization system |
| CN114520703B (en) * | 2020-11-19 | 2023-12-29 | 中国科学院沈阳自动化研究所 | Clock drift compensation method and circuit for time synchronization between industrial network devices |
| CN113078978A (en) * | 2021-03-26 | 2021-07-06 | 杭州加速科技有限公司 | Synchronization method, system and test method for remote multi-ATE semiconductor test equipment |
| CN112995808B (en) * | 2021-04-21 | 2021-10-22 | 北京国科天迅科技有限公司 | FC-AE-1553 network optimization method and system |
| CN113259039A (en) * | 2021-04-30 | 2021-08-13 | 北京国科天迅科技有限公司 | Time synchronization method and device, computer equipment and storage medium |
| CN113938196B (en) * | 2021-11-18 | 2023-03-10 | 北京宇航系统工程研究所 | Bus network communication method based on FC-AE-1553 optical fiber bus architecture |
| CN115589272B (en) * | 2022-10-13 | 2024-04-09 | 中国船舶重工集团公司第七一九研究所 | FC-AE-based high-precision pulse synchronization system |
| CN116684024A (en) * | 2023-05-31 | 2023-09-01 | 中国科学院空间应用工程与技术中心 | FC-AE-1553 boundary clock port state configuration method and system |
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