CN111092687B - Calendar clock synchronization system of FC switching network system - Google Patents
Calendar clock synchronization system of FC switching network system Download PDFInfo
- Publication number
- CN111092687B CN111092687B CN201911257359.6A CN201911257359A CN111092687B CN 111092687 B CN111092687 B CN 111092687B CN 201911257359 A CN201911257359 A CN 201911257359A CN 111092687 B CN111092687 B CN 111092687B
- Authority
- CN
- China
- Prior art keywords
- time
- layer module
- fic
- clock
- driver layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
- H04J3/0644—External master-clock
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q11/00—Selecting arrangements for multiplex systems
- H04Q11/0001—Selecting arrangements for multiplex systems using optical switching
- H04Q11/0005—Switch and router aspects
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q11/00—Selecting arrangements for multiplex systems
- H04Q11/0001—Selecting arrangements for multiplex systems using optical switching
- H04Q11/0005—Switch and router aspects
- H04Q2011/0037—Operation
- H04Q2011/0045—Synchronisation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Electric Clocks (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
The invention discloses a calendar clock synchronization system of an FC switching network system, which realizes high-precision synchronization of calendar time of a whole system and provides global consistent time service for each node in the network; a management mechanism of the main and standby time servers is provided, and the time service reliability of the system is improved; the clock synchronization system of the FC-FS protocol is fully used for realizing high-precision clock synchronization; the characteristics of low time delay, high certainty, broadcast support and the like of the FC switching network are used for realizing 'year, month and day' broadcast transmission; a management mechanism of the main and standby time servers is provided on the basis of a clock synchronization system of an FC-FS protocol so as to improve the reliability of system time service.
Description
Technical Field
The invention relates to a calendar clock synchronization system of a network system, in particular to a calendar clock synchronization system of an FC switching network system.
Background
The fiber switching network constructed based on the FC-SW/FC-FS protocol is a star network with a Fiber Channel (FC) switch as a center, and may be a single switch or a logical switch formed by cascading multiple switches, fig. 1 shows a star network structure in which N-port FC switches are cascaded to form a logical switch, where a Fiber Interface Card (FIC) is a node connected to a switch port through a fiber, and each node has a globally unique id (portid) and is bound to the connected switch port.
The existing clock synchronization system based on clock synchronization primitive sets one FIC in an FC switching network as a clock server and other FICs as clock clients, and the server synchronizes clock values to the clients through an FC switch (which may be a cascade of a plurality of switches). The clock server maintains a system clock source and periodically sends a clock synchronization primitive to the FC switch, the synchronization primitive comprises a 42-bit clock value, after the FC switch receives the clock synchronization primitive, a new clock value is formed by adding time delay in a switching network on the basis of the clock value in the synchronization primitive, the new clock value is updated into the clock synchronization primitive and is forwarded to the client, and the client receives a real clock synchronization value and updates the real clock synchronization value to the local, so that clock synchronization is realized, and the precision of hundreds of nanoseconds can be achieved.
The existing clock synchronization system can meet the requirements of most distributed systems constructed based on FC switching networks on clock synchronization functions, but how to map 42-bit clock synchronization values into system calendar time (year, month, day, minute, second, millisecond, microsecond and hundred nanosecond) is not defined, and the requirements of applications on system calendar clock synchronization cannot be met.
Disclosure of Invention
The invention aims to provide a calendar clock synchronization system of an FC (fiber channel) switching network system, which is used for solving the problems of low system calendar clock synchronization precision and low system time service reliability of a clock synchronization system in the prior art.
In order to realize the task, the invention adopts the following technical scheme:
a FC exchange network system calendar clock synchronization system comprises a main time server, a standby time server, an FC switch and a plurality of time clients;
the main time server is used for splitting the calendar time of the system to obtain first time and second time, wherein the first time comprises time, minutes, seconds, milliseconds, microseconds and hundred nanoseconds, and the second time comprises years, months and days;
the main time server is also used for updating the first time converted into a clock count value by taking 100 nanoseconds as a step length to obtain a clock count value T1；
The FC switch is used for counting the clock count value T1Performing transmission delay synchronization processing to obtain a clock count value T3；
The standby time server and the time client are used for counting the clock count value T3Updating by taking 100 nanoseconds as step length to obtain a clock count value T4；
The standby time server and the time client are also used for counting value T according to clock4And a second time, obtaining the synchronized system calendar time.
Further, the master time server comprises a first upper application module, a first driver layer module and a first FIC driver layer module;
the first upper application module is used for sending the system calendar time to the first driving layer module after obtaining the system calendar time;
the first driving layer module is used for splitting the system calendar time to obtain a first time and a second time;
the first driving layer module is also used for converting the first time into a clock count value T0Then sending the clock count value T to a first FIC driving layer module0In units of hundred nanoseconds;
the first driving layer module is further configured to encapsulate the second time into an ASM frame to obtain an ASM frame, and the first driving layer module sends the ASM frame to the standby time server and the time client;
the first FIC driver layer module is configured to count the clock count value T0Registering and updating by taking 100 nanoseconds as step length to obtain a clock count value T1；
The first FIC driver layer module is further configured to periodically send a clock synchronization primitive to the FC switch, where the clock synchronization primitive includes a clock count value T1。
Further, the FC switch is used for counting the clock count value T1And a transmission delay T2Adding to obtain a clock count value T3(ii) a Wherein said transmissionTime delay T2Delay for line and switch transmissions in said system;
the FC switch is also used for including a clock count value T3The clock synchronization primitive is sent to the standby time server and the time client.
Further, the standby time server comprises a second upper application module, a second driver layer module and a second FIC driver layer module;
the time client comprises a third upper application module, a third driving layer module and a third FIC driving layer module;
the second FIC driving layer module and the third FIC driving layer module are used for counting the clock value T3Registering and updating by taking 100 nanoseconds as step length to obtain a clock count value T4；
The second driving layer module and the third driving layer module are used for storing the ASM frame;
the second upper layer application module and the third upper layer application module are used for according to the ASM frame and the clock count value T4And obtaining the synchronized system calendar time.
Further, the first driving layer module is further configured to convert the first time into a clock count value T0Then, the clock count value T is obtained by adopting the formula I0：
T0(((((h × 60) + min) × 60+ s) × 1000+ ms) × 1000+ μm) × 10+ ns formula I
Where h denotes a number of hours, min denotes a number of minutes, s denotes a number of seconds, ms denotes a number of milliseconds, μm denotes a number of microseconds, and ns denotes a number of hundred nanoseconds.
Further, the second upper layer application module and the third upper layer application module are used for counting the value T according to the ASM frame and the clock count value4The method for obtaining the synchronized system calendar time specifically comprises the following steps:
obtaining a Second time from the ASM frame, converting the Second time into a total number of seconds between 0 minutes and 0 seconds at 1 month, 1 day, 0 hours in 1970, and obtaining a first number of seconds Second1, which has a unit of s;
obtaining the clock count value T4Second to obtain a Second number of seconds Second2, in units of s;
adding the first Second1 and the Second2 to obtain a third Second3 with the unit of s;
obtaining the clock count value T4The number of hundreds of nanoseconds is in units of hundreds of nanoseconds;
adding the third Second number Second3 to 1970, 1, 0 and 0 seconds to obtain a synchronized system calendar first time, wherein the synchronized system calendar first time comprises year, month, day, hour, minute and Second;
converting the hundred nanoseconds into millisecond, microsecond and hundred nanosecond forms to obtain the synchronized second time of the system calendar;
and obtaining the synchronized system calendar time, wherein the synchronized system calendar time comprises a synchronized system calendar first time and a synchronized system calendar second time.
Further, the second driver layer module is configured to determine whether two ASM frames are simultaneously registered, and if so, generate a master time server collision notification and send the master time server collision notification to the second upper application module;
and the third driving layer module is used for judging whether two ASM frames are simultaneously registered or not, and if so, generating a main time server collision notification and then sending the main time server collision notification to the third upper layer application module.
Further, the second FIC driver layer module and/or the second driver layer module are further configured to determine whether the master time server fails, and if so, the second FIC driver layer module does not receive the clock synchronization primitive sent by the first FIC driver layer module any more and the second driver layer module does not receive the ASM frame sent by the first driver layer module any more, and then the second driver layer module sends the ASM frame to the third driver layer module, and the second FIC driver layer module sends the clock synchronization primitive to the third FIC driver layer module;
the third FIC driver layer module and/or the third driver layer module is further configured to determine whether the master time server fails, and if the master time server fails, the third FIC driver layer module does not receive a clock synchronization primitive sent by the first FIC driver layer module any more and the third driver layer module does not receive an ASM frame sent by the first driver layer module any more;
the third driver layer module is further configured to determine whether an ASM frame sent by the second driver layer module is received, and if so, the third driver layer module is further configured to send a master time server fault notification to the third upper application module, and the second driver layer module is further configured to send a master time server fault notification to the second upper application module.
Further, the second FIC driver layer module and the second driver layer module are further configured to determine whether the master time server fails, and specifically include:
the second FIC driving layer module judges whether N continuous clock synchronization primitives are not received and/or whether the second driving layer module receives N continuous ASM frames, if so, whether the main time server fails, wherein N is an integer greater than or equal to 3;
the third FIC driver layer module and the third driver layer module are further configured to determine whether the master time server fails, and specifically include:
the third FIC driver layer module determines whether N consecutive clock synchronization primitives are not received and/or whether the third driver layer module N consecutive ASM frames are not received, and if so, whether the master time server fails.
Further, the first FIC driver layer module counts the clock value T0When registering, the clock count value T is used0Storing the real-time clock register with the effective bit width of 42 bits;
the second FIC driving layer module and the third FIC driving layer module are used for counting the clock value T3When registering, the clock count value T is used3And storing the real-time clock register with the effective bit width of 42 bits.
Compared with the prior art, the invention has the following technical effects:
1. according to the calendar clock synchronization system of the FC switching network system, the system calendar time containing hundred nanoseconds is designed, the clock synchronization system of the FC-FS protocol is fully utilized to realize high-precision clock synchronization, global consistent time service is provided for each node in the network, the precision is improved to hundred nanoseconds on the basis of the traditional calendar time, the time step takes 100 nanoseconds as a unit, and the precision of clock conversion is improved;
2. the FC switching network system calendar clock synchronization system provided by the invention is provided with the standby time server, the main time server is used as a calendar time source at the initial stage of the system, and the standby time server replaces the system as the calendar time source after a fault occurs, so that the reliability of the system time service is improved;
3. the calendar clock synchronization system of the FC switching network system realizes the broadcasting transmission of 'year, month and day' by the characteristics of low time delay, high certainty, broadcasting support and the like of the FC switching network;
4. the calendar clock synchronization system of the FC switching network system provided by the invention provides a management mechanism of the main time server and the standby time server on the basis of the clock synchronization system of the FC-FS protocol, thereby improving the reliability of system time service.
Drawings
FIG. 1 is a schematic diagram of a star network topology centered around FC switches;
fig. 2 is a schematic diagram of a system calendar clock synchronization process provided by the present invention.
Detailed Description
The present invention will be described in detail below with reference to the accompanying drawings and examples. So that those skilled in the art can better understand the present invention. It is to be expressly noted that in the following description, a detailed description of known functions and designs will be omitted when it may obscure the subject matter of the present invention.
The following definitions or conceptual connotations relating to the present invention are provided for illustration:
a time server: an application running on an FC device in the FC network, which is in the role of time distribution, may set an initial system calendar time as the starting point of time for all devices in the FC network, and other devices receive clock synchronization and calibration for the device.
The time client side: the FC device in the FC network, which plays a role of time receiving and synchronizing, receives the system calendar time from the time server, synchronizes and calibrates the system calendar time, and an application program running on the FC device can acquire the system calendar time.
And (3) system calendar time: time information consisting of year, month, day, hour, minute, second, millisecond, microsecond, and hundred nanoseconds is detailed in table 1.
ASM frame: the FC-AE-ASM standard defines a data frame for transmitting year, month and day data.
Clock synchronization primitive: the FC-FS standard defines a clock synchronization mechanism that includes clock synchronization primitives.
FIC: fiber Interface cards (Fibre Interface Card).
A real-time clock register: a register implemented by FIC for storing a first time "hour, minute, second, millisecond, microsecond, hundred nanosecond" as the first portion.
Example (b):
the embodiment discloses a calendar clock synchronization system of an FC switching network system, which comprises a main time server, a standby time server, an FC switch and a plurality of time clients;
the main time server is used for splitting the calendar time of the system to obtain first time and second time, wherein the first time comprises time, minutes, seconds, milliseconds, microseconds and hundred nanoseconds, and the second time comprises years, months and days;
the main time server is also used for updating the first time converted into a clock count value by taking 100 nanoseconds as a step length to obtain a clock count value T1；
The FC switch is used for counting the clock count value T1Performing transmission delay synchronization processing to obtain a clock count value T3；
The standby time server andand the time client is used for counting the clock count value T3Updating by taking 100 nanoseconds as step length to obtain a clock count value T4；
The standby time server and the time client are also used for counting value T according to clock4And a second time, obtaining the synchronized system calendar time.
The embodiment is different from the prior art in that a standby time server is arranged to ensure the stable operation of the system, and when the main time server fails, the standby time server can broadcast the time information, so that the time service reliability of the system is improved.
Optionally, the master time server includes a first upper application module, a first driver layer module, and a first FIC driver layer module;
the first upper application module is used for sending the system calendar time to the first driving layer module after obtaining the system calendar time;
the first driving layer module is used for splitting the calendar time of the system to obtain first time and second time, wherein the first time comprises time, minutes, seconds, milliseconds, microseconds and hundred nanoseconds, and the second time comprises years, months and days;
the first driving layer module is also used for converting the first time into a clock count value T0Then sending the data to a first FIC driving layer module, and counting the value T by a clock0In hundred nanoseconds;
the first driving layer module is further configured to encapsulate the second time into an ASM frame to obtain an ASM frame, and the first driving layer module sends the ASM frame to the second driving layer module and the third driving layer module;
the first FIC driver layer module is used for counting the clock count value T0Registering and updating in 100 ns unit to obtain clock count value T1；
The first FIC driver layer module is further configured to periodically send a clock synchronization primitive to the FC switch, where the clock synchronization primitive includes a clock count value T1；
Optionally, the FC switch is further configured to count the clock count value T1And a transmission delay T2Adding to obtain a clock count value T3(ii) a Wherein the transmission delay T2Delay for line and switch transmission in the system;
the FC switch is also used for including a clock count value T3The clock synchronization primitive is sent to the second FIC driving layer module and the third FIC driving layer module;
optionally, the standby time server includes a second upper application module, a second driver layer module, and a second FIC driver layer module;
the time client comprises a third upper application module, a third driving layer module and a third FIC driving layer module;
the second and third FIC driver layer modules count the clock value T3Registering and updating in 100 ns unit to obtain clock count value T4；
The second driving layer module and the third driving layer module are used for storing ASM frames;
the second upper layer application module and the third upper layer application module are used for counting value T according to ASM frame and clock4And obtaining the synchronized system calendar time.
In this embodiment, as shown in fig. 1, the time management roles in the entire system are unknown in the initial situation, and the upper layer Application (APP) calls the "time management role setting interface" to set the corresponding devices as the Master Time Server (MTS), the standby time server (BTS), or the Time Client (TC) according to the pre-planned time management roles.
The time management role setting interface is used for enabling an upper layer application to set corresponding equipment as a Main Time Server (MTS), a Backup Time Server (BTS) or a Time Client (TC) according to a pre-planned time management role. The time management role, once set, is not allowed to reset to other role values during system operation.
In this embodiment, the master time server first calls a "system calendar time issue interface" to obtain a system calendar time of the FC switching network by using the first upper layer application module (MTS _ APP), and sends the system calendar time to the first driver layer (MTS _ DRV);
the system calendar time issuing interface is used for enabling the MTS upper layer application to transmit the initial system calendar time to a driving layer of the MTS. Allowing for repeated settings during system operation.
The system calendar time acquisition interface is used for realizing acquisition of the current system calendar time by the MTS/BTS/TC upper layer application
When the first driver layer (MTS _ DRV) receives the system calendar time, it splits the system calendar time into two parts: the first part is the first time 'hour, minute, second, millisecond, microsecond, hundred nanosecond', the second part is the second time 'year, month, day', for example, the system calendar time is 2010, 1 month, 1 day 00: 011 second, 10 millisecond, 2 microsecond, 3 hundred nanosecond, then the first time is 0 hour, 1 minute, 1 second, 10 millisecond, 2 microsecond, 3 hundred nanosecond, and the second time is 2010, 1 month, 1 day;
in the embodiment, the calendar time structure of the system is shown in table 1, and the specific implementation can be defined by using a C language structure.
TABLE 1 calendar time structure schematic of system
At this time, the first driving layer module (MTS _ DRV) converts the first time into a clock count value in hundreds of nanoseconds, and optionally, the first driving layer module is further configured to convert the first time into the clock count value T0Then, the clock count value T is obtained by adopting the formula I0：
T0(((((h × 60) + min) × 60+ s) × 1000+ ms) × 1000+ μm) × 10+ ns formula I
Where h denotes a number of hours, min denotes a number of minutes, s denotes a number of seconds, ms denotes a number of milliseconds, μm denotes a number of microseconds, and ns denotes a number of hundred nanoseconds.
In the present embodiment, T is 1 minute, 1 second, 10 milliseconds, 2 microseconds, and 3 hundred nanoseconds when the first time is 00(((((0 × 60) +1) × 60+1) × 1000+10) × 1000+2) × 10+3 ═ 11083 hundred nanoseconds;
in the present embodiment, the first driving layer module (MTS _ D)RV) counting the clock value T0To the first FIC driver module (MTS _ FIC).
At this time, the first FIC driving module (MTS _ FIC) obtains the clock count value T0To count the clock value T0Registering, optionally, the first FIC driver layer module registers the clock count value T0When registering, the clock count value T is used0And storing the real-time clock register with the effective bit width of 42 bits.
After the register is completed, the first FIC driver module (MTS _ FIC) updates the real-time clock register in steps of 100 ns, that is, the clock count value T in the real-time clock calculator is updated every 100 ns0。
The first driving layer module (MTS _ DRV) encapsulates the second time into an ASM frame according to the FC-AE-ASM protocol while processing the first time, and then the first driving layer module (MTS _ DRV) obtains the ASM frame.
The first driver layer module (MTS _ DRV) transmits the ASM frame to the second driver layer module (BTS _ DRV) and the third driver layer module (TC _ DRV) in the form of a switch period broadcast.
Meanwhile, a clock synchronization system defined by a first FIC driver module (MTS _ FIC) FC-FS protocol starts to periodically send clock synchronization primitives, and stores the current clock count value T stored in a real-time clock register1Sent to the FC switch.
The FC switch receives a clock count value T sent by a first FIC driving module (MTS _ FIC) of the main time server1Then, count the value T at the clock1On the basis of the time delay T of the line and the exchange transmission2Obtaining a new clock count value T3Then count the clock value T3To the second FIC driver layer module of the standby time server (BTS _ FIC) and to the third FIC driver layer module of all time clients (TC _ FIC).
At this time, the clock count value T is received by both the second FIC driver layer module (BTS _ FIC) and the third FIC driver layer module (TC _ FIC)3Counting the clock by a value T3Registering, optionally, the clock count value is counted by the second FIC driver layer module and the third FIC driver layer moduleT3When registering, the clock count value T is used3And storing the real-time clock register with the effective bit width of 42 bits.
After the registration is completed, the second FIC driver layer module (BTS _ FIC) updates the real-time clock register of the standby time server in units of 100 nanoseconds; the third FIC driver layer module (TC _ FIC) updates the real-time clock register of the time client in units of 100 nanoseconds.
After the update is completed, the second FIC driver layer module (BTS _ FIC) and the third FIC driver layer module (TC _ FIC) each obtain a clock count value T4。
At the moment, the standby time server and the time client both obtain the clock count value T4And ASM frame, in which the clock count value T4The first time is saved and the ASM frame is saved with the second time.
The standby time server and the time client need to count value T according to the clock4And obtaining system calendar time by the ASM frame, optionally, the second upper layer application module and the third upper layer application module according to the ASM frame and the clock count value T4The method for obtaining the synchronized system calendar time specifically comprises the following steps:
obtaining a Second time from the ASM frame, converting the Second time into a total number of seconds between 0 minutes and 0 seconds at 1 month, 1 day, 0 hours in 1970, and obtaining a first number of seconds Second1, which has a unit of s;
obtaining the clock count value T4Second to obtain a Second number of seconds Second2, in units of s;
adding the first Second1 and the Second2 to obtain a third Second3 with the unit of s;
obtaining the clock count value T4The number of hundreds of nanoseconds is in units of hundreds of nanoseconds;
adding the third Second number Second3 to 1970, 1, 0 and 0 seconds to obtain a synchronized system calendar first time, wherein the synchronized system calendar first time comprises year, month, day, hour, minute and Second;
converting the hundred nanoseconds into millisecond, microsecond and hundred nanosecond forms to obtain the synchronized second time of the system calendar;
and obtaining the synchronized system calendar time, wherein the synchronized system calendar time comprises a synchronized system calendar first time and a synchronized system calendar second time.
In this embodiment, the second time is 1970, 1, 2 days, and the clock count value T is4Is 5 x 108+5 hundred nanoseconds; clock count value T4Including 5 x 108One hundred nanoseconds and 5 one hundred nanoseconds, of which 5 x 108Converting hundred nanoseconds into 50 seconds;
then the first number of seconds Second1 is 24 x 60 x 86400s, the Second number of seconds is 50s, and the hundred nanoseconds is 5 hundred nanoseconds;
therefore, the third Second number Second3 ═ 86450 s;
converting the third Second number Second3 ═ 86450s to 0 minutes 0 and 50 seconds on 1, 2, 1970; the hundred nanoseconds are converted to 0 milliseconds, 0 microseconds, 5 hundred nanoseconds, so the synchronized system calendar time is 0 minutes, 50 seconds, 0 milliseconds, 0 microseconds, 5 hundred nanoseconds at 1 month, 2 days, 0 hours in 1970.
Optionally, the second driver layer module is configured to determine whether two ASM frames are simultaneously registered, and if yes, generate a master time server collision notification and send the master time server collision notification to the second upper layer application module;
and the third driving layer module is used for judging whether two ASM frames are simultaneously registered or not, and if so, generating a main time server collision notification and then sending the main time server collision notification to the third upper layer application module.
If two or more than two Main Time Servers (MTS) are arranged in the system due to some improper reason and the ASM frame transmission of 'year, month and day' is started, the backup time server and the time client receive the ASM frames from different time source devices, the device driver layer reports 'main time server conflict notification' to the application layer, and the device driver layer analyzes and resolves the conflict notification and ensures that only one main time server exists in the system.
Therefore, the invention also provides a main time server conflict detection function, generates a main time server conflict notice, and the notice is reported to the second upper layer application module and/or the third upper layer application module of the standby time server and/or the time client by the second FIC driver layer module and/or the third FIC driver layer module, so that an application integrator can conveniently check and eliminate the main time server conflict phenomenon and reason.
Optionally, the second FIC driver layer module and/or the second driver layer module are further configured to determine whether the master time server fails, and if so, after the second FIC driver layer module no longer receives the clock synchronization primitive sent by the first FIC driver layer module and the second driver layer module no longer receives the ASM frame sent by the first driver layer module, the second driver layer module sends the ASM frame to the third driver layer module, and the second FIC driver layer module sends the clock synchronization primitive to the third FIC driver layer module;
the third FIC driver layer module and/or the third driver layer module is further configured to determine whether the master time server fails, and if the master time server fails, the third FIC driver layer module does not receive a clock synchronization primitive sent by the first FIC driver layer module any more and the third driver layer module does not receive an ASM frame sent by the first driver layer module any more;
optionally, the second FIC driver layer module and the second driver layer module are further configured to determine whether the master time server fails, and specifically include:
the second FIC driving layer module judges whether N continuous clock synchronization primitives are not received and/or whether the second driving layer module receives N continuous ASM frames, if yes, the main time server is in failure;
the third FIC driver layer module and the third driver layer module are further configured to determine whether the master time server fails, and specifically include:
the third FIC driver layer module determines whether N consecutive clock synchronization primitives are not received and/or whether the third driver layer module N consecutive ASM frames are not received, and if so, whether the master time server fails.
In this embodiment, in the system operation process, the standby time server and the time client both monitor the clock synchronization primitive and (or) "year, month and day" information of the MTS, and if the N primitives and (or) the N "year, month and day" information are not received (N is not less than 3), it is determined that the MTS is faulty, the BTS and the TC do not receive the clock synchronization primitive or "year, month and day" information which may be sent by the MTS any more in the following, and the BTS becomes a new time server to send the clock synchronization primitive and broadcast the "year, month and day" information.
The third driver layer module is further configured to determine whether an ASM frame sent by the second driver layer module is received, and if so, the third driver layer module is further configured to send a master time server fault notification to the third upper application module, and the second driver layer module is further configured to send a master time server fault notification to the second upper application module.
In this embodiment, after receiving the "year, month, and day" information sent by the second driver layer module (BTS _ DRV) of the standby time server, the third driver layer module (TC _ DRV) of the time client determines that the time server switching has occurred in the system, and the second driver layer module (BTS _ DRV) and the third driver layer module (TC _ DRV) respectively send a "main time server failure notification" to the second upper layer application module (BTS _ APP) and the third upper layer application module (TC _ APP), so that the application integrator can know and eliminate the time server failure.
The calendar clock synchronization system of the FC switching network system provided by the invention realizes high-precision synchronization of the calendar time of the whole system and provides global consistent time service for each node in the network; a management mechanism of the main and standby time servers is provided, the time service reliability of the system is improved, and high-precision clock synchronization is realized by fully utilizing a clock synchronization system of an FC-FS protocol; the characteristics of low time delay, high certainty, broadcast support and the like of the FC switching network are used for realizing 'year, month and day' broadcast transmission; a management mechanism of the main and standby time servers is provided on the basis of a clock synchronization system of an FC-FS protocol so as to improve the reliability of system time service.
Claims (10)
1. A calendar clock synchronization system of an FC switching network system is characterized by comprising a main time server, a standby time server, an FC switch and a plurality of time clients;
the main time server is used for splitting the calendar time of the system to obtain first time and second time, wherein the first time comprises time, minutes, seconds, milliseconds, microseconds and hundred nanoseconds, and the second time comprises years, months and days;
the main time server is also used for updating the first time converted into a clock count value by taking 100 nanoseconds as a step length to obtain a clock count value T1；
The FC switch is used for counting the clock count value T1Performing transmission delay synchronization processing to obtain a clock count value T3；
The standby time server and the time client are used for counting the clock count value T3Updating by taking 100 nanoseconds as step length to obtain a clock count value T4；
The standby time server and the time client are also used for counting value T according to clock4And a second time, obtaining the synchronized system calendar time.
2. The FC switching network system calendar clock synchronization system of claim 1, wherein the master time server comprises a first upper application module, a first driver layer module, and a first FIC driver layer module;
the first upper application module is used for sending the system calendar time to the first driving layer module after obtaining the system calendar time;
the first driving layer module is used for splitting the system calendar time to obtain a first time and a second time;
the first driving layer module is also used for converting the first time into a clock count value T0Then sending the clock count value T to a first FIC driving layer module0In units of hundred nanoseconds;
the first driving layer module is further configured to encapsulate the second time into an ASM frame to obtain an ASM frame, and the first driving layer module sends the ASM frame to the standby time server and the time client;
the first FIC driver layer module is configured to count the clock count value T0Registering and updating by taking 100 nanoseconds as step length to obtain a clock count value T1；
The first FIC driver layer module is further configured to periodically send a clock synchronization primitive to the FC switch, where the clock synchronization primitive includes a clock count value T1。
3. The FC switching network system calendar clock synchronization system of claim 2, wherein the FC switch is configured to count the clock count value T1And a transmission delay T2Adding to obtain a clock count value T3(ii) a Wherein said transmission delay T2Delay for line and switch transmissions in said system;
the FC switch is also used for including a clock count value T3The clock synchronization primitive is sent to the standby time server and the time client.
4. The FC switching network system calendar clock synchronization system of claim 3, wherein the standby time server comprises a second upper application module, a second driver layer module, and a second FIC driver layer module;
the time client comprises a third upper application module, a third driving layer module and a third FIC driving layer module;
the second FIC driving layer module and the third FIC driving layer module are used for counting the clock value T3Registering and updating by taking 100 nanoseconds as step length to obtain a clock count value T4；
The second driving layer module and the third driving layer module are used for storing the ASM frame;
the second upper layer application module and the third upper layer application module are used for according to the ASM frame and the clock count value T4Obtain synchronized systemAnd summarizing the calendar time.
5. The FC switching network system calendar clock synchronization system of claim 2, wherein the first driver layer module is further configured to convert the first time into a clock count value T0Then, the clock count value T is obtained by adopting the formula I0：
T0(((((h × 60) + min) × 60+ s) × 1000+ ms) × 1000+ μm) × 10+ ns formula I
Where h denotes a number of hours, min denotes a number of minutes, s denotes a number of seconds, ms denotes a number of milliseconds, μm denotes a number of microseconds, and ns denotes a number of hundred nanoseconds.
6. The FC switching network system calendar clock synchronization system of claim 4, wherein the second upper layer application module and the third upper layer application module are based on the ASM frame and the clock count value T4The method for obtaining the synchronized system calendar time specifically comprises the following steps:
obtaining a Second time from the ASM frame, converting the Second time into a total number of seconds between 0 minutes and 0 seconds at 1 month, 1 day, 0 hours in 1970, and obtaining a first number of seconds Second1, which has a unit of s;
obtaining the clock count value T4Second to obtain a Second number of seconds Second2, in units of s;
adding the first Second1 and the Second2 to obtain a third Second3 with the unit of s;
obtaining the clock count value T4The number of hundreds of nanoseconds is in units of hundreds of nanoseconds;
adding the third Second number Second3 to 1970, 1, 0 and 0 seconds to obtain a synchronized system calendar first time, wherein the synchronized system calendar first time comprises year, month, day, hour, minute and Second;
converting the hundred nanoseconds into millisecond, microsecond and hundred nanosecond forms to obtain the synchronized second time of the system calendar;
and obtaining the synchronized system calendar time, wherein the synchronized system calendar time comprises a synchronized system calendar first time and a synchronized system calendar second time.
7. The FC switching network system calendar clock synchronization system of claim 4, wherein the second driver layer module is configured to determine whether two ASM frames are simultaneously registered, and if so, generate a master time server collision notification and send the generated master time server collision notification to the second upper application module;
and the third driving layer module is used for judging whether two ASM frames are simultaneously registered or not, and if so, generating a main time server collision notification and then sending the main time server collision notification to the third upper layer application module.
8. The FC switching network system calendar clock synchronization system of claim 4, wherein the second FIC driver layer module and/or the second driver layer module is further configured to determine whether the master time server fails, and if so, the second FIC driver layer module does not receive the clock synchronization primitive sent by the first FIC driver layer module any more, and after the second driver layer module does not receive the ASM frame sent by the first driver layer module any more, the second driver layer module sends the ASM frame to the third driver layer module, and the second FIC driver layer module sends the clock synchronization primitive to the third FIC driver layer module;
the third FIC driver layer module and/or the third driver layer module is further configured to determine whether the master time server fails, and if the master time server fails, the third FIC driver layer module does not receive a clock synchronization primitive sent by the first FIC driver layer module any more and the third driver layer module does not receive an ASM frame sent by the first driver layer module any more;
the third driver layer module is further configured to determine whether an ASM frame sent by the second driver layer module is received, and if so, the third driver layer module is further configured to send a master time server fault notification to the third upper application module, and the second driver layer module is further configured to send a master time server fault notification to the second upper application module.
9. The FC switching network system calendar clock synchronization system of claim 4, wherein the second FIC driver layer module and the second driver layer module are further configured to determine whether the master time server fails, specifically comprising:
the second FIC driving layer module judges whether N continuous clock synchronization primitives are not received and/or whether the second driving layer module receives N continuous ASM frames, if so, whether the main time server fails, wherein N is an integer greater than or equal to 3;
the third FIC driver layer module and the third driver layer module are further configured to determine whether the master time server fails, and specifically include:
the third FIC driver layer module determines whether N consecutive clock synchronization primitives are not received and/or whether the third driver layer module N consecutive ASM frames are not received, and if so, whether the master time server fails.
10. The FC switching network system calendar clock synchronization system of claim 4, wherein the first FIC driver layer module is configured to count the clock count value T0When registering, the clock count value T is used0Storing the real-time clock register with the effective bit width of 42 bits;
the second FIC driving layer module and the third FIC driving layer module are used for counting the clock value T3When registering, the clock count value T is used3And storing the real-time clock register with the effective bit width of 42 bits.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911257359.6A CN111092687B (en) | 2019-12-10 | 2019-12-10 | Calendar clock synchronization system of FC switching network system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911257359.6A CN111092687B (en) | 2019-12-10 | 2019-12-10 | Calendar clock synchronization system of FC switching network system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111092687A CN111092687A (en) | 2020-05-01 |
| CN111092687B true CN111092687B (en) | 2021-06-25 |
Family
ID=70394945
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201911257359.6A Active CN111092687B (en) | 2019-12-10 | 2019-12-10 | Calendar clock synchronization system of FC switching network system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111092687B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111861399A (en) * | 2020-07-22 | 2020-10-30 | 上海二三四五网络科技有限公司 | Control method and control device for interaction between APP and system calendar |
| CN112214451B (en) * | 2020-10-21 | 2021-08-10 | 成都成电光信科技股份有限公司 | High-speed monitoring recording equipment and method based on system on chip |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105429725A (en) * | 2015-11-17 | 2016-03-23 | 中南大学 | SOPC (System on a Programmable Chip) networking based sub-microsecond level clock synchronizing method and system |
| CN105471539A (en) * | 2015-06-11 | 2016-04-06 | 南京智汇电力技术有限公司 | Method for realizing synchronization data acquisition based on passive optical network |
| CN105515708A (en) * | 2015-12-07 | 2016-04-20 | 中国航空工业集团公司西安航空计算技术研究所 | FC network based clock synchronization precision testing device and method |
| CN106992830A (en) * | 2017-04-05 | 2017-07-28 | 中国科学院空间应用工程与技术中心 | A kind of clock synchronizing method in the networks of FC AE 1553 |
| US10298344B1 (en) * | 2015-03-06 | 2019-05-21 | Marvell International Ltd. | Systems and methods for indicating when frames egress a PHY module of a network device |
-
2019
- 2019-12-10 CN CN201911257359.6A patent/CN111092687B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10298344B1 (en) * | 2015-03-06 | 2019-05-21 | Marvell International Ltd. | Systems and methods for indicating when frames egress a PHY module of a network device |
| CN105471539A (en) * | 2015-06-11 | 2016-04-06 | 南京智汇电力技术有限公司 | Method for realizing synchronization data acquisition based on passive optical network |
| CN105429725A (en) * | 2015-11-17 | 2016-03-23 | 中南大学 | SOPC (System on a Programmable Chip) networking based sub-microsecond level clock synchronizing method and system |
| CN105515708A (en) * | 2015-12-07 | 2016-04-20 | 中国航空工业集团公司西安航空计算技术研究所 | FC network based clock synchronization precision testing device and method |
| CN106992830A (en) * | 2017-04-05 | 2017-07-28 | 中国科学院空间应用工程与技术中心 | A kind of clock synchronizing method in the networks of FC AE 1553 |
Also Published As
| Publication number | Publication date |
|---|---|
| CN111092687A (en) | 2020-05-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10158444B1 (en) | Event-driven precision time transfer | |
| US8107502B2 (en) | Method and apparatus for monitoring packet networks | |
| US8180882B2 (en) | Distributed messaging system and method for sharing network status data | |
| CN111092687B (en) | Calendar clock synchronization system of FC switching network system | |
| US7792153B2 (en) | Sequencing multi-source messages for delivery as partial sets to multiple destinations | |
| CN107579791B (en) | Satellite on-orbit remote measurement data real-time monitoring system suitable for unidirectional communication network | |
| EP3163786B1 (en) | Clock synchronization method and apparatus | |
| CN105515708B (en) | A kind of clock synchronization accuracy test device and method based on FC networks | |
| CN102571911B (en) | Computer time synchronizing and monitoring method based on NTP (Network Time Protocol) protocol | |
| EP2448168A1 (en) | Method and system for bearing time synchronization protocol in optical transport network | |
| WO2015117501A1 (en) | Time synchronization method, programmable logic device, single board and network element | |
| EP3174237A1 (en) | Time synchronization method and apparatus for network devices and time synchronization server | |
| CN102035638A (en) | Clock source selection processing method, device and system | |
| CN102830612A (en) | System and method of high-precision time service and time keeping of broadcast controller | |
| CN104486017B (en) | Satellite time service multi-node synchronization monitoring method based on IP light transmission | |
| CN107959537B (en) | State synchronization method and device | |
| CN102342051B (en) | For coming the method for synchronised clock and relevant system and module by separating transmission first and second data via at least one time distribution protocol | |
| WO2021063300A1 (en) | Clock synchronization communication system and method for rail train | |
| KR100431700B1 (en) | System And Method For Synchronizing Time Between SGSN And GGSN | |
| CN101316161B (en) | Synchronous indication method and system for distributed video | |
| CN107920116A (en) | A kind of onboard networks service data communications method of dynamic extending | |
| US10334539B2 (en) | Metered interface | |
| CN105323028A (en) | Time synchronization method, equipment and system | |
| WO2016127760A1 (en) | User end device changing method, network element management system, and optical network system | |
| CN107370716B (en) | Multicast information processing method and device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |