CN111752881A - Inter-module communication method and system - Google Patents
Inter-module communication method and system Download PDFInfo
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- CN111752881A CN111752881A CN202010574434.8A CN202010574434A CN111752881A CN 111752881 A CN111752881 A CN 111752881A CN 202010574434 A CN202010574434 A CN 202010574434A CN 111752881 A CN111752881 A CN 111752881A
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- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
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Abstract
The embodiment of the invention discloses a method and a system for communication between modules. The inter-module communication method is used for controlling data transmission between a first communication module and a second communication module, wherein the first communication module is connected to the second communication module through a data bus, and the inter-module communication method comprises the following steps: when the first communication module is in a data transmission state, sending a data valid signal to the second communication module through the data bus, and simultaneously writing first section data into the data bus; and when the second communication module is in a data receivable state, sending a receiving permission signal to the first communication module through the data bus, and simultaneously receiving the first section of data transmitted through the data bus. The embodiment of the invention realizes the flexibility of communication data transmission among the modules.
Description
Technical Field
The present invention relates to communications technologies, and in particular, to a method and a system for inter-module communication.
Background
Axi (advanced xtensible inter interface) is a bus protocol, which is the most important part of the amba (advanced microcontroller bus architecture)3.0 protocol proposed by ARM corporation, and is an on-chip bus oriented to high performance, high bandwidth and low latency. The address/control and data phase of the system are separated, unaligned data transmission is supported, meanwhile, in burst transmission, only a first address is needed, simultaneously, a data channel is separately read and written, and outbound transmission access and out-of-order access are supported, and time sequence convergence is easier to perform.
However, the AXI bus protocol is used for communication, data is transmitted in a frame or packet mode, a 4K logical boundary exists, a large number of control signals such as addresses are required, communication data transmission among modules cannot be suspended flexibly, and resetting of any one end of a transmitting end or a receiving end affects the state of the other end.
Disclosure of Invention
The embodiment of the invention provides a method and a system for communication between modules, which are used for realizing the flexibility of communication data transmission between the modules.
To achieve the object, an embodiment of the present invention provides an inter-module communication method for controlling data transmission between a first communication module and a second communication module, the first communication module being connected to the second communication module through a data bus, the inter-module communication method including:
when the first communication module is in a data transmission state, sending a data valid signal to the second communication module through the data bus, and simultaneously writing first section data into the data bus;
and when the second communication module is in a data receivable state, sending a receiving permission signal to the first communication module through the data bus, and simultaneously receiving the first section of data transmitted through the data bus.
Further, the first communication module operates in a first clock cycle, the second communication module operates in a second clock cycle, and the first clock cycle is different from the second clock cycle.
Further, when the first communication module is in a data transmission state, sending a data valid signal to the second communication module through the data bus, and simultaneously writing the first segment of data into the data bus includes:
when the first clock cycle of the first communication module rises, the second effective end of the second communication module receives a data effective signal sent by the first effective end of the first communication module through the data bus;
and when the first communication module is in a data transmission state, the first communication module writes a first section of data into the data bus.
Further, when the second communication module is in a data receivable state, sending a reception permission signal to the first communication module through the data bus, and simultaneously receiving the first segment of data transmitted through the data bus includes:
when a second clock cycle of the second communication module rises, the first permission end of the first communication module receives a receiving permission signal sent by the second permission end of the second communication module through the data bus;
and meanwhile, when the second communication module is in a data receivable state, the second communication module receives the first section of data transmitted through the data bus.
Further, when the first communication module is in a data transmission state, sending a data valid signal to the second communication module through the data bus, and simultaneously writing the first segment of data into the data bus further includes:
the first communication module sends a byte enabling signal to the second communication module based on the information of the valid bytes in the first segment of data.
Further, when the second communication module is in a data receivable state, sending a reception permission signal to the first communication module through the data bus, and receiving the first segment of data transmitted through the data bus further includes:
and the second communication module receives the effective byte of the first segment of data transmitted by the data bus according to the byte enabling signal.
In another aspect, an embodiment of the present invention further provides an inter-module communication system, which includes a first communication module, a data bus, and a second communication module, wherein the first communication module is connected to the second communication module through the data bus,
when the first communication module is in a data transmission state, sending a data valid signal to the second communication module through the data bus, and simultaneously writing first section data into the data bus;
and when the second communication module is in a data receivable state, sending a receiving permission signal to the first communication module through the data bus, and simultaneously receiving the first section of data transmitted through the data bus.
Further, the inter-module communication system further includes:
and the clock source is used for sending a first clock period to the first communication module and sending a second clock period to the second communication module, the first communication module works in the first clock period, the second communication module works in the second clock period, and the first clock period is different from the second clock period.
Further, in the above-mentioned case,
when the first clock cycle of the first communication module rises, the second effective end of the second communication module receives a data effective signal sent by the first effective end of the first communication module through the data bus;
and when the first communication module is in a data transmission state, the first communication module writes a first section of data into the data bus.
Further, in the above-mentioned case,
when a second clock cycle of the second communication module rises, the first permission end of the first communication module receives a receiving permission signal sent by the second permission end of the second communication module through the data bus;
and meanwhile, when the second communication module is in a data receivable state, the second communication module receives the first section of data transmitted through the data bus.
Further, in the above-mentioned case,
the first communication module sends a byte enabling signal to the second communication module based on the information of the valid bytes in the first segment of data.
Further, in the above-mentioned case,
and the second communication module receives the effective byte of the first segment of data transmitted by the data bus according to the byte enabling signal.
In the embodiment of the invention, when the first communication module is in a data transmission state, a data effective signal is sent to the second communication module through the data bus, and meanwhile, first section data is written into the data bus; when the second communication module is in a data receivable state, the second communication module sends a receiving permission signal to the first communication module through the data bus, and simultaneously receives the first section of data transmitted through the data bus, so that the problem that the transmission of communication data among the modules cannot be flexibly suspended at any time is solved, and the effect of flexibility of the transmission of the communication data among the modules is realized.
Drawings
Fig. 1 is a schematic flowchart of an inter-module communication method according to an embodiment of the present invention;
fig. 2 is a flowchart illustrating an inter-module communication method according to a second embodiment of the present invention;
FIG. 3 is a schematic diagram illustrating an operation timing sequence of the inter-module communication method according to the second embodiment of the present invention;
fig. 4 is a flowchart illustrating an inter-module communication method according to a third embodiment of the present invention;
fig. 5 is a schematic structural diagram of an inter-module communication system according to a fourth embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are for purposes of illustration and not limitation. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
Before discussing exemplary embodiments in more detail, it should be noted that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although a flowchart may describe the steps as a sequential process, many of the steps can be performed in parallel, concurrently or simultaneously. In addition, the order of the steps may be rearranged. A process may be terminated when its operations are completed, but may have additional steps not included in the figure. A process may correspond to a method, a function, a procedure, a subroutine, a subprogram, etc.
Furthermore, the terms "first," "second," and the like may be used herein to describe various orientations, actions, steps, elements, or the like, but the orientations, actions, steps, or elements are not limited by these terms. These terms are only used to distinguish one direction, action, step or element from another direction, action, step or element. For example, a first speed difference may be referred to as a second speed difference, and similarly, a second speed difference may be referred to as a first speed difference, without departing from the scope of the present application. The first speed difference and the second speed difference are both speed differences, but they are not the same speed difference. The terms "first", "second", etc. are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features. In the description of the embodiments of the present invention, "a plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.
Example one
As shown in fig. 1, an embodiment of the present invention provides an inter-module communication method, where the inter-module communication method is used to control data transmission between a first communication module and a second communication module, where the first communication module is connected to the second communication module through a data bus, and the inter-module communication method includes:
s110, when the first communication module is in a data transmission state, sending a data valid signal to the second communication module through the data bus, and simultaneously writing first section data into the data bus;
in this embodiment, when the first communication module needs to transmit data to the second communication module and the first communication module is in a data transmittable state, the first communication module sends a data valid signal to the second communication module, and the first communication module writes a first segment of data of the data that needs to be transmitted into the data bus for temporary storage.
And S120, when the second communication module is in a data receivable state, sending a receiving permission signal to the first communication module through the data bus, and receiving the first section of data transmitted through the data bus.
In this embodiment, when the second communication module is in a state capable of receiving data, the second communication module sends a reception permission signal to the first communication module, and when the first communication module also sends a data valid signal to the second communication module, the data bus transmits the first segment of data stored on the first communication module to the second communication module.
When any signal stops sending, namely the first communication module stops sending the data valid signal to the second communication module or the second communication module stops sending the receiving permission signal to the first communication module, the transmission of the communication will stop immediately. It should be noted that the first segment of data does not refer to the first segment of data in sequence, and the first segment of data may be any segment of data in actual communication. Therefore, the first communication module is used as the sending end and the second communication module is used as the receiving end, which are not interfered with each other, the normal work of the sending end cannot be influenced by the operations of resetting the receiving end and the like, and the risk in data transmission is reduced.
In the embodiment of the invention, when the first communication module is in a data transmission state, a data effective signal is sent to the second communication module through the data bus, and meanwhile, first section data is written into the data bus; when the second communication module is in a data receivable state, the second communication module sends a receiving permission signal to the first communication module through the data bus, and simultaneously receives the first section of data transmitted through the data bus, so that the problem that the transmission of communication data among the modules cannot be flexibly suspended at any time is solved, and the effect of flexibility of the transmission of the communication data among the modules is realized.
Example two
As shown in fig. 2 and fig. 3, a second embodiment of the present invention provides an inter-module communication method, which is further optimized based on the first embodiment of the present invention, the inter-module communication method is used to control data transmission between a first communication module and a second communication module, the first communication module is connected to the second communication module through a data bus,
in this embodiment, the first communication module operates in a first clock cycle, the second communication module operates in a second clock cycle, and the first clock cycle and the second clock cycle are different from each other, and the signal is transmitted only when the clock cycle rises. The first communication module comprises a first effective end, a first permission end, a first data end and a first clock end, the second communication module comprises a second effective end, a second permission end, a second data end and a second clock end, the first communication module transmits data to the data bus through the first data end, the second communication module receives the data from the data bus through the second data end, bit width of the data from the data bus can be configured randomly according to requirements, the clock source sends a first clock cycle to the first communication module through the first clock end, and sends a second clock cycle to the second communication module through the second clock end.
The inter-module communication method comprises the following steps:
and S210, when the first clock cycle of the first communication module rises, the second effective end of the second communication module receives a data effective signal sent by the first effective end of the first communication module through the data bus.
S220, when the first communication module is in a data transmission state, the first communication module writes the first section of data into the data bus.
In this embodiment, when the first communication module needs to transmit data to the second communication module and the first communication module is also in a data transmittable state, the first communication module may pull up a valid data signal of the first valid end from a low level to a high level, which indicates that the first communication module is ready to send data.
S230, when the second clock cycle of the second communication module rises, the first permission side of the first communication module receives a permission receiving signal sent by the second permission side of the second communication module through the data bus.
S240, when the second communication module is in a data receivable state, the second communication module receives the first section of data transmitted through the data bus.
In this embodiment, when the second communication module is in a state capable of receiving data, the second communication module will pull up a data valid signal of the second valid end from a low level to a high level, that is, it indicates that the second communication module is ready to receive data, when a second clock cycle of the second communication module is in a rising state, the second communication module will send a receiving permission signal to the first permission end of the first communication module through the second permission end, and simultaneously the data bus will transmit the first segment of data stored in the second communication module to the second communication module.
When any signal stops sending, namely the first communication module stops sending the data valid signal to the second communication module or the second communication module stops sending the receiving permission signal to the first communication module, the transmission of the communication will stop immediately. It should be noted that the first segment of data does not refer to the first segment of data in sequence, and the first segment of data may be any segment of data in actual communication. Similarly, as shown in fig. 3, by the same method, optionally, the first segment of data, the second segment of data, the third segment of data, and more data transmission can be completed in the same clock cycle, and in an alternative embodiment, the first segment of data, the second segment of data, the third segment of data, and more data transmission can also be completed in different clock cycles.
The embodiment of the invention realizes the inter-module communication of the cross-clock on the basis of the first embodiment of the invention, solves the problem that the transmission of the communication data between the cross-clock modules can not be flexibly suspended at any time, and realizes the effect of flexibility of the transmission of the communication data between the cross-clock modules.
EXAMPLE III
As shown in fig. 4, a third embodiment of the present invention provides an inter-module communication method, which is further optimized based on the first embodiment of the present invention, the inter-module communication method is used to control data transmission between a first communication module and a second communication module, where the first communication module is connected to the second communication module through a data bus.
In this embodiment, the first communication module includes a first enable terminal, the second communication module includes a second enable terminal, the first communication module transmits data to the data bus through the first data terminal, and the second communication module receives data from the data bus through the second data terminal.
The inter-module communication method comprises the following steps:
and S310, when the first communication module is in a data transmission state, sending a data valid signal to the second communication module through the data bus, and simultaneously writing the first section of data into the data bus.
S320, the first communication module sends a byte enabling signal to the second communication module based on the information of the effective bytes in the first segment of data.
In this embodiment, when the first communication module needs to transmit data to the second communication module and the first communication module is in a data transmittable state, the first communication module sends a data valid signal to the second communication module, and the first communication module writes a first segment of data of the data that needs to be transmitted into the data bus for temporary storage. When the first communication module writes the first segment of data of the data required to be transmitted into the data bus for temporary storage, the first communication module also sends a byte enabling signal to the second communication module through the first enabling terminal based on the information of the valid byte in the sent first segment of data, and the byte enabling signal is also temporarily stored in the data bus following the first segment of data, wherein the byte enabling signal of one byte can enable the data of 8 bytes to be valid.
S330, when the second communication module is in a data receivable state, sending a receiving permission signal to the first communication module through the data bus, and simultaneously receiving the first section of data transmitted through the data bus.
S340, the second communication module receives the effective byte of the first segment of data transmitted through the data bus according to the byte enable signal.
In this embodiment, when the second communication module is in a state capable of receiving data, the second communication module sends a reception permission signal to the first communication module, and when the first communication module also sends a data valid signal to the second communication module, the data bus transmits the first segment of data stored on the first communication module to the second communication module. When the second communication module receives the first segment of data stored on the data bus, the byte enable signal is received through the second enable terminal at the same time so as to verify whether the data received by the second communication module is valid.
When any signal stops sending, namely the first communication module stops sending the data valid signal to the second communication module or the second communication module stops sending the receiving permission signal to the first communication module, the transmission of the communication will stop immediately. It should be noted that the first segment of data does not refer to the first segment of data in sequence, and the first segment of data may be any segment of data in actual communication. Therefore, the communication bus does not need the cooperation of an address bus, can adapt to different data bit widths, only transmits one data at a time, ensures that the transmission of any data volume can be supported, simplifies the logic complexity of data transmission, and has more flexible transmission and wider applicability.
The embodiment of the invention realizes the function of verifying the validity of data during the communication between the modules on the basis of the first embodiment of the invention, solves the problems that the transmission of the communication data between the modules can not be suspended at any time flexibly and the validity of the data can not be verified, and realizes the effects of flexibility of the transmission of the communication data between the modules and the validity of the data.
Example four
As shown in fig. 5, a fourth embodiment of the present invention provides an inter-module communication system, which includes a first communication module 100, a data bus 200, and a second communication module 300, where the first communication module 100 is connected to the second communication module 300 through the data bus 200.
When the first communication module 100 is in a data transmission state, sending a data valid signal to the second communication module 300 through the data bus 200, and simultaneously writing a first segment of data into the data bus 200;
when the second communication module 300 is in a data receivable state, it sends a reception permission signal to the first communication module 100 through the data bus 200, and receives the first segment of data transmitted through the data bus 200.
In this embodiment, when the first communication module 100 needs to transmit data to the second communication module 300 and the first communication module 100 is in a data transmission state, the first communication module 100 sends a data valid signal to the second communication module 300, and the first communication module 100 writes a first segment of data of the data that needs to be transmitted into the data bus 200 for temporary storage.
When the second communication module 300 is in a state of being able to receive data, the second communication module 300 sends a reception permission signal to the first communication module 100, and when the first communication module 100 is also sending a data valid signal to the second communication module 300, the data bus 200 transmits the first piece of data stored thereon to the second communication module 300.
In an embodiment, the inter-module communication system further includes a clock source 400, where the clock source 400 is configured to send a first clock cycle to the first communication module 100 and a second clock cycle to the second communication module 300, where the first communication module 100 operates in the first clock cycle and the second communication module 300 operates in the second clock cycle, and the first clock cycle is different from the second clock cycle. The transmission of the signal is performed when the clock cycle rises. The first communication module 100 includes a first valid terminal 102, a first permission terminal 105, a first data terminal 103, a first enable terminal 104 and a first clock terminal 101, the second communication module 300 includes a second valid terminal 302, a second permission terminal 305, a second data terminal 303, a second enable terminal 304 and a second clock terminal 301, the first communication module 100 transmits data to the data bus 200 through the first data terminal 103, and the second communication module 300 receives data from the data bus 200 through the second data terminal 303, wherein a bit width of the data from the data bus 200 can be arbitrarily configured according to requirements.
When the first clock cycle of the first communication module 100 rises, the second active terminal 302 of the second communication module 300 receives the data valid signal sent by the first active terminal 102 of the first communication module 100 through the data bus 200; while the first communication module 100 is in a data transmittable state, the first communication module 100 writes a first piece of data into the data bus 200; the first communication module 100 sends a byte enable signal to the second communication module 300 based on the information of the valid bytes in the first piece of data.
In this embodiment, when the first communication module 100 needs to transmit data to the second communication module 300 and the first communication module 100 is in a data transmission state, the first communication module 100 will pull up the valid data signal of the first valid end 102 from a low level to a high level, which means that the first communication module 100 is ready to send data, when the first clock cycle of the first communication module 100 is up, the first communication module 100 will send a valid data signal to the second valid end 302 of the second communication module 300 through the first valid end 102, and at the same time, the first communication module 100 will write the first segment of data of the data that needs to be transmitted into the data bus 200 for temporary storage. When the first communication module 100 writes the first segment of data of the data that needs to be transmitted into the data bus 200 for temporary storage, the first communication module 100 further sends a byte enable signal to the second communication module 300 through the first enable terminal 104 based on the information of the valid byte in the sent first segment of data, and the byte enable signal is also temporarily stored in the data bus 200 following the first segment of data, wherein the byte enable signal of one byte can enable 8 bytes of data to be valid.
When the second clock cycle of the second communication module 300 rises, the first enable terminal 105 of the first communication module 100 receives the permission signal sent by the second enable terminal 305 of the second communication module 300 through the data bus 200; meanwhile, when the second communication module 300 is in a data receivable state, the second communication module 300 receives a first segment of data transmitted through the data bus 200; the second communication module 300 receives the valid byte of the first segment of data transmitted through the data bus 200 according to the byte enable signal.
In this embodiment, when the second communication module 300 is in a state capable of receiving data, the second communication module 300 will pull up the data valid signal of the second valid end 302 from a low level to a high level, which means that the second communication module 300 is ready to receive data, and when the second clock cycle of the second communication module 300 is rising, the second communication module 300 will send a receiving permission signal to the first permission end 105 of the first communication module 100 through the second permission end 305 thereof, and at the same time, the data bus 200 will transmit the first segment of data stored thereon to the second communication module 300. When the second communication module 300 receives the first segment of data stored on the data bus 200, it also receives the byte enable signal through the second enable terminal 304 to verify whether the received data is valid.
When any signal stops transmitting, that is, the first communication module 100 stops transmitting the data valid signal to the second communication module 300 or the second communication module 300 stops transmitting the reception permission signal to the first communication module 100, the transmission of the communication will stop immediately. It should be noted that the first segment of data does not refer to the first segment of data in sequence, and the first segment of data may be any segment of data in actual communication.
According to the embodiment of the invention, through the first communication module 100, the second communication module 300 and the data bus 200, the function of verifying data validity during cross-clock inter-module communication is realized, the problems that the transmission of communication data between the cross-clock inter-modules cannot be flexibly suspended at any time and the data validity is verified are solved, and the effects of flexibility of the transmission of communication data between the cross-clock inter-modules and data validity verification are realized.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (12)
1. An inter-module communication method for controlling data transmission between a first communication module and a second communication module, the first communication module being connected to the second communication module by a data bus, comprising:
when the first communication module is in a data transmission state, sending a data valid signal to the second communication module through the data bus, and simultaneously writing first section data into the data bus;
and when the second communication module is in a data receivable state, sending a receiving permission signal to the first communication module through the data bus, and simultaneously receiving the first section of data transmitted through the data bus.
2. The communication method according to claim 1, wherein the first communication module operates in a first clock cycle, and the second communication module operates in a second clock cycle, and the first clock cycle and the second clock cycle are different.
3. The communication method according to claim 2, wherein the sending a data valid signal to the second communication module via the data bus while the first communication module is in the data transmittable state, and simultaneously writing the first piece of data to the data bus comprises:
when the first clock cycle of the first communication module rises, the second effective end of the second communication module receives a data effective signal sent by the first effective end of the first communication module through the data bus;
and when the first communication module is in a data transmission state, the first communication module writes a first section of data into the data bus.
4. The communication method according to claim 2, wherein the sending a reception permission signal to the first communication module through the data bus while the second communication module is in the data receivable state, and the receiving the first piece of data transmitted through the data bus simultaneously comprises:
when a second clock cycle of the second communication module rises, the first permission end of the first communication module receives a receiving permission signal sent by the second permission end of the second communication module through the data bus;
and meanwhile, when the second communication module is in a data receivable state, the second communication module receives the first section of data transmitted through the data bus.
5. The communication method according to claim 1, wherein the transmitting a data valid signal to the second communication module via the data bus while the first communication module is in the data transmittable state, and simultaneously writing the first piece of data to the data bus further comprises:
the first communication module sends a byte enabling signal to the second communication module based on the information of the valid bytes in the first segment of data.
6. The communication method according to claim 5, wherein the sending a reception permission signal to the first communication module via the data bus while the second communication module is in the data receivable state, and the receiving the first piece of data transmitted via the data bus further comprises:
and the second communication module receives the effective byte of the first segment of data transmitted by the data bus according to the byte enabling signal.
7. An inter-module communication system comprising a first communication module, a data bus and a second communication module, the first communication module being connected to the second communication module via the data bus,
when the first communication module is in a data transmission state, sending a data valid signal to the second communication module through the data bus, and simultaneously writing first section data into the data bus;
and when the second communication module is in a data receivable state, sending a receiving permission signal to the first communication module through the data bus, and simultaneously receiving the first section of data transmitted through the data bus.
8. The communication system of claim 7, further comprising:
and the clock source is used for sending a first clock period to the first communication module and sending a second clock period to the second communication module, the first communication module works in the first clock period, the second communication module works in the second clock period, and the first clock period is different from the second clock period.
9. The communication system of claim 8,
when the first clock cycle of the first communication module rises, the second effective end of the second communication module receives a data effective signal sent by the first effective end of the first communication module through the data bus;
and when the first communication module is in a data transmission state, the first communication module writes a first section of data into the data bus.
10. The communication system of claim 8,
when a second clock cycle of the second communication module rises, the first permission end of the first communication module receives a receiving permission signal sent by the second permission end of the second communication module through the data bus;
and meanwhile, when the second communication module is in a data receivable state, the second communication module receives the first section of data transmitted through the data bus.
11. The communication system of claim 7,
the first communication module sends a byte enabling signal to the second communication module based on the information of the valid bytes in the first segment of data.
12. The communication system of claim 11,
and the second communication module receives the effective byte of the first segment of data transmitted by the data bus according to the byte enabling signal.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112291126A (en) * | 2020-10-23 | 2021-01-29 | 成都天锐星通科技有限公司 | Bus communication system, data transmission method and data reception method |
| WO2021259229A1 (en) * | 2020-06-22 | 2021-12-30 | 深圳鲲云信息科技有限公司 | Inter-module communication method and system |
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| WO2021259229A1 (en) | 2021-12-30 |
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