CN111221756B - Method for high-efficiency downlink data transmission of upper computer - Google Patents
Method for high-efficiency downlink data transmission of upper computer Download PDFInfo
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- CN111221756B CN111221756B CN201911103984.5A CN201911103984A CN111221756B CN 111221756 B CN111221756 B CN 111221756B CN 201911103984 A CN201911103984 A CN 201911103984A CN 111221756 B CN111221756 B CN 111221756B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0815—Cache consistency protocols
- G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
- G06F12/0835—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means for main memory peripheral accesses (e.g. I/O or DMA)
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
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- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
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Abstract
The invention discloses a method for efficiently transmitting data to lower-layer equipment by upper computer software, which comprises the following steps: initializing a memory allocation structure by the upper computer, and writing the initialized related information into the lower-layer equipment; the upper computer and the lower equipment respectively establish a circulating queue with the depth of M, N for storing corresponding information; during data transmission, the upper computer software copies the data to be transmitted into the c-th sub-block of the large memory block with the sequence number a, then integrates the sequence number a, the sequence number c and the data length L into a value R, and writes the value into lower equipment in a register writing mode; the lower-layer equipment obtains the physical address ADDR of the data storage through calculation, and then initiates DMA operation according to the data length L resolved in the integrated value R to obtain the data. The method has the advantages of simpler processing flow, better cross-system portability and higher transmission efficiency.
Description
Technical Field
The invention describes a method for efficiently transmitting data to lower equipment by an upper computer, which has the advantages of simpler processing flow, better cross-system portability and higher transmission efficiency.
Background
When the upper computer transmits data to the lower equipment, a common method is to write a register or DMA (direct memory access) transmission, the register writing efficiency is low, and the requirement of high-speed data transmission cannot be met; the DMA transmission has two modes, one is that the upper computer calls the system interface function to actively initiate the DMA operation, and the other is that the upper computer informs the lower-layer equipment of the physical address and the length information of the data of the DMA transmission, and the lower-layer equipment initiates the DMA operation. In either DMA mode, the problems of confirmation of DMA data transfer completion and multiplexing of physical memory need to be considered.
If the DMA transfer efficiency needs to be improved, the continuity of multiple DMA operations needs to be improved, reducing the interval between each DMA operation as much as possible. For this reason, there is a need for better transmission control methods to reduce the impact of data transmission acknowledgements on the operation continuity.
Disclosure of Invention
The invention designs an upper computer downlink data transmission method for initiating DMA operation based on lower equipment, which can realize continuous DMA operation by a simple algorithm and reduce the influence of each DMA data transmission confirmation on continuous DMA transmission, thereby greatly improving the efficiency of the upper computer downlink data transmission. Because the mode that the lower-layer equipment initiates the DMA operation is adopted, the upper computer software does not need to call the interface function of the operating system to initiate the DMA transmission, and the influence caused by different use flows and modes of the DMA interface functions of each operating system is avoided, so that the method has very good cross-system portability.
The invention adopts the mode that the lower-layer equipment initiates DMA transmission to realize data transmission, so that the memory physical address information of data stored in each DMA transmission is required to be informed to the lower-layer equipment; in a 32-bit system, the physical address needs to occupy 32 bits of storage, in a 64-bit system, the physical address information needs to occupy 64 bits of storage, and besides the physical address information which needs to inform the lower device of DMA transmission, the data length which needs to inform the lower device of DMA transmission also needs to be informed, then a certain bit (assuming that N bits are needed and N must be greater than 0) is also needed to store the data length information. In this way, when the upper computer needs to transmit data to the lower device, the lower device needs to be informed of the information of 32 bit+n bit (32 bit system) or 64 bit+n bit (64 bit system) so that the lower device initiates the DMA operation. If the information is informed by adopting a register writing mode, the information is calculated according to the information length, and according to a 32bit register writing mode, a 32bit system needs to be written into a register for 2 times, and a 64bit system needs to be written into a register for 3 times so as to issue data to equipment once.
Writing 2 or 3 registers can inform the lower-layer equipment that necessary information initiates a DMA operation, and higher efficiency can be realized under the condition of realizing continuous DMA operation. However, due to the limitation of the read-write speed of the register, the register writing operation may still become a bottleneck of data transmission.
Another reason for affecting the efficiency of data transfer is that the completion of a DMA operation is acknowledged, and if a second DMA operation is initiated after waiting for the completion of a data transfer to be acknowledged after initiating a DMA operation, the time in between waiting for the acknowledgement is wasted, which greatly affects the efficiency of data transfer. The invention designs a simple and reliable operation design for confirming the completion of DMA transmission to realize batch transmission and batch confirmation of the DMA.
The invention adopts the mode that the upper computer and the lower equipment use the circular queue to realize the batch transmission and confirmation of the DMA. The lower-layer equipment establishes a queue with depth N for storing DMA information written by the upper computer, and the upper computer writes the DMA information into the lower-layer equipment in a register writing mode when initiating DMA data transmission once. The lower device stores this information in a circular queue. The circular queue is provided with a storage pointer DIP and a completed pointer DFP, the DIP moves forward every time a piece of DMA information is newly stored, meanwhile, the device continuously reads the completed pointer DFP, if the DFP is not equal to the DIP, the fact that the DMA transmission is not completed is indicated, the device initiates the DMA transmission according to the DMA information pointed by the current DFP, after the DMA transmission operation corresponding to the current DFP is completed, the DFP pointer moves forward until the DFP is equal to the DIP, and the fact that all the DMA transmissions are completed is indicated. In addition, the lower device also provides a writable DMA information quantity register for recording the quantity of free storage blocks of the self-circulation queue, and the upper computer can determine whether the DMA information can be continuously written by reading the register. The upper computer is provided with a counter REG_FIFO and a circular queue with a depth of M, M is more than or equal to the depth N of the circular queue of the lower device in order to simplify the algorithm, and each storage item of the circular queue of the upper computer corresponds to a continuous physical memory. The upper computer reads the value of the writable DMA information quantity register of the lower device and stores the value in the counter reg_fifo, and can determine whether the DMA information can be continuously written into the lower device by determining whether the value of reg_fifo is 0. The host computer's circular queue also has two pointers: when the write pointer WP and the release pointer FP initiate downstream data transfer, the data copy to be transferred is first put into the continuous physical memory pointed by WP, and then after confirming that reg_fifo is greater than 0, the write register informs the physical memory address pointed by the lower device WP and the data length information (this information can be simply compressed to 32 bits according to the design in the present invention, and written into the register only once). After writing the DMA information to the lower device, the WP pointer is advanced and reg_fifo is reduced by 1. After a number of writes of consecutive data transfers, the REG_FIFO is decremented to 0, at which time the register of the lower device is again read to update the REG_FIFO value, since during this time the lower device has completed a portion of the DMA transfer, the REG_FIFO read should be a value n greater than 0. The read value n also indicates the number of DMAs that have completed during this time, so the release pointer FP of the upper software queue can be advanced by n positions. Through the cooperation of the circulating queue of the lower-layer equipment, the circulating queue of the upper computer and the writable DMA information quantity register and the counter, continuous DMA operation can be realized without waiting for the completion of the current DMA operation for each data transmission, thereby greatly improving the data transmission efficiency.
Drawings
Fig. 1 shows the memory structure and information compression principle of the upper computer of the present invention.
FIG. 2 illustrates a batch sequential DMA operation implementation flow of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to fall within the scope of the invention.
The invention is applied to the host device which transmits data to the lower-layer I/O device through the control of the upper computer, and the initialization work is needed when the invention is implemented.
When the device is not used, the value is the depth N of the data transmission DMA information cache queue of the lower device.
And then the upper computer applies for a continuous physical memory with a larger A block (A is more than or equal to 1) in the host equipment according to the configuration parameters, and in order to improve the application success rate, the length of the continuous physical memory is generally recommended to be 1MB or 2MB. After the application of the continuous physical memory is completed, dividing the continuous physical memory with each block into C (C is more than or equal to 1) sub-blocks according to the maximum single DMA data length K of practical application. In order to simplify the complexity of the data transmission flow control, it is necessary to ensure that the number of the memory blocks allocated by the upper computer and capable of storing the downlink DMA data is greater than the depth of the data buffer queue of the lower device. The design aims at the transmission control, only needs to consider whether the device cache queue is full so as to suspend the waiting for completing partial DMA transmission, and does not need to consider whether the memory applied by the upper computer software is full at the same time, thereby simplifying the complexity of the transmission control.
After the memory application and division are completed, the number A of the memory blocks, the number C of the sub-blocks divided by each memory block, the length K of each sub-block and the initial physical addresses of the A memory blocks are written into the lower-layer equipment. So far, the initialization process is completed, and the upper computer can start to control continuous data transmission to the lower-layer equipment.
The purpose of the initialization work is to control the device to initiate a DMA transmission request by writing less information (32 bits) into the register during actual data transmission, and on the other hand, the initialization work is also to reduce the use amount of storage resources of the lower device. The memory structure and information compression principle of the upper computer are shown in figure 1.
The following details the memory structure of the upper computer and the principle that the upper computer writes compressed information to the lower equipment to control DMA transmission during data transmission in the invention:
in order to realize continuous DMA operation during batch data transmission, the upper computer stores the data content of each transmission in a memory block queue mode, and the lower equipment also stores DMA information written by the upper computer in a queue mode. The lower layer equipment completes the data transmission operation corresponding to the DMA information stored first according to the sequence of the information stored in the queue, and the storable information count can be increased every time the DMA data transmission operation is completed. The upper computer reads the storable information count, determines the number of completed data transmission according to the change condition of the storable information count and releases the record written first. Both sides realize the confirmation of batch data transmission completion through counting, so the efficiency of data transmission can be greatly improved.
In order to reduce the length of DMA information written to the lower device by the upper computer during each data transmission so as to reduce the number of times of writing into a register as much as possible, a method of directly writing in the physical address and the data length of each DMA cannot be adopted, but the physical address needs to be converted into a corresponding positioning sequence number, the lower device can quickly calculate the memory physical address according to the positioning sequence number, and then initiate DMA to acquire data according to the length information.
However, the memory resources of the lower device are usually extremely limited, and if each physical address of the upper computer memory block queue is stored, the limited memory resources are wasted greatly. The design of the invention can reduce the stored information of the lower equipment and still ensure higher transmission efficiency.
The upper computer applies for the large-block memory, and then the large-block memory is segmented according to a fixed length to obtain a plurality of transmission data buffer areas. The number of the large-block memories applied by the upper computer is A, each large-block memory is divided into C sub-blocks according to the length K, and then the sub-blocks are utilized to form a queue, and the queue depth M=A×C.
During initialization, the upper computer writes the number A of large memory blocks, the number C of sub-blocks segmented by each large memory block and the sub-block length K into the lower computer equipment, and then writes the initial physical addresses A of the large memory blocks one by one 0 、A 1 、A 2 ……A (A-1) 。
During data transmission, the upper computer copies the data into the c-th sub-block of the large memory block with the sequence number a, then integrates the sequence number a, the sequence number c and the data length L into a 32-bit value R, and writes the value into lower equipment in a register writing mode.
The lower device can obtain the physical address Aa of the large-block memory according to the sequence number a, then calculate and obtain the physical address ADDR of the data storage according to the formula addr=aa+ (c×k), and then initiate a DMA operation according to the L parsed out from the integrated value to obtain the data.
After the upper computer and the lower equipment complete the initialization operation, continuous and efficient data transmission operation can be realized according to the following flow. The following describes in detail the implementation flow of batch continuous data transmission of the upper computer with reference to fig. 2:
s201, starting batch downlink data transmission;
s202, reading a register value of the writable DMA information quantity of the lower-layer equipment, and updating a counter REG_FIFO;
s203, judging whether REG_FIFO is 0, if so, indicating that the lower device has a large amount of transmission data which is not transmitted, and entering S204 to wait for a process to wait for a few milliseconds; if REG_FIFO is not 0, then S205 flow may be entered to begin data transfer;
s204, when the REG_FIFO is 0, waiting for a few milliseconds, and then jumping to S202 to read the register again to update the REG_FIFO value;
s205, advancing the release pointer FP according to the newly read register value n until n positions are advanced or the release pointer FP catches up with the write pointer WP. When the release pointer FP is equal to or greater than the memory sub-block M during the forward movement, the release pointer FP is moved to sub-block 0 again. This step is used to confirm the completion status of the data transfer initiated before the host software, when the reg_fifo is 0, the re-read register obtains a value n other than 0 and stores it into the reg_fifo, then it indicates that the lower device has completed n initial data DMA transfer operations, and then the host software can then move the release pointer FP to release the initial write data record so as to free up the memory block for later use;
s206, copying a part of downlink data to a DMA cache physical memory block pointed by the write pointer WP;
s207, the write register informs the lower-layer device of the position information and the data length of the DMA cache physical memory block pointed by the write pointer WP. The method adopts the information compression method described in the introduction, the 32bit value formed by the sub-block sequence number c of the large block memory sequence number a and the data length L is written into a register for 1 time to inform the necessary information of DMA transmission of the lower equipment;
s208, the write pointer WP moves forward;
s209, judging whether WP > = memory subblock M, if WP is more than or equal to M, executing S210 to move WP to the starting position 0 of the cache queue, otherwise executing S211;
s210, a WP pointer points to a physical memory block 0 of a DMA cache queue;
s211, checking whether downlink data are required to be transmitted, if so, jumping to S212 to continue execution, and if all the downlink data are transmitted, jumping to S213 to end the operation;
s212, checking whether the counter REG_FIFO is 0, if so, jumping to S202 to read the value of the register update REG_FIFO again is needed; if not, jumping to S206 to start the next data copy;
s213, the batch transmission is completed, and the process execution is finished.
While the above description of the downstream data transmission method of the present invention has been provided in detail, those skilled in the art will appreciate that embodiments of the present invention may be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, magnetic disk storage, optical storage, and the like) having computer-usable program code embodied therein.
The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks. It will be apparent to those skilled in the art that various modifications and variations can be made to the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.
Claims (2)
1. The method for high-efficiency downlink data transmission of the upper computer is characterized by comprising the following steps of:
s1, distributing A large continuous memory blocks, dividing the A large continuous memory blocks into C equal-length sub-blocks according to a preset length K, and writing the initialized distributed memory block number A, the sub-block number C divided by each memory block, the length K of each sub-block and the initial physical address of each of the A memory blocks into lower-layer equipment;
s2, respectively establishing a circulating queue with the depth of M, N by the upper computer and the lower equipment, wherein M is more than or equal to N, each storage item of the circulating queue of the upper computer corresponds to a continuous physical memory, and the circulating queue of the lower equipment is used for storing DMA information written by the upper computer;
s3, during data transmission, the upper computer software copies the data to be transmitted into the c-th sub-block of the large memory block with the sequence number a, then integrates the sequence number a, the sequence number c and the data length L into a numerical value R, and writes the numerical value into lower equipment in a register writing mode;
s4, the lower-layer equipment acquires a physical address Aa of the large-block memory according to the sequence number a, calculates and acquires a physical address ADDR of data storage according to a formula addr=aa+ (c×k), and initiates DMA operation according to the data length L analyzed from the integrated value R to acquire data;
the method for efficient downlink data transmission of the upper computer is characterized in that step S3 is that before the upper computer copies the data to be transmitted, the upper computer reads the register value of the amount of writable DMA information of the lower device, updates the counter reg_fifo, judges whether the reg_fifo is 0, if 0, waits for a predetermined time, updates the counter reg_fifo again and judges that the reg_fifo is not 0, and starts copying the data to be transmitted.
2. The method for efficient downstream data transmission of a host computer according to claim 1, wherein the host computer and the lower device both use a circular queue to store relevant information of data transmission, and calculate and confirm whether the initially written data transmission request is completed by reading the counter multiple times, so that relevant resources for completing transmission are released in time when continuous data transmission is performed continuously.
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| CN112256617B (en) * | 2020-10-23 | 2021-04-20 | 福州富昌维控电子科技有限公司 | Method and terminal for improving serial port communication efficiency of equipment |
| CN114301992A (en) * | 2021-12-29 | 2022-04-08 | 北京半导体专用设备研究所（中国电子科技集团公司第四十五研究所） | Data transmission method and storage medium |
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