KR102280241B1 - System for controlling memory-access, apparatus for controlling memory-access and method for controlling memory-access using the same - Google Patents

Abstract

An apparatus for controlling memory access according to an embodiment includes a control unit, wherein the control unit receives a first source address among source addresses in a host memory unit and a first target address among target addresses in a target memory unit, The first control is performed for moving data stored in the area indicated by the source address to the area indicated by the first target address, receiving predetermined pointer information, and receiving a second source address among the source addresses from the area indicated by the pointer information and obtaining a second target address among the target addresses, and performing a second control of moving data stored in the area indicated by the second source address to the area indicated by the second target address.

Description

MEMORY ACCESS CONTROL SYSTEM, MEMORY ACCESS CONTROL DEVICE AND MEMORY ACCESS CONTROL METHOD USING THE SAME

The present invention relates to a memory access control system, a memory access control apparatus, and a memory access control method using the same.

Direct memory-access (DMA) is a feature of computer systems that allows certain hardware subsystems to access main system memory (RAM/DRAM) independently of the central processing unit (Host). Without DMA, the host directly reads or writes when performing programmed input/output, and as it occupies most of the workload, other tasks cannot be performed in parallel. With DMA, the host only needs to manage the information that uses DMA to initiate a transfer, then perform other tasks while the transfer is in progress, and finally the DMA controller sends an interrupt to the host when the task is complete. This feature is useful when the host cannot keep up with the data transfer rate, or when the host needs to do something else while waiting for a relatively slow I/O data transfer. Many hardware systems use DMA, including disk drive controllers, graphics cards, network cards, and sound cards. The same is true of the AI accelerator, which has been a hot topic recently. DMA is also used for intra-chip data transfer in multi-core processors. A computer with DMA will be able to transfer data between devices with much less host overhead than a computer without DMA. Similarly, processing elements inside a multi-core processor can send and receive data to and from local memory without occupying processor time, allowing calculation and data transfer to proceed in parallel.

Korean Patent Publication No. 10-2018-0117377 (published on October 29, 2018)

The problem to be solved by the present invention may include improving the above-described DMA. For example, in DMA, there are a direct address access method and an indirect address access method. Among them, the indirect address method has a problem that the time to secure information about a predetermined address is not deterministic. The problem to be solved by the present invention is to solve this problem. It may include improving or resolving.

However, the problems to be solved of the present invention are not limited to those mentioned above, and other problems to be solved that are not mentioned can be clearly understood by those of ordinary skill in the art to which the present invention belongs from the description below. will be.

The apparatus for controlling memory access according to an embodiment includes a control unit, wherein the control unit receives a first source address among the source addresses in the host memory unit and a first target address among target addresses in the target memory unit by receiving from the operation unit, , performs a first control of moving data stored in the area indicated by the first source address to the area indicated by the first target address, receives predetermined pointer information from the host memory unit, and receives the pointer information in the area indicated by the pointer information obtains a second source address from among the source addresses and a second target address from among the target addresses, and performs a second control of moving data stored in the area indicated by the second source address to the area indicated by the second target address do.

A memory access control method according to an embodiment includes receiving a first source address among source addresses in a host memory unit and a first target address among target addresses in a target memory unit in a region indicated by the first source address. performing a first control of moving stored data to an area indicated by the first target address; receiving predetermined pointer information; and a second source address of the source addresses and the second source address from the area indicated by the pointer information obtaining a second target address among target addresses; and moving data stored in the area indicated by the second source address to the area indicated by the second target address.

A memory access control system according to an embodiment includes a calculator, a host memory unit, a first source address among source addresses in the host memory unit, and a first target address among target addresses in the target memory unit by receiving from the operation unit, , performs a first control of moving data stored in the area indicated by the first source address to the area indicated by the first target address, receives predetermined pointer information from the host memory unit, and receives the pointer information in the area indicated by the pointer information obtains a second source address from among the source addresses and a second target address from among the target addresses, and performs a second control of moving data stored in the area indicated by the second source address to the area indicated by the second target address It includes a control unit that

According to an embodiment, in the beginning, DMA is performed according to the direct address method based on the distribution/collection information received from the operation unit, and after that, the address is obtained based on the pointer information obtained from the host memory unit, and based on this, DMA is performed according to an indirect addressing scheme. That is, in the beginning, data movement can be performed immediately by using the address received from the operation unit, and thus, the time required for address fetching in the indirect address method is not consumed in one embodiment. The performance of the memory access control system may be improved.

1 is a schematic configuration diagram of a memory access control system according to an embodiment.
2 is an example of distributed/collected information received by a memory access control apparatus from an operation unit according to an embodiment.
3 is a schematic conceptual diagram of data or information flow in a memory access control system according to an embodiment.
4 is a schematic flowchart of a procedure that can be performed in a memory access control system according to an embodiment.
5 is a schematic timing diagram illustrating a timing in a process in which data is processed for each channel in a memory access control system according to an exemplary embodiment.

Advantages and features of the present invention and methods of achieving them will become apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various different forms, and only these embodiments allow the disclosure of the present invention to be complete, and common knowledge in the art to which the present invention pertains It is provided to fully inform those who have the scope of the invention, and the present invention is only defined by the scope of the claims.

In describing the embodiments of the present invention, if it is determined that a detailed description of a well-known function or configuration may unnecessarily obscure the gist of the present invention, the detailed description thereof will be omitted. In addition, the terms to be described later are terms defined in consideration of functions in an embodiment of the present invention, which may vary according to intentions or customs of users and operators. Therefore, the definition should be made based on the content throughout this specification.

1 is a schematic configuration diagram of a memory access control system 1000 and a target memory unit 2000 according to an embodiment. Referring to FIG. 1 , a memory access control system 1000 includes a memory access control device 100 , a host memory unit 200 , and an operation unit 300 . In addition, although not shown in FIG. 1 , the memory access control apparatus 100 includes a control unit. However, since the configuration diagram shown in FIG. 1 is merely exemplary, the memory access control system 1000 may not include at least one of the configurations shown in FIG. 1 or additionally include a configuration not shown in FIG. 1 . can

First, the target memory unit 2000 may be implemented by a memory for storing data or the like. The target memory unit 2000 may be implemented in a target device separate from the memory access control system 1000 . Alternatively, different from that shown in FIG. 1 , the target memory unit 2000 may be implemented inside the memory access control system 1000 .

Next, the host memory unit 200 may be implemented by a memory for storing data or the like. Various types of information may be stored in the host memory unit 200 . For example, the host memory unit 200 may store general data to be moved/copied. In addition, the host memory unit 200 may store distribution/collection information used in an indirect address access method among DMAs.

Such distributed/collected information may include a pointer indicating a part of the region of the host memory unit 200 . In addition, the address of the host memory unit 200 pointed to by the pointer includes a source address at which data is stored in the host memory unit 200 , a target address to which data is to be written in the target memory unit 2000 , and the host memory unit 200 . At least one of capacity information of data to be read from may be recorded, but is not limited thereto.

The operation unit 300 , also referred to as a host or a central processing unit, is a configuration that manages or controls overall operations of the memory access control system 1000 . The operation unit 300 may be implemented by a memory for storing instructions programmed to perform various functions and a microprocessor for executing these instructions.

The memory access control apparatus 100 is configured to manage or control DMA, that is, direct memory access. The memory access control apparatus 100 may include a controller programmed to perform various functions to be described below.

More specifically, the memory access control apparatus 100 performs the first control and the second control through the control unit.

Among them, the first control receives a first source address among the source addresses in the host memory unit 200 and a first target address among the target addresses in the target memory unit 2000, and the region indicated by the first source address. It may include moving the data stored in the first target address to the area indicated. In this case, the first source address and the first target address may be received from the operation unit 300 . In addition, along with the first source address and the first target address, information on the capacity of data to be moved may be received from the operation unit 300 . In this case, the data to be moved may be data previously designated as to be moved relatively first in the data movement situation, for example, when a movement order is assigned to each data, a predetermined number or Data up to a predetermined capacity may be designated. 2 exemplarily illustrates the above-described first source address, first target address, and capacity information.

That is, according to the first control, data movement is performed according to the first source address, the first target address, and the capacity information received from the operation unit 300 , which corresponds to the direct address method in DMA.

Here, the first source address, the first target address, and the capacity information are information related to the first control, respectively, and the calculation unit 300 calculates the above-described distribution/collection information stored in the host memory unit 200 . After loading, it may be that transformations are created using them. For example, the operation unit 300 designates information to be moved relatively initially among the distributed/collected information stored in the host memory unit 200 by a predetermined capacity, and then uses the designated information as the first source address, the first Target address and capacity information can be transformed and generated. Here, the predetermined capacity may be determined according to the performance of the system.

Meanwhile, the second control receives predetermined pointer information, fetches a second source address among the source addresses and a second target address among the target addresses from an area indicated by the pointer information, and the second source address and moving data stored in the area indicated by , to the area indicated by the second target address. In this case, the pointer information may be received from the host memory unit 200 . In addition, the second source address and the second target address may be obtained from an area of the host memory unit 200 indicated by the pointer information.

That is, according to the second control, data movement is performed based on pointer information received from the host memory unit 200 , which corresponds to an indirect address method among DMAs.

3 conceptually illustrates that the memory access control apparatus 100 performs the above-described first control and second control through such a control unit. Here, since FIG. 3 is merely exemplary, the spirit of the present invention is not construed as being limited to that illustrated in FIG. 3 .

Referring to FIG. 3 , the operation unit 300 transmits a command to the memory access control device 100 to move or transmit at least a portion of data stored in the host memory unit 200 to the target memory unit 2000 ( S10 ). .

At this time, according to an embodiment, distribution/collection information along with such a command may be transmitted from the operation unit 300 to the memory access control apparatus 100 . The distribution/collection information transmitted in S10 may include a first source address, a first target address, and capacity information.

Then, the control unit of the memory access control apparatus 100 acquires data from the host memory unit 200 based on the aforementioned distribution/collection information, and then moves the acquired data to the target memory unit 2000 for a first control (S20, S30). In this case, the moved data may include data corresponding to the capacity information from data stored in the area indicated by the first source address. That is, the first control corresponds to a direct address method among DMAs.

Next, the control unit of the memory access control device 100 receives the distribution/collection information 210 from the host memory unit 200 ( S20 ), and the pointer information included in the distribution/collection information 210 is The second source address and the second target address are fetched from the indicated area, and the data 220 and 230 stored in the area indicated by the second source address are moved to the area 2020 and 2030 indicated by the second target address. 2 is performed (S40, S50). In this case, the moved data may include data corresponding to the capacity information from data stored in the area indicated by the second source address. That is, the second control corresponds to an indirect address method among DMAs.

Meanwhile, the first operation and the second operation described above may be performed for each of a plurality of channels provided in the memory access control apparatus 100 , which will be described with reference to FIG. 4 .

4 is a schematic conceptual diagram of data or information flow in the memory access control system 1000 according to an embodiment. However, since FIG. 4 is merely exemplary, the spirit of the present invention is not limited to that illustrated in FIG. 4 .

Before referring to FIG. 4 , the operation unit 300 generates distribution/collection information ( S100 ). Such distributed/collected information may be generated by being acquired from the host memory unit 200, but is not limited thereto. In addition, the generated distributed/collected information may be generated for each of a plurality of channels provided in the access control apparatus 100 .

Here, the 'channel' refers to a logically or physically distinguishable path used for data transmission.

Next, the operation unit 300 generates a command for each channel ( S110 ). Such a command may include an operation of moving at least a portion of data stored in the host memory unit 200 to the target memory unit 2000 .

Thereafter, the distribution/collection information generated in S100 and the command generated in S110 are transmitted from the operation unit 300 to the memory access control apparatus 100 for each channel ( S120 ).

Then, the memory access control apparatus 100 starts DMA through the control unit ( S200 ).

More specifically, the operation of moving/copying data ( S210 ) is performed based on the information received in S120 . After that, the operation of determining whether an additional command is necessary (S220), if it is determined that an additional command is necessary, loading a new command (S230) so that the new command is operated, otherwise, the operation of moving to S240, It is performed for each of a plurality of channels.

Here, the operation according to S230 may be performed according to the same method used for the indirect address method in DMA. For example, in case of high-performance user logic using basic high-bandwidth, it is composed of multi-form outstanding requests. In this case, some address fetches in the middle of operation (that is, loading additional commands) can be hidden from other requests. there is.

If it is determined in S220 that an additional command is not required in all of the plurality of channels, the control unit of the memory access control apparatus 100 generates an interrupt ( S240 ).

The interrupt generated in S240 is transmitted to the operation unit 300 (S250), and the operation unit 300 organizes the DMA job (S300).

As described above, according to an embodiment, DMA is initially performed according to the direct address method based on the distribution/collection information received from the operation unit, and thereafter, the address is determined based on the pointer information obtained from the host memory unit. After acquisition, DMA is performed according to the indirect address method based on this. That is, in the beginning, data movement can be performed immediately by using the address received from the operation unit, and thus, the time required for address fetching in the indirect address method is not consumed in one embodiment. The performance of the memory access control system may be improved.

FIG. 5 exemplarily illustrates performance improvement in the memory access control system 1000 according to this embodiment. Referring to FIG. 5 , it can be seen that the memory access control system 1000 does not initially take time for address fetching. In addition, the timing at which the DMA operation is performed in each of the plurality of channels may also be unified. In addition, as a single DMA setting, operation types of several channels may be supported in a burst form. Accordingly, by maximizing the utilization of expensive hardware and suppressing the waste of resources, the performance of the entire system may be improved.

Meanwhile, the memory access control method according to an embodiment may be performed by the above-described memory access control apparatus 100 , and such a control method includes the first source address among the source addresses in the host memory unit and the target memory unit. receiving a first target address among target addresses; performing a first control of moving data stored in an area indicated by the first source address to an area indicated by the first target address; receiving; acquiring a second source address among the source addresses and a second target address among the target addresses from an area indicated by the pointer information; and transferring data stored in the area indicated by the second source address to the second It may be performed including moving to an area indicated by the target address.

In addition, as for the control method, the above-described information on the memory access control apparatus 100 may be referred to, and thus a description of the overlapping portion will be omitted.

In addition, in the case of the above-described control method, a computer program storing a computer program stored in a computer-readable recording medium programmed to perform each step included in the above-described management method or a computer program programmed to perform each step of the method It can be implemented in the form of a readable recording medium.

The above description is merely illustrative of the technical idea of the present invention, and various modifications and variations will be possible without departing from the essential quality of the present invention by those skilled in the art to which the present invention pertains. Therefore, the embodiments disclosed in the present invention are not intended to limit the technical spirit of the present invention, but to explain, and the scope of the technical spirit of the present invention is not limited by these embodiments. The protection scope of the present invention should be interpreted by the following claims, and all technical ideas within the scope equivalent thereto should be interpreted as being included in the scope of the present invention.

According to an embodiment, DMA is initially performed according to the direct address method based on the distribution/collection information received from the operation unit, and after that, the address is obtained based on the pointer information obtained from the host memory unit and based on this DMA is performed according to an indirect addressing scheme. That is, in the beginning, data movement can be performed immediately by using the address received from the operation unit, and thus, the time required for address fetching in the indirect address method is not consumed in one embodiment. The performance of the memory access control system may be improved.

1000: computational accelerator

Claims (11)

A memory access control device comprising a control unit, comprising:
The control unit is
The first target address receives data stored in an area indicated by the first source address by receiving a first source address among the source addresses in the host memory unit and the first target address among the target addresses in the target memory unit from the operation unit. performing a first control of moving to an area,
Receives predetermined pointer information directly from the host memory unit to obtain a second source address among the source addresses and a second target address among the target addresses from an area indicated by the pointer information, and a region indicated by the second source address performing a second control of moving the data stored in the second target address to the area indicated by the
Memory access control unit. The method of claim 1,
The control unit is
receiving additional capacity information of data to be read from the first source address, and moving data as much as the capacity information through the first control
Memory access control unit. The method of claim 1,
The control unit is
receiving additional data capacity information to be read from the second source address from the area indicated by the pointer information, and moving data corresponding to the capacity information through the second control
Memory access control unit. delete The method of claim 1,
A plurality of channels on which the first control and the second control are performed are provided in the memory access control device,
The timing at which the first control is performed in each of the plurality of channels is the same
Memory access control unit. The method of claim 1,
The control unit is
performing the second control after performing the first control
Memory access control unit. The method of claim 1,
The first source address and the first target address are,
Information on data of a predetermined capacity that needs to be moved relatively first is generated based on extraction from distribution/collection information stored in the host memory unit,
The second control is
This is performed after the data of the capacity is moved from the area indicated by the first source address to the area indicated by the first target address according to the first control.
Memory access control unit. As a memory access control method performed by a control unit of a memory access control device,
Receiving a first target address from among the source addresses in the host memory unit and the target address in the target memory unit from the operation unit;
performing a first control of moving data stored in the area indicated by the first source address to the area indicated by the first target address;
receiving predetermined pointer information directly from the host memory unit;
obtaining a second source address among the source addresses and a second target address among the target addresses from the area indicated by the pointer information;
moving data stored in the area indicated by the second source address to the area indicated by the second target address
How to control memory access. A computer-readable recording medium storing a computer program programmed to perform including each step included in the control method according to claim 8. A computer program stored in a computer-readable recording medium programmed to perform including each step included in the control method according to claim 8. arithmetic unit,
host memory;
A first source address among the source addresses in the host memory unit and a first target address among the target addresses in the target memory unit are received from the operation unit, and data stored in an area indicated by the first source address is converted to the first target address. performs a first control of moving to an area indicated by , receives predetermined pointer information directly from the host memory unit, and receives a second source address among the source addresses and a second target among the target addresses from the area indicated by the pointer information A control unit that acquires an address and performs a second control of moving data stored in the area indicated by the second source address to the area indicated by the second target address
Memory access control system.

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