CN110321260B - Uvm-based AXI bus interface read-write data comparison method and UVM verification platform - Google Patents

Uvm-based AXI bus interface read-write data comparison method and UVM verification platform Download PDF

Info

Publication number
CN110321260B
CN110321260B CN201910577515.0A CN201910577515A CN110321260B CN 110321260 B CN110321260 B CN 110321260B CN 201910577515 A CN201910577515 A CN 201910577515A CN 110321260 B CN110321260 B CN 110321260B
Authority
CN
China
Prior art keywords
read
write
axi
data
queue
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201910577515.0A
Other languages
Chinese (zh)
Other versions
CN110321260A (en
Inventor
董方旭
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Xian Unilc Semiconductors Co Ltd
Original Assignee
Xian Unilc Semiconductors Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Xian Unilc Semiconductors Co Ltd filed Critical Xian Unilc Semiconductors Co Ltd
Priority to CN201910577515.0A priority Critical patent/CN110321260B/en
Publication of CN110321260A publication Critical patent/CN110321260A/en
Application granted granted Critical
Publication of CN110321260B publication Critical patent/CN110321260B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G06F11/261—Functional testing by simulating additional hardware, e.g. fault simulation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

In order to overcome the technical problem that the design of the existing read-write data comparison scheme is complex, the invention provides an AXI bus interface data read-write comparison method based on UVM and a UVM verification platform, and the invention comprises the following steps: writing the effective write data according to the write address, the write bit width and the write strobe information of the write burst data cycle; in the data reading link: firstly, acquiring a read command identity according to the read data identity, then performing read operation on effective read data according to a read address and a read bit width corresponding to the read command identity, and finally judging the read data.

Description

Uvm-based AXI bus interface read-write data comparison method and UVM verification platform
Technical Field
The invention belongs to the technical field of chip verification, and relates to an AXI bus interface read-write data comparison method based on UVM and a UVM verification platform.
Background
Building a Universal Verification Methodology (UVM) Verification environment to perform an IP (Intellectual Property module) simulation of an AXI (Advanced eXtensible bus Interface) bus Interface, where comparing read and write data of the IP AXI bus Interface is one of the most basic and key inspection mechanisms of the UVM Verification environment, and the method is mainly used for: the smoke test of environment debugging can help a verifier to debug the environment and verify whether the basic circuit of the circuit is correct; in the process of various operations or after the operations are finished, the method is used for checking whether the influence is caused on the data path; help find out the design defect of the bus slave device module; and debugging the conflict mechanism of the read-write path and other operations.
The conventional read-write data comparison principle is shown in fig. 1, in which a monitor captures read and write data streams from an AXI interface component, transfers the read and write data streams to a reference model for processing, and finally performs statistical comparison in a score board to print information of pass (i.e., correct data read from an AXI bus interface) or fail (i.e., incorrect data read from an AXI bus interface). It has the following disadvantages:
1. the reference model and the score board are complex in design and long in development time, and are not easy to be quickly integrated and applied to a platform.
2. A large static storage needs to be defined, and in the simulation process, a fixed memory resource needs to be permanently allocated to the static storage by the simulator, which causes great waste of the memory resource.
3. The read commands may be reordered inside the circuit, and a complex reordering processing logic similar to the functional IP circuit to be verified needs to be added in the reference model, so that the design is very complex.
Disclosure of Invention
In order to overcome the technical problem that the design of the existing read-write data comparison scheme is complex, the invention provides an AXI bus interface data read-write comparison method based on UVM and a UVM verification platform.
The technical scheme of the invention is as follows:
an AXI bus interface read-write data comparison method based on UVM is characterized by comprising the following steps:
in the data writing link:
writing the effective write data according to the write address, the write bit width and the write strobe information of the write burst data cycle;
in the data reading link:
in the data reading link:
firstly, acquiring a read command identity according to the read data identity, then performing read operation on effective read data according to a read address and a read bit width corresponding to the read command identity, and finally judging the read data.
Further, in the data writing link:
the writing operation of the effective write data according to the write address, the write bit width and the write strobe information of the write burst data cycle is as follows:
1.1 In a write command cycle), pressing a write address into an AXI write address queue and pressing a write bit width into an AXI write bit width flag queue;
1.2 In each write burst data cycle of the AXI, taking out a corresponding write address and a write bit width from an AXI write address queue and an AXI write bit width flag queue respectively;
1.3 According to the write bit width taken out in the step 1.2) and the write strobe information of the write burst data period, taking out effective write data bytes from write data, and calculating effective write addresses corresponding to the effective write data bytes according to the write addresses taken out in the step 1.2);
1.4 Store each valid write address and its corresponding valid write data byte as an element in the AXI memory;
in the data reading link:
the reading operation of the valid data according to the reading address, the reading bit width and the reading command identity is as follows:
2.1 In a read command cycle, a read address is pressed into an AXI read address queue, a read bit width is pressed into an AXI read bit width mark queue, and a read command identity is pressed into an AXI read command identity identification queue;
2.2 In each read burst data cycle of the AXI, searching a first queue index corresponding to a read command identity identifier equal to the read command identity identifier from an AXI read command identity identifier queue according to the read data identity identifier, and deleting an element corresponding to the first queue index after obtaining the first queue index;
2.3 According to the first queue index, finding out corresponding read address information from an AXI read address queue, finding out corresponding read bit width information from an AXI read bit width flag queue, then deleting an element corresponding to the read address information from the AXI read address queue, and deleting an element corresponding to the read bit width information from the AXI read bit width flag queue;
2.4 According to the read bit width information obtained in the step 2.3), effective read data bytes are taken out from the read data, and effective read addresses corresponding to the effective read data bytes are calculated according to the read address information obtained in the step 2.3);
2.5 According to the effective read address information obtained in the step 2.4), finding out corresponding data in the AXI memory;
2.6 ) determination of the read data.
Further, 2.6) the determination of the read data is:
and on the valid read data clock edge, comparing the data read out from the AXI bus interface of the design to be tested with the data found out from the AXI memory in the step 2.5), wherein the data read out from the AXI bus interface is correct if the data are equal to each other, and the data read out from the AXI bus interface is incorrect if the data are not equal to each other.
Further, in the step 2.2), the lookup is from the top to the bottom of the AXI read command identity queue.
Further, the write address, the read address, the write bit width, the read bit width, and the read command identification
When pushing into a queue: pressing in from the bottom of the queue; when taking out: pop from the top of the queue or pop according to an index.
Furthermore, the data bit width stored in the AXI memory used in the writing and reading links is the same as the byte bit width.
Further, the first queue index is of integer type.
Further, in step 1.4), for each element stored in the AXI memory, the emulator dynamically allocates a block of memory space for the element.
Further, the AXI memory is an associative array.
Further, the AXI write address queue, the AXI write bit width flag queue, the AXI read address queue, the AXI read bit width flag queue, the AXI read command identity identification queue, and the associated array are all implemented using an object-oriented high-level language.
The invention also provides a UVM verification platform, which comprises an AXI main equipment environment; the AXI master device environment includes a monitor, a driver, and a sequencer; it is characterized in that: the monitor is integrated with a computer program, and the computer program is used for realizing the above-mentioned UVM-based AXI bus interface read-write data comparison method when being run by a processor.
The invention has the beneficial effects that:
1. the invention utilizes the powerful indexing and element searching functions of the queue, solves the comparison mechanism obstacle caused by the rearrangement of the circuit to the command, and greatly reduces the complexity of the design of the comparison mechanism.
2. The invention stores and reads data by using the object-oriented high-level language queue and the association array, has concise and high-efficiency design and is convenient for quick integration and application.
3. The invention introduces the associated array, and the simulator carries out dynamic discontinuous address space distribution on the associated array in the simulation process, thereby greatly reducing the consumption of memory resources in the simulation process.
4. The AXI read-write comparison method is arranged in a monitor, and the development of environment components (a reference model and a score board) is omitted, so that the workload of design and development is reduced, and the UVM top layer can manage the AXI read-write comparison method conveniently.
Drawings
Fig. 1 is a schematic diagram of a conventional AXI bus interface read/write data comparison scheme.
Fig. 2 is a schematic diagram of the write data operation of the AXI bus interface of the present invention.
Fig. 3 is a schematic diagram illustrating the principle of reading data operation and comparing read data and write data of the AXI bus interface according to the present invention.
Fig. 4 is an integration scheme diagram of the comparison method for reading and writing data of the AXI bus interface according to the present invention.
Detailed Description
The invention is further described below with reference to the accompanying drawings.
The UVM-based AXI bus interface read-write data comparison method comprises a data writing link and a data reading link.
Referring to fig. 2, the processing procedure of the data writing link is as follows:
step 1.1), in a write command cycle, pressing a write address into an AXI write address queue, and pressing a write bit width into an AXI write bit width mark queue.
Step 1.2): in each write burst data cycle of the AXI, the corresponding write address and write bit width are taken out from the AXI write address queue and the AXI write bit width flag queue respectively.
Step 1.3) according to the write bit width taken out in step 1.2) and the write strobe information of the write burst data cycle, effective write data bytes are taken out from the write data, and effective write addresses corresponding to the effective write data bytes are calculated according to the write addresses taken out in step 1.2).
Step 1.4) storing each effective write address and the corresponding effective write data byte as an element in an associated array; for each element stored in the associated array, the emulator dynamically allocates a block of memory space for the element.
Referring to fig. 3, the processing procedure of the data reading link is as follows:
step 2.1): in a read command cycle, a read address is pressed into an AXI read address queue, a read bit width is pressed into an AXI read bit width mark queue, and a read command identity is pressed into an AXI read command identity mark queue.
Step 2.2): in each burst data reading period of the AXI, a first queue index corresponding to a read command identity identifier equal to the read data identity identifier is searched from an AXI read command identity identifier queue according to the read data identity identifier, and after the queue index is obtained, an element corresponding to the index is deleted. In the searching process, searching is performed from the top to the bottom of the AXI read command identity identification queue, and when a first read command identity identical to the read data identity is searched, the corresponding index is the first index.
Step 2.3): according to the first queue index, searching corresponding read address information from the AXI read address queue, then deleting an element corresponding to the read address in the AXI read address queue, searching corresponding read bit width information from the AXI read bit width mark queue, and then deleting the element corresponding to the read bit width in the AXI read bit width mark queue.
Step 2.4): and taking out effective read data bytes from the read data according to the read bit width information obtained in the step 2.3), and calculating effective read addresses corresponding to the effective read data bytes according to the read address information obtained in the step 2.3).
Step 2.5): and finding out corresponding data from the association array according to the effective read address obtained in the step 2.4).
Step 2.6): and on a valid read data clock edge, comparing the data read out from the AXI bus interface of the Design Under Test (DUT) with the data found out from the associated array in the step 2.5), wherein the data read out from the AXI bus interface of the Design Under Test (DUT) is correct if the data are equal, and otherwise, the data read out from the AXI bus interface of the Design Under Test (DUT) is wrong.
The "valid write data byte" and the "valid read data byte" related in the above steps have clear and definite provisions in the AXI protocol, specifically, when the level of the AXI clock signal aclk transitions from low to high, and both the interface signals rvatid and rready are high, the read data is valid, and when both the interface signals wvalidd and wready are high, the write data is valid.
The steps are as follows: the read command identity is pressed in from the bottom of the queue when being pressed in the queue, and is popped out from the top of the queue or is taken out according to an index when being taken out, namely, the read command identity can be taken out firstly according to an advanced queue or taken out according to the index. The associated arrays used in the writing and reading links are the same associated array, the data bit width stored in the associated array is the same as the byte bit width (8 bit), and the first queue index is int type (integer type).
As shown in fig. 4, since the monitor is connected to the AXI interface component and is a member of the UVM tree organization, the AXI read-write comparison method (AXI _ RD _ WR _ check) of the present invention may be integrated into the monitor in the form of a plug-in, so as to omit components in the AXI master device environment, that is, omit a reference model and a scoreboard, and facilitate management of the AXI read-write comparison method by the top layer of the UVM verification platform.

Claims (9)

1. An AXI bus interface read-write data comparison method based on UVM is characterized by comprising the following steps:
in the data writing link:
writing the effective write data according to the write address, the write bit width and the write strobe information of the write burst data cycle;
in the data reading link:
firstly, acquiring a read command identity according to a read data identity, then performing read operation on effective read data according to a read address and a read bit width corresponding to the read command identity, and finally judging the read data;
in the data writing link:
the writing operation of the effective write data according to the write address, the write bit width and the write strobe information of the write burst data cycle is as follows:
1.1 In a write command cycle), pressing a write address into an AXI write address queue and pressing a write bit width into an AXI write bit width flag queue;
1.2 In each write burst data cycle of the AXI, taking out a corresponding write address and a write bit width from an AXI write address queue and an AXI write bit width flag queue respectively;
1.3 According to the write bit width taken out in the step 1.2) and the write strobe information of the write burst data cycle, taking out effective write data bytes from write data, and calculating effective write addresses corresponding to the effective write data bytes according to the write addresses taken out in the step 1.2);
1.4 Store each valid write address and its corresponding valid write data byte as an element in the AXI memory;
in the data reading link:
the reading operation of the effective data according to the reading address, the reading bit width and the reading command identity is as follows:
2.1 In a read command cycle, pressing a read address into an AXI read address queue, pressing a read bit width into an AXI read bit width mark queue, and pressing a read command identity into an AXI read command identity mark queue;
2.2 In each read burst data cycle of the AXI, searching a first queue index corresponding to a read command identity identifier equal to the read command identity identifier from an AXI read command identity identifier queue according to the read data identity identifier, and deleting an element corresponding to the first queue index after obtaining the first queue index;
2.3 According to the first queue index, finding out corresponding read address information from an AXI read address queue, finding out corresponding read bit width information from an AXI read bit width flag queue, then deleting an element corresponding to the read address information from the AXI read address queue, and deleting an element corresponding to the read bit width information from the AXI read bit width flag queue;
2.4 According to the read bit width information obtained in the step 2.3), effective read data bytes are taken out from the read data, and effective read addresses corresponding to the effective read data bytes are calculated according to the read address information obtained in the step 2.3);
2.5 According to the effective read address information obtained in the step 2.4), finding out corresponding data in the AXI memory;
2.6 Judgment of read data;
wherein the determination of the read data is:
and comparing the data read out from the AXI bus interface of the design under test with the data found from the AXI memory on the effective read data clock edge, wherein the data read out from the AXI bus interface is correct if the data read out from the AXI bus interface is equal to the data found from the AXI memory, and otherwise, the data read out from the AXI bus interface is incorrect.
2. The UVM-based AXI bus interface read-write data comparison method of claim 1, wherein:
in the step 2.2), the lookup is from the top of the AXI read command identity queue to the bottom.
3. The UVM-based AXI bus interface read-write data comparison method of claim 1, wherein:
the write address, the read address, the write bit width, the read bit width and the read command identity identification
When pushing into a queue: pressing in from the bottom of the queue;
when taking out: pop from the top of the queue or pop according to an index.
4. The UVM-based AXI bus interface read-write data comparison method of claim 1, wherein:
the data bit width stored in the AXI memory used in the writing and reading links is the same as the byte bit width.
5. The UVM-based AXI bus interface read-write data comparison method of claim 1, wherein:
the first queue index is of integer type.
6. The UVM-based AXI bus interface read-write data comparison method of claim 1, wherein: in step 1.4), each time an element is stored in the AXI memory, the emulator dynamically allocates a block of memory space for the element.
7. The UVM-based AXI bus interface read-write data comparison method of claim 1, wherein: the AXI memory is an associative array.
8. The UVM-based AXI bus interface read-write data comparison method of claim 7, wherein: the AXI write address queue, the AXI write bit width mark queue, the AXI read address queue, the AXI read bit width mark queue, the AXI read command identity identification queue and the association array are all realized by an object-oriented high-level language.
9. A UVM verification platform comprising an AXI master device environment; the AXI master device environment includes a monitor, a driver, and a sequencer; the method is characterized in that: a computer program is integrated in the monitor, and when the computer program is executed by a processor, the computer program is used for implementing the UVM-based AXI bus interface read-write data comparison method as claimed in any one of claims 1 to 8.
CN201910577515.0A 2019-06-28 2019-06-28 Uvm-based AXI bus interface read-write data comparison method and UVM verification platform Active CN110321260B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201910577515.0A CN110321260B (en) 2019-06-28 2019-06-28 Uvm-based AXI bus interface read-write data comparison method and UVM verification platform

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201910577515.0A CN110321260B (en) 2019-06-28 2019-06-28 Uvm-based AXI bus interface read-write data comparison method and UVM verification platform

Publications (2)

Publication Number Publication Date
CN110321260A CN110321260A (en) 2019-10-11
CN110321260B true CN110321260B (en) 2023-03-24

Family

ID=68120774

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201910577515.0A Active CN110321260B (en) 2019-06-28 2019-06-28 Uvm-based AXI bus interface read-write data comparison method and UVM verification platform

Country Status (1)

Country Link
CN (1) CN110321260B (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112286746B (en) * 2020-10-31 2023-01-24 拓维电子科技(上海)有限公司 Universal verification platform and method for AXI slave device interface
CN112527705B (en) * 2020-11-05 2023-02-28 山东云海国创云计算装备产业创新中心有限公司 PCIe DMA data path verification method, device and equipment
CN113434544B (en) * 2021-06-02 2022-11-18 中科驭数（北京）科技有限公司 Database data reading method, database data writing method and device
CN114546900A (en) * 2022-01-21 2022-05-27 山东云海国创云计算装备产业创新中心有限公司 Method, system, equipment and storage medium for verifying MCTP controller

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1959661A (en) * 2006-11-21 2007-05-09 北京中星微电子有限公司 Bus interface devices and method
CN102004709A (en) * 2009-08-31 2011-04-06 国际商业机器公司 Bus bridge between processor local bus (PLB) and advanced extensible interface (AXI) and mapping method
WO2012019475A1 (en) * 2010-08-13 2012-02-16 中兴通讯股份有限公司 Access control method and device for reduced latency dynamic random access memory with separate input/output (rldram sio)
CN104750633A (en) * 2013-12-30 2015-07-01 重庆重邮信科通信技术有限公司 Field programmable gate array (FPGA) device access verification device and method
CN105159853A (en) * 2015-09-25 2015-12-16 中国船舶重工集团公司第七0九研究所 DFI standard DDR3 controller based on FPGA
CN105468547A (en) * 2015-11-18 2016-04-06 哈尔滨工业大学 AXI bus based convenient configurable frame data access control system
CN109828941A (en) * 2019-03-06 2019-05-31 苏州浪潮智能科技有限公司 AXI2WB bus bridge implementation method, device, equipment and storage medium

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7457905B2 (en) * 2005-08-29 2008-11-25 Lsi Corporation Method for request transaction ordering in OCP bus to AXI bus bridge design

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1959661A (en) * 2006-11-21 2007-05-09 北京中星微电子有限公司 Bus interface devices and method
CN102004709A (en) * 2009-08-31 2011-04-06 国际商业机器公司 Bus bridge between processor local bus (PLB) and advanced extensible interface (AXI) and mapping method
WO2012019475A1 (en) * 2010-08-13 2012-02-16 中兴通讯股份有限公司 Access control method and device for reduced latency dynamic random access memory with separate input/output (rldram sio)
CN104750633A (en) * 2013-12-30 2015-07-01 重庆重邮信科通信技术有限公司 Field programmable gate array (FPGA) device access verification device and method
CN105159853A (en) * 2015-09-25 2015-12-16 中国船舶重工集团公司第七0九研究所 DFI standard DDR3 controller based on FPGA
CN105468547A (en) * 2015-11-18 2016-04-06 哈尔滨工业大学 AXI bus based convenient configurable frame data access control system
CN109828941A (en) * 2019-03-06 2019-05-31 苏州浪潮智能科技有限公司 AXI2WB bus bridge implementation method, device, equipment and storage medium

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
PCIE3.0接口的SSD硬盘的FPGA实现;宋鹏程等;《微电子学与计算机》;20171231;第34卷(第12期);全文 *
Verification of memory transactions in AXI protocol using system verilog approach;G. Mahesh等;《IEEE Xplore》;20151112;全文 *
支持流水传输的AXI4主机转换接口设计;易清明等;《计算机工程》;20160415;第42卷(第04期);全文 *
面向电子控制器的片上可调试性结构设计;陈芳芳等;《电子器件》;20180630;第41卷(第3期);全文 *

Also Published As

Publication number Publication date
CN110321260A (en) 2019-10-11

Similar Documents

Publication Publication Date Title
CN110321260B (en) Uvm-based AXI bus interface read-write data comparison method and UVM verification platform
CN115841089B (en) System-level chip verification platform and verification method based on UVM
CN114528792B (en) Chip verification method and device, electronic equipment and storage medium
CN112417798B (en) Time sequence testing method and device, electronic equipment and storage medium
CN1801155A (en) Method for combination of original files of hardware design language and checking data files
CN113486625B (en) Chip verification method and verification system
CN115146568B (en) Chip verification system and verification method based on UVM
CN116256621B (en) Method and device for testing core particle, electronic equipment and storage medium
CN102981949A (en) Method for on-line automatic tests of server
CN101923494B (en) Memory controller verification system, method and scoreboard
CN102053898A (en) Method for testing bus interface on PCIE (Peripheral Component Interface Express) slot of host and read-write test method thereof
CN117076337B (en) Data transmission method and device, electronic equipment and readable storage medium
US7055116B2 (en) Assertion-based transaction recording
CN115470125B (en) Log file-based debugging method, device and storage medium
CN112861455B (en) FPGA modeling verification system and method
US6536020B2 (en) Efficient generation of optimum test data
CN107729601B (en) Method and device for configuring RAM in simulation process and computer storage medium
CN115952084A (en) Method and system for verifying access component
CN116070564A (en) Simulation communication method and device based on chip to-be-tested design
CN112463633B (en) Method, device, equipment and medium for checking address decoding of on-chip memory
CN109582523B (en) Method and system for effectively analyzing performance of NVMe (network video recorder) module at front end of SSD (solid State drive)
CN111258838B (en) Verification component generation method, device, storage medium and verification platform
CN112613257A (en) Verification method, verification device, electronic equipment and computer-readable storage medium
US9547568B2 (en) Method and apparatus for verifying circuit design
CN116842902B (en) System-level simulation modeling method for black box model

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant