CN112527705B - PCIe DMA data path verification method, device and equipment - Google Patents

PCIe DMA data path verification method, device and equipment Download PDF

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CN112527705B
CN112527705B CN202011224586.1A CN202011224586A CN112527705B CN 112527705 B CN112527705 B CN 112527705B CN 202011224586 A CN202011224586 A CN 202011224586A CN 112527705 B CN112527705 B CN 112527705B
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dma
pcie
packet
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tlp packet
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CN112527705A (en
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曹铸
邵海波
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Shandong Yunhai Guochuang Cloud Computing Equipment Industry Innovation Center Co Ltd
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Shandong Yunhai Guochuang Cloud Computing Equipment Industry Innovation Center Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0026—PCI express

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Abstract

The application discloses a PCIe DMA data path verification method, which is applied to a verification platform and can establish a PCIe Host and a port connection of the verification platform based on a UVM TLM communication technology, so that a TLP packet written in a remote memory space by a DMA is obtained through the port connection, actual write data is extracted according to effective information of the TLP packet head, and finally the correctness of the PCIe DMA data path is verified by comparing local original write data and the actual write data, thereby overcoming the limitation of DMA read-write operation trigger sequence and access address in a verification environment and remarkably improving the flexibility of a PCIe DMA data path verification scheme. In addition, the application also provides a verification device, equipment and a readable storage medium of the PCIe DMA data path, and the technical effect of the verification device corresponds to that of the method.

Description

PCIe DMA data path verification method, device and equipment
Technical Field
The present application relates to the field of computer technologies, and in particular, to a method, an apparatus, a device, and a readable storage medium for verifying a PCIe DMA data path.
Background
Currently, PCIe is widely used in large scale integrated circuit design. In front-end authentication for SoC (System on Chip) with PCIe devices, authentication for PCIe DMA (Direct Memory Access) is crucial, because the most commonly used function in PCIe controllers for processing large-scale data in bulk is DMA.
The PCIe DMA data path verification scheme commonly used at present simultaneously verifies a read-write data path, and the specific verification process is as follows: sending a write instruction at the equipment end of the data path, and writing a section of known data into a known address space at the host end of the data path; sending a read command from the equipment end and reading data from the host end, wherein the address is the address of the last write command; finally, comparing the two data; if the comparison is successful, the read-write data path is proved to have no problem; otherwise, the read or write data path is proven to be abnormal.
There are two limitations to this authentication scheme: firstly, each triggering of a DMA read operation must occur after the corresponding DMA write operation is completely completed, so the requirements of random testing and stress testing in verification cannot be achieved one hundred percent; second, each DMA read operation must have an address range less than or equal to that of the corresponding write operation, and if the address of the read operation exceeds the address range of the corresponding write operation, the read-back data may also be zero or data that is not written this time.
In summary, in the prior art, the verification scheme for the PCIe DMA data path has limitations on the DMA read-write operation trigger sequence and the access address, which results in poor scheme flexibility.
Disclosure of Invention
The application aims to provide a method, a device, equipment and a readable storage medium for verifying a PCIe DMA data path, which are used for solving the problem that the flexibility of a scheme is poor due to the limitation of DMA read-write operation triggering sequence and access addresses in the conventional verification scheme aiming at the PCIe DMA data path. The specific scheme is as follows:
in order to solve the above technical problem, the present application provides a method for verifying a PCIe DMA data path, which is applied to a verification platform and includes:
s1, establishing port connection between a PCIe Host and a verification platform based on a TLM communication technology of UVM;
s2, sending a DMA write instruction to a PCIe Host, wherein the DMA write instruction carries original write data;
s3, judging whether the PCIe Host receives the TLP packet, and if so, entering S4;
s4, acquiring the TLP packet through the port connection;
s5, judging whether the TLP packet is a DMA write instruction; if so, extracting a data load carried by the TLP packet according to the packet header information of the TLP packet to obtain actual write data;
s6, comparing the original write data with the actual write data; if the comparison result is consistent, the PCIe DMA data writing path is judged to pass the verification, otherwise, the verification is judged not to pass.
Preferably, the establishing a PCIe Host port connection with the verification platform by the UVM-based TLM communication technology includes:
creating a first port and a second port in the UVM component;
establishing connection between the first port and a receiving packet transmission port of a VIP component in a PCIe Host and establishing connection between the second port and a sending packet transmission port of the VIP component in the PCIe Host based on TLM communication technology of UVM;
creating a write function in the first port and the second port respectively, where the write function of the first port is configured to store a TLP packet transmitted by the receive packet transmission port into a first queue, and the write function of the second port is configured to store a TLP packet transmitted by the send packet transmission port into a second queue.
Preferably, the extracting, according to the header information of the TLP packet, the data payload carried by the TLP packet to obtain actual write data includes:
extracting a data load carried by the TLP packet according to the packet header information of the TLP packet; transferring the data load in a byte unit to obtain actual write data; and storing the actual write data into an associated array by taking address information carried by the TLP packet as an index.
Preferably, the determining whether the TLP packet is a DMA write instruction includes:
judging whether the TLP packet is a DMA write instruction or a DMA read instruction according to a first field of the TLP packet;
if yes, judging whether the TLP packet is a DMA write instruction or not according to a second field of the TLP packet.
Preferably, the method further comprises the following steps:
constructing an interrupt program of PCIe DMA;
generating an interrupt indication signal when the PCIe DMA data writing path finishes the writing operation;
according to the captured interrupt indication signal, determining the number of PCIe DMA data writing paths which finish the writing operation at present; and enabling a corresponding number of processes to run the interrupt program in parallel, and executing S4 to S6.
Preferably, after the UVM-based TLM communication technology establishes a PCIe Host port connection with the verification platform, the method further includes:
sending a DMA read instruction to a PCIe Host;
judging whether the PCIe Host receives a TLP packet, if so, acquiring the TLP packet through the port connection to obtain a first TLP packet; judging whether the first TLP packet is a DMA read instruction, if so, storing the first TLP packet to a first queue;
judging whether the PCIe Host sends out a TLP packet or not, if so, acquiring the TLP packet through the port connection to obtain a second TLP packet; judging whether the second TLP packet is a response packet of a DMA read instruction, if so, storing the second TLP packet to a second queue;
for any first TLP packet in the first queue, matching a corresponding second TLP packet according to TAG information of the first TLP packet, and extracting a data load from the second TLP packet obtained by matching to obtain original read data;
obtaining a response packet fed back by the PCIe Host through a data reading path of the PCIe DMA according to the DMA reading instruction, wherein the response packet carries actual reading data;
comparing the original read data with the actual read data; and if the comparison result is consistent, judging that the PCIe DMA read data path passes verification, otherwise, judging that the verification fails.
In a second aspect, the present application provides an apparatus for validating PCIe DMA data paths, which is applied to a validation platform, and includes:
a connecting module: the method comprises the steps that port connection between a PCIe Host and a verification platform is established based on the TLM communication technology of the UVM;
a write instruction sending module: the system comprises a DMA write instruction, a PCIe Host and a Host, wherein the DMA write instruction carries original write data;
a monitoring module: the PCIe Host is used for judging whether a TLP packet is received or not, and if yes, the PCIe Host enters an acquisition module;
an acquisition module: for obtaining the TLP packet through the port connection;
a data extraction module: the TLP module is used for judging whether the TLP packet is a DMA write instruction or not; if so, extracting a data load carried by the TLP packet according to the packet header information of the TLP packet to obtain actual write data;
a comparison module: for comparing the original write data and the actual write data; and if the comparison result is consistent, judging that the PCIe DMA data writing path passes verification, otherwise, judging that the verification fails.
In a third aspect, the present application provides an apparatus for validating a PCIe DMA data path, comprising:
a memory: for storing a computer program;
a processor: for executing the computer program to implement the PCIe DMA data path validation method as described above.
In a fourth aspect, the present application provides a readable storage medium having stored thereon a computer program for implementing, when executed by a processor, a method for PCIe DMA data path validation as described above.
The application provides a PCIe DMA data path verification method, which is applied to a verification platform and comprises the following steps: establishing port connection between a PCIe Host and a verification platform based on a TLM communication technology of UVM; sending a DMA write instruction to a PCIe Host, wherein the DMA write instruction carries original write data; judging whether the PCIe Host receives a TLP packet, if so, acquiring the TLP packet through port connection; judging whether the TLP packet is a DMA write instruction; if so, extracting a data load carried by the TLP packet according to the packet header information of the TLP packet to obtain actual write data; comparing the original write data with the actual write data; and if the comparison result is consistent, judging that the PCIe DMA data writing path passes verification, otherwise, judging that the verification fails.
Therefore, the method establishes port connection between the PCIe Host and the verification platform based on the TLM communication technology of the UVM, so that a TLP packet written in a remote memory space by the DMA is obtained through the port connection, actual write data is extracted according to effective information of the TLP packet head, and finally the correctness of a PCIe DMA write data path is verified by comparing local original write data and the actual write data, thereby overcoming the limitation of triggering sequence and access address of DMA read-write operation in a verification environment, and remarkably improving the flexibility of a PCIe DMA data path verification scheme.
In addition, the present application also provides a verification apparatus, a device and a readable storage medium for PCIe DMA data paths, where the technical effects correspond to the technical effects of the foregoing methods, and are not described herein again.
Drawings
In order to clearly illustrate the embodiments or technical solutions of the present application, the drawings used in the embodiments or technical solutions of the present application will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 is a schematic diagram of a prior art validation scheme for PCIe DMA data paths;
FIG. 2 is a flow chart of a method for verifying a PCIe DMA write data path provided in the present application;
FIG. 3 is a schematic diagram illustrating a verification scheme for a UVM analysis port connection-based PCIe DMA read-write data path according to the present application;
FIG. 4 is a schematic connection diagram of a UVM Analysis port provided herein;
FIG. 5 is a flow chart of a method for verifying a PCIe DMA read data path provided herein;
FIG. 6 is a functional block diagram of an embodiment of an apparatus for verifying a PCIe DMA data path provided in the present application.
Detailed Description
In order that those skilled in the art will better understand the disclosure, the following detailed description will be given with reference to the accompanying drawings. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments in the present application without making any creative effort belong to the protection scope of the present application.
Fig. 1 is a schematic diagram of a verification scheme for PCIe DMA data path in the prior art, where the verification principle in the prior art is as follows: the equipment end of the data path sends a DMA write instruction, and writes 'original data' into the host end of the data path; then, the device side of the data path sends a DMA read instruction, and reads back the part of data from the host side of the data path, and for convenience of description, the read-back data is referred to as "actual data"; finally, the equipment end of the data path compares the actual data with the local original data; if the comparison result is consistent, the PCIe DMA read-write data path is normal, otherwise, the PCIe DMA read-write data path is abnormal or the PCIe DMA write-data path is abnormal.
As can be seen, the existing verification scheme verifies the read data path and the write data path of the PCIe DMA at the same time, so that the scheme has at least the following two limitations, resulting in low flexibility of the whole scheme:
(1) The read operation must be performed after the write operation is completed.
(2) The read address range must be less than or equal to the write address range.
In order to solve the problem, the application provides a method, a device, equipment and a readable storage medium for verifying a PCIe DMA data path, so that limitations on DMA read-write operation trigger sequence and access addresses in a verification environment are overcome, and flexibility of a PCIe DMA data path verification scheme is significantly improved.
Referring to fig. 2 and 3, a first embodiment of a method for verifying a PCIe DMA data path provided in the present application is described below, where the embodiment is applied to a verification platform, and includes:
s201, establishing port connection between a PCIe Host and a verification platform based on a TLM communication technology of UVM;
s202, sending a DMA write instruction to a PCIe Host, wherein the DMA write instruction carries original write data;
s203, judging whether the PCIe Host receives the TLP packet, if so, entering S204; if not, the PCIe Host is continuously monitored until the PCIe Host receives the TLP packet;
s204, acquiring the TLP packet through port connection;
s205, judging whether the TLP packet is a DMA write instruction; if so, extracting a data load carried by the TLP packet according to the packet header information of the TLP packet to obtain actual write data;
s206, comparing the original write data with the actual write data; and if the comparison result is consistent, judging that the PCIe DMA data writing path passes verification, otherwise, judging that the verification fails.
In this embodiment, the PCIe Host serves as a Host end of the PCIe DMA data path, and the verification platform serves as a device end of the PCIe DMA data path. UVM refers to universal authentication methodology, TLM refers to transaction level modeling, and TLP packets refer to PCIe transaction layer packets.
As shown in fig. 3, the process of establishing a port connection between a PCIe Host and a verification platform by using the UVM-based TLM communication technology specifically includes: a connection is established between an analysis port of the PCIe Host and an analysis imp port of the authentication platform. The analysis port is a port provided by a VIP (authentication IP) component of the PCIe Host, and the analysis imp port is a port provided by a UVM component of the authentication platform. The analysis port is used for monitoring whether the PCIe Host receives or sends out a TLP packet, and when the PCIe Host receives or sends out the TLP packet, the TLP packet is transmitted to an analysis imp port of the verification platform through a pre-established port connection, and the analysis imp port is used for processing the received TLP packet.
In some specific embodiments, the extracting, according to the header information of the TLP packet, the data load carried by the TLP packet to obtain the actual write data may specifically be: extracting a data load carried by the TLP packet according to the packet header information of the TLP packet; transferring the data load in a byte unit to obtain actual write data; and storing the actual write data into the associated array by taking the address information carried by the TLP packet as an index.
In some specific embodiments, the determining whether the TLP packet is a DMA write instruction includes: judging whether the TLP packet is a DMA write instruction or a DMA read instruction according to a first field of the TLP packet; if yes, judging whether the TLP packet is a DMA write instruction according to a second field of the TLP packet.
In practical application, an interrupt program of PCIe DMA can be constructed; generating an interrupt indication signal when the PCIe DMA data writing path finishes the writing operation; determining the number of PCIe DMA data writing paths which finish the writing operation at present according to the interrupt indication signal; and enabling a corresponding number of processes to run the interrupt program in parallel, and executing S204 to S206.
As shown in fig. 4, the analysis port may be further divided into a receive packet transmission port and a transmit packet transmission port, and correspondingly, the analysis imp port may be further divided into a first port and a second port. At this time, the process of S201 may specifically be: creating a first port and a second port in the UVM component; the TLM communication technology based on the UVM is used for establishing connection between the first port and a receiving packet transmission port of the VIP component in the PCIe Host, and establishing connection between the second port and a sending packet transmission port of the VIP component in the PCIe Host.
On this basis, a write function may be created in each of the first port and the second port, where the write function of the first port is configured to store the TLP packet transmitted by the receive packet transfer port into the first queue, and the write function of the second port is configured to store the TLP packet transmitted by the send packet transfer port into the second queue.
When the port connection established in S201 includes the connection between the receive packet transmission port and the first port, the verification process for the PCIe DMA write data path as described above may be implemented. Similarly, when the port connection established in S201 includes a connection between the packet transmission sending port and the second port, a verification process for the PCIe DMA read data path may be implemented, as shown in fig. 3 and fig. 5, where the verification process specifically includes the following steps:
s501, sending a DMA read instruction to a PCIe Host;
s502, judging whether the PCIe Host receives a TLP packet or not, if so, acquiring the TLP packet through port connection to obtain a first TLP packet; judging whether the first TLP packet is a DMA read instruction, if so, storing the first TLP packet to a first queue;
s503, judging whether the PCIe Host sends out a TLP packet, if so, acquiring the TLP packet through port connection to obtain a second TLP packet; judging whether the second TLP packet is a response packet of the DMA read instruction, if so, storing the second TLP packet to a second queue;
s504, for any first TLP packet in the first queue, matching a corresponding second TLP packet according to TAG information of the first TLP packet, and extracting a data load from the second TLP packet obtained by matching to obtain original read data;
s505, obtaining a response packet fed back by the PCIe Host through a data reading channel of the PCIe DMA according to the DMA reading instruction, wherein the response packet carries actual reading data;
s506, comparing the original read data with the actual read data; and if the comparison result is consistent, judging that the PCIe DMA read data path passes verification, otherwise, judging that the verification fails.
The method for verifying the PCIe DMA data paths breaks through an inherent verification strategy of 'write-first-read-then-read-last-comparison' aiming at the defects of the PCIe DMA data path verification scheme, completely strips the verification process of a PCIe DMA data writing path and the verification process of a PCIe DMA data reading path, and respectively verifies the correctness of each data path. Therefore, the data of each DMA read operation is not limited by the data of the corresponding DMA write operation, the execution sequence of the read operation is not limited, and the read range of the read operation is not limited. When the data writing path is verified, only data written into a remote memory space by a DMA (direct memory access) at one side of the PCIe Host is concerned; when the read data path is verified, only the data read from the remote memory space by the DMA at the PCIe Host side is concerned.
Specifically, in this embodiment, the effective information of the analysis port and the analysis imp port of the TLM communication in the UVM and the TLP header in the PCIe protocol are used to automatically acquire the data that the DMA writes into the remote memory space and the data that the DMA reads out from the remote memory space, so as to overcome the limitations on the DMA read-write operation triggering order and the access address in the verification environment, and avoid the limit condition that the DMA read operation and the DMA write operation simultaneously act on the same address in a short time, thereby greatly improving the flexibility when the random and pressure test case is constructed in the verification environment, and greatly improving the integrity of the PCIe DMA verification.
It should be noted that this embodiment may be implemented based on RTL-level front-end simulation, and in practical application, if it is ensured that the implementation code of this embodiment is integratable, this embodiment may also be transplanted to a hardware acceleration platform, and applied to simulation of an FPGA platform or software and hardware co-simulation of a simulator.
Moreover, the verification of the high-speed interface IP has higher similarity, the verification strategy and thought set forth in the embodiment are not only applicable to the verification of the PCIe DMA data path, but also can extend the verification scheme described in the embodiment to more verification of the interface IP by using the UVM TLM communication mechanism and the packet attribute specific to the high-speed interface IP, thereby improving the flexibility and completeness of the verification.
The following description starts with a detailed description of a second embodiment of a PCIe DMA data path validation method provided in the present application. Specifically, the second embodiment takes practical applications as an example, and realizes the verification of the PCIe DMA data path based on front-end emulation, and details the verification process.
For a verification platform integrated with a PCIe IP Device, in this embodiment, a PCIe VIP is integrated into the verification platform to simulate a behavior of a PCIe Host, and an analysis port and an analysis imp port in the UVM TLM are used to implement communication between a PCIe Host end VIP component and an UVM component inside the verification platform, so that a DMA write instruction, write data, a DMA read instruction sent by the verification platform monitored by the PCIe Host end and data read back from the Host end can be stored in a predefined data structure in the verification platform for subsequent use in respectively verifying correctness of a DMA write data path and a DMA read data path.
In a specific embodiment, the svt _ PCIe _ dl component (i.e., the aforementioned VIP component) in the PCIe VIP is first used to monitor the TLP packet received and the TLP packet sent out by the PCIe Host. Two analysis _ port ports, received _ tlp _ updated _ port (i.e., the aforementioned receive packet transmission port) and sent _ tlp _ updated _ port (i.e., the aforementioned send packet transmission port) in the component are respectively connected to two analysis _ imp ports, dl _ tlp _ rx _ imp (i.e., the aforementioned first port) and dl _ tlp _ tx _ imp (i.e., the aforementioned second port) defined in the base _ test component (i.e., the aforementioned UVM component) in the verification platform. In a write function corresponding to an analysis imp port, storing a PCIe TLP monitored by the port into two defined queues, where: a queue rx _ TLP _ queue for receiving TLP packets (i.e., the first queue) and a queue tx _ TLP _ queue for sending TLP packets (i.e., the second queue).
An example of implementation code related to connection of an Analysis port and monitoring of a TLP packet is as follows:
v/declaring suffixes of multiple analysis _ imp ports with UVM macros
`uvm_analysis_imp_decl(_dl_tlp_rx)
`uvm_analysis_imp_decl(_dl_tlp_tx)
// defining two imp ports, contents of port transfer and attached components
dl_tlp_rx_imp(tlp,base_test)
dl_tlp_tx_imp(tlp,base_test)
// connect the analysis _ port of VIP with the analysis _ imp of base _ test
received_tlp_observed_port＝dl_tlp_rx_imp
sent_tlp_observed_port＝dl_tlp_tx_imp
// defining the write function corresponding to the analysis _ imp port
function write_dl_tlp_rx,write_dl_tlp_tx
Adding the operation which the user wants to execute into the rx _ tlp _ queue, tx _ tlp _ queue// function, such as storing into a queue
Then, for different characteristics of the PCIe DMA write data path and the PCIe read data path, the present embodiment respectively processes address information of data carried by the PCIe DMA write data path and stores the address information in a predefined data structure according to a certain rule. The verification process for the write data path and the read data path is described below.
For a PCIe DMA write data path, when rx _ TLP _ queue. Size () (i.e., the length of the first queue) is greater than zero, first, it is determined whether the TLP _ type (i.e., the aforementioned first field) of the TLP packet stored in the queue is the MEM _ REQ; if yes, the PCIe Host end receives the TLP packet of the DMA write instruction or the DMA read instruction in the current verification scene; then, determining whether fmt (i.e., the second field) of the TLP packet is a width _ DATA _3_dword or a width _ DATA _4_dword, and if so, indicating that the PCIe Host end receives the TLP packet of the DMA write instruction; by using the first _ dw _ be, last _ dw _ be and length information in the TLP header, payload (i.e., the data payload) carried by the first _ dw _ be, last _ dw _ be and length information is transferred in order by taking bytes as a unit and then stored into a predefined association array, where the association index is address information carried by the TLP header. After the DMA write operation is completed, the verification platform compares the data corresponding to the source address of the local memory space (namely the original write data) with the data corresponding to the target address in the associated array (namely the actual write data), and if the comparison result is consistent, the DMA write data access is correct.
Reasons for the need to reverse the sequence: when the PCIe device side sends 4-byte data, the data is transmitted in units of 1byte starting from the low significant bit, so the PCIe host side receives the byte with the low significant bit first. Therefore, if the actual write data is to be obtained by the data payload carried by the TLP packet, the payload needs to be transposed in bytes. For example, assume that 32'h04030201 is before the blending sequence, and 32' h01020304 is after the blending sequence.
An example of implementation codes related to TLP packet determination and data saving is as follows:
Figure GDA0002943567600000101
Figure GDA0002943567600000111
compared with the PCIe DMA write data path, due to the Non-post attribute of the PCIe Memory Read Request, the verification of the Read data path needs to monitor two packets, namely, the Memory Read Request (i.e., the DMA Read command) received by the PCIe Host end and the Memory Read Completion (i.e., the response packet) sent by the PCIe Host end, and match the two packets together according to Tag information in the packet header. The specific verification process is as follows:
when rx _ TLP _ queue _ size () (i.e., the length of the first queue) is greater than zero, first, it is determined whether the TLP packet's TLP _ type stored in the queue is MEM _ REQ; if yes, the PCIe Host end receives the TLP packet of the DMA write instruction or the DMA read instruction in the current verification scene; then, it is determined whether fmt of the TLP packet is NO _ DATA _3 \/dword or NO _ DATA _4 \/dword, and if yes, the TLP packet indicating that the PCIe Host end receives the DMA read instruction is stored in the predefined queue rx _ TLP _ queue. When tx _ TLP _ queue. Size () (i.e., the length of the second queue) is greater than zero, determining whether TLP packets stored in the queue have TLP _ type CPL and fmt as wide _ DATA _3 \/dword; if yes, the PCIe Host end sends a DMA Read Completion packet in the current verification scene, and the DMA Read Completion packet is stored in a predefined queue tx _ tlp _ queue.
And then matching the DMA Read Request and the Read Completion packet according to Tag information in the DMA Read Request packet and the Read Completion packet, and storing payload carried by the Read Completion packet into a predefined association array after transferring the sequence by taking bytes as a unit by using first _ dw _ be, last _ dw _ be and length information in the packet headers, wherein the association index is address information carried by the DMA Read Request packet header. After the DMA read operation is completed, comparing the data (namely the original read data) corresponding to the source address in the associated array with the data (namely the actual read data) corresponding to the target address of the local memory space, and if the comparison result is consistent, indicating that the DMA read data path is correct.
An example of implementation codes related to TLP packet determination and data saving is as follows:
Figure GDA0002943567600000112
Figure GDA0002943567600000121
on the basis, an interrupt service program of the PCIe DMA can be constructed, so that data comparison aiming at each DMA write operation or read operation in the simulation process can be automatically triggered after the write operation or the read operation is finished, and the requirements of large data volume random and automatic verification in a stress test are met. PCIe DMA generally has multiple write channels and multiple read channels, and specifically may give an independent interrupt indication signal to each channel, and after an interrupt service program for a single channel is constructed, the interrupt service program may be enabled in multiple parallel processes, so as to achieve the purpose of verifying multiple channels in parallel.
An example of interrupt service routine related implementation code is as follows:
Figure GDA0002943567600000122
therefore, the verification method for the PCIe DMA data path provided in this embodiment provides a complete PCIe DMA automatic verification scheme by using the UVM TLM communication mechanism and the PCIe TLP header characteristics, and by integrating the scheme in the verification environment, a verifier can randomly trigger DMA write and read operations in a test case without worrying about the sequence, access address, and when to compare data, thereby greatly improving the flexibility and completeness of verification.
In the following, description is made on a verification apparatus for a PCIe DMA data path provided in an embodiment of the present application, and the verification apparatus for a PCIe DMA data path described below and the verification method for a PCIe DMA data path described above may be referred to correspondingly.
As shown in fig. 6, the PCIe DMA data path verification apparatus of this embodiment is applied to a verification platform, and includes:
the connection module 601: the method comprises the steps that port connection between a PCIe Host and a verification platform is established based on the TLM communication technology of the UVM;
the write command sending module 602: the system comprises a DMA write instruction, a PCIe Host and a Host, wherein the DMA write instruction carries original write data;
the monitoring module 603: the PCIe Host is used for judging whether a TLP packet is received or not, and if yes, the PCIe Host enters an acquisition module;
the obtaining module 604: for obtaining the TLP packet through the port connection;
the data extraction module 605: the TLP module is used for judging whether the TLP packet is a DMA write instruction or not; if so, extracting a data load carried by the TLP packet according to the packet header information of the TLP packet to obtain actual write data;
the comparison module 606: for comparing the original write data and the actual write data; and if the comparison result is consistent, judging that the PCIe DMA data writing path passes verification, otherwise, judging that the verification fails.
The PCIe DMA data path verification apparatus of this embodiment is configured to implement the foregoing PCIe DMA data path verification method, and therefore a specific implementation manner of the apparatus may find an embodiment portion of the PCIe DMA data path verification method in the foregoing, for example, the connection module 601, the write instruction sending module 602, the monitoring module 603, the obtaining module 604, the data extracting module 605, and the comparing module 606, which are respectively configured to implement steps S201, S202, S203, S204, S205, and S206 in the foregoing PCIe DMA data path verification method. Therefore, the detailed description thereof may refer to the description of the respective partial embodiments, which will not be presented herein.
In addition, since the PCIe DMA data path verification apparatus of this embodiment is configured to implement the PCIe DMA data path verification method described above, the role of the PCIe DMA data path verification apparatus corresponds to the role of the method described above, and details are not described here.
In addition, the present application also provides a PCIe DMA data path verification device, including:
a memory: for storing a computer program;
a processor: for executing the computer program to implement the PCIe DMA data path validation method as described above.
Finally, the present application also provides a readable storage medium having stored thereon a computer program for implementing the PCIe DMA data path validation method as described above when executed by a processor.
The embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same or similar parts among the embodiments are referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description.
The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in Random Access Memory (RAM), memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.
The above detailed descriptions of the solutions provided in the present application, and the specific examples applied herein are set forth to explain the principles and implementations of the present application, and the above descriptions of the examples are only used to help understand the method and its core ideas of the present application; meanwhile, for a person skilled in the art, according to the idea of the present application, the specific implementation manner and the application scope may be changed, and in summary, the content of the present specification should not be construed as a limitation to the present application.

Claims (8)

1. A PCIe DMA data path verification method is applied to a verification platform and comprises the following steps:
s1, establishing port connection between a PCIe Host and a verification platform based on a TLM communication technology of UVM;
s2, sending a DMA write instruction to a PCIe Host, wherein the DMA write instruction carries original write data;
s3, judging whether the PCIe Host receives the TLP packet, and if so, entering S4;
s4, acquiring the TLP packet through the port connection;
s5, judging whether the TLP packet is a DMA write instruction; if so, extracting a data load carried by the TLP packet according to the packet header information of the TLP packet to obtain actual write data;
s6, comparing the original write data with the actual write data; if the comparison result is consistent, judging that the PCIe DMA data writing path passes verification, otherwise, judging that the verification does not pass;
after the port connection between the PCIe Host and the verification platform is established by the UVM-based TLM communication technology, the method further includes:
sending a DMA read instruction to a PCIe Host;
judging whether the PCIe Host receives a TLP packet, if so, acquiring the TLP packet through the port connection to obtain a first TLP packet; judging whether the first TLP packet is a DMA read instruction, if so, storing the first TLP packet to a first queue;
judging whether the PCIe Host sends out a TLP packet or not, if so, acquiring the TLP packet through the port connection to obtain a second TLP packet; judging whether the second TLP packet is a response packet of a DMA read instruction, if so, storing the second TLP packet to a second queue;
for any first TLP packet in the first queue, matching a corresponding second TLP packet according to TAG information of the first TLP packet, and extracting a data load from the second TLP packet obtained by matching to obtain original read data;
obtaining a response packet fed back by the PCIe Host through a data reading channel of the PCIe DMA according to the DMA reading instruction, wherein the response packet carries actual read data;
comparing the original read data with the actual read data; and if the comparison result is consistent, judging that the PCIe DMA read data path passes verification, otherwise, judging that the verification fails.
2. The method of claim 1, wherein the UVM-based TLM communication technique establishing a PCIe Host port connection with an authentication platform comprises:
creating a first port and a second port in the UVM component;
establishing connection between the first port and a receiving packet transmission port of a VIP component in a PCIe Host and establishing connection between the second port and a sending packet transmission port of the VIP component in the PCIe Host based on TLM communication technology of UVM;
creating a write function in the first port and the second port respectively, where the write function of the first port is configured to store a TLP packet transmitted by the receive packet transmission port into a first queue, and the write function of the second port is configured to store a TLP packet transmitted by the send packet transmission port into a second queue.
3. The method according to claim 1, wherein the extracting, according to the header information of the TLP packet, the data payload carried by the TLP packet to obtain the actual write data includes:
extracting a data load carried by the TLP packet according to the header information of the TLP packet; transferring the data load in a byte unit to obtain actual write data; and storing the actual write data into an associated array by taking address information carried by the TLP packet as an index.
4. The method of claim 1, wherein said determining whether the TLP packet is a DMA write instruction comprises:
judging whether the TLP packet is a DMA write instruction or a DMA read instruction according to a first field of the TLP packet;
if yes, judging whether the TLP packet is a DMA write instruction according to a second field of the TLP packet.
5. The method of claim 1, further comprising:
constructing an interrupt program of PCIe DMA;
generating an interrupt indication signal when the PCIe DMA data writing path finishes the writing operation;
determining the number of PCIe DMA data writing paths which finish the writing operation at present according to the captured interrupt indication signal; and enabling a corresponding number of processes to run the interrupt program in parallel, and executing S4 to S6.
6. The PCIe DMA data path verification device is applied to a verification platform and comprises the following components:
a connecting module: the method comprises the steps that port connection between a PCIe Host and a verification platform is established based on the TLM communication technology of the UVM;
a write instruction sending module: the system comprises a DMA write instruction, a PCIe Host and a Host, wherein the DMA write instruction carries original write data;
a monitoring module: the PCIe Host is used for judging whether a TLP packet is received or not, and if yes, the PCIe Host enters an acquisition module;
an acquisition module: for obtaining the TLP packet through the port connection;
a data extraction module: the TLP module is used for judging whether the TLP packet is a DMA write instruction or not; if so, extracting a data load carried by the TLP packet according to the packet header information of the TLP packet to obtain actual write data;
a comparison module: for comparing the original write data and the actual write data; if the comparison result is consistent, judging that the PCIe DMA data writing path passes verification, otherwise, judging that the verification fails;
after the port connection between the PCIe Host and the verification platform is established by the UVM-based TLM communication technology, the method further includes:
sending a DMA read instruction to a PCIe Host;
judging whether the PCIe Host receives a TLP packet, if so, acquiring the TLP packet through the port connection to obtain a first TLP packet; judging whether the first TLP packet is a DMA read instruction, if so, storing the first TLP packet to a first queue;
judging whether the PCIe Host sends out a TLP packet or not, if so, acquiring the TLP packet through the port connection to obtain a second TLP packet; judging whether the second TLP packet is a response packet of a DMA read instruction, if so, storing the second TLP packet to a second queue;
for any first TLP packet in the first queue, matching a corresponding second TLP packet according to TAG information of the first TLP packet, and extracting a data load from the second TLP packet obtained by matching to obtain original read data;
obtaining a response packet fed back by the PCIe Host through a data reading channel of the PCIe DMA according to the DMA reading instruction, wherein the response packet carries actual read data;
comparing the original read data with the actual read data; and if the comparison result is consistent, judging that the PCIe DMA read data path passes verification, otherwise, judging that the verification fails.
7. An authentication device for a PCIe DMA data path, comprising:
a memory: for storing a computer program;
a processor: for executing the computer program to implement the PCIe DMA data path validation method as recited in any of claims 1-5.
8. A readable storage medium having stored thereon a computer program for implementing a method for PCIe DMA data path validation as defined in any one of claims 1-5 when executed by a processor.
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