CN110213143B

CN110213143B - 1553B bus IP core and monitoring system

Info

Publication number: CN110213143B
Application number: CN201910423443.4A
Authority: CN
Inventors: 张瑞琰; 安军社; 姜秀杰; 周盛雨
Original assignee: National Space Science Center of CAS
Current assignee: National Space Science Center of CAS
Priority date: 2019-05-21
Filing date: 2019-05-21
Publication date: 2021-04-09
Anticipated expiration: 2039-05-21
Also published as: CN110213143A

Abstract

The invention discloses a 1553B bus IP core, which comprises: a bus transceiver and a main module integrated on the FPGA; the bus transceiver is used for receiving bus messages from a 1553B bus and forwarding the bus messages to the main module; the main module is used for decoding the received bus message, analyzing whether the message is correct or not, acquiring the attribute information and the original information of each message, and then packaging and storing the information according to a packet format. The invention also discloses a 1553B bus monitoring system, which comprises: the IP core and the control module, the IP core further comprises: AXI bus switching; the control module is used for reading out the stored data from the main module through the AXI bus transfer and sending a control instruction and configuration information to the main module. The system is suitable for the application field of satellite electronics, and has light weight, integration and relative independence; the multi-IP core can be used as an IP core to be attached to an on-chip bus protocol, is low in power consumption, relatively independent, capable of being migrated and multiplexed and beneficial to the integration of multiple IP cores in a board.

Description

1553B bus IP core and monitoring system

Technical Field

The invention relates to the field of satellite electronic application, in particular to integration and multiplexing of an IP core in an on-chip bus protocol, and particularly relates to a 1553B bus IP core and a monitoring system.

Background

The MIL-STD-1553B bus is a half-duplex time-division command/response type multi-path transmission data bus, has the characteristics of high reliability and high flexibility, and is widely applied to the field of low-speed communication transmission at the transmission rate of 1 Mbps.

In aerospace integrated electronics, a 1553B data bus is usually used as a data channel to associate subsystems in a satellite system, an airship system and the like, so as to effectively transmit scientific data and control information. 1553B bus topology As shown in FIG. 1, the A/B path can carry 1 BC (bus controller), no more than 31 RT (remote terminal) and 1 MT (monitor).

BC is the initiator of the message on the bus, initiating the communication demand; the RT is the recipient of messages on the bus, receiving control information and data, and feeding back. MT differs from BC and RT in that it does not participate in communication and can operate relatively independently.

For aerospace projects with large limitations on power consumption and resources, the previous monitor design is not suitable. The reasons are as follows:

(1) the resource idle rate is high. The integrated protocol chip integrating the bus controller, the remote terminal and the monitor is widely applied at the present stage, the monitor is often an extended function, the occupied resources in the integrated protocol chip are less, only one mode can be selected for working, and a large amount of resources can be idle only when the monitor function is selected.

(2) The power consumption is high. Considering the design of an independent monitor, the system is mostly used in a ground detection system, and is designed based on a PC end board card, and meanwhile, the system is mainly designed based on a high-power-consumption and high-speed bus, such as a PCI/PCIE bus, and the power consumption is high, which is not beneficial to the transplantation in a device board.

(3) The integration performance is poor. In most designs, when each message is finished, the CPU needs to be reported to generate interruption, the CPU is frequently interacted, and the integration of a plurality of IP cores on a device board is not facilitated.

Disclosure of Invention

The invention provides a 1553B bus filter monitor design oriented to IP integration, which is suitable for the application field of satellite electronics. The invention mainly realizes the design of a lightweight filtering monitor, can be hung on an on-chip bus protocol, and is suitable for the practical application of a satellite electronic equipment board; selectively storing 1553B bus information, and discarding error messages such as errors and overtime; the received bus information is packaged into a format of a message block, and after a plurality of messages are stored, storage playback is used as a processing mode, so that interruption is reduced, the degree of dependence on a processor is reduced, the integration work of a plurality of IP cores is facilitated, and the working mode of delay storage and download playback of satellite and ground communication is more suitable.

In order to achieve the above object, the present invention provides a 1553B bus IP core, which includes: a bus transceiver and a main module integrated on the FPGA;

the bus transceiver is used for receiving bus messages from a 1553B bus and forwarding the bus messages to the main module;

the main module is used for decoding the received bus message, analyzing whether the message is correct or not, acquiring the attribute information and the original information of each message, and then packaging and storing the information according to a packet format.

As an improvement of the above apparatus, the main module includes: the device comprises a configuration unit, two decoders, a channel selection unit, a protocol processing unit and a storage unit;

the configuration unit: the system comprises a processor, a read enabling interface and a data reading interface, wherein the processor is used for receiving configuration information sent by the processor and providing an interrupt generating interface, the read enabling interface and the data reading interface;

the decoder: the device is used for receiving differential Manchester II type codes transmitted by a 1553B bus, and performing serial-parallel conversion and word validity check; the word validity check comprises synchronous head check, parity check and Manchester code check;

the channel selection unit: the decoder is used for selecting one path of effective data from the two decoders and sending the effective data to the protocol processing unit;

the protocol processing unit: the system is used for dividing the beginning and the end of the message, recording a monitoring time mark, analyzing whether the message is correct or not, generating a description word and generating the storage content of the message according to a designed packet format; the packet format includes: attribute information and original information; the attribute information records the coming time mark, message count, packet length, data word number, response interval and description word of the message; storing the original information according to a fixed storage mode of command words, status words and data words;

the storage unit: the data processing device is used for storing the data sent by the protocol processing unit in a circular buffer mode.

As an improvement of the above device, the storage unit is a FIFO.

As an improvement of the above device, the protocol processing unit is divided into: a command word analysis subunit, a response interval subunit, a receive status word subunit, a receive data word subunit and a packed storage subunit;

the command word analysis subunit: for deriving the operating mode by analyzing the command word; updating the corresponding flag bit of the working mode in the description word; entering a response interval subunit; the working mode is as follows: a normal communication mode, a broadcast communication mode, or a mode communication mode; and is also used for judging whether an illegal transmission command exists: an illegal mode command, a reserved mode command, an illegal broadcast command and an illegal mode broadcast command; an error of the mode command is judged when the command word analyzing subunit is in the mode communication mode; an error of the broadcast command is judged when the command word analyzing subunit is in the broadcast communication mode;

the response interval subunit is used for monitoring the word interval time and receiving a transfer task of the next message word; if a non-data word is received, entering a receiving state word subunit; if the data word is received, entering a data word receiving subunit; if the response interval is exceeded, entering a packaging storage subunit; and also for determining whether there is a no response: response time exceeding protocol requirements and no response errors of status words caused by multiple data words; the device is also used for judging that the command word is a data word with multiple errors when receiving the command;

the receiving status word subunit is used for receiving the status word or the second command word and judging according to the receiving and sending bit and the address bit of the received word: if the command word is a sending instruction, the received word is matched with the address bit of the command word and a response interval which accords with the protocol exists between the two words in time, the command word is judged to be a state word, the flag bit of the RT- > BC working mode in the description word is updated, and then the state word is switched to a data word receiving subunit or a packing storage subunit according to whether the data word needs to be received or not; if the command word is a receiving instruction, the address bit of the received word is not matched with the address bit of the command word and no interval exists between the two words, the command word is judged to be a second command word, the flag bit of the RT-RT working mode in the description word is updated, and then the command word is switched to a response interval subunit; if a time interval exists between the two words and the address bits are not matched, the word is considered as a command word of a new message, the recorded command word is discarded, and the command word is transferred to a command word analysis subunit; also for recording the case where the status word shows an error; the register is also used for recording a timeout response caused by response invalidation when the status word generates a word error;

the data word receiving subunit is used for completing multiple cycles of receiving data words, recording the number of the data words and monitoring the waiting time of each data word; the device is also used for judging whether the message length is wrong or not; the error includes: multiple data words and less data words;

and the packing storage subunit is used for storing the obtained attribute information and the original information into the FIFO word by word according to the packet format and recording the attribute information and the original information as the end of the message.

The invention also provides a 1553B bus monitoring system which is characterized by comprising the following components: in the above IP core and control module, the IP core further includes: AXI bus switching;

the control module is used for reading out the stored data from the main module through the AXI bus transfer and sending a control instruction and configuration information to the main module.

As an improvement of the above system, the AXI bus switch sets five registers for the control module to read, including: an enable register, an interrupt generation register, an interrupt wipe register, a FIFO count register, and a FIFO read register.

As an improvement of the above system, the control module comprises: the device comprises a control unit, an interrupt processing unit and a FIFO value reading unit;

the control unit is used for controlling the power-on, power-off and reset of the whole main module;

the interrupt processing unit is used for erasing interrupt;

the read FIFO value cell; the method is used for reading the data of the FIFO in a mode of interrupting reading or reading at any time.

As an improvement of the above system, the interrupt reading is: when the message reaches half full FIFO, an interrupt is generated, and the control module responds to the interrupt to read the stored data in the FIFO.

As an improvement of the above system, the whenever-read is: when the control module has a read request and the main module does not generate an interrupt, the number of the message words in the FIFO is acquired through the FIFO counting register, and then the data in the FIFO is read.

The invention has the advantages that:

1. the invention provides a 1553B bus filtering monitor design facing IP integration, which is suitable for the application field of satellite electronics and has the characteristics of light weight, integration and relative independence:

light weight. A filtered message monitoring mode is adopted, the attributes of complete correct messages and error messages are recorded, the storage load is reduced, and the power consumption is reduced;

integration. The system is suitable for an on-chip bus communication protocol, works as one of the peripherals of AXI in an AMBA bus, and realizes that each subsystem which works relatively independently is arranged in one device board;

and thirdly, relative independence. The interruption is reduced, each message is generated into a message block, a plurality of messages are stored and then read and played back once, and the CPU occupancy rate is reduced;

2. aiming at the current development situation of satellite electronics with low power consumption and strong integration, the invention provides an IP integration-oriented 1553B bus monitor which can be used as an IP core to be attached to an on-chip bus protocol, has low power consumption, is relatively independent, can be migrated and reused, and is beneficial to the on-board integration of multiple IP cores.

Drawings

FIG. 1 is a 1553B bus topology;

FIG. 2 is a schematic diagram of an IP-oriented integrated 1553B bus monitoring system of the present invention;

FIG. 3 is a diagram of a packet format according to the present invention;

FIG. 4 is a flowchart illustrating the operation of the master module snooping in accordance with the present invention;

FIG. 5 is a block diagram of the system test of the present invention;

FIG. 6 is a diagram of the present invention showing the reading of information after an interrupt is generated.

Detailed Description

The invention is described in detail below with reference to the figures and specific embodiments.

Example 1

Embodiment 1 of the present invention provides a 1553B bus IP core, comprising a main module; the main module can work independently and can be flexibly attached to various on-chip bus protocols. The main module realizes the 1553B filtering and monitoring function, packs and stores the received information and provides a message output interface and a message control interface.

As shown in fig. 2, the MT is a master module, receives bus messages through a 1553B bus transceiver, adds attribute information to each message after processing, and packages and stores the messages in the FIFO, and the functions of each unit are as follows:

(1) a configuration unit: including configuration of the AXI bus slave, HPI-AXI bridge translation, providing interrupt feedback and read interfaces.

(2) The A/B path decoder: and receiving the differential Manchester type II code transmitted by the bus, and performing serial-parallel conversion and word validity check (including synchronous head check, parity check and Manchester code check).

(3) A channel selection unit: only one path of the two paths of data is effective and is processed after being selected.

(4) A protocol processing unit: the core of MT design, the division of the message start and end, recording the monitoring time mark, analyzing the message correctness and generating the description word, has the functions of information recording and analysis filtering.

(5) FIFO: and a circular cache mode is adopted, half-full interrupt of a memory is generated, and the capacity is adjustable.

In order to further refine the functional requirements of the MT and facilitate the subsequent deframing and unpacking processing at the ground end, the monitoring range and the storage format of the MT need to be customized. The MT can listen to the correct information transmission content and can identify the five common types of error transmission. The correct communication transmission includes ten types including a broadcast mode and a command mode, and the wrong transmission mode includes word invalidation, message length error, illegal transmission command, response time timeout and status word error indication.

The MT listening range is represented by a custom descriptor, which represents the content attribute of each message, and the meaning of each bit is shown in table 1, which reflects the communication mode and whether an error occurs. The MT stores each received message in the FIFO after packing, and the definition of the packet format is shown in fig. 3. The processed stored information contains the generated information and the original message block. The generated information is information such as a timestamp, a count, a response interval, a description word and the like of the coming message recorded by the MT. The original message block is stored in a fixed storage mode of command word-status word-data word. Anchor 146F is the start information for each packet.

Table 1 description word definitions

MT workflow:

the MT mainly performs analysis based on the message listening mode of the 1553B bus. According to the 1553B bus specification, the synchronization headers for the command word and the status word are identical and cannot be resolved by the decoder. Therefore, only data words can be determined when the data words are transmitted to the protocol processing module. The MT workflow is mainly divided into three parts: analysis of command words, receiving status words, and receiving data words.

Command word analysis: the command word is the beginning of a message, so the first word defaults to a command word. And obtaining the next MT working mode through judgment, and entering common communication modes (BC- > RT, RT- > BC and RT-RTs), a broadcast communication mode and a mode communication mode.

Receiving a status word: and completing the tasks of monitoring the response time and receiving the state word, and simultaneously judging whether the RT state word is matched with the command word. An RT- > RT communication mode, a receive data word mode, or a packed storage mode may be entered.

Receiving a data word: completing multiple cycles of receiving data words, recording the number of data words, and monitoring the data word wait time.

The detailed process is as follows:

1553B the correct information transmission forms on the bus are ten, as shown in Table 1, according to the difference of the number of command words (cmd) and status words (status), the information is divided into 4 categories (the bracketed number in Table 1 is the number of each word, and the message word timing starts with the command word). The MT makes a start-stop partition of each message received on this basis.

Table 2: ten information transmission forms

The protocol processing unit is divided according to the flow, and can be divided into the following parts according to the processing flow: a command word analysis subunit, a response interval subunit, a receive status word subunit, a receive data word subunit and a packed storage subunit;

the command word analysis subunit: for deriving the operating mode by analyzing the command word; updating the corresponding zone bit of the working mode in the description word, and entering a response interval subunit in the next step; the working mode is as follows: a normal communication mode, a broadcast communication mode, or a mode communication mode;

the response interval subunit is used for monitoring the word interval time and receiving a transfer task of the next message word; if a non-data word is received, entering a receiving state word subunit; if the data word is received, entering a data word receiving subunit; if the response interval is exceeded, entering a packaging storage subunit;

the receiving status word subunit is used for receiving the status word or the second command word, judging according to the receiving and sending bit and the address bit of the received word, if the command word is a sending instruction, the received word is matched with the address bit of the command word and a response interval which accords with a protocol exists between the two words in time, judging as the status word, updating a flag bit which describes an RT- > BC working mode in the word, and then switching to a receiving data word subunit or a packaging storage subunit according to whether the data word needs to be received or not; if the command word is a receiving instruction, the address bit of the received word is not matched with the address bit of the command word and no interval exists between the two words, the command word is judged to be a second command word, the flag bit of the RT-RT working mode in the description word is updated, and then the command word is switched to a response interval subunit; if there is a time interval between two words and the address bits are not matched, the word is regarded as the command word of a new message, the recorded command word is discarded, and the command word is transferred to the command word analysis subunit.

The data word receiving subunit is used for completing multiple cycles of receiving data words, recording the number of the data words and monitoring the waiting time of each data word;

and the packing storage subunit is used for storing the obtained attribute information and the original information into the FIFO word by word according to the packet format, and simultaneously storing the number of the stored FIFOs into the FIFO counting register to record the number as the end of the message.

The specific working flow diagram of the protocol processing unit is shown in fig. 4, wherein the broadcast command and the mode command are not shown in detail, and the working modes thereof can be merged in the flow diagram. For example, if the bus message is a broadcast BC- > RTs command, the data word is received through the command word parsing-response interval, and then the step of the packed storage is directly carried out.

The protocol processing unit is designed for common modules with five types of errors, namely word check, message length error, remote response timeout, illegal transmission command and status word error indication record.

And (3) word checking: recording the parity check bit error and the Manchester code error, and identifying in a double-path decoder module; if the command word is correct and the status word or the data word is wrong, recording the wrong status word or data word as 0, and then not monitoring until the next command word is encountered; if the command word is in error, only the attribute information is recorded, and the original information is not recorded.

Message length error: the method comprises the steps of sending data words more frequently and sending data words less frequently; modification of multiple data words: when an instruction is sent, after a data word subunit is received, a data word multi-sending unit is set to identify, and then the data word multi-sending unit is switched to a packing storage subunit; identifying, upon receipt of the instruction, that within the response interval subunit, receipt of the data word results in the sum of the data words exceeding the requirement for the command word; modification of the data word with less transmission: in the data word receiving subunit, the coming time of the data words is monitored, and the coming time of the data words is short if no data words come or the data words are discontinuous;

remote response timeout: including no response and a wrong line response; the non-response is mainly embodied in a response interval subunit, the response time exceeding the protocol requirement and the non-response of the status word caused by the multiple occurrence of the data word; and the overtime response is embodied in the receiving state word subunit, and when the state word generates a word error, the overtime response is caused by response invalidation; the error line response is mainly embodied in the channel selection module, and the command word and the status word are respectively in A, B two paths.

Illegal transmission of commands: including illegal mode commands, reserved mode commands, illegal broadcast commands and illegal mode broadcast commands. An error regarding the mode command is judged at the mode communication pattern in the command word analyzing subunit; an error regarding the broadcast command is judged at the broadcast communication mode in the command word analyzing subunit.

Status word error indication record: the condition that the status word shows errors is recorded, and the bus internal error display is carried out.

Example 2

The embodiment 2 of the invention provides a 1553B bus monitoring system comprising the IP core, and the system also comprises a control module running on an upper computer; the IP core also comprises: AXI bus switching;

the AXI bus switching on the FPGA is a communication connection module, and the communication connection module can read the information in the FIFO and read back the stored data. The communication connection module is added with functions such as a system-on-chip protocol interface and the like on the basis of the main module, and the control module is used for controlling the start and the end of the work of the main module, reading stored 1553B bus information and finishing butt joint communication with the CPU.

In the design of the communication interface, a control signal sent by an upper computer completes information transceiving through an HPI interface, and the information realizes control on an IP core through an HPI-AXI bridge. The upper computer controls the power-on, reset and interruption of the whole load communication board. After the upper computer sends out an instruction for starting the MT to work, the MT starts to monitor bus data, and the monitoring process does not need the participation of the upper computer.

The upper computer only needs to interrupt the processing module and the FIFO value reading module except for controlling the main module to start and close. Therefore, the AXI bus switching only needs to set five registers for the upper computer to read, which are respectively: an enable register, an interrupt generation register, an interrupt wipe register, a FIFO count register, and a FIFO read register.

The FIFO value reading module provides two reading modes, namely interrupt reading and random reading. (1) The reading is interrupted. When the message reaches half full of FIFO, an interrupt is generated, and the upper computer responds to the interrupt to read the data stored in FIFO. (2) After a message is processed, the description word register and the message length register store new analysis data, and the register for storing the attribute information of each message is updated.

The system of the invention is mainly improved by the following three points:

1. the fault tolerance mechanism improvement scheme comprises the following steps:

in the process of 1553B bus transmission, if the error message mode in the bus communication exceeds the monitoring range of the MT under the normal condition, the disorder behavior can occur. The main reasons for this problem are: for the monitor, there is no way to distinguish between the status word and the command word (herein collectively referred to as CMD), and in most cases this occurs due to the mismatch in address between the command word and the status word. In order to improve the fault tolerance of the system, how to pull the protocol processing timing back to the normal timing with less cost needs to be considered so as to receive the next message conveniently.

For example, if BC issues one instruction word, RT, when not responding, BC issues the next instruction word several microseconds apart. For the monitor, the second instruction word is treated as a status word, and the solution of the present invention is: only the last received CMD is used as the initial command word of the next message, and the disorder CMD is not recorded.

2. Interval time accuracy:

considering that the monitor does not participate in the interaction of 1553B communication, the monitor design needs to avoid long-time monitoring to influence the acquisition of subsequent messages. The present invention requires a separate storage state to store the message as each message is processed. If a message transmission error causes the monitor to wait a long time for the next word to arrive, there will be no time to store the message and affect its reception of the next message.

The solution of the invention is as follows: latency is reduced by using an indication signal generated immediately after word sync header recognition. For example, if there are more data words, it takes 20us to wait for the data words to be completely received, and only 3us is required to determine whether there is more data words. Meanwhile, considering that the message interval is not less than 4us, the invention sets the waiting time in an error state, for example, when the data word is sent for a short time, the waiting time does not monitor after reaching 4 us.

3. Coverage perfection:

the invention covers the identification of five common types of errors. The error bit in the description word may have a multi-bit simultaneous 1 condition, such as a data word being infrequently sent while the remote response timeout bit is set. These five types of errors also include errors not specified by the descriptor word, such as word continuity errors (which are stored as one of the infrequent data words in the corresponding flag bits of the descriptor word) and RT response to another bus error (which is processed as an RT timeout response).

The system is written by adopting Verilog Hdl hardware language, and functional simulation and time sequence simulation are verified in Libero Soc v11.8 and ModelSim 10.5c software.

The test block diagram is shown in fig. 5. The FPGA model adopted for the test is A3PE3000 of Actel company, and the processor is a Loongson 1E chip. The input signal source is a full-function 1553B board card of DDC company, the coupling transformer is B-3226, and the bus transceiver chip adopts HI-1568 of HOLT company. After the message is processed by the FPGA board, the message is transmitted into the PC end through the MOXA switch through the USB port, the PC end adopts a VxWorks operating system to control the processor to receive and send instructions, an upper computer program is compiled, the read data is printed on the SecureCRT of the serial port debugging software, and the data output by the monitor is compared with the data output by the DDC monitor. The working frequency of the FPGA board is 32MHz, 16M clock signals with consistent phases are generated after PLL frequency division, the working frequency is provided for MT, and the subsequent clock domain crossing sampling problem is facilitated.

The verification method is divided into error communication and error-free communication. The verification of the erroneous communication is shown in table 2. The verification mode is established according to GJB 5186.6-2005 standard. The authentication information includes:

(1) error-free communication method: BC- > RT, RT- > BC, RT-RT, mode commands without data words, send mode commands with data words, receive mode commands with data words, broadcast BC- > RT, broadcast RT- > RTs, broadcast mode commands without data words and broadcast mode commands with data words.

(2) Error communication mode: including word invalid, illegal transfer command, message length error, response timeout, and status word error indication record.

TABLE 2MT error communication verification scheme

During testing, the FIFO size is set to 16K. The method comprises the steps of inquiring whether interruption triggering exists or not by adopting a polling mode at an upper computer end, reading registers (if the registers are N) for recording the number of the caches in the FIFO if the interruption exists, triggering FIFO to read signals for N times, and printing by a serial port (in order to check information, in a test stage, inquiring whether the registers for recording the number of the caches in the FIFO have values at certain intervals, and reading and printing if the registers have values). Tests have shown that both correct communication and the erroneous communication pattern shown in table 3 can be detected and recorded. As shown in fig. 6, for the data printed after one test FPGA is generated, red boxes in the figure indicate complete record information of one message, 146f is a header, 4000 is a generated description word, 0824 is a command word, 0800 is a data word, and 1004 represents that the piece of information contains 4 data words, which are the last four-bit data 0020,0021,0022 and 0023, respectively. Compared with the full-function BU-65570 board card of DDC company, the information received by the BUs is kept consistent.

After actual test, the monitoring system is verified to realize the design function. The device can be integrated in an on-chip bus protocol, and the requirement of integration is met; the method can correctly monitor information on the bus, judge normal communication and error communication, and realize the design goals of stronger independence and lower resource utilization compared with a fusion chip. And good technical support is provided for subsequent 1553B bus error troubleshooting and analysis.

Finally, it should be noted that the above embodiments are only used for illustrating the technical solutions of the present invention and are not limited. Although the present invention has been described in detail with reference to the embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. A 1553B bus IP core, wherein the IP core comprises: a bus transceiver and a main module integrated on the FPGA;

the main module is used for decoding the received bus message, analyzing whether the message is correct or not, acquiring attribute information and original information of each message, and then packaging and storing the attribute information and the original information according to a packet format;

the main module includes: the device comprises a configuration unit, two decoders, a channel selection unit, a protocol processing unit and a storage unit;

the storage unit: the protocol processing unit is used for storing data sent by the protocol processing unit in a circular cache mode;

the protocol processing unit is divided into: a command word analysis subunit, a response interval subunit, a receive status word subunit, a receive data word subunit and a packed storage subunit;

2. The 1553B bus IP core of claim 1, wherein the storage unit is a FIFO.

3. A 1553B bus monitoring system, characterized in that, the system comprises: the IP core and control module of one of claims 1-2, further comprising on the IP core: AXI bus switching;

4. The 1553B bus monitoring system of claim 3, wherein the AXI bus switch sets five registers for a control module to read, comprising: an enable register, an interrupt generation register, an interrupt wipe register, a FIFO count register, and a FIFO read register.

5. The 1553B bus monitoring system of claim 4, wherein the control module comprises: the device comprises a control unit, an interrupt processing unit and a FIFO value reading unit;

the interrupt processing unit is used for erasing interrupt;

and the reading FIFO value unit is used for reading the FIFO data in an interruption reading or random reading mode.

6. The 1553B bus monitoring system of claim 5, wherein the interrupt read is: when the message reaches half full FIFO, an interrupt is generated, and the control module responds to the interrupt to read the stored data in the FIFO.

7. The 1553B bus monitoring system of claim 5, wherein the Ready-to-read is: when the control module has a read request and the main module does not generate an interrupt, the number of the message words in the FIFO is acquired through the FIFO counting register, and then the data in the FIFO is read.