CN117112420A

CN117112420A - Method and device for debugging system-on-chip

Info

Publication number: CN117112420A
Application number: CN202311076364.3A
Authority: CN
Inventors: 唐益民
Original assignee: Beijing Gengtu Technology Co ltd
Current assignee: Beijing Gengtu Technology Co ltd
Priority date: 2023-08-24
Filing date: 2023-08-24
Publication date: 2023-11-24

Abstract

The present invention relates to the field of chip design, and in particular, to a method and apparatus for debugging a system-on-chip. Mainly comprises the following steps: the method comprises the steps that a host generates debugging information of a system-on-chip, the debugging information is converted into an on-chip bus signal, and the debugging information is sent to a slave machine in the form of the on-chip bus signal through an IIC protocol; the slave generates response information according to the received debugging information, and sends the response information to the host by using an IIC protocol; the host receives the response information through the IIC protocol, analyzes the response information into a bus signal on a chip, analyzes the bus signal on the chip, and obtains a debugging result according to the analyzed response content. The invention provides an SOC debugging means which is compatible with the existing IIC standard and is independent of a CPU, and can conveniently finish the access and debugging of the data in the SOC chip through an IIC interface in the existing system.

Description

Method and device for debugging system-on-chip

Technical Field

The present invention relates to the field of chip design, and in particular, to a method and apparatus for debugging a system-on-chip

Background

A System On Chip (SOC) is a complex circuit System composed of a plurality of intellectual property (Intellectual Property, IP) modules, and generally includes a processor, an analog IP core, a digital IP core, a storage medium or interface, an interconnection IP and interface, a peripheral protocol interface, and the like, which has extremely high complexity and debugging difficulty. Current mainstream SOC test approaches in the industry include standard debug interfaces using joint test workgroup (Joint Test Action Group, abbreviated as JTAG) or interactive debug based on universal asynchronous receiver Transmitter (Universal Asynchronous Receiver/Transmitter, abbreviated as UART). Generally, the JTAG debug interface has good versatility and can be supported by substantially all mainstream debug software. The UART debugging interface is relatively simple, has low requirements, and can be independently designed or flexibly adjusted according to different requirements.

However, both of the above schemes have certain limitations. Firstly, JTAG protocol relies on a more complex Test Access Port (TAP) state machine, which is difficult to Design and realize, and occupies 4 chip pins, in SOC system, JTAG is usually used as an attachment of CPU subsystem or used For Design For Test (DFT), the latter is used For injecting Test vector, rarely exists as independent IP module, the host end also needs specific driving support, which is more troublesome.

In view of this, how to overcome the defects existing in the prior art and solve the problem that the existing system-on-chip debugging method is complex to implement or can not independently perform testing is a problem to be solved in the technical field.

Disclosure of Invention

Aiming at the defects or improvement demands of the prior art, the invention solves the problems that the existing system-on-chip debugging method is complex to realize or can not independently test.

The embodiment of the invention adopts the following technical scheme:

in a first aspect, the present invention provides a method for debugging a system-on-chip, specifically: the method comprises the steps that a host generates debugging information of a system-on-chip, the debugging information is converted into an on-chip bus signal, and the debugging information is sent to a slave machine in the form of the on-chip bus signal through an IIC protocol; the slave generates response information according to the received debugging information, and sends the response information to the host by using an IIC protocol; the host receives the response information through the IIC protocol, analyzes the response information into a bus signal on a chip, analyzes the bus signal on the chip, and obtains a debugging result according to the analyzed response content.

Preferably, the generating the debug information of the system-on-chip specifically includes, when the debug information is a write protocol: the host writes the fields in the write protocol: the first start bit, the first slave address, the write flag, the instruction, the read-write address, the write data and the stop bit; wherein the first start bit is 1 bit, indicating that the write protocol starts; the first slave address is 1 byte, which indicates the slave address to which the debug information needs to be sent; the writing mark is 1 bit, which indicates that the slave needs to write data; the instruction is 1 byte, which indicates the debug instruction that needs to be executed by the slave; the read-write address is 4 1 bytes and represents the read-write address corresponding to the instruction; the writing data is at least 1 byte, which represents the data written into the slave, and the number of bytes is determined according to the instruction; the stop bit is 1 bit indicating that the write protocol is over.

Preferably, the generating the debug information of the system-on-chip specifically includes, when the debug information is a read protocol: the host writes the fields in the read protocol: the second start bit, the second slave address, the write flag, the instruction, the read-write address, the third start bit, the third slave address, the read flag, the first response bit, the no-response and the stop bit; wherein the second start bit is 1 bit, indicating that the read protocol is started; the second slave address is 1 byte, which indicates the slave address to which the debug information needs to be sent; the writing mark is 1 bit, which indicates that the second slave address is the slave address needing writing; the instruction is 1 byte, which indicates the debug instruction that needs to be executed by the slave;

the read-write address is 4 1 bytes and represents the read-write address corresponding to the instruction; the third start bit is 1 byte, indicating that the read-out section starts; the third slave address is 4 bytes, which represents the data reading address in the slave; the reading mark is 1 bit, which indicates that the third slave address is the slave address which needs to be read; the first response bit is 1 bit, which indicates whether the host can continuously write data; whether the response bit is 1 bit indicates whether the host has completed receiving the read data; the stop bit is 1 bit and indicates that the protocol is complete.

Preferably, the instruction is 1 byte, which indicates a debug instruction that needs to be executed by the slave, and specifically includes: the instruction includes the alignment mode of the continuous data stream so that the slave machine can write or read according to different unpacking modes of the continuous data stream.

Preferably, the instruction is 1 byte, which indicates a debug instruction that needs to be executed by the slave, and specifically includes: the instruction contains a read-write attribute mode so as to obtain the timing of early judgment and timely response according to the read-write attribute by the slave machine.

Preferably, the no reply bit is 1 bit, which indicates whether the host has completed receiving the read data, and specifically includes: after the host finishes receiving the read data, a no-answer field is given.

Preferably, the slave generates response information according to the received debug information, and when the debug information is a write protocol, the method specifically includes: the slave writes the response bits after writing the fields of the protocol: wherein, the response bit after the first slave address indicates whether the first slave address is legal or not; a response bit after the instruction indicates whether the slave is idle; the response bit after each read-write address indicates whether the read-write address is legal or not; the reply bit after each write data byte indicates whether the slave can continue writing.

Preferably, the slave generates response information according to the received debug information, and when the debug information is a read protocol, the method specifically includes: the slave machine writes response bits after reading each field of the protocol, and writes read data after reading the mark; wherein, the response bit after the second slave address indicates whether the second slave address is legal; a response bit after the instruction indicates whether the slave is idle; the response bit after each read-write address indicates whether the read-write address is legal or not; each read data is 1 byte, representing data read by a read-write address, the number of bytes being determined by the instruction.

Preferably, the parsing the response information into the on-chip bus signal further includes: when the host computer prepares to write data, if the response bit of the slave computer after the instruction replies a no response, the current transmission is terminated, and retransmission is executed after the specified waiting time.

On the other hand, the invention provides a device for debugging a system-on-chip, which specifically comprises: the IIC protocol analysis module, the FIFO module and the on-chip bus module are used for carrying out the method for debugging the system-on-chip provided by the first aspect, and specifically comprise the following steps: the IIC protocol analysis module is connected with external IIC equipment through an IIC interface, the IIC protocol interface is connected with the FIFO module and the on-chip bus module, and the on-chip bus module is connected with the on-chip system through an on-chip bus protocol; the IIC protocol analysis module analyzes and drives the IIC interface protocol to finish the sending of the debugging information and the receiving of the response information; the FIFO module caches write data in a write protocol; the on-chip bus module converts debug information into on-chip bus signals.

Compared with the prior art, the embodiment of the invention has the beneficial effects that: the debugging information is converted into an on-chip bus signal with a specific format, and the on-chip bus signal is sent to the slave through an integrated circuit bus (Inter-Integrated Circuit, abbreviated as IIC) protocol, and then response information fed back by the slave is received through the IIC protocol, so that the debugging of the SOC is completed. The method provides the SOC debugging means which can be compatible with the existing IIC standard and is independent of the CPU, and access and debugging of data in the SOC chip can be conveniently completed through the IIC interface in the existing system.

Drawings

In order to more clearly illustrate the technical solution of the embodiments of the present invention, the drawings that are required to be used in the embodiments of the present invention will be briefly described below. It is evident that the drawings described below are only some embodiments of the present invention and that other drawings may be obtained from these drawings without inventive effort for a person of ordinary skill in the art.

FIG. 1 is a flowchart of a method for debugging a system-on-chip according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of a basic write protocol according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of a basic read protocol according to an embodiment of the present invention;

fig. 4 is a schematic structural diagram of a device for debugging a system-on-chip according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of a connection mode of a device for testing according to an embodiment of the present invention;

FIG. 6 is a flow chart of the determining process of each response bit in the write protocol according to the present invention;

FIG. 7 is a flow chart of the process for determining each response bit in the read protocol according to the present invention.

Detailed Description

The present invention will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.

The present invention is an architecture of a specific functional system, so that in a specific embodiment, functional logic relationships of each structural module are mainly described, and specific software and hardware implementations are not limited.

In addition, the technical features of the embodiments of the present invention described below may be combined with each other as long as they do not collide with each other. The invention will be described in detail below with reference to the drawings and examples.

In order to solve the problem of the existing SOC debugging mode, the embodiment provides an independent, simpler, highly reliable and highly universal SOC chip debugging means.

When the system-on-chip is debugged, the system-on-chip needs to transmit and receive debugging information to and from the external equipment, and receives response information fed back by the external equipment according to the debugging information; the external equipment can also send debugging information, and the system-on-chip feeds back response information according to the debugging information; it is also possible to perform bi-directional interactions of debug information and response information between two systems on chip. In this embodiment, for clarity of description, a device that transmits debug information is referred to as a master, and a device that receives debug information and feeds back response information is referred to as a slave.

As shown in fig. 1, the method for debugging a system-on-chip provided by the embodiment of the invention specifically includes the following steps:

step 101: the host computer generates the debugging information of the system-on-chip, converts the debugging information into an on-chip bus signal, and sends the debugging information to the slave computer in the form of the on-chip bus signal through an IIC protocol.

Advanced microcontroller bus architecture (Advanced Microcontroller Bus Architecture, abbreviated as AMBA), also known as on-chip bus, is a data transmission scheme widely used in S0C design under ARM architecture, and is also widely used in SOC design projects such as application specific integrated circuits and system chips. AMBA is capable of performing data conversion between various interfaces according to various data transfer protocols. In the method provided by the embodiment, the debug information is converted into the on-chip bus signal through the direct interface of the chip and the on-chip information, and the data interaction between the SOC chip and the IIC interface is completed by using the AMBA, so that the debug information in the SOC can be read and written directly through the IIC protocol without depending on the CPU. Because the AMBA protocol and the IIC protocol are all universal data exchange protocols and have corresponding universal hardware interfaces, the seamless connection between the method provided by the embodiment and the existing software and hardware design can be ensured, and no additional special adaptation of software and hardware is needed.

In the embodiment of the invention, in order to enable the slave to acquire the required debugging instructions and debugging data, in practical implementation, the communication protocol of the debugging information can be determined according to the requirement. The communication protocol needs to contain the required debug instructions and debug data, as well as other communication state data or device state data. Meanwhile, in order for debug information to be able to be transferred over the on-chip bus and IIC interface, the communication protocol also needs to be able to support AMBA and IIC protocols.

Step 102: and the slave generates response information according to the received debugging information, and sends the response information to the host by using the IIC protocol.

After the host sends out the debugging information, the debugging result is obtained according to the response information of the slave. The IIC protocol is a bidirectional communication protocol, so that the slave machine can also return to the host machine by using the IIC protocol according to response information generated by the debug information. Because the IIC interface is a universal data interface, the method provided by the embodiment of the invention is not limited to a software and hardware system of the slave, and only needs to read and write data through the IIC interface, can correspondingly update information and can generate corresponding response information.

After the slave acquires the debugging information, the slave can analyze the debugging information according to the communication protocol and respond correspondingly to generate response information. Accordingly, in order to enable the host to obtain the corresponding data in the reply information, in practical implementations, the communication protocol of the reply information may be determined as needed. The communication protocol needs to include the required response data as well as other communication status data or device status data. Meanwhile, in order for the reply information to be transmitted through the IIC interface, the communication protocol also needs to be able to support the IIC protocol.

Step 103: the host receives the response information through the IIC protocol, analyzes the response information into a bus signal on a chip, analyzes the bus signal on the chip, and obtains a debugging result according to the analyzed response content.

After receiving the response information fed back by the slave machine through the IIC protocol, the host machine can acquire the response information through the on-chip bus, analyze the response information according to the communication protocol, acquire a corresponding debugging result and complete the debugging of the on-chip system chip.

After steps 101 to 103 provided in this embodiment, the system-on-chip can perform convenient data interaction with the external device actively through the on-chip bus, the IIC protocol and the specific communication protocol, and the debugging of the system-on-chip is completed without depending on additional hardware and CPU support.

In the method provided by the embodiment of the invention, the universal data interfaces such as the on-chip bus and the IIC protocol are used for completing the interaction of debugging information and response information. The following provides a useful communication protocol that can carry instructions and data required for debugging and is fully compatible with the IIC standard protocol at the protocol level. It is to be understood that the following communication protocol format is merely an example of one available communication protocol and is not to be taken as a limitation of the protection protocol of the present invention.

(1) When the debug information is a write protocol.

The host writes the fields in the write protocol: the first start bit, the first slave address, the write flag, the instruction, the read-write address, the write data, and the stop bit.

As shown in fig. 2, a schematic diagram of the basic writing protocol is shown. Each bin in the figure represents a bit, and the dark bit is written by the host and used as debug information.

A first Start bit (S) is 1 bit, indicating that the write protocol starts. The slave that receives the debug information starts to parse the debug information from the bit.

The first slave address (SL) is 1 byte (8 bits), which indicates the slave address where debug information needs to be sent. The host sends the debugging information to the slave according to the address, and the slave confirms whether the host should receive the debugging information according to the address.

A Write flag (W) is 1 bit, indicating that the slave needs to Write data. The data written in the slave may be common data stored in the memory of the slave, or may be parameters of a debug instruction, register values of the slave, and the like.

An instruction (CM) is 1 byte, representing a debug instruction that the slave needs to execute. The specific instruction content is determined according to the debugging requirement, when the debugging is carried out, the slave machine executes the instruction, and the execution result is fed back to the host machine as response information.

The read-write Address (AD) is 4 1 bytes, which indicates the read-write address corresponding to the instruction. In the write protocol, the address represents an address written by write data, and may be a register address, a memory address, a file system address, or the like of the slave.

Write Data (WD) is at least 1 byte, representing Data written to the slave, the number of bytes being determined according to the instruction. And the slave writes the data in the write data field into the corresponding position according to the read-write address.

A Stop bit (P) is 1 bit, indicating the end of the write protocol. Since the length of the write data is not determined, it is also necessary to use the stop bit as an end flag, and after the slave analyzes the stop bit, the analysis of the debug command is ended.

Through the protocol, the host can send a debugging instruction which needs to be written with data and corresponding written data to the slave.

(2) When the debug information is a read protocol.

The host writes the fields in the read protocol: the second start bit, the second slave address, the write flag, the instruction, the read-write address, the third start bit, the third slave address, the read flag, the first response bit, the no response and the stop bit.

As shown in fig. 3, a schematic diagram of the basic read protocol is shown. Each bin in the figure represents a bit, and the dark bit is written by the host and used as debug information.

The second start bit (S) is 1 bit, indicating that the read protocol is started. The slave that receives the debug information starts to parse the debug information from the bit.

The second slave address (SL) is 1 byte, indicating the slave address to which debug information needs to be sent. The host sends the debugging information to the slave according to the address, and the slave confirms whether the host should receive the debugging information according to the address.

The write flag (W) is 1 bit, indicating that the second slave address is the slave address to be written. When debugging is carried out, the slave machine needs to write the instruction into the memory first to execute the instruction, so that the instruction field of the read protocol also needs to contain a write mark before the instruction field, which means that the subsequent instruction field needs to be written into the slave machine.

The instruction (CM) is 1 byte, indicating a debug instruction that the slave needs to execute. The specific instruction content is determined according to the debugging requirement, when the debugging is carried out, the slave machine executes the instruction, and the execution result is fed back to the host machine as response information.

The read-write Address (AD) is 4 1 bytes, indicating the read-write address corresponding to the instruction. In the read protocol, the address represents the data address to be read, which may be a register address, a memory address, a file system address, etc. of the slave. The slave reads the data in the corresponding address according to the read-write address, and feeds the read data back to the host as response information.

The third start bit (S) is 1 byte, indicating that the read-out section starts. In the read protocol, the position of the feedback read data needs to be reserved for the slave, so that the slave writes the read data after the third start bit using the other start bit as a split of the master data and the slave data.

The third slave address (SL) is 4 bytes, representing the data read address in the slave. The slave machine confirms whether the slave machine should read data and feed back according to the address, and the host machine distinguishes the slave machine feeding back data according to the address.

A Read flag (R) is 1 bit, and indicates that the third slave address is the slave address to be Read. In order to distinguish the read data of the read slave machine from the data which needs to be written into the slave machine, a read mark is used for identification in a read protocol, and the data after the read mark is the data read by the slave machine.

A first Acknowledgement (AC) bit is 1 bit, indicating whether the host can continue writing data. In the communication protocol provided by the embodiment of the invention, the master machine and the slave machine can feed back the equipment condition or the instruction execution condition to the opposite party by using the response bit, and each response bit can feed back the execution result or the confirmation condition of the previous field. In the read protocol, each slave machine reads data field, each byte will contain a first response bit, after the host machine writes the data of the previous byte into the host machine, the response bit is used to feed back the execution result of the writing action to the slave machine.

The Negative-acknowledgement bit (NA) is 1 bit, indicating whether the host has completed receiving read data. Since the read protocol may include more than one data byte read from the host, and the number of bytes is not determined, when the host completes receiving the read data, all data bytes fed back by the host are received by the host, and the host needs to give a no-answer field to identify that the receiving is completed.

Based on the above-described read and write protocols, it can be seen from the communication protocols in fig. 2 and 3 that only a part of the fields are used for the host to write the debug information, and that another part of the fields of the light bits remain unused for the host. The reserved field can be used as a response bit to be written and sent by the slave so as to feed back the response result of the debugging instruction through the same reading protocol and writing protocol, thereby defining feedback and processing mechanisms of various abnormal conditions. In specific implementation, the acknowledgement bits utilize NACK/ACK transmitted by IIC, and ensure timely feedback of abnormal state by giving different meanings to NACK/ACK signals at different moments.

(1) When the reply message is a write protocol.

The slave writes the reply bits after writing the fields of the protocol.

As shown in fig. 2, a schematic diagram of the basic writing protocol is shown. Each bin in the figure represents a bit, and the light bit is written by the slave and used as a reply bit (AC) in the reply message.

The reply bit after the first slave address (SL) indicates whether the first slave address is valid. After receiving the debugging information, the slave machine judges whether the first slave machine address is a local address or not, and sets the value of the response bit in the response message according to the judging result; the host can determine whether the debug information is sent to the correct host based on the value of the reply bit.

A response bit after the instruction (CM) indicates whether the slave is idle. When the slave is idle, a corresponding instruction can be executed, and after the instruction execution is completed, the slave sets the response bit in the response message to be true; the host may determine whether the instruction has been executed by the slave based on the value of the reply bit.

The response bit after each read-write Address (AD) indicates whether the read-write address is legal or not. After the slave receives the writing protocol, before data writing is required according to a Writing Data (WD) writing instruction in the writing protocol and a position corresponding to the reading and writing address, whether the reading and writing address is legal or not is required to be judged, and the value of the response bit in the response message is set according to the judging result; the host can determine whether the write address is legal according to the value of the response bit.

The reply bit after each Write Data (WD) byte indicates whether the slave can continue writing. After each slave machine writes one byte of data, judging whether the slave machine can continue writing, if so, setting the response bit after the byte as true; the host can determine which write data bytes have been written to the slave based on the value of the reply bit, and whether the slave can continue writing data.

(2) When the reply message is a read protocol.

The slave machine writes the response bit after reading each field of the protocol, and writes the read data after reading the flag.

As shown in fig. 3, a schematic diagram of the basic read protocol is shown. Each cell in the figure represents a bit, and the light bit is written by the slave and used as response information.

The reply bit following the second slave address (SL) indicates whether the second slave address is valid. After receiving the debugging information, the slave machine judges whether the second slave machine address is a local address, and sets the value of the response bit in the response message according to the judging result; the host can determine whether the debug information is sent to the correct host based on the value of the reply bit.

The response bit after each read-write Address (AD) indicates whether the read-write address is legal or not. After the slave receives the writing protocol, the slave needs to read data according to the reading and writing address in the reading protocol, before the data is read, the slave needs to judge whether the reading and writing address is legal or not, and the value of the response bit in the response message is set according to the judging result; the host can determine whether the write address is legal according to the value of the response bit.

Each Read Data (RD) is 1 byte, representing data read by a read-write address, the number of bytes being determined by the instruction. After each slave machine reads one byte of data, sequentially writing the read data into a read data field according to bytes; after receiving the response message, the host sequentially receives each byte in the read data, and sets the response bit after each read data byte.

In some embodiments, the meaning of the response bit in the writing protocol and the reading protocol may be set with reference to the following table, and may also be adjusted according to the meaning and the effect of other fields.

It will be appreciated that in practical applications, the host may also select the processing to be performed next according to the value of the response bit of the slave. When the host computer prepares to write data, if the response bit of the slave computer after the instruction replies a no response, the current transmission is terminated, and retransmission is executed after the specified waiting time. For example, when the host receives the response information returned after the slave receives the read protocol and prepares to receive and write the read data in the response information, if the slave replies with NACK after finding that the slave receives the CM field, the slave can not continue to read the data, the transmission can be terminated, and retransmission is performed after a period of time, so that the loss of the data is avoided.

In the above communication protocol, the CM field is used to carry the debug instruction issued by the host. In practical implementations, the master also needs to transmit some other information to the slaves. Thus, some additional functionality may also be implemented by adding CM bytes. The following simply provides some information that may be carried in the CM field, and in a specific implementation, the content carried in the CM field may be defined as needed.

(1) Alignment mode

The instruction includes the alignment mode of the continuous data stream so that the slave machine can write or read according to different unpacking modes of the continuous data stream.

Different unpacking writing or reading modes of the continuous data stream can be realized through an alignment mode in the CM bytes, and the data integrity is ensured. Meanwhile, by the mode, an accurate AMBA bus request can be sent out, the data transmission efficiency is improved, and the bus occupation is reduced.

In practical implementation, the batch data may be unpacked according to different alignment modes, and the specific alignment mode and unpacking mode may be determined according to the actual data read-write requirements. For example: in a certain practical scenario, the data size to be read and written is: 8Bytes, the starting address of the read-write is: the read-write addresses of the different unpacking modes can be referred to as 0x2000 in the following table.

(2) Read-write attributes

The instruction contains a read-write attribute mode so as to obtain the timing of early judgment and timely response according to the read-write attribute by the slave machine.

In a general IIC protocol, in a slave address writing stage, a slave cannot directly determine whether a request in a debug instruction is a read request or a write request according to a read tag or a write tag, so that the problem that data to be read needs to be waited for and written cannot be buffered in time and is lost may be caused. Therefore, the timing of judging and responding in time can be given to the slave in advance by introducing the read-write attribute in the CM byte,

in order to solve the limitation of the existing SOC chip debugging means, the method for debugging the system on chip provided by the embodiment of the invention adopts the IIC protocol as the physical layer protocol, and designs and realizes the SOC debugging method based on the IIC protocol. Based on the IIC protocol, the system communicates with the debugging host through the form of an IIC slave interface on the SOC to be tested, the debugging information of the host is converted into an internal bus signal, and a series of ACK/NACK mechanisms are designed by utilizing the response of the IIC protocol, so that different transmission requests and error processing are realized. By the method provided by the embodiment, an independent, easy-to-use and high-reliability SOC debugging means compatible with the IIC standard can be realized with extremely low development cost. By integrating the invention in the SOC system, the system can be connected with any host equipment supporting the IIC protocol, thereby facilitating the access and debugging of the data in the chip.

On the basis of the method for debugging the system-on-chip provided by the embodiment, the invention also provides a device for debugging the system-on-chip, which can be used for realizing the method.

Fig. 4 is a schematic diagram of a device architecture according to an embodiment of the present invention. The device comprises: the IIC protocol analysis module, the FIFO module and the on-chip bus module are used for realizing the method for debugging the system-on-chip provided by the embodiment. The IIC protocol analysis module is connected with external IIC equipment through an IIC interface, the IIC protocol interface is connected with the FIFO module and the on-chip bus module, and the on-chip bus module is connected with the on-chip system through an on-chip bus protocol. In practical implementation, each module may be a separate or integrated hardware module or a software logic module.

The IIC protocol analysis module analyzes and drives the IIC interface protocol to finish the sending of the debugging information and the receiving of the response information. The IIC protocol analysis module mainly has the function of analyzing and driving an IIC interface protocol, and is in accordance with a standard IIC protocol to support different communication rates.

The FIFO module buffers write data in the write protocol. The FIFO module has the main function of caching written data and avoiding congestion and data loss.

The on-chip bus module converts debug information into on-chip bus signals. AMBA mainly converts a read-write request into a corresponding AMBA interface behavior, and can be implemented by using a specific bus structure such as AXI, AHB, APB according to requirements and functions.

In some embodiments, the connection between the master and the slave may be made in the manner shown in fig. 5. In the host, the device provided by the embodiment is integrated, and the SOC system in the device can be communicated with any equipment supporting the IIC interface, and can communicate without depending on a CPU after power-on and system reset by using the method provided by the embodiment to interact debugging information and response information. In practical implementation, the device and the IIC interface device provided in this embodiment may be used as a master or a slave in the foregoing embodiments. When the device provided in this embodiment sends debug information, the device provided in this embodiment serves as a master, and the device of the IIC interface serves as a slave; when the device of the IIC interface transmits the debug information, the device of the IIC interface serves as a master, and the apparatus provided in this embodiment serves as a slave.

Errors or anomalies may occur both during communication by the host and from the memory, as well as in response to debug instructions by the device. Therefore, when the device provided in this embodiment is debugged, it is further required to quickly determine the communication state of the other party in advance and process the communication state in time according to the state of the response bit in the communication protocol provided in the above embodiment.

As shown in fig. 6, the determination process for each response bit in the write protocol is as follows.

Step 201: and judging whether the slave addresses are matched according to the response bits after the slave addresses.

Step 202: judging whether the slave equipment is idle according to the response bit after the instruction.

Step 203: and judging whether the requested write address is legal or not according to the response bit after the address is read and written.

Step 204: and judging whether the slave can perform continuous writing according to the response bit after writing the data.

After steps 201 to 204 provided in this embodiment, errors or anomalies common in debugging can be determined, and the device can process in time according to the determination result.

As shown in fig. 7, the determination process for each response bit in the write protocol is as follows.

Step 301: and judging whether the slave addresses are matched according to the response bits after the second slave addresses.

Step 302: judging whether the slave equipment is idle according to the response bit after the instruction.

Step 303: and judging whether the read address of the request is legal or not according to the response bit after the address is read and written.

Step 304: and judging whether the slave addresses are matched according to the response bits after the third slave address.

Step 305: and judging whether the reading of the byte data is finished or not according to the response bit after each byte of the read data.

Step 306: and judging whether continuous reading is carried out according to the response bit after the data reading.

After steps 301 to 306 provided in this embodiment, errors or anomalies common in debugging can be determined, and the device can process in time according to the determination result.

The foregoing description of the preferred embodiments of the invention is not intended to be limiting, but rather is intended to cover all modifications, equivalents, and alternatives falling within the spirit and principles of the invention.

Claims

1. A method for debugging a system-on-chip, comprising:

the method comprises the steps that a host generates debugging information of a system-on-chip, the debugging information is converted into an on-chip bus signal, and the debugging information is sent to a slave machine in the form of the on-chip bus signal through an IIC protocol;

the slave generates response information according to the received debugging information, and sends the response information to the host by using an IIC protocol;

the host receives the response information through the IIC protocol, analyzes the response information into a bus signal on a chip, analyzes the bus signal on the chip, and obtains a debugging result according to the analyzed response content.

2. The method of system-on-chip debugging according to claim 1, wherein when the debugging information is a write protocol, the generating the debugging information of the system-on-chip comprises:

the host writes the fields in the write protocol: the first start bit, the first slave address, the write flag, the instruction, the read-write address, the write data and the stop bit;

wherein the first start bit is 1 bit, indicating that the write protocol starts;

the first slave address is 1 byte, which indicates the slave address to which the debug information needs to be sent;

the writing mark is 1 bit, which indicates that the slave needs to write data;

the instruction is 1 byte, which indicates the debug instruction that needs to be executed by the slave;

the read-write address is 4 1 bytes and represents the read-write address corresponding to the instruction;

the writing data is at least 1 byte, which represents the data written into the slave, and the number of bytes is determined according to the instruction;

the stop bit is 1 bit indicating that the write protocol is over.

3. The method of claim 1, wherein generating the debug information for the system-on-chip when the debug information is a read protocol comprises:

the host writes the fields in the read protocol: the second start bit, the second slave address, the write flag, the instruction, the read-write address, the third start bit, the third slave address, the read flag, the first response bit, the no-response and the stop bit;

wherein the second start bit is 1 bit, indicating that the read protocol is started;

the second slave address is 1 byte, which indicates the slave address to which the debug information needs to be sent;

the writing mark is 1 bit, which indicates that the second slave address is the slave address needing writing;

the third start bit is 1 byte, indicating that the read-out section starts;

the third slave address is 4 bytes, which represents the data reading address in the slave;

the reading mark is 1 bit, which indicates that the third slave address is the slave address which needs to be read;

the first response bit is 1 bit, which indicates whether the host can continuously write data;

whether the response bit is 1 bit indicates whether the host has completed receiving the read data;

the stop bit is 1 bit and indicates that the protocol is complete.

4. A method for debugging a system-on-chip according to claim 2 or 3, wherein the instruction is 1 byte, which indicates that the slave needs to execute a debug instruction, and the method comprises:

5. A method for debugging a system-on-chip according to claim 2 or 3, wherein the instruction is 1 byte, which indicates that the slave needs to execute a debug instruction, and the method comprises:

6. The method of system-on-chip debugging according to claim 3, wherein the no reply bit is 1 bit, indicating whether the host has completed receiving the read data, comprising:

after the host finishes receiving the read data, a no-answer field is given.

7. The method for debugging a system-on-chip of claim 1, wherein when the debugging information is a write protocol, the slave generating response information according to the received debugging information comprises:

the slave writes the response bits after writing the fields of the protocol:

wherein, the response bit after the first slave address indicates whether the first slave address is legal or not;

a response bit after the instruction indicates whether the slave is idle;

the response bit after each read-write address indicates whether the read-write address is legal or not;

the reply bit after each write data byte indicates whether the slave can continue writing.

8. The method for debugging a system-on-chip of claim 1, wherein when the debugging information is a read protocol, the slave generating response information according to the received debugging information comprises:

the slave machine writes response bits after reading each field of the protocol, and writes read data after reading the mark;

wherein, the response bit after the second slave address indicates whether the second slave address is legal;

a response bit after the instruction indicates whether the slave is idle;

each read data is 1 byte, representing data read by a read-write address, the number of bytes being determined by the instruction.

9. The method for debugging a system-on-chip according to claim 1, wherein said parsing the reply information into a bus-on-chip signal further comprises:

when the host computer prepares to write data, if the response bit of the slave computer after the instruction replies a no response, the current transmission is terminated, and retransmission is executed after the specified waiting time.

10. An apparatus for debugging a system-on-chip, comprising: an IIC protocol parsing module, a FIFO module and a bus-on-chip module, for performing the method for system-on-chip debugging provided in any one of claims 1 to 9, comprising:

the IIC protocol analysis module is connected with external IIC equipment through an IIC interface, the IIC protocol interface is connected with the FIFO module and the on-chip bus module, and the on-chip bus module is connected with the on-chip system through an on-chip bus protocol;

the IIC protocol analysis module analyzes and drives the IIC interface protocol to finish the sending of the debugging information and the receiving of the response information;

the FIFO module caches write data in a write protocol;

the on-chip bus module converts debug information into on-chip bus signals.