CN110266442A - A kind of digital signal serial transmission method - Google Patents
A kind of digital signal serial transmission method Download PDFInfo
- Publication number
- CN110266442A CN110266442A CN201910680812.8A CN201910680812A CN110266442A CN 110266442 A CN110266442 A CN 110266442A CN 201910680812 A CN201910680812 A CN 201910680812A CN 110266442 A CN110266442 A CN 110266442A
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- data
- coding
- serial
- digital signal
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Classifications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/0001—Systems modifying transmission characteristics according to link quality, e.g. power backoff
- H04L1/0006—Systems modifying transmission characteristics according to link quality, e.g. power backoff by adapting the transmission format
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/0078—Avoidance of errors by organising the transmitted data in a format specifically designed to deal with errors, e.g. location
- H04L1/0079—Formats for control data
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/0078—Avoidance of errors by organising the transmitted data in a format specifically designed to deal with errors, e.g. location
- H04L1/0083—Formatting with frames or packets; Protocol or part of protocol for error control
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0008—Synchronisation information channels, e.g. clock distribution lines
Abstract
The invention discloses a kind of digital signal serial transmission methods, this method is using list bit serial signal line transmission data and clock, set 4B/5B coding structure and located byte boundary, steady-working state is entered using adaptive synchronicity mechanism control receiving end, 5B serial link data encapsulation format is set, digital signal serial transmission is carried out.The present invention is by setting clock with many aspects such as data, demarcation, synchronous, encapsulation, have the advantages that low-speed serial protocol realization is simple, also there is the transmission bandwidth close to high speed transport protocols lower limit simultaneously, realize effective application of hundred M grades of internal system digital signal serial transmission.
Description
Technical field
The invention belongs to serial transfer techniques fields, and in particular to a kind of digital signal serial transmission method.
Background technique
Currently used serial transmission scheme has two classes, and one kind is low-speed serial agreement, such as I2C, SPI, UART etc., speed
Rate is transmitted between several hundred Kbps to several Mbps using 2-4 root signal wire；Another kind of is HSSI High-Speed Serial Interface (serdes), rate
Usually in about 600Mbps to 10Gbps+, the serial protocol of single line usually uses a pair of of high-speed differential signal line, such as common
GE, PCIEx1, SRIO x1 etc..
Existing serial transmission scheme is primarily present following problems:
(1) existing open serial protocol has the white space of a transmission bandwidth, is exactly tens to this area several hundred Mbps
Between, it is not covered with.Low-speed serial protocol rate is not achieved, and high speed serialization protocol rate is unable to come down again.
(2) for the serial transmission of this rank of 100M~400Mbps, if using high speed serialization agreement, bandwidth waste
While, the technology complexity of bringing is significantly increased, it is often necessary to using the dedicated IP of supplier, requirement to designer compared with
The increased costs of height, equipment debugging and maintenance.
Summary of the invention
The main purpose of the present invention is to provide a kind of digital signal serial transmission methods, it is intended to solve existing method and exist
The above technical problem.
To achieve the above object, the present invention provides a kind of digital signal serial transmission method, comprising the following steps:
Single bit serial signal line is respectively adopted and transmits data and clock from transmitting terminal to receiving end, at road clock
Reason receives data；
4B/5B coding structure is set, and uses link control code located byte boundary；
According to the byte boundary of positioning, steady-working state is entered using adaptive synchronicity mechanism control receiving end；
5B serial link data encapsulation format is set, digital signal serial transmission is carried out.
Further, described single bit serial signal line is respectively adopted to transmit data and clock also from transmitting terminal to receiving end
Include:
Using the homologous clock of system by list bit serial signal line respectively to transmitting terminal and receiving end transmission data and when
Clock.
Further, the setting 4B/5B coding structure specifically:
Data pattern coding, shape are carried out to data 0000-1111 and coding 00010-01011 using 4B/5B coding mode
At 16 data encodings comprising user data 4B；And it sets IDLE coding and is opened as Idle state control code, SOF coding as frame
Head control code, EOF coding are used as End of Frame control code.
It is further, described to use link control code located byte boundary specifically:
By detecting pattern corresponding with IDLE coding, the boundary of 5bit byte is positioned.
It is further, described that steady-working state is entered using adaptive synchronicity mechanism control receiving end specifically:
Set the delay size that receiving end receives serial data；
Detection IDLE coding site is found in displacement；
Judge whether there is more than two continuous correctly IDLE codings；If so, receiving end enters synchronous regime；If
It is no, then readjust the delay size that receiving end receives serial data；
Judge whether there is the IDLE coding of more than one mistake；If so, receiving end enters desynchronizing state, readjust
The delay size of receiving end reception serial data；If it is not, then receiving end goes successively to synchronous regime.
Further, the setting 5B serial link data encapsulation format specifically:
5B serial link data encapsulation format is set as 21 data encodings, including frame data section and free segment；The frame
Data segment includes 16 comprising user data 4B being arranged among the SOF coding of frame beginning, the EOF coding of End of Frame and frame
A data encoding；The free segment includes three continuous IDLE codings of setting.
The beneficial effects of the present invention are: the present invention by clock and many aspects such as data, demarcation, synchronous, encapsulation into
Row setting, has the advantages that low-speed serial protocol realization is simple, while also having the transmission belt close to high speed transport protocols lower limit
Width realizes effective application of hundred M grades of internal system digital signal serial transmission.
Detailed description of the invention
Fig. 1 is digital signal serial transmission method flow schematic diagram of the invention；
Fig. 2 is clock and data transmission schematic diagram in one embodiment of the invention；
Fig. 3 is clock and data transmission schematic diagram in another embodiment of the present invention；
Fig. 4 is adaptive synchronicity mechanism flow diagram in the present invention；
Fig. 5 is 5B serial link data encapsulation format schematic diagram in the present invention.
Specific embodiment
In order to make the objectives, technical solutions, and advantages of the present invention clearer, with reference to the accompanying drawings and embodiments, right
The present invention is further elaborated.It should be appreciated that described herein, specific examples are only used to explain the present invention, not
For limiting the present invention.
Primary solutions provided in an embodiment of the present invention are:
As shown in Figure 1, a kind of digital signal serial transmission method, comprising the following steps:
Single bit serial signal line is respectively adopted and transmits data and clock from transmitting terminal to receiving end, at road clock
Reason receives data；
4B/5B coding structure is set, and uses link control code located byte boundary；
According to the byte boundary of positioning, steady-working state is entered using adaptive synchronicity mechanism control receiving end；
5B serial link data encapsulation format is set, digital signal serial transmission is carried out.
The present invention reduces technology complexity and design cost to solve the problems, such as 100,000,000 grades of serial transmission, proposes
The new digital signal serial transmission method of one kind, cover clock and many aspects such as data, demarcation, synchronous, encapsulation.
In an alternate embodiment of the present invention where, the present invention utilizes transmitting terminal source sync cap, is serially believed by single bit
Number line receives clock, and receiving end handles reception data using with road clock clock, as shown in Figure 2.
Selectively, as shown in figure 3, the present invention also utilize the homologous clock of system by list bit serial signal line respectively to
Transmitting terminal and receiving end transmission data and clock.
The present invention uses the transmission mode of above-mentioned clock and data, is transmitted by single bit signal wire, farthest
Save I/O chip number of pin；And the complex technology that high speed serialization agreement needs to do clock recovery is avoided, is passed simultaneously
The risk of RX sample error is also not present at 100,000,000 grades for defeated rate, and implementation is simple.
In an alternate embodiment of the present invention where, the present invention needs standard when the direction RX is unstringed from serial data line
It determines bit byte boundary, therefore by setting 4B/5B coding structure, and uses link control code located byte boundary.
Programmable logic device (FPGA) of the present invention realizes encoding and decoding, compiles different from traditional 3B/4B coding and 5B/6B
Code, it is contemplated that the storage resource consumption during realizing, speed of tabling look-up, influence of the lookup table circuit to engineering sequential organization, coding
The multiple factors such as efficiency of transmission loss set a kind of new 4B/5B coding structure.
The present invention carries out data pattern volume to data 0000-1111 and coding 00010-01011 using 4B/5B coding mode
Code forms 16 data encodings comprising user data 4B, as shown in table 1.
Table 1, data pattern coding schedule
| Data | Coding |
| 0000 | 00010 |
| 0001 | 01010 |
| 0010 | 10001 |
| 0011 | 00011 |
| 0100 | 10101 |
| 0101 | 01000 |
| 0110 | 10010 |
| 0111 | 00101 |
| 1000 | 10100 |
| 1001 | 00100 |
| 1010 | 01001 |
| 1011 | 01101 |
| 1100 | 10110 |
| 1101 | 01100 |
| 1110 | 00110 |
| 1111 | 01011 |
It can be realized 80% serial transmission efficiency using above-mentioned 4B/5B coding structure.
The present invention does not allow to occur continuous 41 on serial link when carrying out continuous user data transmission.5B
There are 32 patterns, after transmitting 16 data of user data 4B, there remains 16 redundancy patterns, therefore set therein
Several patterns are used as Idle state control code, SOF (Start-of-frame) as link control code, specially setting IDLE coding
Coding is used as End of Frame control code as frame beginning control code, EOF (End-of-frame) coding.
IDLE:11110 indicates Idle state, when serial link does not have user data to need to send, transmission IDLE,
Different from any one data pattern.
SOF:11011, indicates frame boundaries, and frame beginning is different from any one data pattern.
EOF:11101 indicates that frame boundaries, End of Frame are different from any one data pattern.
In 4B/5B coding structure, only IDLE coding will appear continuous 41；Therefore it is encoded by detection and IDLE
Corresponding pattern, i.e. RX are identified as an IDLE coding, thus accurately when detecting continuous 41 and subsequent one 0
Delimit out the boundary of the 5bit in serial signal line.For the data encoding not in upper table, nor the 5B data of control code,
For illegal pattern.
In an alternate embodiment of the present invention where, the present invention judges whether accurately to find by the position of searching IDLE
It has arrived byte boundary and whether receiving end sampling is correct.Commonly used digital device, such as the IO of programmable logic device (FPGA)
Data delay can be adjusted, by adjusting the size of the RX serial data delay received, sample trigger is enable accurately to sample
To the data of RX.Once control code IDLE is wrong, desynchronizing state is entered, the IO delay of RX need to be readjusted, it is ensured that the end RX
Reenter synchronous regime.Using the synchronization mechanism of this constantly adaptive adjustment IO delay, until none of illegal
Until pattern, the end RX, which enters, stablizes correct working condition.
As shown in figure 4, entering steady-working state using adaptive synchronicity mechanism control receiving end specifically:
Set the delay size that receiving end receives serial data；
Detection IDLE coding site is found in displacement；
Judge whether there is more than two continuous correctly IDLE codings；If so, receiving end enters synchronous regime；If
It is no, then readjust the delay size that receiving end receives serial data；
Judge whether there is the IDLE coding of more than one mistake；If so, receiving end enters desynchronizing state, readjust
The delay size of receiving end reception serial data；If it is not, then receiving end goes successively to synchronous regime.
In an alternate embodiment of the present invention where, the present invention sets 5B serial link data encapsulation format, such as Fig. 5 institute
Show.5B serial link data encapsulation format is 21 data encodings, including frame data section and free segment；Frame data section includes setting
16 data encodings comprising user data 4B among the SOF coding of frame beginning, the EOF coding of End of Frame and frame；It is empty
Not busy section includes three continuous IDLE codings of setting.
The present invention combines the advantages of existing disclosed low speed and high speed serial transmission agreement, with low-speed serial agreement
It realizes simple advantage, and is much larger than the transmission bandwidth of low-speed serial agreement；It has the biography close to high speed transport protocols lower limit
Defeated bandwidth has more than the realization of high speed serialization transceiver simply, is the excellent of the internal system digital signal serial transmission of hundred M grades of one kind
Select scheme.
Those of ordinary skill in the art will understand that the embodiments described herein, which is to help reader, understands this hair
Bright principle, it should be understood that protection scope of the present invention is not limited to such specific embodiments and embodiments.This field
Those of ordinary skill disclosed the technical disclosures can make according to the present invention and various not depart from the other each of essence of the invention
The specific variations and combinations of kind, these variations and combinations are still within the scope of the present invention.
Claims (6)
1. a kind of digital signal serial transmission method, which comprises the following steps:
Single bit serial signal line is respectively adopted and transmits data and clock from transmitting terminal to receiving end, is connect using being handled with road clock
Receive data；
4B/5B coding structure is set, and uses link control code located byte boundary；
According to the byte boundary of positioning, steady-working state is entered using adaptive synchronicity mechanism control receiving end；
5B serial link data encapsulation format is set, digital signal serial transmission is carried out.
2. digital signal serial transmission method as described in claim 1, which is characterized in that described that single bit is respectively adopted is serial
Signal wire transmits data and clock from transmitting terminal to receiving end further include:
Data and clock are transmitted to transmitting terminal and receiving end respectively by list bit serial signal line using system homologous clock.
3. digital signal serial transmission method as claimed in claim 2, which is characterized in that the setting 4B/5B coding structure
Specifically:
Data pattern coding is carried out to data 0000-1111 and coding 00010-01011 using 4B/5B coding mode, forms packet
16 data encodings of the 4B containing user data；And IDLE coding is set as Idle state control code, SOF coding as frame beginning control
Code processed, EOF coding are used as End of Frame control code.
4. digital signal serial transmission method as claimed in claim 3, which is characterized in that described to be positioned using link control code
Byte boundary specifically:
By detecting pattern corresponding with IDLE coding, the boundary of 5bit byte is positioned.
5. digital signal serial transmission method as claimed in claim 4, which is characterized in that described to use adaptive synchronicity mechanism
It controls and receives end and enters steady-working state specifically:
Set the delay size that receiving end receives serial data；
Detection IDLE coding site is found in displacement；
Judge whether there is more than two continuous correctly IDLE codings；If so, receiving end enters synchronous regime；If it is not, then
Readjust the delay size that receiving end receives serial data；
Judge whether there is the IDLE coding of more than one mistake；If so, receiving end enters desynchronizing state, readjusts and receive
End receives the delay size of serial data；If it is not, then receiving end goes successively to synchronous regime.
6. digital signal serial transmission method as claimed in claim 5, which is characterized in that the setting 5B serial link data
Encapsulation format specifically:
5B serial link data encapsulation format is set as 21 data encodings, including frame data section and free segment；The frame data
Section includes 16 numbers comprising user data 4B being arranged among the SOF coding of frame beginning, the EOF coding of End of Frame and frame
According to coding；The free segment includes three continuous IDLE codings of setting.
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| CN114024609A (en) * | 2021-11-11 | 2022-02-08 | 中国电子科技集团公司第三十八研究所 | Data composite time sequence transmission method based on SERDES |
| CN115694738A (en) * | 2022-10-31 | 2023-02-03 | 上海铼钠克信息技术有限公司 | Serial error reporting communication system and method |
| WO2023125653A1 (en) * | 2021-12-29 | 2023-07-06 | 国民技术股份有限公司 | Calibration apparatus for low voltage i2c communication, system, and method |
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