CN108011694B - A kind of efficient data exchange method based on FC - Google Patents

A kind of efficient data exchange method based on FC Download PDF

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Publication number
CN108011694B
CN108011694B CN201711225376.2A CN201711225376A CN108011694B CN 108011694 B CN108011694 B CN 108011694B CN 201711225376 A CN201711225376 A CN 201711225376A CN 108011694 B CN108011694 B CN 108011694B
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state machine
port
data
layers
frame
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CN108011694A (en
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陶飞
唐玥
战仕成
邹孝付
李建国
范宜敏
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SNEFETECH Corp
Beihang University
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SNEFETECH Corp
Beihang University
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/0001—Systems modifying transmission characteristics according to link quality, e.g. power backoff
    • H04L1/0006—Systems modifying transmission characteristics according to link quality, e.g. power backoff by adapting the transmission format
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
    • H04B10/25—Arrangements specific to fibre transmission
    • H04B10/2589—Bidirectional transmission
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/0001—Systems modifying transmission characteristics according to link quality, e.g. power backoff
    • H04L1/0009—Systems modifying transmission characteristics according to link quality, e.g. power backoff by adapting the channel coding
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0061—Error detection codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L63/00—Network architectures or network communication protocols for network security
    • H04L63/12—Applying verification of the received information
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L67/00—Network arrangements or protocols for supporting network services or applications
    • H04L67/50—Network services
    • H04L67/56—Provisioning of proxy services
    • H04L67/565—Conversion or adaptation of application format or content
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L67/00—Network arrangements or protocols for supporting network services or applications
    • H04L67/50—Network services
    • H04L67/56—Provisioning of proxy services
    • H04L67/568—Storing data temporarily at an intermediate stage, e.g. caching
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
    • H04L69/22—Parsing or analysis of headers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0008—Synchronisation information channels, e.g. clock distribution lines

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  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Computer Security & Cryptography (AREA)
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Abstract

The invention discloses a kind of, and the efficient data based on FC exchanges method, including：Utilize the conversion module of FC-0 layers in FPGA design FC agreement of high-speed serial datas to low-speed parallel data, high-speed serial digital signal can be converted into the parallel data of relative low speeds by the module, while debounce, locking and the recovery of reference clock are completed by the state machine of design；Using FC-1 layers in FPGA design FC agreement of 8b/10b encoding and decoding, the alignment of transmission word boundary and the detection of transmission word legitimacy, primitive detection, the control of receiver state machine, FC port state machine and transmitter status machine, to guarantee jumping for FC port status；Using FC-2 layers in FPGA design FC agreement of Frame Protocol parsing module, which can complete the parsing, registration and unregistration, buffer area of Frame Protocol to the flow control of buffer area, to guarantee the legitimacy of frame transmission.

Description

A kind of efficient data exchange method based on FC
Technical field
Present invention relates particularly to a kind of, and the efficient data based on FC exchanges method, belongs to electronic engineering and computer science neck Domain.
Background technique
With the development of information technology, big data processing has become the key technology of support upper layer decision.Especially exist Intelligence manufacture field, " made in China 2025 " and " internet+advanced of German Industrial 4.0, American industry internet and China The intelligence manufacture to be realized is not without a large amount of data are included in manufacturing industry ", acquisition including workshop level bottom isomeric data, It handles and transmits, the data transmission between factory level ERP, MES and the data transmission between factory etc..How big data is realized Efficient process is come to support upper layer decision be to realize that intelligence manufacture needs one of the critical issue that solves.There is a large amount of for plant site Heterogeneous resource, the sensing of the lathe of production line, different model including different manufacturers and different agreement executes equipment how Efficiently realizing the data exchange between these heterogeneous resources again is one of the key technology for realizing big data efficient process.
With the development of information technology, there are many Data Transport Protocol standards, including common Industrial Ethernet, Modbus and Zigbee etc., but in terms of the efficiency of data processing, FC (Fiber Channel, optical-fibre channel) agreement tool Standby great advantage.FC has many advantages, such as high bandwidth, low latency, long distance transmission, topological flexible, a variety of upper-layer protocols of support, It is the communication protocol for being adaptation high-performance data transmission requirement and designing.
FC is applied at present in the advanced fighter of the states such as America and Europe, is aviation electronic bus agreement of new generation, is capable of providing The support of unified avionics network of new generation building under avionics system.American National Standard Committee also specially sets up Research optical-fibre channel is used for the sub-committee (ANSI FC-AE) of avionics system, the sub-committee and Boeing, Lip river The cooperations such as gram West Germany-Martin Corporation have formulated one group dedicated for the FC protocol subset of avionics system, i.e. optical-fibre channel is navigated Empty electronic environment (FC-AE).Optical-fibre channel substitutes current aviation electronics major network MIL-STD-1553, it has also become aviation electronics system The inexorable trend of system development, optical-fibre channel will also become the first choice of the unified avionics network of building a new generation.FPGA conduct Programmable hardware logic devices have the parallel processing and hardware-accelerated characteristic of height, are conducive to the realization of FC agreement.
So advanced efficient FC agreement is applied to civil field, realize that the efficient data of manufacture bottom heterogeneous resource are handed over It changes, is capable of the realization early of the great strategy of power-assisted China intelligence manufacture.
Summary of the invention
The technical problem to be solved in the present invention is：A kind of efficient data exchange method based on FC is provided, including：It utilizes For FC-0 layers of high-speed serial data to the conversion module of low-speed parallel data, which can be by high speed in FPGA design FC agreement Serial digital signal is converted into the parallel data of relative low speeds, at the same by the state machine of design complete reference clock debounce, Locking and recovery；Utilize FC-1 layers in FPGA design FC agreement of 8b/10b encoding and decoding, the alignment of transmission word boundary and transmission word Legitimacy detection, primitive detection, the control of receiver state machine, FC port state machine and transmitter status machine, to guarantee the end FC Mouth state jumps；Using FC-2 layers in FPGA design FC agreement of Frame Protocol parsing module, which can complete Frame Protocol Parsing, registration and unregistration, the flow control of buffer area to buffer area, with guarantee frame transmission legitimacy.
The present invention solves its technical problem and adopts the following technical solutions to achieve：A kind of efficient data exchange based on FC Method includes the following steps：
Step 1：Design conversion module of FC-0 layers in FC agreement of the high-speed serial data to low-speed parallel data, the mould High-speed serial digital signal can be converted into the parallel data of relative low speeds by block, while complete reference by the state machine of design Debounce, locking and the recovery of clock.It is implemented as follows：
1. designing module work under the rate of 8.5Gbps, the phaselocked loop of QPLL is selected, keeps FC-0 serioparallel exchange module each CHANNEL (channel) shares same reference clock；
2. utilizing the debounce state machine of FPGA design reference clock, and goes here and there and turn using the clock output after debounce as FC-0 Change the mold the reference clock of block.Debounce state machine controls debounce chip by IIC agreement.According to designing in 1. 8.5Gbps operating rate, the reference clock after the debounce designed herein are 212.5MHZ.K28.5 is designed as control word simultaneously Section, clock correction sequence are 10111100 ＂ of ＂.
Step 2：Design FC-1 layers in FC agreement of 8b/10b encoding and decoding, transmission word boundary is aligned and transmission word is legal Property detection, primitive detection, receiver state machine, FC port state machine and transmitter status machine control, to guarantee the port FC shape State jumps.It is implemented as follows：
1. the encoding and decoding for being arranged FC-1 layers are the inside bit wide (outside of 32bit of the code encoding/decoding mode of 8B/10B, 40bit Bit wide), the reference clock of 212.5MHZ, K28.5 as comma, and in a program examine comma whether be in the low of 40bit 8bit。
2. being designed using VHDL language, multiple subroutine modules simultaneously and concurrently complete the detection of transmission word legitimacy, primitive is examined Survey, receiver state machine, FC port state machine and transmitter status machine.State machine is broadly divided into receiver state machine, transmitter State machine, port state machine.Data are completed after serioparallel exchange and encoding and decoding by FC-0 serioparallel exchange module with 32bit (one Word) it is sent to receiver state machine, receiver operation clock is 212.5MHZ.FC port state machine is completed the activation of link and is led to Cross a series of handshake mechanism completion status conversions.After device power or entrance reset state, the port FC can be held by a series of Mobile phone system enters activated state by non-initialization state, to start normal data communication.Gear send data when, data with 32bit (word) is sent to transmitter status machine, and transmitter work clock is 233.33MHZ.
Step 3：Design FC-2 layers of Frame Protocol parsing module in FC agreement, the module can complete Frame Protocol parsing, Registration and unregistration, the flow control of buffer area to buffer area, to guarantee the legitimacy of frame transmission.It is implemented as follows：
1. the port FC is after FC-1 layers of completion link activation, data are uploaded to FC-2 layers.FC-2 layers first carry out frame Parsing, frame includes SOF delimiter, frame head, payload, cyclic redundancy check field CRC, EOF delimiter.Process registers (PRLI) shape The port of communicating pair can be passed through mapping association composition mapping pair by state machine；Process nullifies (PRLO) state machine and is used to release this Kind mapping relations.The present invention is nullified using implicit, is nullified by continuously transmitting three or more NOS or OLS signals.
2. FC communication port both sides decide through consultation a credit value in advance, synchronized for the communication to both sides.Work as sender After sending a frame data, count value adds 1, and count value subtracts 1 after receiving effective reply of other side.When count value is equal to credit value, Sender, which suspends, to be sent, and is then sent state machine and is continued to monitor count value, and data are again started up when it is less than credit value and are sent.
A kind of efficient data exchange method based on FC that the present invention designs is suitable for Xilinx company Virtex-7FPGA Chip, model XC7VX690T-2FFG1761C；Clock jitter removing chip is the SI5324 of SiLABS company.
The advantages of the present invention over the prior art are that：
(1) the FC-0 serioparallel exchange module of designed, designed can replace the gigabit used in such method design at present to pass The method of defeated IP kernel, can be more flexible, economical design high-speed serial data to low-speed parallel data conversion.
(2) data correctness when clock jitter removing scheme used can guarantee high speed data transfer, the transmission for data The reference clock of different frequency is used with reception, and the stability of data transmit-receive can guarantee as buffering using BRAM.
(3) guarantee that the rate-matched of communicating pair, the method are simple and easy using credit value and transmission frame count value.
Detailed description of the invention
Fig. 1 is overall construction drawing of the invention；
Fig. 2 is FC-0 layers of serioparallel exchange module reference clock connection figure of the present invention；
Fig. 3 is FC-1 layer state machine part-structure design drawing of the present invention；
Fig. 4 is FC-2 layers of registration part flow chart of the present invention；
Fig. 5 is FC-2 layers of part-structure design drawing of the present invention.
Specific embodiment
Further detailed description is done to the present invention with reference to the accompanying drawing.
The present invention relates to a kind of, and the efficient data based on FC exchanges method, and the fpga chip used is Xilinx company XC7VX690T-2FFG1761C, clock jitter removing chip are the SI5324 of SiLABS company.It is as follows that content is embodied：
FC-0 layers：The conversion of fiber-optic signal and electric signal is completed using SFP module.FC-0 is the bottom of FC, i.e. physics Link layer, including transmission medium, transmitter, receiver and interface, it is general support with cable or optical cable connection, it is specified that transmission Rate is the multiple proportion of 1.0625Gbps.FC-0 serioparallel exchange state machine is designed based on FPGA and using VHDL language, with reality Conversion of the existing high-speed serial signals to low-speed parallel data.
The relevant configuration of the FC-0 serioparallel exchange module of design is as follows：The rate of 8.5Gbps, the CHANNEL being connected with SFP Positioned at BANK113.It is 8.5Gbps for rate, selects the phaselocked loop of QPLL, make each CHANNEL with same reference clock.FC-0 The design of serioparallel exchange module is verified using loopback test, including proximal end PCS, proximal end PMA, distal end PCS, distal end PMA.Selection REFCLK0 is reference clock, and by SI5324 chip to reference clock debounce.Wherein when the reference of FC-0 serioparallel exchange module Clock cut-in method is as shown in Fig. 2, system clock divide and be connected on debounce chip SI5324 by DCM IP kernel by FPGA, use IIC protocol configuration SI5324 chip completes debounce, then clock is connected back at FC-0 serioparallel exchange module.Iic bus includes Two signal line of SDA, SCL, SCL control clock, and SDA transmits data, and all data are with the transmission of 8bit byte.Utilize IIC agreement It is fashionable to specified register write, device address to be configured is first write, then write the address of register corresponding position to be configured to, then write number According to.IIC agreement of the invention selects a general line system chip U52 to configure by PCA9548IIC eight, and PCA9548 chip address is " 1110100 ", it include 8 channels IIC, configuration U52 chip will then use CH7, first to PCA9548 chip and Si5324 chip Reset operation is carried out, two chips are that high level is to work normally.Pass through IIC protocol format later for IIC_SDA/SCL_ MAIN is connected with Si5324_SDA/SCL, and Slave Address is " 1110100 ", Control Register be " 10000000 " selection CH7 is indicated.Last IIC communication standard protocol is written to Si5324 chip register to be configured.This When device address be " 1101000 ", the i.e. address of Si5324 chip.The N1_HS of Si5324 is 6, NC1_LS 6, and N2_HS is 9, N2_LS 316, N31 79.The reference clock REFCLK0 that can be detected FC-0 serioparallel exchange module after configuration is 212.5MHZ.Proximal end winding may be implemented at this time.Balanced mode selects LMP low-power consumption mode, to be suitable for line rate< The short-range applications of 11.2Gb/s, channel differential loss<The case where 12dB.After selecting this mode, proximal end winding can be multiple in selection Normal use in the case where channel.Interrupt voltage selects FLOAT, and CDR is locked at this time, and remote loop may be implemented.Due to FC Agreement only uses K28.5 as control byte, so selecting comma for K28.5, clock correction sequence is 10111100 ＂ of ＂, this When transmission word can be with snap border.Loop back mode can be set as normal mode after loopback test.
FC_1 layers：FC-0 serioparallel exchange module is configured according to FC agreement, FC-0 serioparallel exchange module is made to complete 8b/ 10b encoding and decoding, transmission word boundary alignment.It is set as the code encoding/decoding mode of 8B/10B, (32bit's is outer for the inside bit wide of 40bit Position is wide), the reference clock of 212.5MHZ, K28.5 as comma, and in a program examine comma whether be in the low of 40bit 8bit completes encoding and decoding, word alignment with this.
Multiple subroutine modules simultaneously and concurrently, which are designed, using VHDL language completes the detection of transmission word legitimacy, primitive inspection Survey, receiver state machine, FC port state machine and transmitter status machine.As shown in figure 3, state machine is broadly divided into receiver state Machine, transmitter status machine, port state machine.Data by FC-0 serioparallel exchange module complete after serioparallel exchange and encoding and decoding with The rxdata of 32bit is sent to receiver state machine, and transmission clock clk2 is 212.5MHZ.Receiver state machine includes primitive Table is primitive, general data or illegal data with detection data.State machine includes 3 states：(1) synch lost state. (2) word synchronous regime is obtained.(3) reset state.Wherein obtain word synchronous regime includes 4 sub- states again, is respectively：(1) do not have There is illegal transmissions word to be detected.(2) the 1st illegal transmissions words are detected.(3) the 2nd illegal transmissions words are detected. (4) the 3rd illegal transmissions words are detected.Only when state machine is in synchronous regime, transmission word, word clock could be believed Number, validity information pass to upper layer.Data are carried out after legitimacy detection in receiver state machine with 32bit's (word) Rx_out is uploaded to port state machine rx_in.The activation that port state machine completes link completes shape by a series of handshake mechanisms State conversion.When device power or enter reset state after, the port FC can by a series of handshake mechanisms by non-initialization state into Enter activated state, to start normal data communication.In the normal course of work, if dropout has occurred, request is super When, when the abnormal conditions such as link failure or step-out, there is corresponding mechanism in the port FC to carry out recovery link, the behaviour such as investigation failure Make.When port state machine is activated state, rx_out is to upper-layer protocol for bottom data upload, the upper-layer protocol data to be sent Tx_in is sent by transmitter status machine.When port state machine is not in activated state, then sent by transmitter status machine a series of Primitive agreement.Transmitter status machine state mainly includes three states：Invalid state, operating conditions, fault case.When state machine is in work Attempt to send by the bit data stream of coding the port shape to corresponding FC chain road transmitter status machine in operating conditions when posing The data tx_out that state machine is sent is sent to txdata_in.Data reach FC-0 by transmitter status machine with txdata_out Layer serioparallel exchange module.System clock clk1 is 233.33MHZ.
FC-2 layers：The parsing of multiple subroutine modules completion Frame Protocols simultaneously and concurrently is designed using VHDL language and is set Meter, registration and unregistration, the flow control of buffer area to buffer area.FC-2 layers mainly define link traffic and signaling protocol two The behavior and parameter of aspect.Defined in link traffic the main ports behaviors such as Fabric Login, port registration, process registers and Parameter meaning defines the composed structure of frame, the definition of frame head parameter, frame transmission process, N-port and the end F in signaling protocol The behavior of mouth, the method etc. of flow control.The data of FC-2 are as unit of frame.The invention mainly relates to device data frame and extensions Link data frame.Device data is used to transmit data between port；Extension link data is used to extend link service command, including Port and switching fabric registration and unregistration stop to exchange, request transmission state etc..As shown in Figure 4 and Figure 5, port is at FC-1 layers After completing link activation, data are uploaded to FC-2 layers.FC-2 first parses frame, frame include SOF delimiter, frame head, Payload, cyclic redundancy check field CRC, EOF delimiter.The frame head of extension link service data frame includes that a large amount of needs are negotiated Port information, needs communication network to distribute port address, and payload is filled by fixed communication parameter；The frame head of data frame uses fixation Parameter, payload are filled by user.Registration switching fabric registration is completed after parsing to frame, determines network operating parameters.With Fig. 4 For, port sends Fabric Login extension link service request (FLOGI), when port is in switching fabric but other side port When not supporting N-port to distribute, other side can reply the reject frame of a F_RJT.Port will do it second of framework after receiving F_RJT Until other side replys ACC.N-port distribution is supported when port is in switching fabric and other side port, can reply an ACC confirmation Frame, and distribute ID.When port is in point-to-point topology, other side port can reply an ACC acknowledgement frame and be shown to be a N-terminal Mouthful.Port can and each want that the N-port communicated is registered after completing exchange registration, and if it is N-port, two-port can compare end Mouth title, a WWN big side will initiate PLOGI frame, and another party waits and replys ACC.If other side is the port F, N-port passes through Fabric Login knows that other those N-ports are available, sends PLOGI to destination port, and after receiving ACC, port registration terminates.Knot Process registers can also be carried out after the completion of structure registration and port registration, after can directly mapping an information unit to N-port Scsi target.Process registers (PRLI) order allows the subsequent one or more in the port A to map mapping association corresponding with the port B Composition mapping pair；Process nullifies (PRLO) order and is used to release this operative relationship.Need to pass through cancellation after the completion of port communication Release topological relation.The present invention is nullified using implicit, is nullified by continuously transmitting three or more NOS or OLS signals.To guarantee Port will not receive the information more than its ability to accept, and communication system will use flow control.The present invention using buffer area to delay Rush the flow control in area.Design has frame transmitting counter BB_credit_cnt in transmitter.It, which is counted, when initial resets, and works as hair After the side of sending sends a frame data, counter can add 1, can subtract 1 after receiving the R_RDY of other side.Communicating pair is discussed slow in registration Area reliability BB_credit is rushed, stops sending when counter reaches BB_credit.And first write-in is slow as long as having frame by other side It deposits, sends R_RDY after reading a burst of and reply, can receive next frame.
In conclusion a kind of efficient data exchange method based on FC that the present invention designs, including：Utilize FPGA design FC-0 layers of high-speed serial data to low-speed parallel data conversion module, design FC-1 layers of encoding and decoding and port state machine control System designs FC-2 layers of Frame Protocol parsing module to complete the parsing, registration and unregistration, buffer area of Frame Protocol to the stream of buffer area Amount control, to guarantee the legitimacy of frame transmission, the efficient exchange of realization data that can be more flexible, economic.
The content that description in the present invention is not described in detail belongs to the prior art well known to professional and technical personnel in the field.
The above is only a preferred embodiment of the present invention, it is noted that for the ordinary skill people of the art For member, various improvements and modifications may be made without departing from the principle of the present invention, these improvements and modifications are also answered It is considered as protection scope of the present invention.

Claims (2)

1. a kind of efficient data based on FC exchanges method, which is characterized in that include the following steps：
Step 1：Design conversion module of FC-0 layers in FC agreement of the high-speed serial data to low-speed parallel data, the module energy Enough parallel datas that high-speed serial digital signal is converted into relative low speeds, while reference clock is completed by the state machine of design Debounce, locking and recovery, be implemented as follows：
1. designing module work under the rate of 8.5Gbps, the phaselocked loop of QPLL is selected, each channel of FC-0 serioparallel exchange module is made Share same reference clock；
2. utilizing the debounce state machine of FPGA design reference clock, and using the clock output after debounce as FC-0 serioparallel exchange mould The reference clock of block, debounce state machine control debounce chip by IIC agreement, according to 1. middle design in 8.5Gbps Operating rate, the reference clock after the debounce designed herein is 212.5MHZ, while designing K28.5 as control byte, clock Correction sequence is 10111100 ＂ of ＂；
Step 2：Design FC-1 layers in FC agreement of 8b/10b encoding and decoding, the alignment of transmission word boundary and transmission word legitimacy inspection It surveys, primitive detection, the control of receiver state machine, FC port state machine and transmitter status machine, to guarantee FC port status It jumps, is implemented as follows：
1. the encoding and decoding for being arranged FC-1 layers be the code encoding/decoding mode of 8B/10B, 40bit inside bit wide 32bit external bit wide, As comma, and in a program, whether inspection comma is in the low 8bit of 40bit to reference clock, the K28.5 of 212.5MHZ；
2. using VHDL language design multiple subroutine modules simultaneously and concurrently complete the detection of transmission word legitimacies, primitive detection, Receiver state machine, FC port state machine and transmitter status machine, state machine are broadly divided into receiver state machine, transmitter status Machine, port state machine, data after FC-0 serioparallel exchange module completion serioparallel exchange and encoding and decoding with mono- word of 32bit by being transmitted To receiver state machine, receiver operation clock is 212.5MHZ, and FC port state machine completes the activation of link and passes through a system The conversion of column handshake mechanism completion status, after device power or entrance reset state, the port FC can pass through a series of handshake mechanisms Activated state is entered by non-initialization state, to start normal data communication, when sending out data, data are with 32bit mono- Word is sent to transmitter status machine, and transmitter work clock is 233.33MHZ；
Step 3：FC-2 layers in FC agreement of Frame Protocol parsing module is designed, which can complete the parsing of Frame Protocol, registration It is implemented as follows with cancellation, the flow control of buffer area to buffer area with guaranteeing the legitimacy of frame transmission：
1. the port FC is after FC-1 layers of completion link activation, data are uploaded to FC-2 layers, and FC-2 layers first parse frame, Frame includes SOF delimiter, frame head, payload, cyclic redundancy check field CRC, EOF delimiter, process registers (PRLI) state machine The port of communicating pair can be passed through mapping association composition mapping pair；Process nullifies (PRLO) state machine and is used to release this reflect Relationship is penetrated, is nullified using implicit, is nullified by continuously transmitting three or more NOS or OLS signals；
2. FC communication port both sides decide through consultation a credit value in advance, synchronized for the communication to both sides, when sender sends After one frame data, count value adds 1, and count value subtracts 1 after receiving effective reply of other side, when count value is equal to credit value, sends Side's pause is sent, and is then sent state machine and is continued to monitor count value, and data are again started up when it is less than credit value and are sent.
2. a kind of efficient data based on FC as described in claim 1 exchanges method, it is characterised in that：The method is applicable in In Xilinx company Virtex-7FPGA chip, model XC7VX690T-2FFG1761C；Clock jitter removing chip is SiLABS public The SI5324 of department.
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