CN113490080A - Multi-port FC switching host and switching method - Google Patents
Multi-port FC switching host and switching method Download PDFInfo
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- CN113490080A CN113490080A CN202110719241.1A CN202110719241A CN113490080A CN 113490080 A CN113490080 A CN 113490080A CN 202110719241 A CN202110719241 A CN 202110719241A CN 113490080 A CN113490080 A CN 113490080A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q11/00—Selecting arrangements for multiplex systems
- H04Q11/0001—Selecting arrangements for multiplex systems using optical switching
- H04Q11/0005—Switch and router aspects
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
- H04B10/40—Transceivers
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q11/00—Selecting arrangements for multiplex systems
- H04Q11/0001—Selecting arrangements for multiplex systems using optical switching
- H04Q11/0005—Switch and router aspects
- H04Q2011/0037—Operation
- H04Q2011/005—Arbitration and scheduling
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Abstract
An optical signal is converted into a digital signal through an optical module, then the digital signal passes through a GTX channel and is decoded by 8b/10b, serial data is converted into 16-bit parallel data, and the data is transmitted to an input end. The signal is processed by word synchronization, frame analysis and the like at the input end. A part of signals (such as link activation signals) are processed and not forwarded; a part of signals (such as switch login) are forwarded to the PCIE bus and finally transmitted to upper-layer software for processing; the data to be forwarded (e.g. data sent by port 1 to port 16) is transmitted to the switching module. The switching module carries out scheduling arbitration on the data to be forwarded and forwards the data to the corresponding port. And the data is forwarded to the output end of a certain interface, the parallel data passes through a GTX channel, the parallel data is converted into serial data, and finally the serial data is converted into optical signals through an optical transceiver and sent out.
Description
Technical Field
The invention relates to a multi-port FC switching host system and a switching method, belonging to the technical field of communication.
Background
FC (fiber channel) protocol, which is the main protocol in the next generation of high-speed communication transmission field, is widely used in the communication technology field due to its advantages of low latency and high reliability. FC switches, i.e., fibre channel switches, are being researched and developed by various companies and research institutes because of their core status and importance.
With the continuous change of technology, FC switches have been developed from the first 1Gbps, 2Gbps to 4Gbps, 8Gbps and even higher, but foreign manufacturers have almost monopolized the FC switch market, and in the process of developing FC switches in China, foreign ban on core chips is sometimes accompanied. Therefore, the research on the FC switch with the independent intellectual property right and the switching method has important significance.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: the optical signal is converted into digital signal by optical module, then through GTX channel, after 8b/10b decoding, serial data is converted into 16 bit parallel data, and transferred into input end. The signal is processed by word synchronization, frame analysis and the like at the input end. A part of signals (such as link activation signals) are processed and not forwarded; a part of signals (such as switch login) are forwarded to the PCIE bus and finally transmitted to upper-layer software for processing; the data to be forwarded (e.g. data sent by port 1 to port 16) is transmitted to the switching module. The switching module carries out scheduling arbitration on the data to be forwarded and forwards the data to the corresponding port. And the data is forwarded to the output end of a certain interface, the parallel data passes through a GTX channel, the parallel data is converted into serial data, and finally the serial data is converted into optical signals through an optical transceiver and sent out.
The purpose of the invention is realized by the following technical scheme:
the embodiment of the invention provides a multi-port FC switch host, which comprises a plurality of ports, an optical interface and an optical transceiver corresponding to each port, and a switch module; each port comprises a GTX channel, an input port, an output port, a PCIE bus and upper-layer software;
the optical interface is used for receiving optical fiber signals transmitted by external optical fiber equipment, converting the optical fiber signals into electric signals and transmitting the electric signals to the optical transceiver;
the optical transceiver is used for sending the received electric signals to the GTX channel;
the GTX channel is used for decoding the received electric signals, converting serial data into parallel data and then sending the parallel data to the input port;
the input port sends data which does not need to be forwarded to the output interface, and sends the data which needs to be forwarded to the PCIE bus;
the PCIE bus sends the received data to upper software for processing, and receives the data processed by the upper software and sends the data to an output interface of a corresponding port;
the output port sends the received data out through the GTX channel, the optical receiver and the optical interface in sequence.
In an embodiment of the present invention, the upper layer software is configured to complete protocol processing of the E port and the F port, and the protocol response frame is sent to the output interface of the corresponding port through the PCIE bus.
In an embodiment of the present invention, a flow control counter is set in an output port, and is used for controlling flow from BUFFER to BUFFER, so as to prevent frame loss.
In one embodiment of the present invention, the GTX channel performs 8b/10b decoding.
In an embodiment of the present invention, the switching module adopts a CROSSBAR non-blocking structure.
The embodiment of the invention provides a switching method of a multi-port FC switching host, which adopts the multi-port FC switching host;
the switching method of any port A comprises the following steps:
after the optical signal passes through an optical interface and an optical transceiver in sequence, decoding is carried out by utilizing a GTX channel, serial data is converted into parallel data, and the parallel data is sent to an input port;
the input port performs word synchronization and frame analysis on the parallel data;
the input port sends the data after the frame analysis which needs to be forwarded to upper software through a PCIE bus, the data after the frame analysis which does not need to be forwarded is sent to the output port, and the output port sends the received data out through a GTX channel, an optical receiver and an optical interface in sequence; the upper layer software sends the data after the frame analysis to be transmitted to the exchange module;
the switching module dispatches and arbitrates the data after the frame analysis which needs to be forwarded, and then sends the data to the output port of the corresponding port B; and the output port of the port B sends the received data to a GTX channel of the port B, converts the parallel data into serial data, and finally sends the serial data out through the optical receiver and the optical interface of the port B.
In one embodiment of the present invention, the GTX channel is used to 8b/10b decode the digital signal and convert the serial data into 16-bit parallel data.
In an embodiment of the present invention, the data to be forwarded includes data sent by any port to other ports and switch login data.
In one embodiment of the invention, the exchange rate is 2.125Gb/s or 4.25 Gb/s.
In an embodiment of the invention, an input and output dual-scheduling method is adopted in the FC switching process, the head-to-head blocking phenomenon of input signals is reduced, the processing speed is increased, and the throughput is improved.
Compared with the prior art, the invention has the following beneficial effects:
(1) by adopting the scheme of the invention, the head-to-head blocking phenomenon of the input signal can be effectively reduced, and the processing speed and the throughput can be effectively improved.
(2) The invention is based on autonomous controllable nationwide production design and is not influenced by the forbidden use of foreign devices.
(3) And an input and output dual-scheduling scheme is adopted in the FC switching process, and output ports perform parallel scheduling and output, so that the scheduling efficiency can be effectively improved.
(4) The FC exchange process is mainly realized in the FPGA, can get rid of the constraint of a special realization chip, is solidified into an IP core with independent intellectual property rights, and is convenient to migrate and popularize.
Drawings
Fig. 1 is a block diagram of an overall scheme of FC switching on which the method of the embodiment of the present invention is based.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
Example 1:
a multi-port FC switch host comprises a plurality of ports, an optical interface and an optical transceiver corresponding to each port, and a switch module; each port comprises a GTX channel, an input port, an output port, a PCIE bus and upper-layer software;
the optical interface is used for receiving optical fiber signals transmitted by external optical fiber equipment, converting the optical fiber signals into electric signals and transmitting the electric signals to the optical transceiver;
the optical transceiver is used for sending the received electric signals to the GTX channel;
the GTX channel is used for decoding the received electric signals, converting serial data into parallel data and then sending the parallel data to the input port;
the input port sends data which does not need to be forwarded to the output interface, and sends the data which needs to be forwarded to the PCIE bus;
the PCIE bus sends the received data to upper software for processing, and receives the data processed by the upper software and sends the data to an output interface of a corresponding port;
the output port sends the received data out through the GTX channel, the optical receiver and the optical interface in sequence.
The upper layer software is used for completing the protocol processing of the E port and the F port, and the protocol response frame is sent to the output interface of the corresponding port through the PCIE bus. And a flow control counter is arranged in the output port and is used for controlling flow from the BUFFER to the BUFFER, so that frame loss is prevented. The GTX channel performs 8b/10b decoding. The switching module adopts a CROSSBAR non-blocking structure.
A switching method of a multi-port FC switching host adopts the multi-port FC switching host;
the switching method of any port A comprises the following steps:
after the optical signal passes through an optical interface and an optical transceiver in sequence, decoding is carried out by utilizing a GTX channel, serial data is converted into parallel data, and the parallel data is sent to an input port;
the input port performs word synchronization and frame analysis on the parallel data;
the input port sends the data after the frame analysis which needs to be forwarded to upper software through a PCIE bus, the data after the frame analysis which does not need to be forwarded is sent to the output port, and the output port sends the received data out through a GTX channel, an optical receiver and an optical interface in sequence; the upper layer software sends the data after the frame analysis to be transmitted to the exchange module;
the switching module dispatches and arbitrates the data after the frame analysis which needs to be forwarded, and then sends the data to the output port of the corresponding port B; and the output port of the port B sends the received data to a GTX channel of the port B, converts the parallel data into serial data, and finally sends the serial data out through the optical receiver and the optical interface of the port B.
Example 2:
based on the embodiment 1, the FC exchange host system adopts an FPGA + PowerPC architecture, the FPGA selects SMQ7K325T of the wiry company, and is responsible for the logic of FC exchange, and 16-way FC exchange is realized through a high-speed GTX interface, where the 16 th way is a management port, the mounted FLASH chip is SM25QU256MX of the wiry company, and the capacity is 256 Mb; the CSP2020 of the Middling 58 is selected by the PowerPC to be responsible for managing the exchange process, upper-layer protocol software is deployed in the PowerPC, the PowerPC exchanges data with the FPGA through a high-speed PCIE bus, a mounted DDR chip is SM41J256M8M of the national Wire company, and the capacity is 2 Gb; the network PHY chip JSC88E1111 of the middle power system 32 can perform configuration management and setting for FC switching by outputting a 1-channel PowerPC gigabit network.
The FPGA chip SMQ7K325T of the national Wien company contains 840 digital signal processors, 445 BRAMs with 36Kb, 326080 logic units, 10 CMTs, 1 PCIE2.1, 16 GTX and other programmable resources, can realize high-performance digital signal processing, large-capacity logic operation and other applications, and has high-bandwidth data throughput capability.
The PowerPC chip CSP2020 of the mid-Power 58 is equipped with a dual-core Power Architecture e500, a main frequency of 1.2GHz, supports double-precision floating-point arithmetic, and supports various high-speed interfaces including a 4-way high-speed SerDes interface, a 3-way PCIE interface, a 2-way RapidIO interface, and the like.
The DDR memory chip SM41J256M8M of the national Wien company has the storage capacity of 2Gbit and the storage structure of 256Mb X8, and is a synchronous dynamic random access memory.
The FLASH chip SM25QU256MX of the national Wien company is a nonvolatile serial Nor FLASH memory, supports standard SPI, Dual SPI, Quad SPI and other operation modes, and has the maximum fast reading frequency of 133 MHz.
The JSC88E1111 of the medium electric power system 32 is a gigabit Ethernet transceiver, can output 1 path 10/100/1000BASE-T, supports interfaces such as GMII, TBI, RGMII, RTBI and SGMII, and conforms to the 802.3 protocol.
As shown in fig. 1, the optical signal is converted into a digital signal through an optical module, and then through a GTX channel, serial data is converted into 16-bit parallel data through 8b/10b decoding, and the data is transmitted to the input terminal. The signal is processed by word synchronization, frame analysis and the like at the input end. A part of signals (such as link activation signals) are processed and not forwarded; a part of signals (such as switch login) are forwarded to the PCIE bus and finally transmitted to upper-layer software for processing; the data to be forwarded (e.g. data sent by port 1 to port 16) is transmitted to the switching module. The switching module carries out scheduling arbitration on the data to be forwarded and forwards the data to the corresponding port. And the data is forwarded to the output end of a certain interface, the parallel data passes through a GTX channel, the parallel data is converted into serial data, and finally the serial data is converted into optical signals through an optical transceiver and sent out.
The specific FC exchange steps are as follows:
step 1, converting an optical signal into a digital signal through an optical module, then entering an FPGA, then passing through a GTX channel, decoding through 8b/10b, converting serial data into 16-bit parallel data, and transmitting the data into an input end. And performing word synchronization, and completing the analysis function of the FC frame by a link activation and frame analysis module.
Step 2, processing a part of signals (such as link activation signals) without forwarding;
step 3, a part of signals (such as switch login) are forwarded to the PCIE bus and finally transmitted to upper-layer software for processing;
and 4, transmitting the data to be forwarded (such as the data transmitted from the port 1 to the port 16) to the switching module.
And 5, the switching module carries out scheduling arbitration on the data to be forwarded, carries out forwarding scheduling according to the routing table configured by the software, and forwards the data to the corresponding port.
And 6, the data is transmitted to the output end of a certain interface, the parallel data is converted into serial data through a GTX channel, and finally the serial data is converted into optical signals through an optical transceiver and sent out.
And 7, the PowerPC internal software completes protocol processing of the E port and the F port, a protocol response frame is sent to a sending module of the FPGA through a PCIE bus to be sent out, a flow control counter is set at the sending port, flow control from the BUFFER to the BUFFER is carried out, and frame loss is prevented.
The whole FC switching process can realize FC switching of 16 ports from port 1 to port 16, and the switching rate can be set to 2.125Gb/s and 4.25Gb/s through software.
An input and output dual scheduling scheme is employed in the FC switching process. By adopting the scheme, the head-to-head blocking phenomenon of input signals can be effectively reduced, and the parallel scheduling and output of the output ports can be realized, so that the processing speed can be effectively improved, and the throughput can be effectively improved.
Those skilled in the art will appreciate that those matters not described in detail in the present specification are well known in the art.
Although the present invention has been described with reference to the preferred embodiments, it is not intended to limit the present invention, and those skilled in the art can make variations and modifications of the present invention without departing from the spirit and scope of the present invention by using the methods and technical contents disclosed above.
Claims (10)
1. A multi-port FC switch host comprises a plurality of ports, an optical interface and an optical transceiver corresponding to each port, and a switch module; each port comprises a GTX channel, an input port, an output port, a PCIE bus and upper-layer software;
the optical interface is used for receiving optical fiber signals transmitted by external optical fiber equipment, converting the optical fiber signals into electric signals and transmitting the electric signals to the optical transceiver;
the optical transceiver is used for sending the received electric signals to the GTX channel;
the GTX channel is used for decoding the received electric signals, converting serial data into parallel data and then sending the parallel data to the input port;
the input port sends data which does not need to be forwarded to the output interface, and sends the data which needs to be forwarded to the PCIE bus;
the PCIE bus sends the received data to upper software for processing, and receives the data processed by the upper software and sends the data to an output interface of a corresponding port;
the output port sends the received data out through the GTX channel, the optical receiver and the optical interface in sequence.
2. The multi-port FC switching host of claim 1, wherein the upper layer software is configured to complete protocol processing for the E-port and the F-port, and the protocol response frame is sent to the output interface of the corresponding port via the PCIE bus.
3. The multi-port FC switch host of claim 1, wherein a flow control counter is provided in the output port for BUFFER-to-BUFFER flow control to prevent frame loss.
4. The multi-port FC switch host of claim 1, wherein the GTX channel performs 8b/10b decoding.
5. The multi-port FC switch host of claim 1, wherein the switch module employs a CROSSBAR non-blocking architecture.
6. A method of switching a multi-port FC switch host, characterized by using the multi-port FC switch host of claim 1;
the switching method of any port A comprises the following steps:
after the optical signal passes through an optical interface and an optical transceiver in sequence, decoding is carried out by utilizing a GTX channel, serial data is converted into parallel data, and the parallel data is sent to an input port;
the input port performs word synchronization and frame analysis on the parallel data;
the input port sends the data after the frame analysis which needs to be forwarded to upper software through a PCIE bus, the data after the frame analysis which does not need to be forwarded is sent to the output port, and the output port sends the received data out through a GTX channel, an optical receiver and an optical interface in sequence; the upper layer software sends the data after the frame analysis to be transmitted to the exchange module;
the switching module dispatches and arbitrates the data after the frame analysis which needs to be forwarded, and then sends the data to the output port of the corresponding port B; and the output port of the port B sends the received data to a GTX channel of the port B, converts the parallel data into serial data, and finally sends the serial data out through the optical receiver and the optical interface of the port B.
7. The switching method according to claim 6, wherein the GTX channel is used for 8b/10b decoding of the digital signal and converting the serial data into 16-bit parallel data.
8. The switching method according to claim 6, wherein the data to be forwarded includes data addressed to other ports by any port, and switch login data.
9. The switching method as claimed in claim 6, wherein the switching rate is 2.125Gb/s or 4.25 Gb/s.
10. The switching method according to claim 6, wherein the FC switching process adopts an input and output dual scheduling method, thereby reducing the head-to-head blocking phenomenon of input signals, and improving the processing speed and the throughput.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN114050838A (en) * | 2021-10-30 | 2022-02-15 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | 100Gbps bandwidth RapidIO signal source |
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