CN110006538A - A kind of no TEC un-cooled infrared focal plane array reading circuit - Google Patents
A kind of no TEC un-cooled infrared focal plane array reading circuit Download PDFInfo
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- CN110006538A CN110006538A CN201910213758.6A CN201910213758A CN110006538A CN 110006538 A CN110006538 A CN 110006538A CN 201910213758 A CN201910213758 A CN 201910213758A CN 110006538 A CN110006538 A CN 110006538A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01J—MEASUREMENT OF INTENSITY, VELOCITY, SPECTRAL CONTENT, POLARISATION, PHASE OR PULSE CHARACTERISTICS OF INFRARED, VISIBLE OR ULTRAVIOLET LIGHT; COLORIMETRY; RADIATION PYROMETRY
- G01J5/00—Radiation pyrometry, e.g. infrared or optical thermometry
- G01J5/10—Radiation pyrometry, e.g. infrared or optical thermometry using electric radiation detectors
- G01J5/20—Radiation pyrometry, e.g. infrared or optical thermometry using electric radiation detectors using resistors, thermistors or semiconductors sensitive to radiation, e.g. photoconductive devices
- G01J5/22—Electrical features thereof
- G01J5/24—Use of specially adapted circuits, e.g. bridge circuits
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01J—MEASUREMENT OF INTENSITY, VELOCITY, SPECTRAL CONTENT, POLARISATION, PHASE OR PULSE CHARACTERISTICS OF INFRARED, VISIBLE OR ULTRAVIOLET LIGHT; COLORIMETRY; RADIATION PYROMETRY
- G01J5/00—Radiation pyrometry, e.g. infrared or optical thermometry
- G01J5/10—Radiation pyrometry, e.g. infrared or optical thermometry using electric radiation detectors
- G01J5/20—Radiation pyrometry, e.g. infrared or optical thermometry using electric radiation detectors using resistors, thermistors or semiconductors sensitive to radiation, e.g. photoconductive devices
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Abstract
The present invention discloses a kind of no TEC un-cooled infrared focal plane array reading circuit, is related to un-cooled infrared focal plane array technical field.The reading circuit includes bias generating circuit, column grade analog front circuit and row grade circuit；Row grade circuit, including row class mirror-image pixel are selected switch control by row, can export third bias voltage；Bias generating circuit, with row grade circuit connection, input terminal connects the output end of row grade circuit；It is generated according to the constant pressure of input and third bias voltage and exports the first bias voltage and the second bias voltage；Column grade analog front circuit, including blind element；Column grade analog front circuit is connect with bias generating circuit, and input terminal connects the output end of bias generating circuit, obtains two-way electric current, and carry out generated two-way difference between currents across resistance amplification and as voltage output.Using technical solution of the present invention, makes circuit that there is the stabilization output point not influenced by underlayer temperature and self-heating effect, enhance the stability of circuit.
Description
Technical field
The present invention relates to un-cooled infrared focal plane array technical fields, and in particular to a kind of no TEC uncooled ir is burnt
Planar array reading circuit.
Background technique
Critical component one of of the reading circuit as un-cooled infrared focal plane array (IRFPA), major function is pair
The small-signal of infrared detector induction is pre-processed (such as integral, amplification, filtering, sampling/holding) and array signal
Parallel/serial row conversion.
It in the prior art, can be with such as Figure of description traditional reading out structure circuit of difference current up and down shown in FIG. 1
One step completes the elimination and signal amplification of underlayer temperature effect, and can carry out offset correction by adjusting Veb and Vfid bias；
Its disadvantage is mainly: 1, the noise of front end bias can be directly amplified, thus be required bias noise very high；2. due to self-heating
Effect, so that pixel blind element resistance value is unequal, output bias point can not be automatically determined；3. its circuit gain changes with underlayer temperature
It is larger, cause dynamic range under various substrate can the loss of energy and offset correction failure；
It can be seen that, due to the influence of process deviation, self-heating effect and underlayer temperature, making in traditional reading circuit
The data fluctuations that must be read out are larger, can also introduce some unnecessary noises, seriously affect the stabilization for reading quality and circuit
Property.
Summary of the invention
In order to solve the problems in the existing technology, the embodiment of the invention provides a kind of no TEC uncooled ir is burnt
Planar array reading circuit.
The embodiment of the present application provides a kind of no TEC un-cooled infrared focal plane array reading circuit, including bias generates
Circuit, column grade analog front circuit and row grade circuit；Wherein,
It include row class mirror-image pixel (Rsm) and row choosing switch (RSEL<i>) in row grade circuit；When row grade circuit is opened by row choosing
When closing (RSEL<i>) control and being strobed, third bias voltage (V is exported to bias generating circuitRsm)；
The output end of the input terminal connection row grade circuit of bias generating circuit；According to the constant pressure (V of inputb) and third biasing
Voltage (VRsm) generate and export the first bias voltage (Veb) and the second bias voltage (Vfid)；
Include in column grade analog front circuit blind element (Rd)；The input terminal connection bias of column grade analog front circuit generates electricity
The output end on road, according to the first bias voltage (Veb) and the second bias voltage (Vfid) two-way electric current is obtained, and to generated
Two-way difference between currents (Idiff) carry out across resistance amplification and as output voltage (Vagc) output.
Preferably, bias generating circuit includes at least the first bias generation sub-circuit and the second bias generation sub-circuit, point
The first bias voltage (Veb) and the second bias voltage (V are not exportedfid)。
In some embodiments, as constant pressure (Vb) input when, by the first bias generation sub-circuit PMOS tube grid electricity
Pressure is used as the first bias voltage (Veb), output to column grade analog front circuit；
Second bias generation sub-circuit is according to third bias voltage (VRsm) generate the second bias voltage (Vfid), utilize second
Source in bias generation sub-circuit follows structural circuit by the second bias voltage (Vfid) replicate and export to column grade AFE(analog front end) electricity
Road.
Preferably, the first bias generation sub-circuit and the second bias generation sub-circuit, row grade circuit, column grade AFE(analog front end) electricity
Road connection；Including at least the first mirror image circuit, the second mirror image circuit, the first operational amplifier (OPA1), the first mirror image blind element
(Rdm0), the second mirror image blind element (Rdm1) and power supply (Vsk)；
First mirror image circuit respectively with the second mirror image circuit, the first operational amplifier (OPA1), the first mirror image blind element
(Rdm0), the second mirror image blind element (Rdm1) connection.
Preferably, the first mirror image circuit includes the first PMOS tube (MP1) and the second PMOS tube (MP2), the first PMOS tube
(MP1) grid is connect with the grid of the second PMOS tube (MP2)；Second mirror image circuit includes the first NMOS tube (MN1) and second
The grid of NMOS tube (MN2), the first NMOS tube (MN1) is connect with the grid of the second NMOS tube (MN2)；
First mirror image blind element (Rdm0) first end, the second mirror image blind element (Rdm1) first end connect with power supply (Vsk)；
The source electrode of first PMOS tube (MP1), drain electrode respectively with the first mirror image blind element Rdm0Second end, the first NMOS tube (MN1) drain electrode
Connection；The source electrode of second PMOS tube (MP2), drain electrode respectively with the second mirror image blind element (Rdm1) second end, row grade circuit connection；
The drain electrode of second NMOS tube (MN2) is connect with the second bias generation sub-circuit；Source electrode, the 2nd NMOS of first NMOS tube (MN1)
Manage the source grounding of (MN2)；
The negative input end of first operational amplifier (OPA1), positive input terminal, output end respectively with the first PMOS tube (MP1)
Source electrode, constant pressure (Vb), the connection of the grid of the first PMOS tube (MP1).
Preferably, in the first bias generation sub-circuit, when constant pressure input, by the first PMOS in the first mirror image circuit
The grid of (MP1) and the grid voltage of the second PMOS tube (MP2) are managed as the first bias voltage (Veb), output to column grade is simulated
Front-end circuit.
Preferably, the first bias generation sub-circuit further includes decoupling capacitor (C1)；The first end of decoupling capacitor (C1), second
End is connect with power supply (Vsk), the first mirror image circuit respectively.
Preferably, the second bias generation sub-circuit and the first bias generation sub-circuit, row grade circuit and column grade AFE(analog front end)
Circuit connection；Structural circuit, the second source is followed to follow structural circuit, third NMOS tube (MN3) and second including at least the first source
Operational amplifier (OPA2)；
Grid, the source electrode of third NMOS tube (MN3) follow structural circuit, the first bias generation sub-circuit with the first source respectively
Connection；Second source follows structural circuit to follow structural circuit to connect with the first source；The negative input of second operational amplifier (OPA2)
End, positive input terminal, output end follow structural circuit to connect with the source electrode of third NMOS tube (MN3), row grade circuit, the first source respectively
It connects.
Preferably, it includes the first current source (Ib3) and third PMOS tube (MP3) that the first source, which follows structural circuit,；Second source
Following structural circuit includes the second current source (Ib4) and the 4th PMOS tube (MP4)；
The source electrode of third PMOS tube (MP3) is connected to the first current source (Ib3), the source electrode connection of the 4th PMOS tube (MP4)
To the second current source (Ib4)；The source electrode of third PMOS tube (MP3) is connect with the grid of third NMOS tube (MN3)；Second operation is put
The output end of big device (OPA2) is connect with the grid of third PMOS tube (MP3) and the grid and the 4th of third PMOS tube (MP3)
The grid of PMOS tube (MP4) connects.
Preferably, the second bias generation sub-circuit is according to the third bias voltage (V of row grade circuit outputRsm) obtain third
The source voltage of PMOS tube (MP3) follows structural circuit and the second source to follow structural circuit by third PMOS tube through the first source
(MP3) source voltage copies to the source electrode of the 4th PMOS tube (MP4) and as the second bias voltage (Vfid), output to column grade
Analog front circuit.
Preferably, column grade analog front circuit includes at least Pixel-level sub-circuit, power supply (Vsk), blind element (Rd), the 5th
PMOS tube (MP0), the 4th NMOS tube (MN0) and automatic gain calibration sub-circuit；The grid of 5th PMOS tube (MP0), the 4th
The grid of NMOS tube (MN0) is connect with bias generating circuit, and is received respectively as the input terminal of column grade analog front circuit
First bias voltage (Veb), the second bias voltage (Vfid)；
First end, the second end of blind element (Rd) are connect with the source electrode of power supply (Vsk), the 5th PMOS tube (MP0) respectively；4th
The drain electrode of NMOS tube (MN0), source electrode are connect with the drain electrode of the 5th PMOS tube (MP0), Pixel-level sub-circuit respectively；Wherein, pixel
Grade sub-circuit includes pixel (Rs).
Preferably, automatic gain calibration sub-circuit includes at least third operational amplifier (OPA0), across resistance (Rg) and capacitor
(Cc)；
The negative input end of third operational amplifier (OPA0) is connect with the drain electrode of the 5th PMOS tube (MP0)；Capacitor (Cc)
First end and first end across resistance (Rg) are connect with the negative input end of third operational amplifier (OPA0)；The second of capacitor (Cc)
End and the second end across resistance (Rg) are connect with the output end of third operational amplifier (OPA0)；Wherein, third operational amplifier
(OPA0) output voltage (V is exportedagc)。
In further embodiments, in the first bias generation sub-circuit, as constant pressure (Vb) input when, the first mirror image circuit
In include NMOS tube grid voltage as the first bias voltage (Veb), output to column grade analog front circuit；
Second bias generation sub-circuit is according to the third bias voltage (V of row grade circuit outputRsm) obtain third PMOS tube
(MP3) grid voltage and as the second bias voltage (Vfid), output to column grade analog front circuit.
Preferably, the first bias generation sub-circuit and the second bias generation sub-circuit, row grade circuit and column grade AFE(analog front end)
Circuit connection；Including at least the first mirror image circuit, the second mirror image circuit, the first operational amplifier (OPA1), the second operation amplifier
Device (OPA2), the first mirror image blind element (Rdm0) and the second mirror image blind element (Rdm1)；
First mirror image circuit and the second mirror image circuit, the second bias generation sub-circuit and row grade circuit connection；First mirror image
Blind element (Rdm0) first end, the second mirror image blind element (Rdm1) first end connect with the first mirror image circuit；First operation amplifier
Device (OPA1), second operational amplifier (OPA2) are connect with the first mirror image circuit, the second mirror image circuit respectively.
Preferably, the first mirror image circuit includes the first NMOS tube (MN1) and the second NMOS tube (MN2) and the first NMOS tube
(MN1) grid is connect with the grid of the second NMOS tube (MN2)；The negative input end of first operational amplifier (OPA1), positive input
End, output end respectively with the source electrode of the first NMOS tube (MN1), constant pressure (Vb), the connection of the grid of the first NMOS tube (MN1)；
Second mirror image circuit includes the grid of third NMOS tube (MN3) and the 4th NMOS tube (MN4) and third NMOS tube (MN3)
Pole is connect with the grid of the 4th NMOS tube (MN4)；Negative input end, positive input terminal, the output end of second operational amplifier (OPA2)
It is connect respectively with the grid of the source electrode of third NMOS tube (MN3), common-mode voltage Vcm, third NMOS tube (MN3)；Third NMOS tube
(MN3) drain electrode of drain electrode, the 4th NMOS tube (MN4) respectively with the second bias generation sub-circuit, row grade circuit connection.
Preferably, in the first bias generation sub-circuit, as constant pressure (Vb) input when, include first in the first mirror image circuit
The grid voltage of NMOS tube (MN1) and the second NMOS tube (MN2) is as the first bias voltage (Veb), before output to column grade simulation
Terminal circuit.
Preferably, the second bias generation sub-circuit and the first bias generation sub-circuit, row grade circuit and column grade AFE(analog front end)
Circuit connection；Including at least third mirror image circuit, third PMOS tube (MP3), the 4th PMOS tube (MP4), third operational amplifier
(OPA3), four-operational amplifier (OPA4) and common-mode current source (Vdet)；
Third mirror image circuit includes the first PMOS tube (MP1) and the second PMOS tube (MP2), and the first PMOS tube (MP1)
Grid and the connection of the grid of the second PMOS tube (MP2)；Source electrode, the source electrode of the second PMOS tube (MP2) of first PMOS tube (MP1) are equal
It is connect with common-mode current source (Vdet), the drain electrode of the first PMOS tube (MP1) is connect with the first bias generation sub-circuit；Third PMOS tube
(MP3) source electrode, drain electrode are connect with the source electrode of the drain electrode of the second PMOS tube (MP2), the 4th PMOS tube (MP4) respectively；Third fortune
Positive input terminal, negative input end and the output end for calculating amplifier (OPA3) are separately connected the source of capable grade circuit, third PMOS tube (MP3)
The grid of pole and third PMOS tube (MP3)；Positive input terminal, negative input end and the output end difference of four-operational amplifier (OPA4)
Connect common-mode voltage Vcm, the source electrode of the 4th PMOS tube (MP4) and the grid of the 4th PMOS tube (MP4).
Preferably, the second bias generation sub-circuit is according to the third bias voltage (V of row grade circuit outputRsm) obtain third
The grid voltage of PMOS tube (MP3) and as the second bias voltage (Vfid), output to column grade analog front circuit.
Preferably, column grade analog front circuit includes Pixel-level sub-circuit, common-mode current source (Vdet), blind element (Rd), the 5th
PMOS tube (MP0), the 4th NMOS tube (MN0) and automatic gain calibration sub-circuit；
The source electrode of 5th PMOS tube (MP0), drain electrode connect with the drain electrode of Pixel-level sub-circuit, the 4th NMOS tube (MN0) respectively
It connects；The first end of blind element (Rd) is connect with the source electrode of the 5th NMOS tube (MN0), the second end ground connection of blind element (Rd)；Automatic gain
Calibration sub-circuit is connect with the drain electrode of the 5th PMOS tube (MP0)；
The grid of 5th PMOS tube (MP0), the grid of the 5th NMOS tube (MN0) are connect with bias generating circuit, and point
The first bias voltage (Veb), the second bias voltage (V are not received as the input terminal of column grade analog front circuitfid)。
Preferably, column grade analog front circuit generates the according to the first bias voltage (Veb) and blind element (Rd) that receive
One electric current；Column grade analog front circuit is according to the second bias voltage (V receivedfid) and column grade analog front circuit include
Pixel (Rs) generates the second electric current；Two-way difference between currents (I is obtained according to the first electric current and the second electric currentdiff)。
The invention has the benefit that the invention discloses a kind of no TEC un-cooled infrared focal plane array reading circuit,
The first bias voltage (Veb) and the second bias voltage (V generatedfid) circuit can be made to have not by underlayer temperature and self-heating
The stabilization output point of effects, the noise of introducing is less, ensure that broader operating temperature range, while enhancing circuit
Stability.
Detailed description of the invention
Illustrate the embodiment of the present invention or technical solution in the prior art in order to clearer, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
Some embodiments of invention for those of ordinary skill in the art without creative efforts, can be with
It obtains other drawings based on these drawings.
Fig. 1 is traditional lower difference current reading out structure circuit；
Fig. 2 is a kind of box on no TEC un-cooled infrared focal plane array reading point road disclosed in the embodiment of the present invention one
Figure；
Fig. 3 is a kind of circuit on no TEC un-cooled infrared focal plane array reading point road disclosed in the embodiment of the present invention two
Schematic diagram；
Fig. 4 is a kind of the second traditional bias-voltage generating circuit schematic diagram disclosed in the embodiment of the present invention two；
Fig. 5 is a kind of the second traditional bias-voltage generating circuit schematic diagram disclosed in the embodiment of the present invention two；
Fig. 6 is a kind of circuit on no TEC un-cooled infrared focal plane array reading point road disclosed in the embodiment of the present invention three
Schematic diagram.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall within the protection scope of the present invention.
Embodiment one
Circuit block diagram as shown in Figure 2 discloses a kind of no TEC un-cooled infrared focal plane array reading circuit, packet
Include bias generating circuit 2, column grade analog front circuit 3 and row grade circuit 1；The bias generating circuit 2 respectively with the column grade
Analog front circuit 3 and the row grade circuit 1 connection；
The row grade circuit 1, including row class mirror-image pixel and row choosing switch；The row grade circuit 1 is selected switch control by row,
Third bias voltage can be exported；
The input terminal of the bias generating circuit 2 connects the output end of the row grade circuit 1, has constant pressure input for working as
When, it is generated together with third bias voltage and exports the first bias voltage and the second bias voltage；
The input terminal of the column grade analog front circuit 3 connects the output end of the bias generating circuit 2, obtains two-way phase
Same electric current, and generated two-way difference between currents are carried out across resistance amplification and as voltage output.
Specifically, the bias generating circuit 2 includes at least the first bias generation sub-circuit and the second bias generates son electricity
Road exports the first bias voltage Veb and the second bias voltage V respectivelyfid。
More specifically, the first bias generation sub-circuit and the second bias generation sub-circuit, the row grade circuit 1
And the column grade analog front circuit 3 connects；Including at least the first PMOS tube MP1, the second PMOS tube MP2, the first NMOS tube
MN1, the second NMOS tube MN2, the first operational amplifier OPA1, the first mirror image blind element Rdm0, the second mirror image blind element Rdm1And power supply
Vsk；
The first mirror image blind element Rdm0First end, the second mirror image blind element Rdm1First end with the power supply
Vsk connection；The source electrode of the first PMOS tube MP1, drain electrode respectively with the first mirror image blind element Rdm0Second end, described
The drain electrode of one NMOS tube MN1 connects；The source electrode of the second PMOS tube MP2, drain electrode respectively with the second mirror image blind element Rdm1's
Second end, the row grade circuit 1 connection；The drain electrode of the second NMOS tube MN2 is connect with the second bias generation sub-circuit；
The source grounding of the source electrode of the first NMOS tube MN1, the second NMOS tube MN2；The grid of the first PMOS tube MP1
It is connect with the grid of the second PMOS tube MP2；The grid of the grid of the first NMOS tube MN1 and the second NMOS tube MN2
Pole connection；
The negative input end of the first operational amplifier OPA1, positive input terminal, output end respectively with first PMOS tube
The grid connection of the source electrode, constant pressure Vb, the first PMOS tube MP1 of MP1.
Further, in the first bias generation sub-circuit, when constant pressure input, by first PMOS tube
The grid voltage of the grid of MP1 and the second PMOS tube MP2 are as the first bias voltage Veb, output to the column grade
Analog front circuit 3.
Further, the first bias generation sub-circuit further includes decoupling capacitor C1；The first of the decoupling capacitor C1
End, second end are connect with the grid of the power supply Vsk, the second PMOS tube MP2 respectively.
More specifically, the second bias generation sub-circuit and the first bias generation sub-circuit, the row grade circuit 1
And the column grade analog front circuit 3 connects；Structure, the second source is followed to follow structure, third NMOS tube including at least the first source
MN3, second operational amplifier OPA2 and power supply Vsk；
The grid of the third NMOS tube MN3, source electrode, drain electrode follow structure, described first partially with first source respectively
Press generation sub-circuit, power supply Vsk connection；Second source follows structure to follow structure to connect with first source；Described second
The negative input end of operational amplifier OPA2, positive input terminal, output end source electrode, the row with the third NMOS tube MN3 respectively
Grade circuit 1, first source follow structure to connect.
Further, it includes the first current source Ib3 and third PMOS tube MP3 that first source, which follows structure,；Described second
It includes the second current source Ib4 and the 4th PMOS tube MP4 that source, which follows structure,；
The source electrode of the third PMOS tube MP3 is connected to the first current source Ib3, the source of the 4th PMOS tube MP4
Pole is connected to the second current source Ib4；The grid of the source electrode of the third PMOS tube MP3 and the third NMOS tube MN3
Connection；The output end of the second operational amplifier OPA2 is connect with the grid of the third PMOS tube MP3 and the third
The grid of PMOS tube MP3 is connect with the grid of the 4th PMOS tube MP4.
Further, the second bias generation sub-circuit is obtained according to the third bias voltage that the row grade circuit 1 exports
The source voltage for taking the third PMOS tube MP3 follows structure and second source to follow structure described through first source
The source voltage of third PMOS tube MP3 copies to the source electrode of the 4th PMOS tube MP4 and as second bias voltage
Vfid, output to the column grade analog front circuit 3.
Specifically, the column grade analog front circuit 3 includes Pixel-level sub-circuit, power supply Vsk, blind element Rd, the 5th PMOS
Pipe MP0, the 4th NMOS tube MN0 and automatic gain calibration sub-circuit；Grid, the 4th NMOS of the 5th PMOS tube MP0
The grid of pipe MN0 is connect with the bias generating circuit 2；The grid of the 5th PMOS tube MP0, the 4th NMOS tube
The grid of MN0 receives first bias voltage, described second partially respectively as the input terminal of the column grade analog front circuit 3
Set voltage.
First end, the second end of the blind element Rd connects with the source electrode of the power supply Vsk, the 5th PMOS tube MP0 respectively
It connects；The drain electrode of the 4th NMOS tube MN0, source electrode respectively with the drain electrode of the 5th PMOS tube MP0, the Pixel-level sub-circuit
Connection；Wherein, the Pixel-level sub-circuit includes pixel Rs.
Further, the automatic gain calibration sub-circuit includes at least third operational amplifier OPA0, across resistance Rg and electricity
Hold Cc；
The negative input end of the third operational amplifier OPA0 is connect with the drain electrode of the 5th PMOS tube MP0；The electricity
The first end and the first end across resistance Rg for holding Cc are connect with the negative input end of the third operational amplifier OPA0；It is described
The second end of capacitor Cc and the second end across resistance Rg are connect with the output end of the third operational amplifier OPA0；Its
In, the third operational amplifier OPA0 exports Vagc.
Specifically, the column grade analog front circuit 3 is generated according to first bias voltage and blind element Rd received
First electric current；The column grade analog front circuit 3 generates the second electricity according to second bias voltage and pixel Rs received
Stream；
The two-way difference between currents, that is, first electric current and second electric current current difference.
More specifically, the first bias generation sub-circuit and the second bias generation sub-circuit, the row grade circuit 1
And the column grade analog front circuit 3 connects；It may include the first mirror image circuit, the second mirror image circuit, the first operational amplifier
OPA1, second operational amplifier OPA2, the first mirror image blind element Rdm0And the second mirror image blind element Rdm1；
First mirror image circuit and second mirror image circuit, the second bias generation sub-circuit and row grade electricity
Road 1 connects；The first mirror image blind element Rdm0First end, the second mirror image blind element Rdm1First end with first mirror
As circuit connection；The first operational amplifier OPA1, the second operational amplifier OPA2 are electric with first mirror image respectively
Road, second mirror image circuit connection.
Further, first mirror image circuit includes the first NMOS tube MN1 and the second NMOS tube MN2 and described first
The grid of NMOS tube MN1 is connect with the grid of the second NMOS tube MN2；The negative input of the first operational amplifier OPA1
End, positive input terminal, output end grid with the source electrode of the first NMOS tube MN1, constant pressure Vb, the first NMOS tube MN1 respectively
Pole connection；
Second mirror image circuit includes third NMOS tube MN3 and the 4th NMOS tube MN4 and the third NMOS tube MN3
Grid is connect with the grid of the 4th NMOS tube MN4；The negative input end of the second operational amplifier OPA2, positive input terminal,
Grid of the output end with the source electrode of the third NMOS tube MN3, common-mode voltage Vcm, the third NMOS tube MN3；Described
The drain electrode of three NMOS tube MN3, the drain electrode of the 4th NMOS tube MN4 respectively with the second bias generation sub-circuit, the row
Grade circuit 1 connects.
Further, in the first bias generation sub-circuit, when constant pressure input, first mirror image circuit
In include NMOS tube grid voltage as the first bias voltage Veb, output to the column grade analog front circuit 3.
More specifically, the second bias generation sub-circuit and the first bias generation sub-circuit, the row grade circuit 1
And the column grade analog front circuit 3 connects；Including at least third mirror image circuit, third PMOS tube MP3, the 4th PMOS tube MP4,
Third operational amplifier OPA3, four-operational amplifier OPA4 and common-mode current source Vdet；
The third mirror image circuit includes the first PMOS tube MP1 and the second PMOS tube MP2, and the first PMOS tube MP1
Grid connected with the grid of the second PMOS tube MP2；The source of the source electrode of the first PMOS tube MP1, the second PMOS tube MP2
It is extremely connect with the common-mode current source Vdet, the drain electrode of the first PMOS tube MP1 and the first bias generation sub-circuit connect
It connects；The source electrode of the third PMOS tube MP3, drain electrode respectively with the drain electrode of the second PMOS tube MP2, the 4th PMOS tube MP4
Source electrode connection；Positive input terminal, negative input end and the output end of the third operational amplifier OPA3 is separately connected the row grade electricity
The grid on road 1, the source electrode of the third PMOS tube MP3 and the third PMOS tube MP3；The four-operational amplifier OPA4's
Positive input terminal, negative input end and output end are separately connected common-mode voltage Vcm, the source electrode of the 4th PMOS tube MP4 and described
The grid of four PMOS tube MP4.
Further, the second bias generation sub-circuit is obtained according to the third bias voltage that the row grade circuit 1 exports
Take the grid voltage of the third PMOS tube MP3 and as second bias voltage, output to the column grade AFE(analog front end) electricity
Road 3.
Specifically, the column grade analog front circuit 3 includes Pixel-level sub-circuit, common-mode current source Vdet, blind element Rd, the 5th
PMOS tube MP0, the 4th NMOS tube MN0 and automatic gain calibration sub-circuit；
The source electrode of the 5th PMOS tube MP0, drain electrode respectively with the Pixel-level sub-circuit, the 5th NMOS tube MN0
Drain electrode connection；The first end of the blind element Rd is connect with the source electrode of the 4th NMOS tube MN0, the second end of the blind element Rd
Ground connection；The automatic gain calibration sub-circuit is connect with the drain electrode of the 5th PMOS tube MP0；
The grid of the 5th PMOS tube MP0, the 5th NMOS tube MN0 grid with the bias generating circuit 2
Connection, and first bias voltage, second biasing are received respectively as the input terminal of the column grade analog front circuit 3
Voltage.
Embodiment two
In one embodiment of the invention, electrical block diagram as shown in Figure 3 is disclosed；Electricity is generated including bias
Road 1, column grade analog front circuit 2, row grade circuit 3 and Pixel-level circuit 4；Wherein, bias generating circuit 1 includes at least first partially
Press generation sub-circuit and the second bias generation sub-circuit；First bias generation sub-circuit and the second bias generation sub-circuit difference are defeated
First bias voltage and the second bias voltage out；
Wherein, the first bias generation sub-circuit may include the first PMOS tube MP1, the second PMOS tube MP2, the first NMOS tube
MN1, the second NMOS tube MN2, the first operational amplifier OPA1, second operational amplifier OPA2, the first mirror image blind element Rdm0, second
Mirror image blind element Rdm1, decoupling capacitor C1 and power supply Vsk；It should be noted that the first mirror image blind element Rdm0, the second mirror image blind element Rdm1
There is good calorifics to connect between circuitry substrate, it is believed that the first mirror image blind element Rdm0, the second mirror image blind element Rdm1Temperature
It is permanent equal with underlayer temperature, it can the variation of sensor circuit underlayer temperature.
Specifically, the output end of the first operational amplifier OPA1 respectively with the grid of the first PMOS tube MP1, the second PMOS tube
The grid of MP2 connects and the grid of the first PMOS tube MP1 is connect with the grid of the second PMOS tube MP2；The source of first PMOS tube MP1
Pole is connect with the negative input end of the first operational amplifier OPA1；The positive input terminal of first operational amplifier OPA1 is constant pressure Vb；Electricity
Source Vsk respectively with the first mirror image blind element Rdm0First end, the second mirror image blind element Rdm1First end connection, the first PMOS tube MP1
Source electrode and the first mirror image blind element Rdm0Second end connection, the source electrode of the second PMOS tube MP2 and the second mirror image blind element Rdm1?
The connection of two ends；The drain electrode of second PMOS tube MP2 is connected with row grade circuit 3；The drain electrode of second PMOS tube MP2 also with the second bias
Generation sub-circuit connection；
In the present embodiment, it is exported the grid of the first PMOS tube MP1 as the first bias voltage Veb.
In the present embodiment, the grid of the first NMOS tube MN1 is connect with the grid of the second NMOS tube MN2, constitutes current mirror
Structure；
In the present embodiment, the first end of decoupling capacitor C1 is connect with power supply Vsk, and second end is with the second PMOS tube MP2's
Grid connection.
In the present embodiment, the second bias generation sub-circuit may include the first source follow structure, the second source follow structure,
Third NMOS tube MN3, second operational amplifier OPA2 and capacitor C2；Wherein, it includes the first current source that the first source, which follows structure,
Ib3 and third PMOS tube MP3；It includes the second current source Ib4 and the 4th PMOS tube MP4 that second source, which follows structure,；
Specifically, the source electrode of third PMOS tube MP3 is connected to the source electrode connection of the first current source Ib3, the 4th PMOS tube MP4
To the second current source Ib4；The 2nd PMOS in the positive input terminal of second operational amplifier OPA2 and the first bias generation sub-circuit
The drain electrode of pipe connects, and negative input end is connected with the source electrode of third NMOS tube MN3, the grid of output end and third PMOS tube MP3
Connection；The grid of third NMOS tube MN3 is connect with the source electrode of third PMOS tube MP3；The first end and third PMOS tube of capacitor C2
The grid of MP3 connects, second end ground connection.
In the present embodiment, the source electrode of the 4th PMOS tube MP4 is drawn and is a little used as the second bias voltage VfidOutput.
In the present embodiment, column grade analog front circuit 2 may include power supply Vsk, blind element Rd, the 5th PMOS tube MP0,
Four NMOS tube MN0 and automatic gain calibration (Automatic Gain Calibration, AGC) circuit；Wherein, agc circuit packet
Third operational amplifier OPA0 is included, across resistance Rg, capacitor Cc.
Specifically, the first end of blind element Rd is connect with power supply Vsk, and second end is connect with the source electrode of the 5th PMOS tube MP0, the
The drain electrode of five PMOS tube MP0 is connect with the drain electrode of the 4th NMOS tube MN0.
More specifically, the drain electrode of the negative input end of the third operational amplifier OPA0 in agc circuit and third PMOS tube MP0
Connection；The first end of capacitor Cc and across resistance Rg first end connect with the negative input end of third operational amplifier OPA0, capacitor
The second end of Cc and across resistance Rg second end connect with the output end of third operational amplifier OPA0；Wherein, third operation is put
Big device OPA0 exports Vagc.
In the present embodiment, row grade circuit 3 includes row class mirror-image pixel Rsm and row choosing switch RSEL<i>of switch line-by-line；
Wherein, the both ends of mirror image pixel Rsm are connect with the first end of the second end of the first row choosing switch, the second row choosing switch respectively；The
The first end of a line choosing switch is connect with the drain electrode of the second PMOS tube MP2；The second end of second row choosing switch can be grounded；
It should be noted that Rsm makees shading treatment, make it by the anti-dazzling screen for being constantly equal to underlayer temperature from temperature
Fixed radiation.
In the present embodiment, Pixel-level circuit 4 includes pixel Rs and row choosing switch RSEL；Wherein, the both ends of pixel Rs point
It is not connect with the first end of the second end of the third line choosing switch, fourth line choosing switch；The first end and the 4th of the third line choosing switch
The source electrode of NMOS tube MN0 connects；The second end of fourth line choosing switch can be grounded.
It is briefly described as follows the working principle of circuit in the present embodiment.
In the case where not considering mismatch caused by fabrication error, the source voltage terminal of the first PMOS tube MP1 is by the first operation
The negative input end of amplifier OPA1 determines, it is assumed that the gain of OPA1 is sufficiently high, the voltage of negative input end be clamped to it is just defeated
Enter to hold it is approximately equal, i.e.,
V-=V+=Vb……(1)
Then the voltage at the both ends resistance Rdm0 is VRdm0=Vsk-Vb……(2)
The electric current for then flowing through Rdm0 is
The grid end voltage of first PMOS tube MP1 and the second PMOS tube MP2 i.e. the first bias voltage Veb:
Veb=VGP1,2=Vb+|VGSP1|……(4)
The value of Veb has been obtained by (4) formula, wherein | VGSP1| it is the absolute value of the first PMOS tube MP1 gate source voltage.
In the present embodiment, the source voltage terminal of the second PMOS tube MP2 is that the first bias voltage Veb subtracts the second PMOS tube
The gate source voltage of MP2 is poor, i.e.,
VSP2=Veb-|VGSP2|=Vb+|VGSP1|-|VGSP2|……(5)
Generally, the current expression of the PMOS transistor in saturation region is
Wherein, μP、CoxThe respectively gate medium capacitor of PMOS tube carrier mobility and unit area, is determined by processing technology
It is fixed.|VTH| it is the threshold voltage of transistor, is determined by processing technology and the source of transistor-body end current potential.For transistor
Channel width-over-length ratio is determined by design.
Specifically, it is according to the electric current that (6) formula obtains flowing through MP1
Similarly for flowing through the electric current of MP2 and Rdm1, there is following relationship:
Wherein, VSP2For the current potential of MP2 source；
Due to VSP2=Veb-|VGSP2|=Vb+|VGSP1|-|VGSP2|……(9)
Above three formulas are compared it can be found that for MP1 and MP2, μPCox、|VTH|、VGIt is equal, by design so thatWithMatching, while making Rdm0And Rdm1Matching, then flow through MP1, MP2, Rdm0、Rdm1Electric current it is approximately equal, reach
To matched effect.
By above-mentioned method, the approximately equal electric current of size obtained on MP1 and MP2 branch road is
Similarly, the electric current of the branch road where Rd and MP0 is also approximately equal with the electric current of MP1, MP2 branch road, is
The derivation of above-mentioned (5)-(10) formula, gives the approximately equal current expression on MP0, MP1, MP2, i.e.,
(10) formula.
Since electric current of the mirror image pixel Rsm and MP2 on same branch, Rsm is also approximately atOn Rsm
Voltage is approximately
Then the voltage of second operational amplifier OPA2 positive input terminal is VRsm, in the enough situations of OPA2 gain, bear defeated
Enter the voltage at end since the clamping effect of amplifier is also approximately at VRsm；
The grid end voltage of NMOS transistor MN3 is as a result,
The grid end voltage of PMOS transistor MP3 is
The grid end voltage of 4th PMOS tube MP4 and the grid end voltage of MP3 are identical, source voltage terminal i.e. the second bias voltage
Vfid is
In the present embodiment, the first bias voltage Veb is as the PMOS crystal for being used to bias blind element in column grade reading circuit
The grid voltage of pipe is biased blind element Rd, makes to generate blind element electric current Id on blind element Rd.In Rdm0, Rdm1, MP0, MP1, MP2 ruler
In very little matched situation, the value of the electric current Id generated by the above method is all approximately
It should be noted that Rdm0 is mirror image blind element, there is good calorifics to connect between circuitry substrate, it is believed that
The temperature perseverance of Rdm0 is equal with underlayer temperature, therefore the Id value generated in this way follows underlayer temperature to change, i.e.,
It can be with the variation of sensor circuit underlayer temperature.
Above-mentioned (14) formula gives the expression formula of the second bias voltage Vfid, and the second bias voltage Vfid is simulated as column grade
Front-end circuit 2 is used to bias the grid voltage of the 4th NMOS tube MN0 of pixel, is biased to pixel Rs, makes to generate picture on pixel Rs
The expression formula of elementary current Is, Is are as follows
(14) formula is substituted into (15) formula, is obtained
Wherein, | VGSP3|、|VGSP4| be MP3 and MP4 gate source voltage absolute value of the difference, MP3 and MP4 respectively with the first electric current
Source Ib3 and the second current source Ib4 constitute source and follow structure, by match MP3 and MP4 size and the first current source Ib3 with
The size of current of second current source Ib4, can make | VGSP3| with | VGSP4| equal, then (16) formula becomes
In above-mentioned (17) formula, Rsm is as thermal insulation between row class mirror-image pixel and substrate and Rsm makees shading treatment,
The fixed radiation for coming from temperature and being constantly equal to the anti-dazzling screen of underlayer temperature being subject to；Rs is exhausted as heat between pixel, with substrate
Edge receives external radiation.Since thermal insulation, Rsm and Rs have self-heating effect all between substrate by Rsm and Rs.?
When being strobed, due to Joule heat change in resistance occurs for Rsm and Rs, but the variation of the two is synchronous, therefore this variation
It is cancelled in Is.
In the present embodiment, in column grade reading circuit, the electric current Idiff read is pixel electric current Is and blind element electric current
The difference of Id.When pixel Rs receives fixed radiation (fixed signal input), reading circuit preferably exports should be fixed for one
Value, i.e., either underlayer temperature variation or self-heating effect, the equilibrium state of circuit shall not be influenced.
In traditional structure, Vfid, Veb cannot generally follow self-heating effect, underlayer temperature variation in real time；If
Underlayer temperature changes at this time, then the value of blind element Rd follows underlayer temperature to change, and blind element electric current Id also follows underlayer temperature to change, but
Be that Vfid cannot incude underlayer temperature, Is caused underlayer temperature can not to be followed to change, though at this time circuit should be stable at it is a certain
The state of fixed output, the actually value of Idiff are not capable of fixing；In addition, it should be noted that, since blind element Rd temperature is permanent
Equal to underlayer temperature, self-heating effect can be ignored, and Rs has self-heating effect, between the two as caused by self-heating
The non-equilibrium output for also leading to circuit deviates original stable point；I.e. in traditional architectures, even if external input is fixed value,
Its output valve can not be stablized, but drift about with self-heating effect and underlayer temperature variation, this centainly will affect reading
Mass.
In embodiment disclosed by the invention, when the radiation that Rs and Rsm are equally fixed, Rsm and Rs are with identical
Resistance value, identical temperature coefficient equally has self-heating effect, therefore Rs and Rsm cancel out each other, then above-mentioned (17) formula can be with
It indicates are as follows:
It should be noted that (18) formula be Rs by fixed external radiation in the case where pixel electric current, use IS0It indicates.
Wherein, V in (18) formulaGSN3Be MN3 gate source voltage it is poor, by its size, technological parameter and the electric current for flowing through it
It determining, the electric current on MN3 is that the current-mirror structure duplication constituted from MN1, MN2 is got, it is approximately equal with the electric current on MN1, i.e.,VGSN0Be MN0 gate source voltage it is poor, by its size, technological parameter and flow through its electric current and determine, the electric current on MN0
As IS0.It is available by the current expression on MN0 and MN3, when the matching of the size of MN0 and MN3, VGSN3With VGSN0It is approximate
Equal, the electric current for flowing through two metal-oxide-semiconductors is approximately equal, isThen (18) formula becomes
It should be noted that IS0Pixel current value when being pixel Rs by fixed external radiation；(19) formula shows IS0
It is not influenced by self-heating effect, and the first mirror image blind element R can be passed throughdm0To follow the variation of underlayer temperature.According to above-mentioned
Analysis, blind element electric current Id areThe differential electrical flow valuve Idiff read at this time are as follows:
Idiff=Id-Is0=0 ... (20)
Available, when Rs and Rsm is by identical fixed radiation, the output of reading circuit can stablize 0, and not
It is influenced by underlayer temperature and self-heating effect.
It is above-mentioned in the present solution, when Rs is by fixed external radiation, the first bias voltage Veb of generation and the second bias voltage
VfidReading circuit can be made to export the stable output point not influenced by underlayer temperature and self-heating effect；Illustrate below in picture
The working principle of circuit when first Rs is by the external radiation changed.
When pixel Rs is by the external radiation changed, the electric current for flowing through blind element Rd is stillAnd flow through pixel Rs
Electric current generation can change, between the two generate difference current Idiff.
When Rs is by the external radiation changed, temperature change occurs and resistance value is caused to change, has become RS+ΔRS, below
Analyze IsVariation
Branch where MP0 meets following formula
VGSN0=Vfid-IsRS……(22)
(22) formula is substituted into (21) formula, is had
(23) formula both ends differentiate to Rs, remaining parameter is unrelated with Rs in addition to Is, Rs, obtains
It is obtained by (24) formula
Wherein,For the transconductance value of metal-oxide-semiconductor.
(25) in formula, by rationally designing, g can be mademRs> > 1,1+gmRs≈gmRs, then (25) formula becomes
It is available in conjunction with (26) formula and (19) formula, if the current value of Rs is I when circuit 0 exportsS0, then when Rs changes delta
RsWhen, the current value on Rs is
Is=IS0+ΔIs……(27)
Difference read current I at this timediffFor
In above formula, Vsk、VbIt is the amount unrelated with underlayer temperature, self-heating effect；It is the value of pixel Rs change in resistance
The ratio between with initial value, self-heating effect is cancelled.And the first mirror image blind element Rdm0It is amount related with underlayer temperature, therefore Idiff
Follow underlayer temperature change and it is unrelated with self-heating effect.
In the present embodiment, in IdiffRear class, formed by third operational amplifier OPA0, across resistance Rg and capacitor Cc
Agc circuit, wherein across resistance Rg=N*Rdm0, N is amplification factor, RgWith substrate there is good calorifics to connect, substrate can be incuded
Temperature；Then IdiffAfter agc circuit, changes into voltage value and export, be
Vagc=VCM-Idiff*Rg……(30)
Wherein Rg、Rdm0Underlayer temperature is followed to change simultaneously, the result after cancelling out each other only remains amplification factor N, then
(32) V obtained in formulaagcThe variation of pixel resistance value can be read, and be with underlayer temperature and self-heating effect all
Unrelated amount.
Traditional the second bias-voltage generating circuit as shown in figure 4, the output by operational amplifier directly generates Vfid,
And directly drive it is array-supported, wherein single-row load is given by
Wherein, s=j ω, CgsIt is metal-oxide-semiconductor gate-source parasitic capacitance, gmIt is metal-oxide-semiconductor mutual conductance.The load of array is so that feedback loop
The stability on road is difficult to ensure.
A kind of traditional solution increases the increasing of level-one unit as shown in figure 5, generating in Vfid between loop and the load of column grade
Beneficial amplifier, isolation feedback control loop and column grade load.The shortcomings that this way is that operational amplifier can introduce biggish noise and fortune
The metal-oxide-semiconductor grid end of the output and column grade reading circuit of calculating amplifier is connected directly, and noise is directly coupled to the I of readingdiffIn
It goes, influences to read effect.It is visibly different with traditional solution to be, the source voltage of third PMOS tube MP3 in this programme
The the second bias voltage Vfid as generated, but column grade analog front circuit directly is not directly driven using the voltage of this point
2, but taken out from feedback control loop a bit, follow structure that the voltage is copied to the source electrode of the 4th PMOS tube MP4 using source,
So that the point is not in feedback control loop, the noise of introducing is smaller, and drives column grade analog front circuit 2 with the point, to loop
Stability does not influence；
It should be noted that in the present embodiment, row class mirror-image pixel Rsm is the same with pixel Rs, switch RSEL is selected by row
Control；When being expert at choosing to the i-th row, row class mirror-image pixel Rsm and pixel Rs is strobed simultaneously, all with self-heating effect, and
The generation of second bias voltage Vfid is the voltage based on the both ends Rsm, and the voltage at the both ends Rsm be based on the electric current for flowing through Rsm,
And the electric current is generated by Rdm0, can incude underlayer temperature, it is final the result is that underlayer temperature and self-heating can be incuded by generating
Second bias voltage Vfid of effect.Resulting effect is exactly that circuit can be with autobalance, not by the shadow of underlayer temperature
It rings.
It should also be noted that, the first bias voltage Veb is that the feedback loop based on OPA1 and MP1 generates, the point
It is a low speed node, does not need big bandwidth, therefore limit bandwidth with bulky capacitor C1, it is ensured that the loop has good
Loop stability；By connection decoupling capacitor C1 to power supply Vsk, may be implemented to enhance the low-pass filtering of offset noise simultaneously
The stability of Veb generation loop；Meanwhile decoupling capacitor C1 can be filtered the noise of the first bias voltage Veb, reduce inclined
Press noise；
It should also be noted that, in column grade transimpedance gain amplifying circuit, the tunable capacitor of the both ends parallel connection of gain blind element Rg
Cc.Under various substrate, the phase margin of adjustable circuit, shortening Vagc is expert at steady with foundation required when row switching
It fixes time, to extend the time of integration of rear class, greatly improves signal-to-noise ratio.
Embodiment three
In another embodiment of the invention, electrical block diagram as shown in FIG. 6 is disclosed；Electricity is generated including bias
Road 1, column grade analog front circuit 2, row grade circuit 3 and Pixel-level circuit 4；Wherein, bias generating circuit 1 includes at least first partially
Generation sub-circuit and the second bias generation sub-circuit are pressed, the first bias generation sub-circuit and the second bias generation sub-circuit difference are defeated
First bias voltage and the second bias voltage out；
Wherein, the first bias generation sub-circuit may include the first NMOS tube MN1, the second NMOS tube MN2, third NMOS tube
MN3, the 4th NMOS tube MN4, the first operational amplifier OPA1, second operational amplifier OPA2, the first mirror image blind element Rdm0And second
Mirror image blind element Rdm1；It should be noted that the first mirror image blind element Rdm0, the second mirror image blind element Rdm1Have between circuitry substrate good
Calorifics connection, it is believed that the first mirror image blind element Rdm0, the second mirror image blind element Rdm1Temperature perseverance it is equal with underlayer temperature
With the variation of sensor circuit underlayer temperature.
Specifically, the output end of the first operational amplifier OPA1 respectively with the first NMOS tube MN1, the second NMOS tube MN2
Grid connects and the grid of the first NMOS tube MN1 is connect with the grid of the second NMOS tube MN2；The source electrode of first NMOS tube MN1 with
The negative input end of first operational amplifier OPA1 connects；First mirror image blind element Rdm0First end, the second mirror image blind element Rdm1?
One end is connect with the source electrode of the source electrode of the first NMOS tube MN1, the second NMOS tube MN2 respectively, the first mirror image blind element Rdm0Second
End, the second mirror image blind element Rdm1Second end be grounded；The output end of second operational amplifier OPA2 respectively with third NMOS tube
The grid of MN3, the grid connection of the 4th NMOS tube MN4 and the grid of third NMOS tube MN3 and the grid of the 4th NMOS tube MN4 connect
It connects；The negative input end of second operational amplifier OPA2 is connect with the source electrode of third NMOS tube MN3；The drain electrode of third NMOS tube MN3,
Source electrode is connect with the drain electrode of the first PMOS tube MP1, the drain electrode of the first NMOS tube MN1 respectively；The source electrode of 4th NMOS tube MN4 and
The drain electrode of two NMOS tube MN2 connects, and the drain electrode of the 4th NMOS tube MN4 is connect with Pixel-level circuit 4, also generates son with the second bias
Circuit connection；
In the present embodiment, it is exported the grid of the first NMOS tube MN1 as the first bias voltage Veb.
It should be noted that the grid of the first NMOS tube MN1 is connect with the grid of the second NMOS tube MN2, current mirror is constituted
Structure；The grid of third NMOS tube MN3 is connect with the grid of the 4th NMOS tube MN4, constitutes current-mirror structure；
In the present embodiment, the second bias generation sub-circuit may include the first PMOS tube MP1, the second PMOS tube MP2,
Three PMOS tube MP3, the 4th PMOS tube MP4, third operational amplifier OPA3, four-operational amplifier OPA4 and common-mode current source
Vdet；
Specifically, the drain electrode of the first PMOS tube MP1 is connect with the drain electrode of third NMOS tube MN3, the source of the first PMOS tube MP1
Pole is connect with common-mode current source Vdet；The source electrode and drain electrode of second PMOS tube MP2 is separately connected common-mode current source Vdet and the 3rd PMOS
The source electrode of pipe MP3；The drain electrode of third PMOS tube MP3 is connect with the source electrode of the 4th PMOS tube MP4；The drain electrode of 4th PMOS tube MP4
Ground connection；The drain electrode of the positive input terminal of third operational amplifier OPA3 and the 4th NMOS tube MN4 in the first bias generation sub-circuit
Connection, negative input end are connect with the source electrode of third PMOS tube MP3；The negative input end of four-operational amplifier OPA4 and the 4th PMOS
The source electrode of pipe MP4 connects；
In the present embodiment, using the grid of third PMOS tube MP3 as the second bias voltage VfidOutput.
It should be noted that the grid of the second PMOS tube MP2 of the second bias generation sub-circuit and the first bias generate son
The grid of first PMOS tube MP1 of circuit connects, and constitutes current-mirror structure；
In the present embodiment, column grade analog front circuit 2 includes blind element Rd, the 5th PMOS tube MP0, the 5th NMOS tube MN0
And automatic gain calibration (Automatic Gain Calibration, AGC) circuit；Wherein, agc circuit is including being the 5th operation
Amplifier OPA0, across resistance Rg, capacitor Cc.
Specifically, the source electrode of the 5th PMOS tube MP0 is connect with Pixel-level circuit 4, the drain electrode of drain electrode and the 5th NMOS tube MN0
The grid of connection, the 5th NMOS tube MN0 inputs the second bias voltage Vfid；The grid of 5th NMOS tube MN0 inputs the first biased electrical
Veb is pressed, the source electrode of the 5th NMOS tube MN0 is connect with the first end of blind element Rd, the second end ground connection of blind element Rd；
More specifically, the drain electrode of the negative input end and the 5th PMOS tube MP0 of the 5th operational amplifier OPA0 in agc circuit
Connection；The first end of capacitor Cc and across resistance Rg first end connect with the negative input end of the 5th operational amplifier OPA0, capacitor
The second end of Cc and across resistance Rg second end connect with the output end of the 5th operational amplifier OPA0；Wherein, the 5th operation is put
Big device OPA0 exports Vagc.
In the present embodiment, row grade circuit 3 includes the row class mirror-image pixel Rsm and row choosing switch RSEL of switch line-by-line；Its
In, the both ends of mirror image pixel Rsm are connect with the first end of the second end of the first row choosing switch, the second row choosing switch respectively；Second
The second end of row choosing switch is connect with the drain electrode of the 4th NMOS tube MN4；The first end and common-mode current source Vdet of the first row choosing switch
Connection；
It should be noted that Rsm makees shading treatment, make it by the anti-dazzling screen for being constantly equal to underlayer temperature from temperature
Fixed radiation.
In the present embodiment, Pixel-level circuit 4 includes pixel Rs and row choosing switch RSEL；Wherein, the both ends of pixel Rs point
It is not connect with the first end of the second end of the third line choosing switch, fourth line choosing switch；The first end and common mode of the third line choosing switch
Power supply Vdet connection；The second end of fourth line choosing switch is connect with the source electrode of the 5th PMOS tube MP0.
It should also be noted that, in the present embodiment, constant pressure biasing is carried out to blind element Rd and the first mirror image blind element Rdm, and
Constant biasing is carried out to pixel Rs and mirror image pixel Rsm, and Rs and Rsm are placed in high voltage domain, Rd and Rdm are placed in low-voltage
Domain, effectively improves the rejection ability of the noise to common-mode current source Vdet, and does not need the Vb of high voltage.
It is briefly described as follows the working principle of circuit in the present embodiment.
First in the case where not considering process mismatch and the enough situations of OPA1 gain, based on the first operational amplifier OPA1 and
Vb generates electric current on Rdm0
Then, it is based on the first mirror image blind element Rdm0With the second mirror image blind element Rdm1Matching, the first NMOS tube MN1 and second
The matching of NMOS tube MN2 obtains electric current approximately uniform with Rdm0 on Rdm1 and pixel Rd, and the electric current can follow substrate
Temperature change:
Generating based on this electric current, on the class mirror-image pixel Rsm that is expert at can follow underlayer temperature to change and incude self-heating effect
The voltage answered
Voltage VRsmAs the positive input of third operational amplifier OPA3, when OPA3 gain is enough, the electricity of negative input end
Pressure is approximately:
That is the source voltage terminal of third PMOS tube MP3 is alsoThe grid end voltage of MP3 isAnd the voltage is used as the second bias voltage Vfid, is biased to MP0；
Vfid is generated in loop, and the branch current of PMOS tube MP3 and MP4 are obtained by the current mirror duplication of Rdm0 branch, ensure that pair
The constant biasing of MP3, and the electric current is in ratio with the electric current for flowing through Rsm branch；So that mirror image matching degree is high, avoid increasing use
The shading pixel of row grade and introduce influence loop stability parasitic capacitance；Then the voltage and current on pixel Rs is respectively
In the case where pixel Rs, mirror image pixel Rsm receiving identical fixed radiation, Rsm and Rs resistance value matches and adds certainly
Fuel factor is cancelled out each other, i.e.,
At third NMOS tube MN3 and the 5th matched situation of NMOS tube MN0 size, | VGSP3|=| VGSP0|, have
By (2) formula and (8) formula it is found that when Rs, Rsm receive identical fixed radiation, circuit is in fixed input state,
That is:
Idiff=Is0-Id=0 ... (9)
By (9) formula it is found that exporting automatic stabilisation when circuit is in fixed input, with underlayer temperature and self-heating effect without
It closes.
When Rs is by the external radiation changed, when resistance value changes, the electric current for flowing through MP0 can meet
To (10) formula both sides derivation, obtain
Wherein,For the transconductance value of metal-oxide-semiconductor.
In (11) formula, by rationally designing, g can be mademRs> > 1,1+gmRs≈gmRs, then (11) formula becomes
Then
After agc circuit, exports and be
(14) in formula,Self-heating effect is offset, the V of acquisitionagcThe variation of pixel resistance value can be read, and is and substrate
Temperature and all unrelated amount of self-heating effect.
It should be noted that biasing the first mirror image blind element Rdm0 using constant pressure Vb in technical solution disclosed in the present embodiment
After generate constant current, matched using device parameters so that generate identical constant current on Rdm1 and Rd, recycle the constant current in Rsm
Upper acquisition voltage Vrsm.And Rd, Rdm0, Rdm1 are biased in low voltage domain, are to be generated based on Vb and ground level, due to Horizon
The noise in face is smaller, greatly reduces the noise of introducing；Constant pressure Vb does not need too high voltage simultaneously, does not need using boosting electricity
Road obtains a high Vb, avoids a possibility that noise is introduced from booster circuit；Additionally, due to circuit using mirror image
Structure, the noise on Vdet are common mode amount for Rs and Rsm, and this framework has the common-mode noise on Vdet good
Rejection ability.
It should also be noted that, disclosed in the present embodiment in technical solution, used second operational amplifier OPA2 and
Four-operational amplifier OPA4, effect are to arrive the drain potential clamper of the drain electrode of the first NMOS tube MN1, third PMOS tube MP3
Common-mode voltage Vcm, in column grade analog front circuit 2, the drain electrode of the 5th NMOS tube MN0 and the 5th PMOS tube MP0 are due to the 5th fortune
The clamping action for calculating amplifier OPA0 is also common-mode voltage Vcm, ensure that between the first NMOS tube MN1 and the 5th NMOS tube MN0,
There is better matching degree between third PMOS tube MP3 and the 5th PMOS tube MP0.
It should also be noted that, the first mirror image blind element Rdm0 carries out constant pressure biasing by Vb, generates constant current and pass through first
PMOS tube MP1 copies to MP3 and MP4 branch road by the current-mirror structure that MP1 and MP2 are constituted, it is steady that preferable loop may be implemented
It is qualitative.
In the present embodiment, the electric current of the second mirror image blind element Rdm1 branch generates control second by the first bias voltage Veb
NMOS tube MN2 is generated, as the first mirror image blind element Rdm0 branch, the constant biasing mirror image pixel Rsm of generation, in mirror image pixel
The lower end Rsm generates a bias, it is now desired to by this bias " replicated " to the lower end of pixel Rs, carry out to pixel same inclined
It sets, specific way disclosed in the present embodiment is: third operational amplifier OPA3 will terminated to just under mirror image pixel Rsm
Input terminal, for third operational amplifier OPA3 negative input end due to clamping action, voltage is identical as the lower end of mirror image pixel Rsm, warp
Voltage value subtracts after crossing MP3 | Vgsp3 | it is the second bias voltage Vfid；The voltage value of the lower end pixel Rs is Vfid+ | Vgsp0
|, in the matched situation of MP3 and MP0, | Vgsp3 | and | Vgsp0 | it can cancel out each other, then the voltage of the lower end Rs is exactly mirror image picture
The voltage of first lower end Rsm is constant biasing；For the second bias voltage Vfid loop, passed through using current-mirror structure duplication
The constant current that blind element Rd is generated, rather than directly connect and generate the second bias voltage Vfid in the lower end of mirror image pixel Rsm, be because of
Mirror image pixel Rsm shading may introduce the parasitic capacitance for influencing stability；Using method disclosed in the present embodiment, so that
Mirror image matching degree is high, avoids increasing the shading pixel using row grade and introducing the parasitic capacitance for influencing loop stability.
In the present embodiment, the power supply noise of introducing is reduced for the design of voltage domain, and avoids the need for high biasing
Voltage Vb and introduce new noise；In the loop for generating the second bias voltage Vfid, using the structure of this programme, it may be implemented
Good loop stability.
It is emphasized that the current-mirror structure being previously mentioned in embodiment two and embodiment three, default analyzes current mirror
Structural circuit only has the case where column, but can also be in parallel using multiple row actually in current-mirror structure, such as embodiment three
In, mirror image pixel Rsm, the 4th NMOS tube MN4, the second NMOS tube MN2 branch can be with multiple row parallel connection, the second PMOS tube MP2, third
PMOS tube MP3 and the 4th PMOS tube MP4 branch can be with multiple row parallel connections；In embodiment two, MP2 branch can also be with multiple row parallel connection；It can
Further to improve the matching degree of device, reduce the noise of mirror image circuit, but cost makes to increase power consumption.In performance and power consumption
Between how to select this depend on designer demand, but all this programme state within the scope of.
More than, it is merely preferred embodiments of the present invention, but scope of protection of the present invention is not limited thereto, it is any
In the technical scope disclosed by the present invention, any changes or substitutions that can be easily thought of by those familiar with the art, all answers
It is included within the scope of the present invention.Therefore, protection scope of the present invention should be subject to the protection scope in claims.
Claims (20)
1. a kind of no TEC un-cooled infrared focal plane array reading circuit, which is characterized in that including bias generating circuit, column grade
Analog front circuit and row grade circuit；Wherein,
It include row class mirror-image pixel (Rsm) and row choosing switch (RSEL<i>) in the row grade circuit；When the row grade circuit is by institute
When stating row choosing switch (RSEL<i>) control and being strobed, Xiang Suoshu bias generating circuit exports third bias voltage (VRsm)；
The input terminal of the bias generating circuit connects the output end of the row grade circuit；According to the constant pressure (V of inputb) and it is described
Third bias voltage (VRsm) generate and export the first bias voltage (Veb) and the second bias voltage (Vfid)；
Include in the column grade analog front circuit blind element (Rd)；The input terminal connection of the column grade analog front circuit is described partially
The output end for pressing generation circuit, according to first bias voltage (Veb) and the second bias voltage (Vfid) obtain two-way electricity
Stream, and to generated two-way difference between currents (Idiff) carry out across resistance amplification and as output voltage (Vagc) output.
2. circuit according to claim 1, which is characterized in that the bias generating circuit is generated including at least the first bias
Sub-circuit and the second bias generation sub-circuit export first bias voltage (Veb) and second bias voltage respectively
(Vfid)。
3. circuit according to claim 2, which is characterized in that as the constant pressure (Vb) input when, will first bias production
The grid voltage of PMOS tube is as first bias voltage (Veb), output to the column grade AFE(analog front end) electricity in raw sub-circuit
Road；
The second bias generation sub-circuit is according to the third bias voltage (VRsm) generate the second bias voltage (Vfid), it utilizes
Source in second bias generation sub-circuit follows structural circuit by the second bias voltage (Vfid) replicate and export to the column
Grade analog front circuit.
4. circuit according to claim 2, which is characterized in that the first bias generation sub-circuit and second bias
Generation sub-circuit, the row grade circuit, column grade analog front circuit connection；Including at least the first mirror image circuit, the second mirror
As circuit, the first operational amplifier (OPA1), the first mirror image blind element (Rdm0), the second mirror image blind element (Rdm1) and power supply (Vsk)；
First mirror image circuit respectively with second mirror image circuit, first operational amplifier (OPA1), the first mirror image
Blind element (Rdm0), the second mirror image blind element (Rdm1) connection.
5. circuit according to claim 4, which is characterized in that first mirror image circuit includes the first PMOS tube (MP1)
With the second PMOS tube (MP2), the grid of first PMOS tube (MP1) is connect with the grid of second PMOS tube (MP2)；Institute
Stating the second mirror image circuit includes the first NMOS tube (MN1) and the second NMOS tube (MN2), the grid of first NMOS tube (MN1)
It is connect with the grid of second NMOS tube (MN2)；
The first mirror image blind element (Rdm0) first end, the second mirror image blind element (Rdm1) first end with the power supply
(Vsk) it connects；The source electrode of first PMOS tube (MP1), drain electrode respectively with the first mirror image blind element Rdm0Second end, institute
State the drain electrode connection of the first NMOS tube (MN1)；The source electrode of second PMOS tube (MP2), drain electrode respectively with second mirror image
Blind element (Rdm1) second end, the row grade circuit connection；The drain electrode of second NMOS tube (MN2) and second bias produce
Raw sub-circuit connection；The source grounding of the source electrode of first NMOS tube (MN1), second NMOS tube (MN2)；
The negative input end of first operational amplifier (OPA1), positive input terminal, output end respectively with first PMOS tube
(MP1) source electrode, constant pressure (Vb), the connection of the grid of first PMOS tube (MP1).
6. circuit according to claim 5, which is characterized in that in the first bias generation sub-circuit, when the perseverance
When pressure input, by the grid of the grid of the first PMOS tube (MP1) in first mirror image circuit and second PMOS tube (MP2)
Pole tension is as first bias voltage (Veb), output to the column grade analog front circuit.
7. circuit according to claim 4, which is characterized in that the first bias generation sub-circuit further includes decoupling capacitor
(C1)；First end, the second end of the decoupling capacitor (C1) are connect with the power supply (Vsk), first mirror image circuit respectively.
8. circuit according to claim 2, which is characterized in that the second bias generation sub-circuit and first bias
Generation sub-circuit, the row grade circuit and column grade analog front circuit connection；Including at least the first source follow structural circuit,
Second source follows structural circuit, third NMOS tube (MN3) and second operational amplifier (OPA2)；
Grid, the source electrode of the third NMOS tube (MN3) follow structural circuit, first bias to produce with first source respectively
Raw sub-circuit connection；Second source follows structural circuit to follow structural circuit to connect with first source；Second operation
The negative input end of amplifier (OPA2), positive input terminal, output end source electrode, the row with the third NMOS tube (MN3) respectively
Grade circuit, first source follow structural circuit to connect.
9. circuit according to claim 8, which is characterized in that it includes the first current source that first source, which follows structural circuit,
(Ib3) and third PMOS tube (MP3)；It includes the second current source (Ib4) and the 4th PMOS tube that second source, which follows structural circuit,
(MP4)；
The source electrode of the third PMOS tube (MP3) is connected to first current source (Ib3), the 4th PMOS tube (MP4)
Source electrode is connected to second current source (Ib4)；The source electrode of the third PMOS tube (MP3) and the third NMOS tube (MN3)
Grid connection；The output end of the second operational amplifier (OPA2) connect with the grid of the third PMOS tube (MP3) and
The grid of the third PMOS tube (MP3) is connect with the grid of the 4th PMOS tube (MP4).
10. circuit according to claim 9, which is characterized in that the second bias generation sub-circuit is according to the row grade
Third bias voltage (the V of circuit outputRsm) source voltage that obtains the third PMOS tube (MP3), it is followed through first source
Structural circuit and second source follow structural circuit that the source voltage of the third PMOS tube (MP3) is copied to the described 4th
The source electrode of PMOS tube (MP4) and as the second bias voltage (Vfid), output to the column grade analog front circuit.
11. circuit according to claim 2, which is characterized in that the column grade analog front circuit includes at least Pixel-level
Sub-circuit, power supply (Vsk), blind element (Rd), the 5th PMOS tube (MP0), the 4th NMOS tube (MN0) and automatic gain calibration electricity
Road；The grid of 5th PMOS tube (MP0), the grid of the 4th NMOS tube (MN0) connect with the bias generating circuit
It connects, and receives first bias voltage (Veb), described second partially respectively as the input terminal of the column grade analog front circuit
Set voltage (Vfid)；
The first end of the blind element (Rd), the second end source electrode with the power supply (Vsk), the 5th PMOS tube (MP0) respectively
Connection；The drain electrode of 4th NMOS tube (MN0), source electrode respectively with the drain electrode of the 5th PMOS tube (MP0), the Pixel-level
Sub-circuit connection；Wherein, the Pixel-level sub-circuit includes pixel (Rs).
12. circuit according to claim 11, which is characterized in that the automatic gain calibration sub-circuit includes at least third
Operational amplifier (OPA0), across resistance (Rg) and capacitor (Cc)；
The negative input end of the third operational amplifier (OPA0) is connect with the drain electrode of the 5th PMOS tube (MP0)；The electricity
The first end and the first end across resistance (Rg) for holding (Cc) connect with the negative input end of the third operational amplifier (OPA0)
It connects；The second end of the capacitor (Cc) and the second end across resistance (Rg) are defeated with the third operational amplifier (OPA0)
Outlet connection；Wherein, the third operational amplifier (OPA0) exports output voltage (Vagc)。
13. circuit according to claim 2, which is characterized in that in the first bias generation sub-circuit, when the perseverance
Press (Vb) input when, the grid voltage for the NMOS tube for including in first mirror image circuit is as first bias voltage
(Veb), it exports to the column grade analog front circuit；
The second bias generation sub-circuit is according to the third bias voltage (V of the row grade circuit outputRsm) obtain the 3rd PMOS
Manage the grid voltage of (MP3) and as the second bias voltage (Vfid), output to the column grade analog front circuit.
14. circuit according to claim 2, which is characterized in that the first bias generation sub-circuit is inclined with described second
Press generation sub-circuit, the row grade circuit and column grade analog front circuit connection；Including at least the first mirror image circuit, second
Mirror image circuit, the first operational amplifier (OPA1), second operational amplifier (OPA2), the first mirror image blind element (Rdm0) and the second mirror
As blind element (Rdm1)；
First mirror image circuit and second mirror image circuit, the second bias generation sub-circuit and the row grade circuit connect
It connects；The first mirror image blind element (Rdm0) first end, the second mirror image blind element (Rdm1) first end with first mirror
As circuit connection；First operational amplifier (OPA1), the second operational amplifier (OPA2) respectively with first mirror
As circuit, second mirror image circuit connect.
15. circuit according to claim 14, which is characterized in that first mirror image circuit includes the first NMOS tube
(MN1) and the grid of the second NMOS tube (MN2) and the grid of first NMOS tube (MN1) and second NMOS tube (MN2)
Connection；The negative input end of first operational amplifier (OPA1), positive input terminal, output end respectively with first NMOS tube
(MN1) source electrode, constant pressure (Vb), the connection of the grid of first NMOS tube (MN1)；
Second mirror image circuit includes third NMOS tube (MN3) and the 4th NMOS tube (MN4) and the third NMOS tube (MN3)
Grid connect with the grid of the 4th NMOS tube (MN4)；It is the negative input end of the second operational amplifier (OPA2), just defeated
Enter end, output end respectively with the source electrode of the third NMOS tube (MN3), common-mode voltage Vcm, the third NMOS tube (MN3)
Grid connection；Drain electrode, the drain electrode of the 4th NMOS tube (MN4) of the third NMOS tube (MN3) are inclined with described second respectively
Press generation sub-circuit, the row grade circuit connection.
16. circuit according to claim 15, which is characterized in that in the first bias generation sub-circuit, when described
Constant pressure (Vb) input when, the grid comprising the first NMOS tube (MN1) and the second NMOS tube (MN2) in first mirror image circuit is electric
Pressure is used as first bias voltage (Veb), output to the column grade analog front circuit.
17. circuit according to claim 2, which is characterized in that the second bias generation sub-circuit is inclined with described first
Press generation sub-circuit, the row grade circuit and column grade analog front circuit connection；Including at least third mirror image circuit, third
PMOS tube (MP3), the 4th PMOS tube (MP4), third operational amplifier (OPA3), four-operational amplifier (OPA4) and common mode electricity
Source (Vdet)；
The third mirror image circuit includes the first PMOS tube (MP1) and the second PMOS tube (MP2), and first PMOS tube
(MP1) grid is connected with the grid of second PMOS tube (MP2)；The source electrode of first PMOS tube (MP1), described second
The source electrode of PMOS tube (MP2) is connect with the common-mode current source (Vdet), the drain electrode of first PMOS tube (MP1) and described the
The connection of one bias generation sub-circuit；The source electrode of the third PMOS tube (MP3), drain electrode respectively with second PMOS tube (MP2)
Drain electrode, the 4th PMOS tube (MP4) source electrode connection；The positive input terminal of the third operational amplifier (OPA3), bear it is defeated
Enter end and output end is separately connected the row grade circuit, the source electrode of the third PMOS tube (MP3) and the third PMOS tube
(MP3) grid；Positive input terminal, negative input end and the output end of the four-operational amplifier (OPA4) are separately connected common mode electricity
Press Vcm, the source electrode of the 4th PMOS tube (MP4) and the grid of the 4th PMOS tube (MP4).
18. 7 circuit according to claim 1, which is characterized in that the second bias generation sub-circuit is according to the row grade electricity
Third bias voltage (the V of road outputRsm) obtain the grid voltage of the third PMOS tube (MP3) and as second biasing
Voltage (Vfid), output to the column grade analog front circuit.
19. circuit according to claim 1, which is characterized in that the column grade analog front circuit includes Pixel-level son electricity
Road, common-mode current source (Vdet), blind element (Rd), the 5th PMOS tube (MP0), the 4th NMOS tube (MN0) and automatic gain calibration electricity
Road；
The source electrode of 5th PMOS tube (MP0), drain electrode respectively with the Pixel-level sub-circuit, the 4th NMOS tube (MN0)
Drain electrode connection；The first end of the blind element (Rd) is connect with the source electrode of the 5th NMOS tube (MN0), the blind element (Rd)
Second end ground connection；The automatic gain calibration sub-circuit is connect with the drain electrode of the 5th PMOS tube (MP0)；
The grid of 5th PMOS tube (MP0), the grid of the 5th NMOS tube (MN0) connect with the bias generating circuit
It connects, and receives first bias voltage (Veb), described second partially respectively as the input terminal of the column grade analog front circuit
Set voltage (Vfid)。
20. circuit according to claim 1, which is characterized in that the column grade analog front circuit is according to the institute received
It states the first bias voltage (Veb) and the blind element (Rd) generates the first electric current；The column grade analog front circuit is according to receiving
The second bias voltage (Vfid) and the column grade analog front circuit include pixel (Rs) generate the second electric current；According to
First electric current and second electric current obtain the two-way difference between currents (Idiff)。
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