CN109962830A - A kind of efficient CAN interface based on FPGA - Google Patents
A kind of efficient CAN interface based on FPGA Download PDFInfo
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- CN109962830A CN109962830A CN201711451959.7A CN201711451959A CN109962830A CN 109962830 A CN109962830 A CN 109962830A CN 201711451959 A CN201711451959 A CN 201711451959A CN 109962830 A CN109962830 A CN 109962830A
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- fpga
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L12/40006—Architecture of a communication node
- H04L12/40032—Details regarding a bus interface enhancer
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L2012/40208—Bus networks characterized by the use of a particular bus standard
- H04L2012/40215—Controller Area Network CAN
Abstract
The present invention provides a kind of efficient CAN interface based on FPGA, hardware includes 2 bit level conversion chip of FPGA, monolithic CAN transceiver and monolithic；By CAN transceiver by CAN bus information access, then two link signal of sending and receiving is sent to FPGA after 2 bit level conversion chip are converted；Inside the FPGA, main control module is realized using programmable logic；The logic for simulation numeral integrated chip SJA1000 is fixed with inside the FPGA, as CAN controller, the CAN controller directly docks main control module；Method of the clock division in conjunction with phaselocked loop is used inside the FPGA, and reference clock is generated inside FPGA.The present invention is directed to the fpga chip of all models, does not need CAN controller, reference clock crystal oscillator, the realization CAN interface of simple and efficient.
Description
Technical field
The present invention relates in the technical field of Design of Digital Circuit, a kind of efficient CAN bus based on FPGA is particularly related to
Interface.
Background technique
CAN protocol is a kind of general communication standard, and it is ISO that full name in English, which is Controller Area Network,
The serial communication protocol of International standardization.Communication bus based on CAN protocol be it is a kind of it is totally digitilized, two-way, serial, it is asynchronous and
Mostly main fieldbus.Now, the high-performance and reliability of CAN is accepted, and is widely used in industrial automation, ship
Oceangoing ship, Medical Devices, industrial equipment etc..A variety of brand automobiles, intelligent sail body control system, the information transmission system all adopt
It is communicated with CAN bus.
CAN bus defers to osi model, operates mainly in data link layer and physical layer.CAN protocol has the special feature that packet
Include: 1) in bus free, all units can independently start to send information, realize multi host control；2) all message
(standard frame, extension frame) is all sent with fixed format, realizes the compatibility of distinct interface；3) each unit is not similar to " address "
Information, when bus adding unit, the software and hardware and application layer of other units are all had no need to change；4) according to the rule of whole network
Mould can set different communication speeds；5) other units can be requested to send data by transmission " remote control frame "；6) all units
With error detection function；7) CAN can will cause the unit of bus continuous fault to be isolated away from bus；8) CAN bus can
To connect multiple units simultaneously, theoretically there is no limit for unit sum.
FPGA is a kind of field programmable gate array, has the characteristics that integrated level is high, logic function is strong, speed is fast.Monolithic
FPGA is designed using hardware logic language (VHDL, Verlog), customized powerful logic function may be implemented, to substitute
And the function of comprehensive a variety of special digital integrated chips.
Existing FPGA device (XILINX company, altera corp) does not support CAN protocol, connects without dedicated CAN
Mouthful.
It usually realizes the CAN bus communication based on FPGA, needs to increase dedicated CAN bus control in FPGA device periphery
Device, such as SJA1000, PCA82C200.Circuit structure is as shown in Figure 1.For CAN transceiver as unit CAN interface node, connection is outer
Portion's CAN bus, control signal reach the physical layer in bus from CAN transceiver, and vice versa.Common CAN transceiver has
PCA82C250.CAN controller is responsible for executing the CAN protocol defined in CAN specification, completes data conversion, message buffer and examination
Filtering.Since CAN controller needs to adjust, unit communications baud rate is consistent with data transmission bauds in CAN bus, and CAN is controlled
Device should access external reference clock.The logic level of common CAN controller output is 5V, and needing will by electrical level transferring chip
5V voltage is converted into the interface voltage of FPGA.FPGA receives the signal of CAN controller output, extracts the information in CAN bus.
The CAN interface based on FPGA of above method design, circuit design redundancy is complicated, needs to increase a variety of outsides
Chip improves design cost, increases circuit layout difficulty；Meanwhile CAN controller has multiple groups control signal, data-signal output,
The I/O resource of excessive FPGA is occupied, wiring increases difficulty.
Summary of the invention
The efficient CAN interface based on FPGA that the embodiment of the invention provides a kind of, in order to solve base in the prior art
In the problem that the CAN interface circuit design redundancy of FPGA is complicated, at high cost, wiring difficulty is big.
In order to solve the above-mentioned technical problem, the embodiment of the present invention adopts the following technical scheme that
A kind of efficient CAN interface based on FPGA, hardware include 2 bit level of FPGA, monolithic CAN transceiver and monolithic
Conversion chip；By CAN transceiver by CAN bus information access, then two link signal of sending and receiving by 2 bit levels turn
After changing chip conversion, it is sent to FPGA；Inside the FPGA, main control module is realized using programmable logic；The FPGA
Inside is fixed with the logic for simulation numeral integrated chip SJA1000, and as CAN controller, the CAN controller is directly right
Connect main control module；Method of the clock division in conjunction with phaselocked loop is used inside the FPGA, and reference clock is generated inside FPGA.
Wherein, the method for the logic of the simulation numeral integrated chip SJA1000 are as follows: including CAN nucleus module, mouthpiece
Logic, acceptance fitration are managed, FIFO is received and sends buffering；
Transmitting-receiving and CAN protocol communication, CAN nucleus module of the CAN nucleus module for CAN message frame should be supported
The agreement of CAN2.0B, and directly connect with the sending and receiving signal of CAN transceiver output；The CAN nucleus module, which reads to send, to be delayed
The data in area are rushed, a complete information frame are packaged by CAN protocol, according to bus timing register in interface management logic
Baud rate preset value, by information frame sequential be sent to receive signal link on；Conversely, according to CAN2.0B agreement and fixed wave
Special rate, CAN nucleus module judge whether signalling chain road has information to reach and read information frame, transmit after extracting effective information
To acceptance fitration；
The interface management logic is connected with external piloting control module, for explaining the order from main control module；It is described
Interface management logical internal include multiple groups register, for being addressed to register, to main control module provide interrupting information and
Control information；
The acceptance fitration is filtered for docking breath of collecting mail, and only acceptance filtenng passes through and zero defect, could handle
Received information frame, which is sent into, receives FIFO buffer area；The acceptance fitration is the ID of reception information compared with the content of identification code
Compared with, decide whether receive information；Identification code is obtained by the storage value in reading mask register；The acceptance fitration is by FPGA
In comparator resource realize；
The reception FIFO is the buffer area between main control module and acceptance filtenng, is connect from CAN bus for storing
The ID and data of receipts；Receiving FIFO has 64 bytes, first in, first out, and the interface management logic can access at any time；The reception
FIFO is realized using the FIFO resource carried in FPGA；
The transmission buffering is 13 bytes for storing a complete information frame, length, and main control module can be directly by ID
It is sent into data and sends buffer area, then set the transmission request position of command register, starting CAN nucleus module, which is read, sends buffering
The data in area；The transmission buffering is realized by RAM resource.
Preferably, the register in the interface management logic includes control register, command register, Status register
Device, interrupt register, mask register, bus timing register, data storage register, interrupt enable register, arbitration are lost
It loses and captures register, each register functions are realized using ROM resource in FPGA.
The invention has the benefit that the embodiment of the invention provides a kind of efficient CAN interface based on FPGA, hardware packet
Include 2 bit level conversion chip of FPGA, monolithic CAN transceiver and monolithic；By CAN transceiver by CAN bus information access, then
Two link signal of sending and receiving is sent to FPGA after a 2 bit level conversion chips are converted；Inside the FPGA, utilize
Programmable logic realizes main control module；It is fixed with the logic for simulation numeral integrated chip SJA1000 inside the FPGA, makees
For CAN controller, the CAN controller directly docks main control module；Using clock division and phaselocked loop knot inside the FPGA
The method of conjunction, generates reference clock inside FPGA.The present invention is directed to the fpga chip of all models, does not need CAN bus control
Device processed, reference clock crystal oscillator, the realization CAN interface of simple and efficient；The CAN interface controlled using FPGA, in hardware design
A piece of CAN controller, a piece of external crystal-controlled oscillation, two panels electrical level transferring chip can be reduced；Circuit board upward wiring is by original simultaneously
14 are reduced to 2, save interconnection resource on circuit board, save the I/O resource of FPGA.
Detailed description of the invention
Fig. 1 is the CAN interface circuit connecting relation figure of FPGA in the prior art；
Fig. 2 is the circuit relationships figure of the efficient CAN interface provided in an embodiment of the present invention based on FPGA；
Fig. 3 is the SJA1000 internal structure chart of the efficient CAN interface provided in an embodiment of the present invention based on FPGA.
Specific embodiment
With reference to the attached drawing in the embodiment of the present invention, technical solution in the embodiment of the present invention carries out clear, complete
Ground description, it is clear that the described embodiment is only a part of the embodiment of the present invention, instead of all the embodiments.Based on this hair
Bright embodiment, those of ordinary skill in the art's every other implementation obtained without creative labor
Example, belongs to protection scope of the present invention.
Referring to attached drawing 2 and Fig. 3, the embodiment of the invention provides a kind of efficient CAN interface based on FPGA, hardware packet
Include 2 bit level conversion chip of FPGA, monolithic CAN transceiver and monolithic；By CAN transceiver by CAN bus information access, then
Two link signal of sending and receiving is sent to FPGA after a 2 bit level conversion chips are converted；Inside FPGA, utilization can be compiled
Journey logic realizes main control module；It is fixed with the logic for simulation numeral integrated chip SJA1000 inside FPGA, is controlled as CAN
Device processed, CAN controller directly dock main control module；Method of the clock division in conjunction with phaselocked loop is used inside FPGA, in FPGA
Inside generates reference clock.
In the embodiment of the present invention, cardinal principle is as follows:
1) programmability powerful according to FPGA, resource abundant, simulation CAN control special digital integrated chip
The function of SJA1000, and the SJA1000 logic of simulation is fixed in the sub-regions inside FPGA；
2) it is generated inside FPGA using FPGA internal clocking resource using method of the clock division in conjunction with phaselocked loop
Reference clock (10MHz to 24MHz), substitution external crystal-controlled oscillation are inputted as reference clock；
3) CAN controller and reference clock are integrated in inside FPGA, and the control signal of CAN controller output is directly in FPGA
Inside is docked with main control module, so as to avoid the cabling of control signal on circuit boards；
4) access FPGA is two-way CAN receiving and transmitting signal (Tx, Rx), it is only necessary to a piece of 2 bit level conversion chip.
Efficient CAN interface circuit structure based on FPGA is as shown in Fig. 2, first will be total by CAN transceiver PCA82C250
Differential signal on line is converted into two-way sending and receiving signal.It is by 2 electrical level transferring chip SN74LVC2T45 that 5V signal is electric
Pressure is converted into FPGA interface voltage.And two-way sending and receiving signal is sent directly into FPGA universal I/O port.
Inside FPGA, main control module is realized using programmable logic.Meanwhile in fixed regional simulation CAN controller
The logic function of SJA1000.The CAN controller of simulation directly docks main control module inside FPGA.Utilize the overall situation inside FPGA
Clock sources are generated stable 16MHz reference clock by clock division and PHASE-LOCKED LOOP PLL TECHNIQUE, adjust the CAN controller of simulation
Baud rate is consistent with baud rate in bus.
It is present invention part relatively difficult to achieve using FPGA programmable logic and homegrown resource simulation SJA1000 function.Such as Fig. 3
Shown, SJA1000 internal structure is mainly made of 5 parts, and main implementation method is as follows:
1) CAN nucleus module: it is responsible for the transmitting-receiving of CAN message frame and the realization of CAN protocol.CAN nucleus module should be supported
The agreement of CAN2.0B, and directly connect with the receiving and transmitting signal (Tx, Rx) of CAN transceiver output.CAN nucleus module, which is read, to be sent
Data in buffer area are packaged into a complete information frame by CAN protocol, are deposited according to bus timing in interface management logic
The baud rate preset value of device, sends information frame sequential on Tx.Conversely, according to CAN2.0B agreement and fixed baud rate,
Whether CAN nucleus module judges to have information to reach on Rx and reads information frame, and (Information ID is not more than 64 after extraction effective information
The data of position) send acceptance fitration to；
2) interface management logic: being connected with external piloting control module, explains the order from main control module.Interface management is patrolled
Collecting internal includes multiple groups register.Interface management logic is responsible for being addressed register, to main control module offer interrupting information
With control information.Main register in interface management logic includes control register, command register, status register, in
Disconnected register, mask register, bus timing register, data storage register, interrupt enable register, arbitration, which are lost, to be captured
Register.Each register functions can be realized using ROM resource in FPGA.Connection with main control module includes: D [7:0] ---
Being responsible for effective information transmitted in both directions, RST, --- being responsible for resetting all registers, ALE --- responsible address information input is enabled,
CS --- it is enabled being responsible for piece choosing, WR --- being responsible for writing enabled, RD --- is responsible to read enabled, INT --- is responsible for interrupt output；
3) acceptance fitration: the responsible filtering for receiving information, only acceptance filtenng pass through and zero defect, could be received
Information frame, which is sent into, receives FIFO buffer area.The ID of reception information compared with the content of identification code, decision is acceptance fitration
No reception information.Identification code is obtained by the storage value in reading mask register.Acceptance fitration can be by the comparison in FPGA
Device resource is realized；
4) receive FIFO: receiving FIFO is the buffer area between main control module and acceptance filtenng, total from CAN for storing
Received ID and data on line.Receiving FIFO has 64 bytes, and first in, first out can be accessed at any time by interface management logic.The mould
Block can be realized using the FIFO resource carried in FPGA；
5) send buffering: a complete information frame can be stored by sending buffer area, and length is 13 bytes, and main control module can be with
Directly ID and data are sent into and send buffer area, then sets the transmission request position of command register, starting CAN nucleus module is read
Send the data of buffer area.Sending buffering can be realized with RAM resource.
Above each section realized by Verlog language design, using in FPGA global clock resource, multiplier resources, patrol
Collect resource, RAM, FIFO, comparator resource etc..
Efficient CAN interface technology provided in an embodiment of the present invention based on FPGA, the fpga chip suitable for all series.
The feature that can be had by oneself for FPGA, realizes the CAN communication of simple and efficient.
The embodiment of the invention provides a kind of efficient CAN interface based on FPGA, hardware include FPGA, monolithic CAN transmitting-receiving
2 bit level conversion chip of device and monolithic；By CAN transceiver by CAN bus information access, then two link signal of sending and receiving warp
After crossing a 2 bit level conversion chips conversion, it is sent to FPGA；Inside the FPGA, is realized and led using programmable logic
Control module；The logic for simulation numeral integrated chip SJA1000 is fixed with inside the FPGA, it is described as CAN controller
CAN controller directly docks main control module；Method of the clock division in conjunction with phaselocked loop is used inside the FPGA, in FPGA
Portion generates reference clock.The present invention is directed to the fpga chip of all models, does not need CAN controller, reference clock crystal oscillator,
The realization CAN interface of simple and efficient；Using the CAN interface of FPGA control, a piece of CAN control can be reduced in hardware design
Device, a piece of external crystal-controlled oscillation, two panels electrical level transferring chip；Circuit board upward wiring is reduced to 2 by original 14 simultaneously, saves electricity
Interconnection resource on the plate of road saves the I/O resource of FPGA.
In the description of this specification, particular features, structures, materials, or characteristics can be real in any one or more
Applying can be combined in any suitable manner in example or example.
Certainly, the present invention can also have other various embodiments, without deviating from the spirit and substance of the present invention,
Those skilled in the art can make various corresponding changes and modifications according to the present invention, but these change and modification are all
It should belong to scope of protection of the claims of the invention.
Claims (3)
1. a kind of efficient CAN interface based on FPGA, which is characterized in that hardware includes FPGA, monolithic CAN transceiver and monolithic 2
Bit level conversion chip；By CAN transceiver by CAN bus information access, then two link signal of sending and receiving by one 2
After electrical level transferring chip conversion, it is sent to FPGA；Inside the FPGA, main control module is realized using programmable logic；Institute
The logic being fixed with inside FPGA for simulation numeral integrated chip SJA1000 is stated, as CAN controller, the CAN controller
Directly dock main control module；Method of the clock division in conjunction with phaselocked loop is used inside the FPGA, and base is generated inside FPGA
Punctual clock.
2. the efficient CAN interface according to claim 1 based on FPGA, which is characterized in that the simulation numeral integrates core
The method of the logic of piece SJA1000 are as follows: including CAN nucleus module, interface management logic, acceptance fitration, receive FIFO and hair
Send buffering；
Transmitting-receiving and CAN protocol communication, CAN nucleus module of the CAN nucleus module for CAN message frame should support CAN2.0B
Agreement, and directly with CAN transceiver output sending and receiving signal connect；The CAN nucleus module, which is read, to be sent in buffer area
Data are packaged into a complete information frame by CAN protocol, according to the baud rate of bus timing register in interface management logic
Preset value sends information frame sequential to and receives on signal link；Conversely, according to CAN2.0B agreement and fixed baud rate, CAN
Nucleus module judges whether signalling chain road has information to reach and read information frame, sends examination filter to after extracting effective information
Wave device；
The interface management logic is connected with external piloting control module, for explaining the order from main control module；The interface
Managing logical internal includes multiple groups register, for being addressed to register, provides interrupting information and control to main control module
Information；
The acceptance fitration is filtered for docking breath of collecting mail, and only acceptance filtenng passes through and zero defect, could be reception
Information frame be sent into receive FIFO buffer area；The acceptance fitration the ID of reception information compared with the content of identification code,
Decide whether to receive information；Identification code is obtained by the storage value in reading mask register；The acceptance fitration is by FPGA
Comparator resource realize；
The reception FIFO is the buffer area between main control module and acceptance filtenng, received from CAN bus for storing
ID and data；Receiving FIFO has 64 bytes, first in, first out, and the interface management logic can access at any time；The reception FIFO is adopted
It is realized with the FIFO resource carried in FPGA；
The transmission buffering is 13 bytes for storing a complete information frame, length, and main control module can be directly by ID sum number
Buffer area is sent according to being sent into, then sets the transmission request position of command register, starting CAN nucleus module, which is read, sends buffer area
Data；The transmission buffering is realized by RAM resource.
3. the efficient CAN interface according to claim 2 based on FPGA, which is characterized in that in the interface management logic
Register include control register, command register, status register, interrupt register, mask register, bus timing are posted
Storage, data storage register, interrupt enable register, arbitration, which are lost, captures register, and each register functions are using in FPGA
ROM resource is realized.
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110321304A (en) * | 2019-07-05 | 2019-10-11 | 山东浪潮人工智能研究院有限公司 | Bus communication system under vehicle environment between FPGA and STM32 |
| CN111049718A (en) * | 2019-12-30 | 2020-04-21 | 北京京航计算通讯研究所 | CAN bus simulation monitoring method |
| CN111158339A (en) * | 2019-12-30 | 2020-05-15 | 北京京航计算通讯研究所 | CAN bus simulation monitoring system |
| CN111610757A (en) * | 2020-04-02 | 2020-09-01 | 天津七所精密机电技术有限公司 | Multichannel multi-protocol dimming control module |
| CN112433969A (en) * | 2020-11-08 | 2021-03-02 | 中国航空工业集团公司洛阳电光设备研究所 | CAN data receiving and transmitting method based on MCU IO and SJA1000 |
| CN115065572A (en) * | 2022-02-28 | 2022-09-16 | 西安电子科技大学 | CAN FD controller for vehicle-mounted electronic system |
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| CN110321304A (en) * | 2019-07-05 | 2019-10-11 | 山东浪潮人工智能研究院有限公司 | Bus communication system under vehicle environment between FPGA and STM32 |
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| CN112433969A (en) * | 2020-11-08 | 2021-03-02 | 中国航空工业集团公司洛阳电光设备研究所 | CAN data receiving and transmitting method based on MCU IO and SJA1000 |
| CN115065572A (en) * | 2022-02-28 | 2022-09-16 | 西安电子科技大学 | CAN FD controller for vehicle-mounted electronic system |
| CN115065572B (en) * | 2022-02-28 | 2023-09-29 | 西安电子科技大学 | CAN FD controller for vehicle-mounted electronic system |
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