CN109359731A - A kind of Processing with Neural Network method and device based on chip design defect - Google Patents
A kind of Processing with Neural Network method and device based on chip design defect Download PDFInfo
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Abstract
The present embodiments relate to a kind of Processing with Neural Network method and devices based on chip design defect, which comprises obtains the type of the design defect of chip；Neural network is adjusted according to the type, so that the neural network operates normally on the chip；Wherein, the type of the design defect of the chip includes at least following one: input/output data caching does not adapt to the scale of neural network in abnormal operating state, arithmetic element design error, accelerator, by modifying or adjusting to deep neural network model, so that neural network adapts to the hardware configuration for mistake occur again, operation target is completed.
Description
Technical field
The present embodiments relate to nerual network technique field more particularly to a kind of nerve nets based on chip design defect
Network processing method and processing device.
Background technique
As deep neural network (Deep Neural Network, DNN) is in the fast development of artificial intelligence field, more
The calculating and the calculating mode of more application specific of greater amount are needed come more applications.Therefore the operation of neural network is gradually
Prolong Shen from general-purpose platform (CPU, GPU) to dedicated platform (FPGA, DSP, application specific processor and accelerator), this has also been expedited the emergence of largely
R & D design and the manufacture for handling the special circuit and application specific processor of neural network become an emerging neck of DNN development
Domain.Multiple groups arithmetic element is generally comprised in neural network processor structure, these arithmetic elements perhaps composition systolic arrays or
It forms multistage flowing water and carries out concurrent operation, and form a flexible data path, a new dedicated framework can bring 50
To the promotion of 1000 times of operation efficiencies.However since design is lacked experience, the development cycle is short, and exploitation chain is long, and neural network is fast
The reasons such as fast evolution support the integrated circuit R & D design of neural network inevitably to start a leak, mistake and estimate deficiency, so that stream
Expected effect even neural network kernel failure is not achieved in chip after piece production, causes very big time and economic loss,
The result is that catastrophic.
Processor design defect is that some or certain set of circuits causes under normal circumstances, neural network/deep learning
Algorithm has certain processor design defect as the operational model flexibly with static state abundant or Dynamic link library
There is correction capability.In traditional processor design field, once some kernel module damages, it will cause the mistakes of entire kernel
Effect.
Therefore, the processing method in reply chip design defect to neural network is lacked in existing scheme.
Summary of the invention
The embodiment of the present invention provides a kind of Processing with Neural Network method and device based on chip design defect, by depth
Degree neural network model is modified or is adjusted, so that neural network adapts to the hardware configuration for mistake occur again, completes operation
Target.
In a first aspect, the embodiment of the present invention provides a kind of Processing with Neural Network method based on chip design defect, comprising:
Obtain the type of the design defect of chip；
Neural network is adjusted according to the type, so that the neural network operates normally on the chip；
Wherein, the type of the design defect of the chip includes at least following one:
Input/output data caching does not adapt to the scale or fortune of neural network in abnormal operating state, accelerator
Calculate unit design fault.
It is in a possible embodiment, described that neural network is adjusted according to the type, comprising:
When the type of the design defect of the chip is that input/output data caching is in abnormal operating state, adjust
The rate of the input/output data of the whole input/output data caching is adjusted.
In a possible embodiment, the setting adjusts the input/output number of the input/output data caching
According to rate, comprising:
The number of plies of neural network model and every layer of scale are modified, each input data reads the quantity of weight, adjustment fortune
It calculates unit and caches the frequency for reading data and being output to output caching from input data.
In a possible embodiment, the setting adjusts the data address of the inputoutput data caching, packet
It includes:
The scale of the input and output layer of neural network model is modified, the address range of input into/output from cache is read in adjustment, around
Open cache invalidation site.
It is in a possible embodiment, described that neural network is adjusted according to the type, comprising:
When the type of the design defect of the chip is that accelerator does not adapt to the scale of neural network, by the nerve
Network split is at multiple sub-networks, so that the accelerator adapts to each sub-network.
It is in a possible embodiment, described that neural network is adjusted according to the type, comprising:
When the type of the design defect of the chip designs fault for arithmetic element, by the corresponding operation mould of arithmetic element
Formula is added in the training process of neural network, keeps the arithmetic element operation mode of operation and failure in the training process
It is identical, so that neural network adapts to the incorrect operation mode of accelerator.
Second aspect, the embodiment of the present invention provide a kind of Processing with Neural Network device based on chip design defect, comprising:
Obtain module, the type of the design defect for obtaining chip；
Module is adjusted, for being adjusted according to the type to neural network, so that the neural network is in the core
On piece operates normally；
Wherein, the type of the design defect of the chip includes at least following one:
Input/output data caching does not adapt to the scale or fortune of neural network in abnormal operating state, accelerator
Calculate unit design fault.
In a possible embodiment, the adjustment module, specifically for the class of the design defect when the chip
When type is that input/output data caching is in abnormal operating state, so that the input of input/output data caching/defeated
The rate of data is adjusted out.
In a possible embodiment, the adjustment module, specifically for modify neural network model the number of plies and
Every layer of scale and each input data read the quantity of weight, and adjustment arithmetic element caches from input data and reads data
Or it writes and exports data cached frequency.
In a possible embodiment, the adjustment module, the input specifically for modification neural network model are defeated
The scale of layer out, adjustment arithmetic element, which caches to read data or write from input data, exports data cached address range.
In a possible embodiment, the adjustment module, specifically for the class of the design defect when the chip
When type is that accelerator does not adapt to the scale of neural network, the neural network is split into multiple sub-networks, so that described add
Fast device adapts to each sub-network.
In a possible embodiment, the adjustment module, specifically for the class of the design defect when the chip
When type designs fault for arithmetic element, corresponding operation mode is added in the training process of neural network, makes training
Operation in journey is identical as the operation mode holding of arithmetic element that accelerator fails, so that neural network is adapting to accelerator not just
True operation mode.
Processing with Neural Network scheme provided in an embodiment of the present invention based on chip design defect, passes through the acquisition chip
The type of design defect；Neural network is adjusted according to the type, so that the neural network is on the chip just
Often operation；By modifying or adjusting to deep neural network model, so that neural network adapts to the hard of mistake occur again
Part structure completes operation target.
Detailed description of the invention
Fig. 1 is a kind of Processing with Neural Network method flow signal based on chip design defect provided in an embodiment of the present invention
Figure；
Fig. 2 provides a kind of structural representation of Processing with Neural Network device based on chip design defect for the embodiment of the present invention
Figure；
Fig. 3 provides a kind of hardware configuration of Processing with Neural Network equipment based on chip design defect for the embodiment of the present invention
Schematic diagram.
Specific embodiment
In order to make the object, technical scheme and advantages of the embodiment of the invention clearer, below in conjunction with the embodiment of the present invention
In attached drawing, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described embodiment is
A part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, those of ordinary skill in the art
Every other embodiment obtained without making creative work, shall fall within the protection scope of the present invention.
In order to facilitate understanding of embodiments of the present invention, it is further explained below in conjunction with attached drawing with specific embodiment
Bright, embodiment does not constitute the restriction to the embodiment of the present invention.
Fig. 1 is a kind of Processing with Neural Network method flow signal based on chip design defect provided in an embodiment of the present invention
Figure, as shown in Figure 1, this method specifically includes:
The type of the design defect of S101, acquisition chip.
Wherein, the type of the design defect of the chip includes at least following one:
Inputoutput data caching does not adapt to the scale or operation of neural network in abnormal operating state, accelerator
Unit design fault.
S101, neural network is adjusted according to the type, so that the neural network is normal on the chip
Operation.
Specifically, when the type of the design defect of the chip is that input/output data caching is in non-normal working shape
When state, the input/output data rate of the input/output data caching is adjusted.Such as, neural network accelerator is due to inputting number
Control access is caused to fail according to caching (neural network input layer data buffer storage, IDB) controller cisco unity malfunction, the touching of failure
For hair reason when to be the data cache content be sky, cache controller state machine enters error condition, and then causes data path mixed
Disorderly, the input data that a part is read becomes messy code, can modify the quantity that each input data reads weight, reduces operation
Unit caches the frequency for reading data from input data.
Wherein, the operation mode of neural network accelerator is to obtain an input data x (i), keeps it all with this layer
Weight w is multiplied one by one, obtains a part of y of output of this layer, finally sums.
It is assumed that an input layer is 300, hidden layer 30, three layers of DNN network that output layer is 10 are not on the accelerator
It can work normally, because 30 weights of the every reading of arithmetic element just need to read an input data caching.Now again more
Change its model, the three layers of DNN model and the re -training model of 300x100x30 is become, since hidden layer has more multi-neuron
Operation is needed, each input data will obtain 100 weights and just take next input data, to effectively reduce operation list
Member caches the frequency of access evidence from input data, error condition is avoided, in the case where only having modified neural network model layer
Above-mentioned accelerator design mistake is evaded.
When the type of the design defect of the chip is that accelerator does not adapt to the scale of neural network, by the nerve
Network split is at multiple sub-networks, so that the accelerator adapts to each sub-network.
It is assumed that can only support all connecting nodes less than 10000 when neural network accelerator design, input layer cannot surpass
1024 are crossed, neural network of the output layer no more than 64.It is 960 now with an input layer, hidden layer 480, output
The DNN network that layer is 10, the network cannot be run on the accelerator, because its whole connecting node has reached 465600
It is a, far beyond design requirement.
Such as neural network can be split, be divided into 9 using neural network is split into multiple sub-network modes
Sub-network, wherein the fractionation that 8 sub-networks are the 1st, 2 layer, the size of each sub-network is 120x60, each sub-network connection section
Point is 7200；The fractionation that remaining 1 sub-network is the 2nd, 3 layer, size 480x10, sub-network connecting node number are 4800.This
The each sub-network of sample meets design requirement.Wherein the data connection between preceding 8 sub-networks is partially removed effective to realize
It is longitudinal sectional.In this way when training, or the big network of entire 960x480x10 is trained, in reasoning then using fractionation
Sub-network gradually calculated, to extend the ability of the accelerator.
In addition to above-mentioned fractionation, neural network can also be split using other way, the number of the sub-network splitted into
9 are not limited solely to, can be split according to actual needs, this present embodiment is not especially limited.
It designs and staggers the time for arithmetic element operation mode when the type of the design defect of the chip, by corresponding operation mould
Formula is added in the training process of neural network, makes the operation of the arithmetic element of operation and accelerator failure in the training process
Mode keeps identical, so that neural network adapts to the corresponding failure of accelerator operation mode.Such as, a neural network be using
The training that FANN software carries out, the software use floating-point and carry out operation to neural network, and rounding error is not present.Change now
The operation mode of FANN so that its value exported every time all carries out docking and is rounded to an integer, such FANN software become and
Hardware is consistent.It re-uses the software and carries out neural model training, then the model takes into account rounding error, in hardware
In maintain it is consistent.
Processing with Neural Network method provided in an embodiment of the present invention based on chip design defect, passes through the acquisition chip
The type of design defect；Neural network is adjusted according to the type, so that the neural network is on the chip just
Often operation；By modifying or adjusting to deep neural network model, so that neural network adapts to the hard of mistake occur again
Part structure completes operation target.
Fig. 2 provides a kind of structural representation of Processing with Neural Network device based on chip design defect for the embodiment of the present invention
Figure, as shown in Fig. 2, the device specifically includes:
Obtain module 201, the type of the design defect for obtaining chip；
Module 202 is adjusted, for being adjusted according to the type to neural network, so that the neural network is described
It is operated normally on chip；
Wherein, the type of the design defect of the chip includes at least following one:
Input/output data caching does not adapt to the scale of neural network, operation in abnormal operating state, accelerator
Unit design fault.
Optionally, the adjustment module 202, the type specifically for the design defect when the chip are input/output
When data buffer storage is in abnormal operating state, the input/output data rate of the input/output data caching is adjusted.
Optionally, the adjustment module 202, it is and every specifically for modifying the number of plies, every layer of the scale of neural network model
A input data reads the quantity of weight, and adjustment arithmetic element, which caches to read data or be written to from input data, exports caching
The frequency of data.
Optionally, the adjustment module 202, the scale of the input and output layer specifically for modifying neural network model, is adjusted
Whole arithmetic element, which caches to read data or write from input data, exports data cached address range.
Optionally, the adjustment module 202, the type specifically for the design defect when the chip are that accelerator cannot
Adapt to neural network scale when, the neural network is split into multiple sub-networks so that the accelerator adapt to it is each
Sub-network.
Optionally, the adjustment module 202, the type specifically for the design defect when the chip are arithmetic element fortune
Calculation mode, which is designed, staggers the time, and corresponding operation mode is added in the training process of neural network, is made in the training process
Operation is identical as the operation mode holding for the arithmetic element that accelerator fails, so that neural network adapts to the incorrect fortune of accelerator
Calculation mode.
Processing with Neural Network device provided in an embodiment of the present invention based on chip design defect, passes through the acquisition chip
The type of design defect；Neural network is adjusted according to the type, so that the neural network is on the chip just
Often operation；By modifying or adjusting to deep neural network model, so that neural network adapts to the hard of mistake occur again
Part structure completes operation target.
Fig. 3 provides a kind of hardware configuration of Processing with Neural Network equipment based on chip design defect for the embodiment of the present invention
Schematic diagram, as shown in figure 3, the equipment specifically includes:
Processor 310, memory 320, transceiver 330.
Processor 310 can be central processing unit (English: central processing unit, CPU) or CPU and
The combination of hardware chip.Above-mentioned hardware chip can be specific integrated circuit (English: application-specific
Integrated circuit, ASIC), programmable logic device (English: programmable logic device, PLD) or
A combination thereof.Above-mentioned PLD can be Complex Programmable Logic Devices (English: complex programmable logic
Device, CPLD), field programmable gate array (English: field-programmable gate array, FPGA), general battle array
Row logic (English: generic array logic, GAL) or any combination thereof.
Memory 320 is for storing various applications, operating system and data.Memory 320 can pass the data of storage
It is defeated by processor 310.Memory 320 may include volatile memory, non-volatile dynamic random access memory (English:
Nonvolatile random access memory, NVRAM), phase change random access memory (English: phase change
RAM, PRAM), magnetic-resistance random access memory (English: magetoresistive RAM, MRAM) etc., a for example, at least magnetic
Disk storage device, Electrical Erasable programmable read only memory (English: electrically erasable programmable
Read-only memory, EEPROM), flush memory device, such as anti-or flash memory (NOR flash memory) or anti-and flash memory
(NAND flash memory), semiconductor devices, such as solid state hard disk (English: solid state disk, SSD) etc..Storage
Device 320 can also include the combination of the memory of mentioned kind.
Transceiver 330, for sending and/or receiving data, transceiver 330 can be antenna etc..
The course of work of each device is as follows:
Processor 310, the type of the design defect for obtaining chip.
Processor 310 is also used to be adjusted neural network according to the type, so that the neural network is described
It is operated normally on chip.
Wherein, the type of the design defect of the chip includes at least following one:
Input/output data caching does not adapt to the scale of neural network, operation in abnormal operating state, accelerator
Unit design fault.
Optionally, processor 310 are also used to when the type of the design defect of the chip be at inputoutput data caching
When abnormal operating state, the input data rate of the inputoutput data caching is adjusted.
Optionally, processor 310 are also used to when the type of the design defect of the chip be input/output data caching
When in abnormal operating state, adjustment arithmetic element from input data cache read data or write output it is data cached
Address range.
Optionally, processor 310, are also used to modify the quantity that each input data reads weight, adjustment arithmetic element from
The frequency of input/output data caching access data.
Optionally, processor 310 are also used to when the type of the design defect of the chip be that accelerator does not adapt to nerve
When the scale of network, the neural network is split into multiple sub-networks, so that the accelerator adapts to each sub-network.
Optionally, processor 310 are also used to when the type of the design defect of the chip be that arithmetic element operation mode is set
When meter error, corresponding operation mode is added in the training process of neural network, make operation in the training process with plus
The operation mode of the arithmetic element of fast device failure keeps identical, so that neural network adapts to the incorrect operation mode of accelerator.
Processing with Neural Network equipment provided in this embodiment based on chip design defect can be base as shown in Figure 3
In the Processing with Neural Network equipment of chip design defect, the Processing with Neural Network as shown in figure 1 based on chip design defect can be performed
All steps of method, and then realize the technical effect of the Processing with Neural Network method based on chip design defect shown in Fig. 1, tool
Body please refers to Fig. 1 associated description, and for succinct description, therefore not to repeat here.
Professional should further appreciate that, described in conjunction with the examples disclosed in the embodiments of the present disclosure
Unit and algorithm steps, can be realized with electronic hardware, computer software, or a combination of the two, hard in order to clearly demonstrate
The interchangeability of part and software generally describes each exemplary composition and step according to function in the above description.
These functions are implemented in hardware or software actually, the specific application and design constraint depending on technical solution.
Professional technician can use different methods to achieve the described function each specific application, but this realization
It should not be considered as beyond the scope of the present invention.
Above-described specific embodiment has carried out further the purpose of the present invention, technical scheme and beneficial effects
It is described in detail, it should be understood that being not intended to limit the present invention the foregoing is merely a specific embodiment of the invention
Protection scope, all within the spirits and principles of the present invention, any modification, equivalent substitution, improvement and etc. done should all include
Within protection scope of the present invention.
Claims (10)
1. a kind of Processing with Neural Network method based on chip design defect characterized by comprising
Obtain the type of the design defect of chip；
Neural network is adjusted according to the type, so that the neural network operates normally on the chip；
Wherein, the type of the design defect of the chip includes at least following one:
Input/output data caching does not adapt to the scale of neural network, arithmetic element in abnormal operating state, accelerator
Design fault.
2. the method according to claim 1, wherein described be adjusted neural network according to the type,
Include:
When the type of the design defect of the chip is that input/output data caching is in abnormal operating state, adjustment mind
The quantity of the parameters such as scale and weight through layer each among network, so that the input/output of input/output data caching
The rate of data is adjusted.
3. according to the method described in claim 2, it is characterized in that, the data of the setting input/output data caching
Address is adjusted, comprising:
The scale for adjusting neural network input input layer, allows the neural network that data buffer storage is made full use of not fail
Part gets around fail address.
4. the method according to claim 1, wherein described be adjusted neural network according to the type,
Include:
When the type of the design defect of the chip is that accelerator does not adapt to the scale of neural network, by the neural network
Multiple sub-networks are split into, so that the accelerator adapts to each sub-network.
5. the method according to claim 1, wherein described be adjusted neural network according to the type,
Include:
When the type of the design defect of the chip designs fault for arithmetic element, the corresponding operation mode of arithmetic element is added
Enter into the training process of neural network, the arithmetic element operation mode of operation and failure in the training process is made to keep phase
Together, so that neural network adapts to the incorrect operation mode of accelerator.
6. a kind of Processing with Neural Network device based on chip design defect characterized by comprising
Obtain module, the type of the design defect for obtaining chip；
Module is adjusted, for being adjusted according to the type to neural network, so that the neural network is on the chip
It operates normally；
Wherein, the type of the design defect of the chip includes at least following one:
Input/output data caching does not adapt to the scale of neural network, arithmetic element in abnormal operating state, accelerator
Design fault.
7. device according to claim 6, which is characterized in that the adjustment module, specifically for setting when the chip
When the type for counting defect is that input/output data caching is in abnormal operating state, the rule of each layer of neural network model are adjusted
The quantity of the parameters such as mould and weight, so that the rate of the input/output data of input/output caching is adjusted.
8. device according to claim 7, which is characterized in that it is defeated to be specifically used for adjustment neural network for the adjustment module
The scale for entering input layer, the part for allowing the neural network that data buffer storage is made full use of not fail get around fail address.
9. device according to claim 6, which is characterized in that the adjustment module, specifically for setting when the chip
When the type of meter defect is that accelerator does not adapt to the scale of neural network, the neural network is split into multiple sub-networks,
So that the accelerator adapts to each sub-network.
10. device according to claim 6, which is characterized in that the adjustment module, specifically for setting when the chip
When the type of meter defect designs fault for arithmetic element, corresponding operation mode is added in the training process of neural network,
Keep operation in the training process identical as the arithmetic element operation mode holding of failure, so that neural network adapts to accelerator not
Correct operation mode.
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Cited By (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11403069B2 (en) | 2017-07-24 | 2022-08-02 | Tesla, Inc. | Accelerated mathematical engine |
| US11409692B2 (en) | 2017-07-24 | 2022-08-09 | Tesla, Inc. | Vector computational unit |
| CN115272287A (en) * | 2022-08-19 | 2022-11-01 | 哈尔滨市科佳通用机电股份有限公司 | Fault detection method, medium and system for rail wagon buffer and slave plate |
| US11487288B2 (en) | 2017-03-23 | 2022-11-01 | Tesla, Inc. | Data synthesis for autonomous control systems |
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| US11561791B2 (en) | 2018-02-01 | 2023-01-24 | Tesla, Inc. | Vector computational unit receiving data elements in parallel from a last row of a computational array |
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| US11636333B2 (en) | 2018-07-26 | 2023-04-25 | Tesla, Inc. | Optimizing neural network structures for embedded systems |
| US11665108B2 (en) | 2018-10-25 | 2023-05-30 | Tesla, Inc. | QoS manager for system on a chip communications |
| US11681649B2 (en) | 2017-07-24 | 2023-06-20 | Tesla, Inc. | Computational array microprocessor system using non-consecutive data formatting |
| US11734562B2 (en) | 2018-06-20 | 2023-08-22 | Tesla, Inc. | Data pipeline and deep learning system for autonomous driving |
| US11748620B2 (en) | 2019-02-01 | 2023-09-05 | Tesla, Inc. | Generating ground truth for machine learning from time series elements |
| US11790664B2 (en) | 2019-02-19 | 2023-10-17 | Tesla, Inc. | Estimating object properties using visual image data |
| US11816585B2 (en) | 2018-12-03 | 2023-11-14 | Tesla, Inc. | Machine learning models operating at different frequencies for autonomous vehicles |
| US11841434B2 (en) | 2018-07-20 | 2023-12-12 | Tesla, Inc. | Annotation cross-labeling for autonomous control systems |
| US11893393B2 (en) | 2017-07-24 | 2024-02-06 | Tesla, Inc. | Computational array microprocessor system with hardware arbiter managing memory requests |
| US11893774B2 (en) | 2018-10-11 | 2024-02-06 | Tesla, Inc. | Systems and methods for training machine models with augmented data |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103076996A (en) * | 2013-01-08 | 2013-05-01 | 深圳市硅格半导体有限公司 | Phase change random access memory (PCRAM) control method and system |
| CN106485317A (en) * | 2016-09-26 | 2017-03-08 | 上海新储集成电路有限公司 | A kind of neutral net accelerator and the implementation method of neural network model |
| CN106650922A (en) * | 2016-09-29 | 2017-05-10 | 清华大学 | Hardware neural network conversion method, computing device, compiling method and neural network software and hardware collaboration system |
| CN107437110A (en) * | 2017-07-11 | 2017-12-05 | 中国科学院自动化研究所 | The piecemeal convolution optimization method and device of convolutional neural networks |
| CN107451659A (en) * | 2017-07-27 | 2017-12-08 | 清华大学 | Neutral net accelerator and its implementation for bit wide subregion |
| CN108090560A (en) * | 2018-01-05 | 2018-05-29 | 中国科学技术大学苏州研究院 | The design method of LSTM recurrent neural network hardware accelerators based on FPGA |
-
2018
- 2018-09-27 CN CN201811127453.5A patent/CN109359731B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103076996A (en) * | 2013-01-08 | 2013-05-01 | 深圳市硅格半导体有限公司 | Phase change random access memory (PCRAM) control method and system |
| CN106485317A (en) * | 2016-09-26 | 2017-03-08 | 上海新储集成电路有限公司 | A kind of neutral net accelerator and the implementation method of neural network model |
| CN106650922A (en) * | 2016-09-29 | 2017-05-10 | 清华大学 | Hardware neural network conversion method, computing device, compiling method and neural network software and hardware collaboration system |
| CN107437110A (en) * | 2017-07-11 | 2017-12-05 | 中国科学院自动化研究所 | The piecemeal convolution optimization method and device of convolutional neural networks |
| CN107451659A (en) * | 2017-07-27 | 2017-12-08 | 清华大学 | Neutral net accelerator and its implementation for bit wide subregion |
| CN108090560A (en) * | 2018-01-05 | 2018-05-29 | 中国科学技术大学苏州研究院 | The design method of LSTM recurrent neural network hardware accelerators based on FPGA |
Non-Patent Citations (1)
| Title |
|---|
| 高放: "面向片上异构多核系统的机器学习算法并行化技术研究", 《中国博士学位论文全文数据库 信息科技辑》 * |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
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| US11681649B2 (en) | 2017-07-24 | 2023-06-20 | Tesla, Inc. | Computational array microprocessor system using non-consecutive data formatting |
| US11409692B2 (en) | 2017-07-24 | 2022-08-09 | Tesla, Inc. | Vector computational unit |
| US11893393B2 (en) | 2017-07-24 | 2024-02-06 | Tesla, Inc. | Computational array microprocessor system with hardware arbiter managing memory requests |
| US11403069B2 (en) | 2017-07-24 | 2022-08-02 | Tesla, Inc. | Accelerated mathematical engine |
| US11561791B2 (en) | 2018-02-01 | 2023-01-24 | Tesla, Inc. | Vector computational unit receiving data elements in parallel from a last row of a computational array |
| US11797304B2 (en) | 2018-02-01 | 2023-10-24 | Tesla, Inc. | Instruction set architecture for a vector computational unit |
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| US11562231B2 (en) | 2018-09-03 | 2023-01-24 | Tesla, Inc. | Neural networks for embedded devices |
| US11983630B2 (en) | 2018-09-03 | 2024-05-14 | Tesla, Inc. | Neural networks for embedded devices |
| US11893774B2 (en) | 2018-10-11 | 2024-02-06 | Tesla, Inc. | Systems and methods for training machine models with augmented data |
| US11665108B2 (en) | 2018-10-25 | 2023-05-30 | Tesla, Inc. | QoS manager for system on a chip communications |
| US11816585B2 (en) | 2018-12-03 | 2023-11-14 | Tesla, Inc. | Machine learning models operating at different frequencies for autonomous vehicles |
| US11537811B2 (en) | 2018-12-04 | 2022-12-27 | Tesla, Inc. | Enhanced object detection for autonomous vehicles based on field view |
| US11908171B2 (en) | 2018-12-04 | 2024-02-20 | Tesla, Inc. | Enhanced object detection for autonomous vehicles based on field view |
| US11610117B2 (en) | 2018-12-27 | 2023-03-21 | Tesla, Inc. | System and method for adapting a neural network model on a hardware platform |
| US11748620B2 (en) | 2019-02-01 | 2023-09-05 | Tesla, Inc. | Generating ground truth for machine learning from time series elements |
| US11567514B2 (en) | 2019-02-11 | 2023-01-31 | Tesla, Inc. | Autonomous and user controlled vehicle summon to a target |
| US11790664B2 (en) | 2019-02-19 | 2023-10-17 | Tesla, Inc. | Estimating object properties using visual image data |
| CN115272287A (en) * | 2022-08-19 | 2022-11-01 | 哈尔滨市科佳通用机电股份有限公司 | Fault detection method, medium and system for rail wagon buffer and slave plate |
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